A solid state storage device temperature control method

Abstract

The application provides a solid state storage device temperature control method, including a solid state disk master control chip of a multi-CPU core architecture, a front-end core Core0 periodically sampling solid state disk disc each part sensor temperature value, and calculating a composite temperature, sending the composite temperature to an auxiliary core mCore4; a back-end core Core2, Core3 real-time collecting respective working logical unit number quantity, and feeding back to the auxiliary core mCore4; the auxiliary core mCore4 accumulates and averages the sampling data, and detects whether the composite temperature exceeds a conditional threshold value, if exceeding the threshold value, then according to the actual load level and temperature grade adjustment logical unit number maximum concurrent number limit value; the back-end core Core2, Core3 gets the concurrent number limit value from the auxiliary core mCore4, and adjusts the flash memory controller. The application saves computing power and improves input and output performance, ensures that the solid state disk temperature and power consumption are limited without losing too much performance, and guarantees the accuracy and real-time of the maximum logical unit number concurrent number calculation result.

Description

Technical Field

[0001] This invention relates to a temperature control method for solid-state storage devices, belonging to the field of solid-state drive technology. Background Technology

[0002] Solid-state storage devices are widely used in high-speed, frequent read / write storage systems due to their fast I / O response speed. However, their power consumption is usually positively correlated with their performance. Under high-load read / write scenarios, the temperature of solid-state drives (SSDs) often rises rapidly (especially when heat dissipation is limited). When the temperature exceeds a certain level, the stability of the data stored in the internal flash memory chips will decrease, and the lifespan of other components may also be affected. Therefore, temperature control measures are needed to limit the performance and power consumption of SSDs and ensure that they operate within a safe temperature range.

[0003] Among the components of a solid-state drive (SSD), the flash memory chips typically consume the most power during operation. This is because there are a large number of flash memory chips integrated within the SSD, they operate at high concurrency, and each chip consumes a significant amount of power (especially when executing write commands), thus contributing substantially to the SSD's temperature rise. Therefore, a method is needed to control temperature by limiting the concurrency of the flash memory chips through the firmware backend program. Summary of the Invention

[0004] The purpose of this invention is to provide a temperature control method for solid-state storage devices, which saves computing power, improves input and output performance, ensures that the temperature and power consumption of solid-state drives are limited without losing too much performance, and guarantees the accuracy and real-time performance of the calculation results of the maximum logical unit number concurrency.

[0005] To achieve the above objectives, the present invention employs the following technical solution:

[0006] The solid-state drive controller chip includes a multi-CPU core architecture, comprising four large cores: Core0, Core1, Core2, and Core3, and two small cores: mCore4 and mCore5; Core0 is the front-end core, Core1 and Core2 are algorithm cores, Core3 is the back-end core, Core2 is also a back-end core, and mCore4 is an auxiliary core;

[0007] The front-end core Core0 periodically samples the temperature values ​​of sensors in various parts of the solid-state drive, calculates the composite temperature, and sends the composite temperature to the auxiliary core mCore4.

[0008] The backend cores Core2 and Core3 collect the number of their respective working logical unit numbers in real time and feed them back to the auxiliary core mCore4;

[0009] The auxiliary core mCore4 accumulates and averages the sampled data and checks whether the composite temperature exceeds the condition threshold. If it exceeds the threshold, it adjusts the maximum concurrency limit of the logic unit number according to the actual load level and temperature range.

[0010] Backend cores Core2 and Core3 obtain the concurrency limit from the auxiliary core mCore4 and adjust the flash controller accordingly.

[0011] Preferably, the condition threshold is 68-70℃.

[0012] Preferably, each logical unit number is configured with a logical unit number control block data structure to manage the status of that logical unit number and the currently executed and subsequent pending flash commands;

[0013] Each channel of the flash memory controller is configured with a channel management block data structure, which stores the logical unit number of the command being executed, the control block handle, and the attribute parameters of the channel in order of priority.

[0014] The messages sent by the algorithm core Core1 to the backend cores Core2 and Core3 are assigned to the command execution list of the corresponding channel's logical unit number according to their flash physical address;

[0015] Preferably, the specific method for the backend cores Core2 and Core3 to collect the number of their respective working logical unit numbers in real time is as follows:

[0016] Add an attribute member to the logical unit number control block to reflect the number of commands executed on each logical unit number; add an attribute member to the channel management block to indicate the number of logical unit numbers currently executing commands under a channel; add a count value accessible to all cores in the global scope of the firmware program to represent the total number of logical unit numbers executing commands under all channels; implement the counting of the concurrent number of logical unit numbers.

[0017] Two global variables are defined and shared among multiple cores, representing the maximum number of logical unit numbers allowed to execute commands under each channel and the maximum number of logical unit numbers allowed to execute commands under all channels of the entire SSD, respectively, to limit the concurrent number of logical unit numbers; the global variables are calculated and assigned values ​​through the auxiliary core mCore4, and the backend cores Core2 and Core3 use the global variables to determine the number of logical unit numbers.

[0018] Preferably, the backend cores Core2 and Core3 use global variables to determine the number of logical unit numbers in the following specific way:

[0019] When the firmware backend program is about to send a new read, write, erase, or other command to the flash controller, it checks whether the number of working logical cell numbers in the global and new command channels has not reached the upper limit. If the condition is met, the new command is sent to the flash controller and the count value of the working logical cell numbers is updated. Otherwise, the new command is temporarily suspended to ensure that the number of concurrent logical cell numbers does not exceed the upper limit.

[0020] After a command in a logical unit number is successfully executed, the firmware first increments the attribute in the logical unit number control block that reflects the number of commands executed on each logical unit number by 1. If this value is 1 after the increment, the logical unit number will just change from an idle state to a command execution state. The attribute member of the channel management block to which the logical unit number belongs, which represents the number of logical unit numbers currently executing commands under a channel, and the global variable representing the maximum number of logical unit numbers allowed to execute commands under all channels of the entire solid-state drive, are also incremented by 1 respectively.

[0021] When the command in the logical unit number finishes execution, the attribute in the logical unit number control block that reflects the number of commands executed on each logical unit number is decremented by 1. If it becomes 0, it means that all commands for that logical unit number have been completed and it has entered an idle state. At this time, the attribute member of the channel management block to which the logical unit number belongs, which represents the number of logical unit numbers currently executing commands under a channel, and the global variable representing the maximum number of logical unit numbers allowed to execute commands under all channels of the entire solid-state drive, are also decremented by 1.

[0022] Preferably, the auxiliary core mCore4 adjusts the maximum concurrent limit of the logic unit number according to the actual load level and temperature setting in the following specific way:

[0023] If the composite temperature reaches or exceeds the threshold condition for entering temperature control, the temperature control state is entered, the sampling of the average load of the logic unit number is stopped, and the limit ratio is determined according to the upper limit of the number of logic unit numbers and the temperature level.

[0024] The limiting ratio p is a variable that is related to both the load level L0 and the temperature difference ΔT between the composite temperature and the temperature control threshold. The higher L0 and ΔT are, the smaller p is, that is, the greater the limiting range. The load level L0 is the average number of logic unit numbers sampled before entering the temperature control.

[0025] The formula for calculating the restriction ratio is as follows:

[0026] p = α * L0 + β * △T + γ,

[0027] Wherein, α, β, and γ represent proportionality coefficients, which are calculated using the least squares method based on the limiting ratio p, the load level L0, and the temperature difference ΔT between the composite temperature and the temperature control threshold.

[0028] This is used to calculate all channels after entering the temperature control and the maximum allowed number of concurrent logical unit numbers under each channel, and synchronize this information to the backend cores Core2 and Core3.

[0029] If the composite temperature is lower than the threshold condition for exiting temperature control, and the solid-state drive is currently in temperature control mode, then the maximum number of concurrent logical unit numbers for all channels and individual channels will be restored to the normal unlimited state, and the sampling process for the load of each back-end core logical unit number will be resumed.

[0030] Preferably, the upper limit of the number of logical unit numbers is as follows: If the solid-state drive has not entered the temperature control state and the detected composite temperature is lower than the threshold condition for entering the temperature control state, then the instantaneous load level of the sampled back-end core logical unit numbers is accumulated and averaged to obtain the actual load of the logical unit numbers in the most recent period of time, which is used as the upper limit of the number of logical unit numbers after entering the temperature control state.

[0031] Preferably, when not in use and when entering temperature control for the first time, the sampling period for the average load of the logic unit number is a fixed value of once every two seconds;

[0032] After the auxiliary core mCore4 completes one temperature control state, it re-enters the temperature control state and adjusts the sampling period according to the change of the current composite temperature relative to the previous one, and sets the time point for the next sampling and processing.

[0033] Adjust the sampling cycle based on the fluctuation of the composite temperature relative to the last time it entered the temperature control state.

[0034] Preferably, the method for adjusting the sampling period based on the fluctuation of the composite temperature relative to the previous temperature control state is as follows:

[0035] Calculate the absolute value of the temperature change rate, which is equal to the temperature difference between the two sampling times divided by the sampling period of the previous sampling.

[0036] When the absolute value of the temperature change rate is greater than or equal to 0.5℃ / s, the fluctuation is large, and the sampling period is directly set to the minimum value;

[0037] When the absolute value of the temperature change rate is 0.2~0.5℃ / s, the fluctuation is relatively large, and the sampling period should be shortened by 25% compared to the previous one;

[0038] When the absolute value of the temperature change rate is 0.03~0.2℃ / s, the fluctuation is small, and the sampling period is extended by 30% compared to the previous one;

[0039] When the absolute value of the temperature change rate is less than 0.03℃ / s, the fluctuation is very small, and the sampling period is directly set to a fixed value.

[0040] The advantages of this invention are: the implementation of each sub-step of the temperature control function in the solid-state drive firmware, such as composite temperature sampling, flash load level sampling, and concurrent control of logical unit number commands, is split and implemented on multiple CPU cores. Compared with implementing the entire process on a single core, this reduces the pressure on CPU computation and helps save computing power and improve I / O performance.

[0041] The back-end core limits the concurrent number of logical unit numbers based on a program architecture that manages logical unit numbers in software. This implementation can solve the problem when the flash controller module used by the solid-state drive does not have the function of directly controlling the concurrent number of logical unit numbers in hardware.

[0042] Before entering temperature control, the average number of logical unit numbers of commands being executed by the backend is sampled to determine the load type. After entering temperature control, a matching limiting strategy is adopted for loads of different pressure intensities, which can ensure that the temperature and power consumption of the solid-state drive are limited without losing too much performance.

[0043] Dynamically adjusting the sampling and processing cycle of the auxiliary core based on the temperature change range helps ensure the accuracy and real-time performance of the maximum logic unit number concurrency calculation results. Attached Figure Description

[0044] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0045] Figure 1 This is a schematic diagram illustrating the communication process and content of each core in this invention.

[0046] Figure 2 A schematic diagram of the firmware backend's judgment and control process for verifying the concurrent number of logical unit numbers.

[0047] Figure 3 A schematic diagram of the firmware backend's judgment and control process for verifying the concurrent number of logical unit numbers.

[0048] Figure 4 This temperature control implementation scheme is illustrated by the flowchart of the auxiliary core mCore4 adjusting the maximum concurrent number limit of the logic unit number. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] The solid-state drive (SSD) temperature control solution mentioned in this invention is based on a multi-CPU core architecture SSD controller chip, including four large cores (Core0-3) that handle computationally intensive business logic such as the front-end, algorithm, and back-end of the SSD firmware, respectively. Two smaller cores (mCore4 and mCore5) act as auxiliary cores, handling functions with relatively low real-time and performance requirements, such as serial communication. The front-end core (Core0) periodically samples temperature values ​​from sensors on various parts of the SSD and calculates the composite temperature. The two back-end cores (Core2 and Core3) collect the number of their respective working logic unit numbers in real time and feed it back to the auxiliary core (mCore4). mCore4 accumulates and averages the sampled data and checks if the composite temperature exceeds a threshold. If it does, it adjusts the maximum concurrent limit of the logic unit number based on the actual load level and temperature range. The back-end cores (Core2 and Core3) obtain this concurrency limit from mCore4 and adjust their command sending behavior to the flash memory controller accordingly. The communication process between these cores is as follows: Figure 1 As shown.

[0051] Since the solid-state drive temperature control strategy limits power consumption by dynamically adjusting the number of concurrent logical unit numbers, the focus of this method is on the logic for checking and determining the current number of concurrent logical unit numbers on the back-end cores Core2 and Core3, as well as the implementation of the function on the auxiliary core mCore4 to calculate the maximum number of concurrent logical unit numbers based on load and temperature sampling values.

[0052] 1. Implementation of the backend core logic unit number concurrency check and determination logic:

[0053] The firmware backend program described in this method is implemented based on a software logical unit number management framework. Each logical unit number is set up with a logical unit number control block data structure to manage the status of the logical unit number and the currently executed and subsequent pending flash commands. Each channel of the flash controller is also set up with a channel management block data structure to store the logical unit number control block handle of the currently executing command and other attribute parameters of the channel according to priority.

[0054] All messages sent from the firmware FTL algorithm core to the backend core will be assigned to the command execution list of the corresponding channel's logical unit number based on their flash physical address.

[0055] To count the concurrency of logical unit numbers, property members `cmd_exec_cnt` and `active_lun_num` are added to the logical unit number control block and the channel management block respectively. The former reflects the number of commands executed on each logical unit number. Generally, only one flash read / write command can be executed on a logical unit number at the same time. However, if the flash memory particles support multi-Plane asynchronous independent read operations on the logical unit number, multiple commands may be executed simultaneously on a logical unit number. This variable is introduced to avoid double counting the number of logical unit numbers. The latter represents the number of logical unit numbers currently executing commands under a channel. In addition, a count value `g_all_active_luns` that can be accessed by each core is added globally in the firmware program, representing the total number of logical unit numbers currently executing commands under all channels.

[0056] To limit the concurrency of logical unit numbers, two globally shared variables `g_ch_max_luns_ctrl` and `g_all_max_luns_ctrl` are defined among multiple cores, representing the maximum number of logical unit numbers allowed to execute commands under each channel and the maximum number of logical unit numbers allowed to execute commands under all channels of the entire solid-state drive respectively. Adding the limit of the number of logical unit numbers for each channel based on the global logical unit number limit aims to prevent some channels from monopolizing all available logical unit number resources for a long time, causing other channels to be blocked. These two parameters are calculated and assigned by the auxiliary core mCore4, and the backend cores Core2 and Core3 use their values for judgment.

[0057] Specifically, the judgment process is as follows:

[0058] When the firmware backend program is ready to send new read / write / erase commands to the flash controller, it will check whether the number of logical unit numbers currently working globally and in the channel where the new command is located has not reached the upper limit, that is, it meets the conditions of `g_all_active_luns` (global) < `g_all_max_luns_ctrl` and `active_lun_num` (current channel) < `g_ch_max_luns_ctrl`. If the conditions are met, the new command will be sent to the flash controller and the count value of the logical unit numbers in work will be updated as described below. Otherwise, the new command will be postponed to ensure that the number of concurrent logical unit numbers does not exceed the upper limit at the same time.

[0059] After a command on a logical unit number is successfully executed, the firmware first increments the `cmd_exec_cnt` attribute of the control block for that logical unit number by 1. If the value is 1 after the increment, the logical unit number has just transitioned from an idle state to a command execution state. At this time, the `active_lun_num` attribute of the channel management block to which the logical unit number belongs and the global variable `g_all_max_luns_ctrl` are also incremented by 1. When the command on the logical unit number finishes execution, the `cmd_exec_cnt` attribute of the control block for that logical unit number is decremented by 1. If it becomes 0, it indicates that all commands for that logical unit number have been completed and it has entered an idle state. At this time, the `active_lun_num` attribute of the channel management block to which the logical unit number belongs and the global variable `g_all_max_luns_ctrl` are also decremented by 1.

[0060] The above firmware backend's judgment and control of the number of concurrent logical unit numbers can be summarized as follows: Figure 2 and 3 The process is shown below.

[0061] 2. Implementation of the auxiliary core's process for adjusting the maximum concurrency limit of the maximum logical unit number:

[0062] The auxiliary core mCore4 periodically samples the composite temperature (g_tmp_cps) from the front-end core Core0 and the number of logical unit numbers currently executing commands (g_all_active_luns) from the back-end cores Core2 and Core3, and then determines whether to limit the maximum concurrency of logical unit numbers based on this data.

[0063] If the solid-state drive has not previously entered temperature control mode, and the detected composite temperature is lower than the threshold condition for entering temperature control, the instantaneous load level of the sampled back-end logical unit number (g_all_active_luns under the respective management channels of Core2 and Core3) is accumulated and averaged to obtain the actual load of the logical unit number in the recent period, which serves as the upper limit of the number of logical units after entering temperature control.

[0064] If the composite temperature reaches or exceeds the threshold condition for entering temperature control, the system enters temperature control mode, stops sampling the average load of the logical unit number, determines the limit ratio based on the average load level and temperature level of the logical unit number before entering temperature control, and calculates the maximum allowed concurrent logical unit number of all channels and each channel after entering temperature control (g_all_max_luns_ctrl, g_ch_max_luns_ctrl), and synchronizes it to the backend cores Core2 and Core3.

[0065] The limiting ratio p is a variable that is related to both the load level L0 (i.e., the average number of LUNs sampled before entering temperature control) and the degree to which the composite temperature exceeds the temperature control threshold ΔT. The higher L0 and ΔT are, the smaller p is, that is, the greater the limiting range.

[0066] The formula for calculating the restriction ratio p is as follows:

[0067] p = α * L0 + β * △T + γ,

[0068] Where α, β, and γ are coefficients calculated using the least squares method from each (L0, ΔT, p) sample group.

[0069] The coefficients are first obtained by actual measurement of the most suitable limiting ratio values ​​p under some discrete condition points (L0, △T), and then statistically compiled into a data table. Then, two-dimensional linear regression fitting is performed to obtain the coefficients.

[0070] The maximum number of concurrent logical unit numbers across all channels is Lmax(global) = L0 * p, and the maximum number of concurrent logical unit numbers for a single channel is Lmax(chan) = Lmax(global) / Nch, where Nch is the number of channels in the flash controller.

[0071] If the combined temperature is below the threshold condition for exiting temperature control and the solid-state drive is currently in temperature control mode, the maximum number of concurrent logical unit numbers for all channels and individual channels will be restored to the normal unlimited state, and the sampling process for the load of each back-end core logical unit number will be resumed.

[0072] After the auxiliary core mCore4 completes the above processing, it adjusts the sampling period according to the change in the composite temperature relative to the previous one, and sets the time point for the next sampling and processing. For the first time entering the temperature control state, the sampling period is a fixed value. After entering the temperature control state, if the composite temperature fluctuates greatly relative to the previous one, the sampling period is appropriately shortened within a certain range of change, and vice versa.

[0073] The specific method for adjusting the sampling period based on the fluctuation of the composite temperature relative to the previous temperature control state is as follows:

[0074] Calculate the absolute value of the temperature change rate, which is equal to the temperature difference between the two sampling times divided by the sampling period of the previous sampling.

[0075] When the absolute value of the temperature change rate is greater than or equal to 0.5℃ / s, the fluctuation is large, and the sampling period is directly set to the minimum value;

[0076] When the absolute value of the temperature change rate is 0.2~0.5℃ / s, the fluctuation is relatively large, and the sampling period should be shortened by 25% compared to the previous one;

[0077] When the absolute value of the temperature change rate is 0.03~0.2℃ / s, the fluctuation is small, and the sampling period is extended by 30% compared to the previous one;

[0078] When the absolute value of the temperature change rate is less than 0.03℃ / s, the fluctuation is very small, and the sampling period is directly set to a fixed value.

[0079] The firmware auxiliary core's process for adjusting the maximum concurrency limit of the logic unit number is as follows: Figure 4 As shown.

[0080] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A temperature control method for a solid-state storage device, characterized in that, The solid-state drive controller chip includes a multi-CPU core architecture, comprising four large cores: Core0, Core1, Core2, and Core3, and two small cores: mCore4 and mCore5; Core0 is the front-end core, Core1 and Core2 are algorithm cores, Core3 is the back-end core, Core2 is also a back-end core, and mCore4 is an auxiliary core; The front-end core Core0 periodically samples the temperature values ​​of sensors in various parts of the solid-state drive, calculates the composite temperature, and sends the composite temperature to the auxiliary core mCore4. The backend cores Core2 and Core3 collect the number of their respective working logical unit numbers in real time and feed them back to the auxiliary core mCore4; The auxiliary core mCore4 accumulates and averages the sampled data and checks whether the composite temperature exceeds the condition threshold. If it exceeds the threshold, it adjusts the maximum concurrency limit of the logic unit number according to the actual load level and temperature range. Backend cores Core2 and Core3 obtain the concurrency limit from the auxiliary core mCore4 and adjust the flash controller accordingly; The auxiliary core mCore4 adjusts the maximum concurrent limit of the logic unit number according to the actual load level and temperature setting in the following specific way: If the composite temperature reaches or exceeds the threshold condition for entering temperature control, the temperature control state is entered, the sampling of the average load of the logic unit number is stopped, and the limit ratio is determined according to the upper limit of the number of logic unit numbers and the temperature level. The limiting ratio p is a variable that is related to both the load level L0 and the temperature difference ΔT between the composite temperature and the temperature control threshold. The higher L0 and ΔT are, the smaller p is, that is, the greater the limiting range. The load level L0 is the average number of logic unit numbers sampled before entering the temperature control. The formula for calculating the restriction ratio is as follows: p = α * L0 + β * △T + γ, Wherein, α, β, and γ represent proportionality coefficients, which are calculated using the least squares method based on the limiting proportion p, load level L0, and temperature difference ΔT between the composite temperature and the temperature control threshold obtained in the partial sample group during actual measurement. This is used to calculate all channels after entering the temperature control and the maximum allowed number of concurrent logical unit numbers under each channel, and synchronize this information to the backend cores Core2 and Core3. If the composite temperature is lower than the threshold condition for exiting temperature control, and the solid-state drive is currently in temperature control mode, then the maximum number of concurrent logical unit numbers for all channels and individual channels will be restored to the normal unlimited state, and the sampling process for the load of each back-end core logical unit number will be resumed.

2. The temperature control method for solid-state storage devices according to claim 1, characterized in that, The threshold temperature is 68-70℃.

3. The temperature control method for solid-state storage devices according to claim 1, characterized in that, Each logical unit number is assigned a logical unit number control block data structure to manage the status of that logical unit number and the currently executing and subsequent pending flash commands; Each channel of the flash memory controller is configured with a channel management block data structure, which stores the logical unit number of the command being executed, the control block handle, and the attribute parameters of the channel in order of priority. The messages sent by the algorithm core Core1 to the backend cores Core2 and Core3 are assigned to the command execution list of the corresponding channel's logical unit number according to their flash physical address.

4. The temperature control method for solid-state storage devices according to claim 3, characterized in that, The specific method by which the backend cores Core2 and Core3 collect the number of their respective working logical unit numbers in real time is as follows: Add an attribute member to the logical unit number control block to reflect the number of commands executed on each logical unit number; add an attribute member to the channel management block to indicate the number of logical unit numbers currently executing commands under a channel; add a count value accessible to all cores in the global scope of the firmware program to represent the total number of logical unit numbers executing commands under all channels; implement the counting of the concurrent number of logical unit numbers. Two global variables are defined and shared among multiple cores, representing the maximum number of logical unit numbers allowed to execute commands under each channel and the maximum number of logical unit numbers allowed to execute commands under all channels of the entire SSD, respectively, to limit the concurrent number of logical unit numbers; the global variables are calculated and assigned values ​​through the auxiliary core mCore4, and the backend cores Core2 and Core3 use the global variables to determine the number of logical unit numbers.

5. The temperature control method for solid-state storage devices according to claim 4, characterized in that, The specific method by which the backend cores Core2 and Core3 use global variables to determine the number of logical unit numbers is as follows: When the firmware backend program is about to send a new read, write, erase, or other command to the flash controller, it checks whether the number of working logical cell numbers in the global and new command channels has not reached the upper limit. If the condition is met, the new command is sent to the flash controller and the count value of the working logical cell numbers is updated. Otherwise, the new command is temporarily suspended to ensure that the number of concurrent logical cell numbers does not exceed the upper limit. After a command in a logical unit number is successfully executed, the firmware first increments the attribute in the logical unit number control block that reflects the number of commands executed on each logical unit number by 1. If this value is 1 after the increment, the logical unit number will just change from an idle state to a command execution state. The attribute member of the channel management block to which the logical unit number belongs, which represents the number of logical unit numbers currently executing commands under a channel, and the global variable representing the maximum number of logical unit numbers allowed to execute commands under all channels of the entire solid-state drive, are also incremented by 1 respectively. When the command in the logical unit number finishes execution, the attribute in the logical unit number control block that reflects the number of commands executed on each logical unit number is decremented by 1. If it becomes 0, it means that all commands for that logical unit number have been completed and it has entered an idle state. At this time, the attribute member of the channel management block to which the logical unit number belongs, which represents the number of logical unit numbers currently executing commands under a channel, and the global variable representing the maximum number of logical unit numbers allowed to execute commands under all channels of the entire solid-state drive, are also decremented by 1.

6. The temperature control method for solid-state storage devices according to claim 1, characterized in that, The upper limit of the number of logical unit numbers is as follows: If the solid-state drive has not entered the temperature control state and the detected composite temperature is lower than the threshold condition for entering temperature control, the instantaneous load level of the sampled back-end core logical unit numbers is accumulated and averaged to obtain the actual load of the logical unit numbers in the most recent period, which is used as the upper limit of the number of logical unit numbers after entering temperature control.

7. The temperature control method for a solid-state storage device according to claim 6, characterized in that, When not in use and when entering temperature control for the first time, the sampling period for the average load of the logic unit number is a fixed value of once every two seconds; After the auxiliary core mCore4 completes one temperature control state, it re-enters the temperature control state and adjusts the sampling period according to the change of the current composite temperature relative to the previous one, and sets the time point for the next sampling and processing. Adjust the sampling cycle based on the fluctuation of the composite temperature relative to the last time it entered the temperature control state.

8. The temperature control method for a solid-state storage device according to claim 7, characterized in that, The specific method for adjusting the sampling period based on the fluctuation of the composite temperature relative to the previous temperature control state is as follows: Calculate the absolute value of the temperature change rate, which is equal to the temperature difference between the two sampling times divided by the sampling period of the previous sampling. When the absolute value of the temperature change rate is greater than or equal to 0.5℃ / s, the fluctuation is large, and the sampling period is directly set to the minimum value; When the absolute value of the temperature change rate is 0.2~0.5℃ / s, the fluctuation is relatively large, and the sampling period should be shortened by 25% compared to the previous one; When the absolute value of the temperature change rate is 0.03~0.2℃ / s, the fluctuation is small, and the sampling period is extended by 30% compared to the previous one; When the absolute value of the temperature change rate is less than 0.03℃ / s, the fluctuation is very small, and the sampling period is directly set to a fixed value, that is, the original maximum value.

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