Instant and permanent self-destruction method in 3D NAND for data security purposes

Abstract

3D NAND instant and permanent self-destruction method for data security purposes. Devices and techniques are described that perform an operation that irreversibly prevents access to a set of memory cells. The operation provides a strong erase bias to the select gate transistors of a NAND string. The erase bias initiates a phenomenon that permanently increases their threshold voltages in the select gate transistors. This prevents access to the memory cells, such as program or read operations. The operation can involve one or more erase-verify iterations. In each erase-verify iteration, an erase bias is applied to the select gate transistors, such as by charging the channel of the NAND string and controlling the control gate voltage of the select gate transistors at a lower level, causing a relatively high channel-to-control gate voltage.

Description

Background Technology

[0001] This disclosure relates to the operation of memory devices.

[0002] The use of semiconductor memory devices has become increasingly popular in various electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials, such as floating gates or charge trapping materials, can be used in such memory devices to store charges representing data states. For example, charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure. An example of a 3D memory structure is a bit-cost scalable (BiCS) architecture that includes alternating conductive and dielectric layers.

[0004] Memory devices include memory cells that can be arranged in series in a NAND string, for example, where select-gate transistors are provided at the ends of the NAND string to selectively connect the channels of the NAND string to source lines or bit lines. However, various challenges exist in operating such memory devices. Attached Figure Description

[0005] Figure 1A This is a block diagram of an exemplary memory device.

[0006] Figure 1B yes Figure 1A A block diagram of the arrangement of the memory device 100, wherein the control circuitry 130 on the first die 130a communicates with the memory structure 126 on the separate second die 126b.

[0007] Figure 2 It describes Figure 1A A block diagram of one embodiment of the sensing block 51.

[0008] Figure 3 Depicting Figure 1A An exemplary implementation of the power control circuit 115 is used to provide voltage to a block of memory cells in a plane.

[0009] Figure 4 This is a perspective view of an exemplary memory die 400, in which blocks of memory cells are provided in corresponding planes P0 and P1.

[0010] Figure 5 Depicting Figure 1A An exemplary transistor 520 of the memory structure 126.

[0011] Figure 6 Depicting Figure 4An exemplary cross-sectional view of a portion of block B0-0, containing NAND strings 700n and 710n.

[0012] Figure 7A Depicting and Figure 4 and Figure 6 An exemplary view of the NAND string in consistent block B0-0.

[0013] Figure 7B Depicting Figure 7A An exemplary top view of block B0-0, having a corresponding NAND string, bit line, and sensing circuitry.

[0014] Figure 8A The threshold voltage (Vth) distribution of an eight-state memory device is depicted.

[0015] Figure 8B An exemplary Vth distribution (Vth distribution 810) of the select gate transistor during programming and an exemplary Vth distribution (Vth distribution 811) during erasure in a normal erase operation are depicted.

[0016] Figure 8C An exemplary Vth distribution (Vth distribution 810) of the select gate transistor during programming is depicted, as well as an exemplary Vth distribution (Vth distribution 812) when erased using a sufficiently strong erase bias voltage, which causes an increase in the threshold voltage of some select gate transistors.

[0017] Figure 9A Depicting Figure 7A A portion of the NAND string 700n shows the accumulation of electrons in the blocking oxide (BOX) 663 after a disabled operation.

[0018] Figure 9B A graph depicting the number of select-gate transistors with high upper tail Vth versus erase voltage Verase is presented.

[0019] Figure 9C A graph depicting the sigma of a page versus the count of faulty bits per page is shown.

[0020] Figure 10A An overview diagram depicts the process of permanently preventing access to memory cells.

[0021] Figure 10B and Figure 10A The process of permanently preventing access to multiple blocks in a memory cell is consistently described.

[0022] Figure 10C and Figure 10A The process of permanently preventing access to a single block in a memory cell is consistently described.

[0023] Figure 10D and Figure 10A The process of permanently preventing access to individual sub-blocks in a memory cell is consistently described.

[0024] Figure 11A and Figure 10A Step 1003 consistently describes the process of applying an erase bias voltage to the selected gate transistor.

[0025] Figure 11B and Figure 10A Step 1003 and Figure 11A The process of performing verification tests for the gate selector transistor is consistently described.

[0026] Figure 12A and Figure 11A The process consistently depicts the direction towards Figure 7A An example voltage is applied to the NAND string 700n, where a disable erase bias is applied to the SGD transistor 716 and the SGS transistor 701.

[0027] Figure 12B and Figure 11B The process consistently depicts the direction towards Figure 7A An exemplary voltage is applied to the NAND string 700n, wherein a verification voltage is applied to the SGD transistor 716 and the SGS transistor 701.

[0028] Figure 12C and Figure 11A The process consistently depicts the direction towards Figure 7A An exemplary voltage is applied to the NAND string 700n, wherein a disable erase bias is applied to the SGD transistor 716 but not to the SGS transistor 701.

[0029] Figure 12D and Figure 11B The process consistently depicts the direction towards Figure 7A An exemplary voltage is applied to the NAND string 700n, wherein a verification voltage is applied to the SGD transistor 716 but not to the SGS transistor 701.

[0030] Figure 13 Depicting in relation to Figure 11A and 11B The exemplary waveform is consistent with the process of operation. Detailed Implementation

[0031] An apparatus and technique are described that perform an operation to irreversibly prevent access to a set of memory cells. This operation provides a strong erase bias voltage to the select-gate transistors of a NAND string. The erase bias voltage causes a permanent increase in the threshold voltage of the select-gate transistors. This prevents access to the memory cells, such as preventing programming or read operations.

[0032] In some memory devices, such as NAND strings within a block or sub-block, memory cells are interconnected. Each NAND string includes a number of memory cells connected in series between one or more drain-side select-gate transistors (SGD transistors) and one or more source-side select-gate transistors (SGS transistors), the drain-side select-gate transistors being connected to the drain terminal of a bitline of the NAND string, and the source-side select-gate transistors being connected to the source terminal of a set of NAND strings or other memory strings or connected memory cells. The select-gate transistors are also referred to as select gates. Additionally, memory cells may be arranged with a common control gate line (e.g., a word line) that acts as a control gate. The set of word lines extends from the source side of the block to the drain side of the block. See, for example, [link to relevant documentation]. Figure 7A Memory cells can be connected in other types of serial connections, and also in other ways.

[0033] In a 3D memory structure, memory cells can be arranged in vertical NAND strings within a stack in a substrate, where the stack includes alternating conductive and dielectric layers. The conductive layers act as word lines connecting to the memory cells. Each NAND string can have a pillar shape intersecting the word lines to form the memory cell. Additionally, each NAND string includes individual layers extending vertically within the stack. See, for example... Figure 6 The NAND string 700n contains a channel 660 and a charge trapping layer 664. The source terminal 700s of the NAND string is connected to the substrate 611, and the drain terminal 700d of the NAND string is connected to the bit line BL0. See, for example, [link to documentation]. Figure 6 .

[0034] Memory structures, including those described above, are widely used for storage and data transfer in consumer devices, enterprise systems, and industrial applications due to their non-volatility, affordability, high storage density, and access speed. Consumer needs typically include high durability and long data retention times. However, in some scenarios, it is desirable to permanently prevent access to the memory structure, such as for devices containing sensitive data that have reached the end of their usable life or are no longer owned by authorized personnel. For example, consider a mobile phone or laptop lost by its owner who wishes to disable the device via a remote signal. Or consider an unrecoverable satellite or unmanned aerial vehicle. Preventing data access can also prevent any other use of the memory structure, such as storing new data or testing the memory structure to determine its characteristics. In these or other scenarios, permanently disabling the memory structure and the bare die is desired to protect the data.

[0035] One method to prevent data access in a memory structure is to erase the data during an erase operation. However, a typical erase operation takes a relatively long time to erase all blocks on the bare die, such as tens of seconds. Furthermore, the erase operation does not prevent further use and testing of the memory structure. Another method is to erase blocks that have been reserved for storing the parameters used during the startup of the memory device. Such blocks are called read-only memory (ROM) blocks, such as user ROM blocks, because they are typically programmed only once at manufacturing and subsequently read during the lifetime of the memory device. However, the parameters can typically be recovered from backup locations. Other methods rely on supplying very high voltages, such as 80V, to physically destroy the memory circuitry through burning.

[0036] However, this method requires additional components, which contradicts the goal of reducing size and weight.

[0037] The techniques presented in this paper address the above and other issues. In one aspect, an operation is performed to permanently increase the threshold voltage of the select-gate transistors within a NAND string. This operation involves providing a strong erase bias to the select-gate transistors. The erase bias causes the threshold voltage of the select-gate transistors to be permanently increased above a verification voltage, which is greater than the threshold voltage of the memory cell. This prevents the memory cell from being programmed or read. The select-gate transistors can be located at the drain and / or source terminals of the NAND string.

[0038] This operation may involve one or more erase-verify iterations. In each erase-verify iteration, such as by charging the channel of the NAND string and keeping the control gate voltage of the select gate transistor at a low level, an erase bias is applied to the select gate transistor, thereby making the channel-to-control gate voltage relatively high. In one method, an erase pulse with the amplitude of Verase is applied to the substrate to charge the channel, on which blocks of memory cells are formed. If the erase bias is high enough, such as Figure 8C The phenomenon described can occur, which increases the threshold voltage (Vth) of some select-gate transistors. A verification test can be performed to determine if a minimum number of select-gate transistors have a Vth higher than the verification voltage Vverify. If the verification test passes, the operation is complete. If the verification test fails, another erase-verify iteration can be performed, in which the amplitude and / or duration of Verase is increased. Therefore, the erase bias can be increased in subsequent erase-verify iterations after the initial erase-verify iteration.

[0039] In one approach, the operation can be performed on both the SGD and SGS transistors. Alternatively, the operation can be performed on the SGD transistor but not on the SGS transistor, or on the SGS transistor but not on the SGD transistor.

[0040] Operations can be performed simultaneously on a set of blocks, on a single block, or on a single sub-block of a block. When operations are performed on a set of blocks, verification tests can be performed on a selected block from multiple blocks. This saves time compared to performing the verification operation on each block from multiple blocks. In one approach, the block selected for verification testing can be a user ROM block, while the other blocks in the set are user data blocks. This approach is useful because user ROM blocks are known to be good and defect-free. Figure 4 B1-0 is an example user ROM block.

[0041] This operation can be considered as a permanent erase operation, a disable operation, or a self-destruct operation of the memory cell.

[0042] These and other features will be discussed further below.

[0043] Figure 1AThis is a block diagram of an exemplary memory device. Memory device 100, such as a non-volatile memory system, may include one or more memory dies 108. Memory die 108 or a chip includes a memory structure 126 (such as an array of memory cells), control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines through row decoder 124 and via bit lines through column decoder 132. Read / write circuitry 128 includes multiple sensing blocks 51, 52, ..., 53 (sensing circuitry) and allows pages of memory cells to be read or programmed in parallel. A typical controller 122 is included in the same memory device 100 (e.g., a removable memory card) along with one or more memory dies 108. The controller may reside on a die 127 separate from the memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120, and between the controller and one or more memory dies 108 via line 118.

[0044] The memory structure can be 3D. A memory structure can include one or more arrays of memory cells comprising a 3D array. A memory structure can include a monolithic 3D memory structure in which multiple memory levels are formed above (and not within) a single substrate, such as a wafer, without having an intermediate substrate. A memory structure can include any type of non-volatile memory monolithically formed in one or more physical levels of an array of memory cells, the one or more physical levels having active regions disposed above a silicon substrate. A memory structure can be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0045] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126 and includes state machine 112, on-chip address decoder 114, and power control circuitry 115. Storage area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, state machine 112 is software programmable. In other embodiments, state machine 112 does not use software and is implemented entirely in hardware (e.g., circuitry).

[0046] The on-chip address decoder 114 provides an address interface between the hardware addresses used by decoders 124 and 132 and the addresses used by the host or memory controller. Power control circuitry 115 controls the power and voltage supplied to the word lines, select gate lines, bit lines, and source lines during memory operation. It may include drivers for word lines, SGS and SGD transistors, and source lines. See also... Figure 3 In one approach, the sensing block may include a bit line driver.

[0047] In some implementations, some of the components can be combined. In various designs, one or more (alone or in combination) of the components, other than memory structure 126, can be considered as at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any one or a combination of the following: control circuit 110, state machine 112, decoders 114 and 132, power control module 115, sensing blocks 51, 52, ..., 53, read / write circuit 128, controller 122, etc. The state machine is a circuit that can control the operation of control circuit 110. In some embodiments, the state machine may be implemented or replaced by a microprocessor, microcontroller, and / or RISC processor.

[0048] An off-chip controller 122 (which is circuitry in one embodiment) may include a processor 122e, memories such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct several read errors. For example, RAM 122b may store uncommitted data. During programming, a copy of the data to be programmed is stored in RAM 122b until programming is successfully completed. In response to successful completion, data is erased from RAM 122b and committed or released to a block of memory cells. RAM 122b may store one or more word lines of data.

[0049] A memory interface 122d may also be provided. The memory interface, which communicates with the ROM, RAM, and processor, is a circuit that provides an electrical interface between the controller and the memory die. For example, the memory interface can change the format or timing of signals, provide buffering, surge isolation, latch I / O, etc. The processor can issue commands to the control circuitry 110 (or any other component of the memory die) via the memory interface 122d.

[0050] The memory in controller 122 (such as ROM 122a and RAM 122b) includes code such as an instruction set, and the processor is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, the processor may access code from a subset 126a of memory structures (such as reserved areas of memory cells in one or more word lines).

[0051] For example, code can be used by controller 122 to access memory structures, such as for programming, reading, or erasing operations. The code may include boot code and control code (e.g., an instruction set). Boot code is software that initializes the controller during the boot or startup process and enables the controller to access memory structures. The code can be used by the controller to control one or more memory structures. During startup, processor 122e retrieves boot code from ROM 122a or subset 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code contains drivers for basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0052] For example, the controller of RAM 122b and / or control circuit 110 can store parameters indicating the expected number of failed bits in the block. These parameters may include, for example, the number of bits in each cell stored in the memory cell, a portion of the word line programmed in the block or sub-block, a portion of the sub-block programmed in the block, the strength of the ECC process used to store and read data in the block, the duration of the pre-fetch voltage pulse (if used), and read accuracy, such as bit line or word line voltage set time and the number of sensed passes.

[0053] Typically, control code may contain instructions to perform the functions described herein, including the flowcharts further discussed below, and to provide these voltage waveforms, including the voltage waveforms further discussed below. Control circuitry may be configured to execute instructions to perform the functions described herein.

[0054] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces and / or one or more input / output devices that communicate with the one or more processors.

[0055] Other types of non-volatile memory besides NAND flash memory can also be used.

[0056] Semiconductor memory devices include volatile memory devices (such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices), non-volatile memory devices (such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”)), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in NAND or NOR configurations.

[0057] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements such as antifuse or phase-change materials, and optional switching elements such as diodes or transistors. Further as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0058] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is a collection of series transistors that include memory cells and SG transistors.

[0059] NAND memory arrays can be configured such that the array consists of multiple strings of memory, where each string comprises multiple memory elements sharing a single bit line and being accessed in groups. Alternatively, memory elements can be configured such that each element is individually accessible, for example, in a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements can be configured in other ways.

[0060] Semiconductor memory elements located within and / or on a substrate can be arranged in a three-dimensional manner.

[0061] Memory elements can be arranged in an ordered array, such as multiple rows and / or columns, within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0062] 3D memory arrays are arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in a three-dimensional manner (i.e. in the x, y, and z directions, where the z direction is substantially perpendicular to the main surface of the substrate, and the x and y directions are substantially parallel to the main surface of the substrate).

[0063] As a non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., in the y-direction), with each column having multiple memory elements. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0064] In a 3D NAND memory array, memory elements can be coupled together to form a vertical NAND string spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. 3D memory arrays can also be designed in NOR and ReRAM configurations.

[0065] Typically, in a monolithic 3D memory array, one or more memory device levels are formed over a single substrate. Alternatively, the monolithic 3D memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may comprise a semiconductor such as silicon. In a monolithic 3D array, the layer constituting each memory device level of the array is typically formed on top of the layer of the memory device level below the array. However, layers of adjacent memory device levels in a monolithic 3D memory array may be shared or may have intermediate layers between memory device levels.

[0066] Typically, associated circuitry is required for the operation and communication of the memory elements. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory elements to perform functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and / or on separate substrates. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0067] Figure 1B yes Figure 1AA block diagram of the arrangement of a memory device 100, wherein control circuitry 130 on a first die 130a communicates with a memory structure 126 on a separate second die 126b. The control circuitry may communicate with the memory structure and the die 126b via, for example, a memory interface 131 similar to a memory interface 122d. An example of a memory interface (I / F) includes JEDEC's Common Flash Memory Interface. The techniques described herein can be implemented with a control die 130a combined with one or more memory dies 126b, wherein the memory die contains the memory structure 126, and the control die contains control circuitry representing all or a subset of the peripheral circuitry of the memory structure. The control circuitry may be on the same die as the multiple memory cells or on a different die than the multiple memory cells.

[0068] For example, the memory structure may include non-volatile memory cells. In some embodiments, the memory die and control die are combined. Control circuitry 130 may include a collection of circuitry that performs memory operations (e.g., write, read, erase, or others) on the memory structure. Control circuitry may include state machine 112, memory region 113, on-chip address decoder 114, and power control circuitry 115. In another embodiment, a portion of read / write circuitry 128 is located on control die 130a and another portion of read / write circuitry is located on memory die 126b. For example, read / write circuitry may include a sense amplifier. The sense amplifier may be located on the control die and / or the memory die.

[0069] The term "memory die" can refer to a bare semiconductor die containing non-volatile memory cells for data storage. The term "control circuitry" can refer to a bare semiconductor die containing control circuitry for performing memory operations on the non-volatile memory cells on the memory die. Typically, many bare semiconductor dies are formed from a single semiconductor wafer.

[0070] Figure 2 It describes Figure 1A A block diagram of one embodiment of the sensing block 51. The individual sensing block 51 is partitioned into one or more core portions referred to as sensing modules 60-63 or sensing amplifiers, and a common portion referred to as management circuitry 190. In one embodiment, each sensing circuit is connected to a corresponding bit line and NAND string, and the common management circuitry 190 is connected to a collection of multiple (e.g., four or eight) sensing circuits. Each of the sensing circuits communicates with its associated management circuitry via a data bus 176. Therefore, there are one or more management circuits communicating with the sensing circuitry of the collection of storage elements (memory cells).

[0071] As an example, sensing circuit 60 operates during the programming loop to provide a precharge / programming disable voltage to an unselected bit line or a programming enable voltage to a selected bit line. The unselected bit line is connected to an unselected NAND string and to an unselected memory cell within it. The unselected memory cell can be a memory cell within an unselected NAND string, where the memory cell is connected to either a selected word line or an unselected word line. Alternatively, the unselected memory cell can be a memory cell within a selected NAND string, where the memory cell is connected to an unselected word line. The selected bit line is connected to the selected NAND string and to the selected memory cell within it.

[0072] The sensing circuit 60 also operates during the verification test in the programming loop to sense memory cells, thereby determining whether the memory cell has been programmed by reaching the assigned data state, for example, indicated by its Vth exceeding the verification voltage of the assigned data state. The sensing circuit 60 also operates during the read operation to determine the data state in which the memory cell has been programmed. The sensing circuit 60 also operates during the erase operation in the verification test to determine whether the Vth of multiple memory cells is below the verification voltage. The sensing circuit performs sensing by determining whether the conductive current in the connected bit lines is above or below a predetermined threshold level. This indicates whether the Vth of the memory cell is above or below the corresponding word line voltage.

[0073] The sensing circuit 60 also operates in the disable operation as described at the beginning to permanently increase the threshold voltage of the select gate transistor to prevent access to the memory cell. The sensing circuit determines whether the Vth of the select gate transistor is higher than the verification voltage Vverify applied to the control gate of the select gate transistor.

[0074] The sensing circuit may include a selector 56 or a switch connected to transistor 55 (e.g., nMOS). Based on the voltage at the control gate 58 and drain 57 of transistor 55, the transistor may operate to pass through the gate or to clamp the bit line. When the voltage at the control gate is sufficiently higher than the voltage at the drain, the transistor may operate to pass through the gate to conduct the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, a programming disable voltage such as 1-2V may be used when pre-charging and disabling unselected NAND strings. Alternatively, a programming enable voltage such as 0V may be used to allow programming in selected NAND strings. Selector 56 may pass a supply voltage Vdd (e.g., 3-4V) to the control gate of transistor 55 to operate it to pass through the gate.

[0075] When the voltage at the control gate is lower than the voltage at the drain, transistor 55 operates as a source follower to set or clamp the bit line voltage to Vcg-Vth, where Vcg is the voltage at the control gate 58 and Vth (e.g., 1V) is the threshold voltage of transistor 55. This assumes the source line is at 0V. This mode can be used during sensing operations such as read and verification operations. Therefore, the bit line voltage is set by transistor 55 based on the voltage output by selector 56. For example, selector 56 can pass Vbl_sense + Vth (e.g., 1.5V) to transistor 55 to provide Vbl_sense (e.g., 0.5V) on the bit line. Vbl selector 173 can pass a relatively high voltage, such as Vdd, to the drain 57, which is higher than the control gate voltage on transistor 55, to provide source follower mode during sensing operations.

[0076] Vbl selector 173 can pass one of several voltage signals. For example, Vbl selector 173 can pass a programming disable voltage that increases from an initial voltage (e.g., 0V) to a programming disable voltage (e.g., Vbl_inh) for the corresponding bit line of an unselected NAND string during the programming loop. Vbl selector 173 can also pass a programming enable voltage signal, such as 0V, for the corresponding bit line of a selected NAND string during the programming loop. For example, the Vbl selector can pass a programming enable voltage signal, such as 0V, based on a command from processor 192. Figure 3 The voltage driver 340 selects the voltage signal.

[0077] In one approach, the selector 56 of each sensing circuit can be controlled separately from the selectors of other sensing circuits. The Vbl selector 173 of each sensing circuit can also be controlled separately from the Vbl selectors of other sensing circuits.

[0078] During sensing, sensing node 171 is charged to an initial voltage, such as 3V, Vsense_init. The sensing node is then passed to a bitline via transistor 55, and the amount of decay of the sensing node is used to determine whether the memory cell is in a conductive or non-conductive state. Specifically, comparator circuit 175 determines the amount of decay by comparing the sensing node voltage with a trip voltage during sensing. If the sensing node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is at or below the verification voltage. If the sensing node voltage does not decay below the trip voltage Vtrip, the memory cell is in a non-conductive state and its Vth is above the verification voltage. For example, comparator circuit 175 sets sensing node latch 172 to 0 or 1 based on whether the memory cell is in a conductive or non-conductive state. Data in the sensing node latch can be read by processor 192 and used to update bits in trip latch 174. Subsequently, for the next programming loop, the bits in the jump latch can be used by the processor along with the allocated data state in latches 194-197 to determine whether the memory cell and NAND string are selected or not for programming in the programming loop, and thereby appropriately enable or disable the bit line voltages passing through the bit lines accordingly. Latches 194-197 can be considered as data latches or user data latches, as they store the data to be programmed into the memory cell.

[0079] Management circuitry 190 includes a processor 192, four exemplary sets of data latches 194-197 for sensing circuits 60-63 respectively, and an I / O interface 196 coupled between the sets of data latches and the data bus 120. A set of three data latches (e.g., including individual latches LDL, MDL, and UDL) may be provided for each sensing circuit. In some cases, a different number of data latches may be used. In the embodiment where each unit contains three bits, the LDL stores bits of the lower page of data, the MDL stores bits of the middle page of data, and the UDL stores bits of the upper page of data.

[0080] Processor 192 performs calculations, such as determining data to be stored in the sensed memory cells and storing the determined data in a set of data latches. Each set of data latches 194-197 is used to store data bits determined by processor 192 during a read operation and to store data bits introduced from data bus 120 during a programming operation, representing write data intended to be programmed into memory. I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

[0081] During a read operation, the system operates under the control of state machine 112, which supplies different control gate voltages to the addressed memory cell. As it steps through various predetermined control gate voltages corresponding to different memory states supported by the memory, the sense current can skip one of these voltages, and the corresponding output is provided from the sensing circuit to the processor 192 via data bus 176. At this time, by considering the tripping events of the sensing module and information about the control gate voltage applied from the state machine via input line 193, the processor 192 determines the resulting memory state. It then calculates a binary code for the memory state and stores the resulting data bits in data latches 194-197.

[0082] Some implementations may include multiple processors 192. In one embodiment, each processor 192 will include output lines (not shown) such that each of the output lines is wired-OR'd together. In some embodiments, the output lines are inverted before being connected to the OR'd lines. Because the state machine receiving the OR'd lines can determine when all the bits being programmed have reached the desired level, this configuration allows for rapid determination during programming verification tests when the programming process is complete. For example, when each bit has reached its desired level, a logic zero for that bit will be sent to the OR'd line (or the data one will be inverted). When all bits output data 0 (or the data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing circuits, the state machine needs to read the OR'd lines eight times, or logic can be added to the processor 192 to accumulate the results of the associated bit lines, so that the state machine only needs to read the OR'd lines once. Similarly, by correctly selecting the logic level, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0083] During the programming or verification operation of a memory cell, the data to be programmed (written data) is stored from the data bus 120 in a set of data latches 194-197. During reprogramming, the corresponding set of data latches for the memory cell can store data indicating when the memory cell is allowed to be reprogrammed based on the programming pulse amplitude.

[0084] Programming operations, under the control of a state machine, apply a series of programming voltage pulses to the control gate of the addressed memory cell. Each voltage pulse can be incremented in amplitude by a certain step from the previous programming pulse in a processed process called incremental step-pulse programming. Each programming pulse is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, processor 192 monitors the read-back memory state associated with the desired memory state. When the two agree, processor 192 sets the bit line to a programming-disabled mode, for example, by updating its latches. This prevents further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0085] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some implementations, the data latches are implemented as shift registers, such that parallel data stored therein is converted into serial data for the data bus 120 and vice versa. All data latches corresponding to read / write blocks of memory cells can be linked together to form a block shift register, allowing blocks of data to be serially input or output. In particular, a library of read / write modules is employed such that each of its data latch sets will sequentially shift data into or out of the data bus as if they were part of the shift register for the entire read / write block.

[0086] Data latches identify when an associated memory cell has reached certain mileposts in a programming operation. For example, a latch might indicate that the Vth of a memory cell is below a specific verification level. Data latches indicate whether a memory cell is currently storing one or more bits from a data page. For example, an LDL latch might be used to store the lower page of data. The LDL latch toggles (e.g., from 0 to 1) when the bits of the lower page are stored in the associated memory cell. For three bits per cell, an MDL or UDL latch toggles when the bits of the middle page or the lower page are stored in the associated memory cell, respectively. This occurs when the associated memory cell has completed programming.

[0087] Figure 3 Depicting Figure 1A An exemplary implementation of the power control circuit 115 is provided to supply voltage to a block of memory cells in a plane. In one approach, the circuitry shown can be repeated for each plane of the bare die. In this example, the memory structure 126 includes a set of four associated blocks B0-0 through B0-3, and another set of four associated blocks B0-4 through B0-7. See also Figure 4 A block can lie in one or more planes. Figure 1A The line decoder 124 provides voltage to the word line and select gate control line of each block via transistor 322. In one approach, a separate line decoder is provided for each block. The line decoder provides control signals to the through transistors that connect the block to the line decoder. In another approach, the through transistors for each set of blocks are controlled by a common control gate voltage. Thus, all the through transistors for a set of blocks are either on or off at a given time. If the through transistor is on, the voltage from the line decoder is provided to the corresponding control gate line or word line. If the through transistor is off, the line decoder is disconnected from the corresponding control gate line or word line, causing the voltage to float on the corresponding control gate line or word line.

[0088] For example, control gate line 312 is connected to transistor sets 313-316, which in turn are connected to control gate lines B0-4 to B0-7, respectively. Control gate line 317 is connected to transistor sets 318-321, which in turn are connected to control gate lines B0-0 to B0-3, respectively.

[0089] Typically, programming or reading operations are performed one at a time on a selected sub-block within a block. Erasing operations can be performed on the selected block or sub-block. The line decoder can connect global control line 302 to local control line 303. Control lines represent conductive paths. Voltage is supplied from several voltage drivers on the global control line. Some voltage drivers can supply voltage to switches 350 connected to the global control line. Transistor 324 is controlled to allow voltage to pass from the voltage drivers to the switches 350.

[0090] The voltage driver may include a selected data word line (WL) driver 347, which provides a voltage on the selected data word line during programming or read operations. During the programming loop of a programming operation, driver 147 may provide a pre-charge voltage and a programming voltage on the WLn. Driver 348 may be used for unselected data word lines, and dummy word line drivers 349 and 349a may be used respectively on... Figure 6 Voltage is provided on the dummy word lines WLDD and WLDS.

[0091] The voltage driver can also include separate SGD drivers for each sub-block. For example, SGD drivers 346, 346a, 346b, and 346c can be provided for SB0, SB1, SB2, and SB3 respectively, such as... Figure 7AThe SGD driver provides voltage to the control line connected to the control gate of the SGD transistor (drain-side selected gate transistor). In one option, the SGS driver 345 is common to different sub-blocks in the block and provides voltage to the control line connected to the control gate of the SGS transistor (source-side selected gate transistor).

[0092] Various components including the line decoder can receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

[0093] The p-well voltage driver 330 provides a voltage Vp-well to the p+ contact 612b in the p-well region 611b, for example, via a conductive path 682. See also Figure 6 In one approach, the p-well region 611b is common to the block. The Vp-well can be used with Figure 12 and... Figure 13 The Verase is the same. The set of bit lines 342 is also shared by the block. The source line (SL) voltage driver 331 provides voltage Vsl to the n+ contact 612c in the p-well region 611b, for example, via local interconnect 651.

[0094] Bit line voltage driver 340 includes a voltage source that supplies voltage to bit line 342. For example, the bit line voltage used to sense in an erase verification test could be 0.5V.

[0095] In such Figures 4 to 7B In the stacked memory device depicted, a collection of connected memory cells can be arranged in NAND strings that extend vertically upward from a substrate. In one approach, the bottom (or source end) of each NAND string is in contact with a substrate (e.g., a well region), and the top (or drain end) of each NAND string is connected to a corresponding bit line.

[0096] Figure 4 This is a perspective view of an exemplary memory die 400, wherein multiple blocks of memory cells are provided in corresponding planes P0 and P1, and... Figure 1A Consistent. The memory die comprises: a substrate 611; an intermediate region 402 in which blocks of memory cells are formed; and an upper region 403 in which one or more upper metal layers are patterned to form bit lines. Planes P0 and P1 represent corresponding isolation regions formed in the substrate 611. Additionally, a first block sequence 405 of n blocks labeled B0-0 to B0-n-1 is formed in P0, and a second block sequence 415 of n blocks labeled B1-0 to B1-n-1 is formed in P1. Each plane may have associated row and column control circuitry, such as... Figure 1A The row decoder 124, the read / write circuit 128, and the column decoder 132.

[0097] In one approach, control circuitry 110 can be shared across planes, and can be located in the peripheral region of the bare core. Each plane can have a separate set of bit lines.

[0098] By providing blocks of memory cells across multiple planes, parallel operations can be performed on those planes. For example, blocks in different planes can be erased simultaneously.

[0099] The substrate 611 may also support circuitry beneath the block, as well as one or more lower metal layers patterned in the conductive path to carry signals from the circuitry.

[0100] In this example, memory cells are formed in vertical NAND strings within a block. Each block includes a stacked area of ​​memory cells, where alternating levels of stacked bodies represent word lines. In one possible approach, each block has opposing hierarchical sides from which vertical contact bodies extend upwards to an upper metal layer to form connections to conductive paths. Although two planes are depicted as an example, other examples may use four or more planes. One plane per bare die is also possible.

[0101] Multiple blocks typically comprise user data blocks and one or more read-only memory (ROM) blocks, such as user ROM blocks. User data blocks are used for repeated programming, reading, and erasing operations throughout the lifetime of the memory device. These blocks typically store user data provided by the host. As mentioned at the beginning, ROM blocks (also called user ROM blocks) typically retain the same data and are not altered throughout the lifetime of the memory device. For example, data in user ROM blocks may include identifying bad (defective) columns or bad blocks within the user data blocks. Data in user ROM blocks may include parameters that configure the memory device after startup. One or more user ROM blocks are tested during manufacturing to ensure they are free of defects.

[0102] When the memory device boots up, bad column data is read by the controller and used to provide a column replacement table for use during read and write operations. In some cases, to improve reliability, ROM blocks store data using one bit per cell. User data blocks can store data at a higher density of two or more bits per cell.

[0103] For example, B1-0 can be a user ROM block, while the remaining blocks B0-0 to B0-n-1 and B1-1 to B1-n-1 are user data blocks.

[0104] Figure 5 Depicting Figure 1AAn exemplary transistor 520 of the memory structure 126. For example, the transistor includes a control gate CG, a drain D, a source S, and a channel CH, and may represent a memory cell or a select-gate transistor. The drain end of the transistor is optionally connected to a bit line BL via one or more other transistors in the NAND string, and the source end of the transistor is optionally connected to a source line SL via one or more other transistors in the NAND string. For example, the transistor may represent a memory cell or a select-gate transistor.

[0105] Figure 6 Depicting Figure 4 An exemplary cross-sectional view of a portion of block B0-0, including NAND strings 700n and 710n. In this example, NAND strings 700n and 710n are in different sub-blocks SB0 and SB1, respectively. The block includes a stack 610 of alternating conductive layers (word line layers) and dielectric layers. The layers may be rectangular plates having a height in the z-direction, a width in the y-direction, and a length in the x-direction.

[0106] A stack is depicted as comprising one or more layers, but optionally may include alternating conductive and dielectric layers. The stack includes a collection of alternating conductive and dielectric layers, in which memory vias are formed during fabrication.

[0107] The conductive layers include SGS, WLDS, WL0-WL95, WLDD, and SGD(0). The conductive layer connected to the control gate of the memory cell is called a word line, and the conductive layers connected to the control gates of the source-side select-gate transistor and the drain-side select-gate transistor are called source-side control lines and drain-side control lines, respectively. WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells that are not eligible to store user data. Dummy memory cells may have the same construction as data memory cells, but are considered by the controller to be ineligible to store any data type containing user data. One or more dummy memory cells may be provided at the drain and / or source ends of the NAND string of the memory cell to provide a gradient transition on the channel voltage gradient. The use of dummy memory cells is optional. WL0-WL95 are data word lines connected to data memory cells that are eligible to store user data. By way of example only, the stack contains ninety-six data word lines. DL is an exemplary dielectric layer.

[0108] The top 610t and bottom 610b of the stack are depicted. WL95 is the topmost data word line or conductive layer, and WL0 is the bottommost data word line or conductive layer.

[0109] NAND strings are formed by etching memory vias in the stack and then depositing multiple thin layers of material along the sidewalls of the memory vias. Memory cells are formed where word lines intersect with the multiple thin layers, and select gate transistors are formed in regions where SGS and SGD control lines intersect with the multiple thin layers. For example, drain-side select gate transistor 716 is formed in the region where SGD control lines intersect with the multiple thin layers, source-side select gate transistor 701 is formed in the region where SGS control lines intersect with the multiple thin layers, the topmost data memory cell 714 is formed in the region where WL95 word lines intersect with the multiple thin layers, and the bottommost data memory cell 703 is formed in the region where WL0 word lines intersect with the multiple thin layers.

[0110] Multiple thin layers can be formed into a ring layer and can be deposited, for example, using atomic layer deposition. For example, the layer can include a barrier oxide layer 663, a charge trapping layer 664 or a film such as silicon nitride (Si3N4) or other nitrides, a tunneling layer 665 (e.g., gate oxide), and a channel 660 (e.g., including polysilicon). A dielectric core 666 (including silicon oxide) can also be provided. Word lines or control lines can include a metal such as tungsten. In this example, all layers are provided within memory vias. In other methods, some layers can be provided within word line or control line layers. Multiple thin layers form columnar active regions (AA) of a NAND string.

[0111] A stack is formed on a substrate 611. In one approach, the substrate includes a p-well region 612 connected to the source end of a NAND string. The p-well region may include an epitaxial region 612a extending upward adjacent to a source-side select gate transistor. The p-well region may include an n+ contact 612c connected to a local interconnect 651 for receiving source line voltages, and a p+ contact 612b connected to a conductive path 682 for receiving p-well voltages. The local interconnect 651 may include a conductive material 651b, such as a metal, surrounded by an insulating material 651a to prevent metal conduction with adjacent word lines. In one possible implementation, the p-well region is formed in an n-well 613, which in turn is formed in a p-type semiconductor region 614 of the substrate.

[0112] The source terminal 700s of the NAND string 700n is located at the bottom 610b of the stack 610 and is connected to the p-well. The drain terminal 700d of the NAND string 700n is located at the top 610t of the stack and is connected to the bit line BL0 via a bit line contact 680 comprising an n-type material.

[0113] Because the length of the channel is not formed on the substrate, NAND strings can be considered to have floating body channels.

[0114] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are drawn from the channel into the charge trapping layer and through the tunneling layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the channels of the NAND string are charged, such as by applying a forward erase pulse to the substrate via local interconnect 651, causing holes to be injected into the charge trapping layer.

[0115] Figure 7A Depicting and Figure 4 and Figure 6 An exemplary view of the NAND strings in a consistent block B0-0. The NAND strings are arranged in a 3D configuration within sub-blocks of the block. Each sub-block contains multiple NAND strings, with one exemplary NAND string depicted. For example, SB0, SB1, SB2, and SB3 include exemplary NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings are... Figure 6 Each subblock consistently features data word lines, dummy word lines, and select gate lines. Each subblock comprises a set of NAND strings extending in the x-direction and sharing a common SGD line or control gate layer. NAND strings 700n, 710n, 720n, and 730n reside in subblocks SB0, SB1, SB2, and SB3, respectively. Programming of the blocks can occur based on the word line programming sequence. One option is to program memory cells in different portions of the word lines in different subblocks, one subblock at a time, and then program the memory cells of the next word line. For example, this could involve programming WL0 in SB0, SB1, SB2, then SB3, then programming WL1 in SB0, SB1, SB2, then SB3, and so on. For example, the word line programming sequence could begin at the source end word line of WL0 and end at the drain end word line of WL95.

[0116] In an erase operation, the entire block is typically erased, but it is also possible to erase a portion of the block, such as by erasing selected sub-blocks of the block and / or by erasing memory cells connected to a subset of word lines less than all word lines.

[0117] Multiple memory cells of B0-0 are arranged in NAND strings, wherein each NAND string includes a continuous charge trapping layer along its length. NAND strings 700n, 710n, 720n, and 730n have channels 700a, 710a, 720a, and 730a, respectively. Additionally, NAND string 700n includes an SGS transistor 701, dummy memory cells 702, data memory cells 703-714, dummy memory cells 715, and an SGD transistor 716. NAND string 710n includes an SGS transistor 721, dummy memory cells 722, data memory cells 723-734, dummy memory cells 735, and an SGD transistor 736. NAND string 720n includes an SGS transistor 741, dummy memory cells 742, data memory cells 743-754, dummy memory cells 755, and an SGD transistor 756. The NAND string 730n includes an SGS transistor 761, a dummy memory cell 762, data memory cells 763-774, a dummy memory cell 775, and an SGD transistor 776.

[0118] This example depicts one SGD transistor at the drain terminal of each NAND string and one SGS transistor at the source terminal of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in the NAND string.

[0119] Figure 7B Depicting Figure 7A An exemplary top view of block B0-0, showing the corresponding NAND strings, bit lines, and sensing circuitry. This view is in the xy-plane. Each circle represents a NAND string. In this example, sixteen NAND strings are depicted per sub-block. SB0 contains... Figure 7A The NAND string 700n and the additional NAND strings 700n1-700n15. SB1 contains Figure 7A The NAND string 710n and the additional NAND strings 710n1-710n15. SB2 contains... Figure 7A The NAND string 720n and the additional NAND strings 720n1-720n15. SB3 contains... Figure 7A The NAND string 730n and the additional NAND strings 730n1-730n15.

[0120] The set of bit lines BL0-BL15 is connected to NAND strings. Each bit line is connected to a corresponding set of NAND strings, containing one NAND string from each sub-block. For example, BL0 is connected to NAND strings 700n, 710n, 720n, and 730n in the set of NAND strings 799, BL1 is connected to NAND strings 700n1, 710n1, 720n1, and 730n1, and so on. Each bit line is also connected to... Figure 2 The sensing circuits 60-63 are corresponding sensing circuits. For example, BL0-BL15 are connected to sensing circuits SC0-SC15 respectively.

[0121] In the verification test for disabling the erase operation as described herein, a verification voltage Vverify is applied to the select-gate transistor. See also Figure 13 Simultaneously, each sensing circuit senses the current on the corresponding bit line based on the sum of the currents in the corresponding NAND strings connected to the bit line. For example, SC0 can sense the current on BL0 based on the currents on NAND strings 700n, 710n, 720n, and 730n. Therefore, the verification test can involve sensing the current in the set of NAND strings connected to each bit line. If the current is below a specified level, the set of NAND strings passes the verification test, for example, if the threshold voltage of the select-gate transistors in the set of NAND strings is higher than Vverify. If at least a minimum number of select-gate transistors pass the verification test, the block passes the verification test. In another possible approach, this sensing occurs one sub-block at a time for each bit line.

[0122] A collection of NAND strings (which may include all NAND strings in a block or sub-block) can be considered to have passed the verification test when all or almost all of the selected gate transistors pass the verification test. For example, this may occur when at least 1-5% of the NAND strings pass the verification test.

[0123] Figure 8A The threshold voltage (Vth) distribution of an eight-state memory device is depicted. As an example, eight data states or three bits per cell are depicted. In another example, two data states (one bit per cell), four data states (two bits per cell), or sixteen data states (four bits per cell) are used per memory cell. The vertical axis depicts the number of memory cells on a logarithmic scale, and the horizontal axis depicts the threshold voltage on a linear scale. The Vth distribution can represent all memory cells connected to word lines or all memory cells in a block. After erasing the block, a Vth distribution 800 is obtained, representing the erase state. The erase operation is complete when the Vth of all or almost all memory cells is below the verification voltage VvEr.

[0124] The memory cells then undergo programming operations. Each memory cell will have an assigned data state. Some memory cells are assigned to an erase state without programming. Most memory cells are programmed to higher states such as AF, as represented in this example by Vth distributions 801-807 respectively. These memory cells undergo verification testing using verification voltages VvA-VvG. Programming higher-state memory cells may interfere with erase-state memory cells, causing Vth distribution 801 to widen and shift upwards. The memory cells can be read using read voltages VrA-VrG.

[0125] Figure 8B An exemplary Vth distribution (Vth distribution 810) of the select gate transistor during programming and an exemplary Vth distribution (Vth distribution 811) during erasure in a normal erase operation are depicted. The Vth of the select gate transistor can be set during manufacturing, for example, by programming the select gate transistor. Figure 8B and Figure 8C In the graph, the vertical axis depicts the number of select-gate transistors on a logarithmic scale, and the horizontal axis depicts the threshold voltage on a linear scale. For example, select-gate transistors can be programmed in a manner similar to that used for memory cells by injecting charge into a charge-trapping layer. The programmed Vth is typically maintained over the lifetime of the select-gate transistor, but it can be periodically measured and adjusted. An exemplary Vth for a programmed select-gate transistor is 2-4V.

[0126] Figure 8C An exemplary Vth distribution (Vth distribution 810) of a select-gate transistor during programming and an exemplary Vth distribution (Vth distribution 812) during erasure using a sufficiently strong erase bias voltage induces an increase in the threshold voltage of some select-gate transistors. As mentioned, this phenomenon can occur in select-gate transistors where the threshold voltage is permanently and irreversibly increased when a strong erase bias voltage is applied. The erase bias voltage refers to the channel-to-control-gate voltage. This phenomenon has been observed in tests and is thought to involve electrons tunneling back from the select-gate line to the barrier oxide layer. For example, electrons are trapped in a defective or trapped state in a barrier oxide layer comprising Al2O3. Such defects are thought to be caused during the manufacturing process and are primarily located at the top and bottom of the block, at the drain and source ends of the NAND string, respectively. Therefore, this phenomenon is more likely to occur for SDG and SGS transistors than for memory cells, since SGD and SGS transistors are located at the top and bottom of the stack, respectively.

[0127] This phenomenon can also occur much more strongly with dummy memories, as they are typically located near the drain and source ends of the NAND string.

[0128] The drain endpoint can be considered as the first end of the NAND string, and the source endpoint as the second end, or the source endpoint can be considered as the first end of the NAND string, and the drain endpoint as the second end.

[0129] Vth distribution 812 is significantly wider than Vth distribution 810 and extends both below and above Vth distribution 810. This change represents the variation that occurs when the phenomenon of Vth increase due to the erase bias occurs. For some select-gate transistors, the erase bias reduces Vth as expected during normal erase operation. However, for other select-gate transistors, the erase bias increases due to this phenomenon. See also Figures 9A-9C Tests showed that the increase in Vth is permanent and irreversible. For example, applying a gentle erase bias to the select-gate transistor and baking the memory chip does not reverse the increase in Vth.

[0130] A portion 812a of the Vth distribution 812 represents the select-gate transistors that pass the verification test relative to Vverify. These select-gate transistors have Vth > Vverify. In one method, the disable operation is successfully completed if a minimum number of select-gate transistors pass the verification test, for example, it may be 1-15% of the select-gate transistors in a block or a portion of a block. The minimum number is the number of bits ignored.

[0131] In an exemplary implementation, the operation will irreversibly increase the threshold voltage of at least a minimum number of select gate transistors by at least 2V. For example, the Vth of the select gate transistors can be increased from 2-4V to 4-6V or higher.

[0132] Figure 9A Depicting Figure 7A A portion of the NAND string 700n is shown, illustrating the accumulation of electrons in the barrier oxide (BOX) 663 after a disable operation. This portion of the NAND string includes data memory cells 703 and 704 and associated word lines WL94 and WL95, dummy memory cell 705 and associated word line WLDD, and select gate transistor 706 and associated select gate line or control line SGD(0). A barrier oxide (BOX) layer 663, a charge trapping layer (CTL) 664, a tunneling oxide layer (TUN) 665, and a channel (CH) 660 are also depicted. In this example, these layers extend continuously throughout the NAND string from the source end to the drain end. The material provides a MANOS or metal (W)-alumina (Al2O3)-nitride (Si3N4)-oxide (SiO2)-silicon (Si) structure.

[0133] For example, during a disable operation, an erase bias causes electrons (depicted by "-") to transition from the select gate line SGD(0) to a portion 663a of the blocking oxide layer associated with the select gate transistor 706. The erase bias can be provided by applying an erase pulse Verase via the substrate to the channel to charge the channel (increase the voltage of the channel) to about 15 - 25V, for example, while applying a lower voltage Vsg_dis, such as 0 - 5V, to the select gate transistor. This provides a channel-to-gate voltage of at least 10, 15, or 20V, for example, which is sufficient to trigger the above-described phenomenon. In contrast, during a normal erase operation, the voltage of the select gate transistor can be floated or driven at a higher level (e.g., 10 - 15V), which results in a lower channel-to-gate voltage such that the above-described phenomenon does not occur. [[ID=!]]

[0134] For memory cells, Vunsel = 6 - 8V is applied to the corresponding word line. Memory cells typically do not have the above-described defect. Such a bias for memory cells can cause the Vth to remain relatively constant or result in a decrease in the Vth of the memory cells.

[0135] Figure 9B A graph of the number of select gate transistors having a high upper tail Vth versus the erase voltage Verase is depicted. The vertical axis depicts the number of select gate transistors whose Vth is above the 2.5 sigma level. A higher number indicates a wider Vth distribution, such as Figure 8C the Vth distribution 812. The erase bias increases as Verase increases. When Verase < Vx transition voltage, the number is relatively low, such that Figure 8B the Vth distribution 811 is obtained. In contrast, when Verase > Vx, the number increases significantly, such that Figure 8C the Vth distribution 812 is obtained. The appropriate value of Vx can be determined from testing.

[0136] Figure 9C A graph of the sigma of a page versus the number of failed bits per page is depicted. Graph 900 represents a relatively low FBC in the case of normal erase, program, and read operations. Different pages of data have different FBCs represented by a distribution where sigma = 0 is the midpoint. Graph 901 represents a very high FBC in the case of a disabled erase operation, demonstrating that data cannot be read from the memory cells once the operation is completed. In particular, when the Vth of the select gate transistor is higher than the highest available control gate voltage, which can be applied to the select gate transistor using the on-chip power supply, the select gate transistor will remain in a non-conductive state, such that the Vth of the memory cell cannot be read.

[0137] Figure 10AAn overview diagram of the process for permanently preventing access to a memory cell is depicted. At step 1000, an event occurs that guarantees permanent disabling of access to the memory cell in the device. For example, the event could be that a user has lost the memory device or no longer needs the memory device. At step 1001, the user issues a request to disable access to the memory cell, where the memory cell is in a NAND string with a select-gate transistor. For example, the user could access the interface of a host device communicating with the memory device. In another approach, the request is issued automatically in a self-destruct mode (such as when the memory device cannot communicate with the host device for a period of time). At step 1002, the host device sends a disable command to a state machine or other circuitry associated with the memory device. At step 1003, the state machine executes a command including applying a disable erase bias voltage to the select-gate transistor and performing a verification test to determine if a minimum number of select-gate transistors have a threshold voltage higher than the verification voltage. This step can be performed in each of one or more erase-verification iterations until the verification test is passed. In another option, the erase bias voltage is applied once or more but no subsequent associated verification test is performed.

[0138] It can provide a dedicated command that allows users to easily and quickly trigger the disable operation. The corresponding parameters can be provided, including:

[0139] F_Vera: The initial magnitude of the erase voltage. This can be higher than the initial erase voltage for a normal erase operation.

[0140] F_DVera: The step size of the incremental erase voltage amplitude in successive erase-verify iterations.

[0141] F_NTME: Eraser pulse duration. This can be longer than the erase pulse duration of a normal erase operation. Furthermore, the erase pulse width may be longer when the disable operation involves many or all blocks on the die, as charging the NAND string channels across a relatively large number of blocks can take a relatively long time.

[0142] F_delta_NTME: The step size of the incremental erase voltage duration in successive erase-verify iterations.

[0143] F_Vverify: Erase-verify voltage.

[0144] F_BSPF: Number of bits to ignore in the verification test

[0145] The prefix "F" indicates that the operation is disabled. Similar parameters can be provided for normal erase operations.

[0146] For example, an off-chip controller 122 can send a command to an on-chip control circuit 110 that includes a state machine 112 associated with a disable operation. The on-chip control circuit 110, which includes the state machine 112, can execute the command to perform the disable operation and return a report of the operation's status to the controller 122.

[0147] In one method, control circuitry (122, 130) is configured to be connected to a plurality of memory cells (702-715, 722-735, 742-755, 762-775), wherein the plurality of memory cells are arranged in a NAND string (700n-700n15, 710n-710n15, 720n-720n15, or 730n-730n15), and the NAND string includes select-gate transistors (701, 716, 721, 736, 741, 756, 761, 776). Additionally, a memory interface (122d, 131) is connected to circuitry, and the circuitry is configured to issue commands via the memory interface to perform an operation that irreversibly increases the threshold voltage of the select-gate transistor to a level higher than a verification voltage, wherein the operation applies a channel-to-gate voltage to the select-gate transistor.

[0148] Figure 10B and Figure 10A The process of permanently preventing access to multiple blocks in a memory cell is consistently described. At step 1010, a command to disable access to all blocks, including user data blocks and user ROM blocks, is received in the memory die or device. For example, the command can be received from the host at a state machine. At step 1011, the state machine applies a disable erase bias voltage to the select gate transistors of all blocks. Decision step 1012 determines whether the user ROM blocks pass a verification test. If decision step 1012 is true, then at step 1013, the state machine reports a pass status to the host. If decision step 1012 is false, then step 1014 increases the erase bias voltage magnitude and / or duration for the next erase-verify iteration. As mentioned, verification tests can be performed on selected blocks from the set of blocks subjected to the disable operation. Disabling all blocks on the die is appropriate, for example, when all blocks potentially contain sensitive data that should not be disclosed.

[0149] Figure 10C and Figure 10AThe process of permanently preventing access to a single block in a memory cell is consistently described. At step 1020, a command to disable access to the single block is received. At step 1021, the state machine applies a disable erase bias voltage to the select gate transistor of the single block. Decision step 1022 determines whether the single block passes the verification test. If decision step 1022 is true, then at step 1023, the state machine reports a pass status to the host. If decision step 1022 is false, then step 1024 increases the erase bias voltage amplitude and / or duration for the next erase-verification iteration. Disabling a single block on a bare die is appropriate, for example, when a particular block potentially contains sensitive data that should not be disclosed. Multiple single-block disable operations can be performed to disable multiple blocks. A subset of all blocks on a bare die can also be disabled simultaneously.

[0150] Figure 10D and Figure 10A The process of permanently preventing access to a single sub-block in a memory cell is consistently described. At step 1030, a command to disable access to the single sub-block is received. At step 1031, the state machine applies a disable erase bias voltage to the select gate transistor of the single sub-block. Decision step 1032 determines whether the single sub-block passes a verification test. If decision step 1032 is true, then at step 1033, the state machine reports a pass status to the host. If decision step 1032 is false, then step 1034 increases the erase bias voltage amplitude and / or duration for the next erase-verification iteration. Disabling a single sub-block on a bare die is appropriate, for example, when a particular sub-block potentially contains sensitive data that should not be disclosed. Multiple single-sub-block disable operations can be performed to disable multiple sub-blocks within a block. Multiple sub-blocks of a block can also be disabled simultaneously.

[0151] Figures 10B-10D The verification operation can potentially be omitted, for example, as long as the magnitude and duration of the erase bias are sufficient to complete the disable operation.

[0152] Figure 11A and Figure 10A Step 1003 consistently describes the process of applying an erase bias voltage to the select-gate transistor. Both the SGD and SGS transistors control access to memory cells in the NAND string. If either type of transistor undergoes a disable operation, memory cells cannot be accessed. Therefore, in one implementation of the disable operation, both the SGD and SGS transistors are disabled. In another implementation of the disable operation, either the SGD or SGS transistor is disabled, rather than both. The select-gate transistor that is not disabled can receive the same voltage, Vunsel, as the memory cells in the disable operation.

[0153] Step 1100 begins the process of applying a disable erase bias to a select gate transistor. The transistor is associated with a set of memory cells, and accessing the set of memory cells is disabled. Step 1101 includes applying Verase to the substrate to charge the channels of the NAND strings to ~Verase (approximate Verase). Step 1102 includes applying a control gate voltage Vsg_dis < Verase to the select gate transistor. The magnitude of the erase bias suitable for performing the disable operation can be determined from testing on a particular memory device. Step 1103 includes applying a control gate voltage Vunsel < Verase to the memory cells. Erasing the memory cells is not required in the disable operation of the select gate transistor. Optionally, the memory cells are at least partially erased during the disable operation.

[0154] Steps 1101 and 1102 can be simultaneous. Steps 1101 - 1103 can also be simultaneous.

[0155] Figure 11B associated with Figure 10A step 1003 of Figure 11A consistently depicts the process of performing a verification test for a select gate transistor. Step 1110 begins the verification test of the select gate transistor. Step 1111 includes applying Vverify to the select gate transistor. Step 1112 includes applying Vread to the memory cells. This provides the memory cells in a conductive state to allow sensing the Vth of the select gate transistor. Step 1113 includes a sensing circuit in the NAND string. Steps 1111 and 1112 can be simultaneous. Steps 1111 - 1113 can also be simultaneous.

[0156] The SGD transistor is an example of a first select gate transistor and the SGS transistor is an example of a second select gate transistor. Alternatively, the SGS transistor is an example of a first select gate transistor and the SGD transistor is an example of a second select gate transistor.

[0157] In one method, an erase bias is applied to the SGD and SGS transistors simultaneously. In another method, an erase bias is applied to the SGD and SGS transistors separately, for example using separate erase pulses.

[0158] As mentioned by Figure 8C the Vth distribution 812 of

[0159] Figure 12A associated with Figure 11A the process of Figure 7AAn exemplary voltage is applied to the NAND string 700n, wherein an erase bias is disabled applied to the SGD transistor 716 and the SGS transistor 701. For example, to apply an erase bias as a channel-to-gate bias, a control gate voltage Vsg_dis (e.g., 0-5V) is applied to the SGD transistor 716 and the SGS transistor 701, while an erase voltage Verase (e.g., 15-25V) is applied to the channel of the NAND string via the substrate. The memory cells including dummy memory cells 702 and 715 and data memory cells 703-714 receive a voltage Vunsel (e.g., 6-8V).

[0160] Figure 12B and Figure 11B The process consistently depicts the direction towards Figure 7A An exemplary voltage is applied to the NAND string 700n, wherein a verification voltage is applied to the SGD transistor 716 and the SGS transistor 701. In such... Figure 12A After applying an erase bias voltage to the SGD and SGS transistors, a verification test is performed to determine whether the erase bias voltage causes the Vth of the SGD and / or SGS transistors to increase above Vverify. Vverify is applied to the SGD transistor 716 and the SGS transistor 701, while a read pass voltage Vread (e.g., 8-10V) is applied to the memory cell. Vread provides the memory cell with a strongly conductive state, allowing the Vth of the SGD and SGS transistors to be sensed.

[0161] Figure 12C and Figure 11A The process consistently depicts the direction towards Figure 7A An exemplary voltage is applied to the NAND string 700n, wherein a disable erase bias is applied to the SGD transistor 716 but not to the SGS transistor 701. As mentioned, the SGD transistor can be disabled without disabling the SGS transistor, as in this example, or the SGS transistor can be disabled without disabling the SGD transistor. Vsg_dis is applied to the SGD transistor 716, while a voltage Vsg1 (e.g., 10-15V) is applied to the SGS transistor 701. Vsg1 > Vsg_dis.

[0162] In the option of disabling the SGS transistor but not the SGD transistor, Vsg_dis is applied to the SGS transistor 701, while the voltage Vsg1 is applied to the SGD transistor 716.

[0163] Figure 12D and Figure 11B The process consistently depicts the direction towards Figure 7AAn exemplary voltage is applied to the NAND string 700n, wherein a verification voltage is applied to the SGD transistor 716 but not to the SGS transistor 701. In such... Figure 12C After applying an erase bias voltage to the SGD transistor, a verification test is performed to determine whether the erase bias voltage causes the Vth of the SGD transistor to increase above Vverify. Vverify is applied to the SGD transistor 716, while a read pass voltage Vread (e.g., 8-10V) is applied to the memory cell and the SGD transistor 701.

[0164] In the option of disabling the SGS transistor but not the SGD transistor, after applying an erase bias to the SGS transistor, a verification test is performed to determine whether the erase bias causes the Vth of the SGS transistor to increase above Vverify. Vverify is applied to the SGS transistor 701, while Vread is applied to the memory cell and the SGD transistor 716.

[0165] Figure 13 Depicting in relation to Figure 11A and 11B The following are exemplary waveforms in a consistent operation. The vertical direction represents voltage, and the horizontal direction represents a common time scale. Three erase-verify iterations EV1-EV3 are depicted as examples, where the disable operation is completed after EV3. In general, one or more erase-verify iterations can be used to complete the disable operation. EV1-EV3 are examples of one or more consecutive erase-verify iterations in a disable operation.

[0166] Voltage signal 1300 represents the erase voltage Verase. This could be, for example, a voltage applied to the substrate and / or bit lines of the block. In the voltage signal, erase pulses 1301, 1302, and 1303 have amplitudes of Verase1, Verase2, and Verase3, respectively. Each erase pulse charges the channel of the NAND string in the block. The erase pulse can have an initial amplitude of, for example, 15-25V and increases with each erase-verify iteration.

[0167] Voltage signal 1310 represents the voltage Vmem applied to the memory cell. During erase pulses 1301, 1302, and 1303, as depicted by lines 1311, 1313, and 1315 respectively, Vmem is set to Vunsel. During the time interval between erase pulses, as depicted by lines 1312, 1314, and 1316, Vmem is set to Vread to allow sensing of the SGD transistor in this example.

[0168] Voltage signal 1320 represents the voltage Vsg applied to the select-gate transistor undergoing a disabled erase operation. During erase pulses 1301, 1302, and 1303, as depicted by lines 1321, 1323, and 1325, respectively, Vsg is set to Vsg_dis. During the time interval between erase pulses, as depicted by lines 1322, 1324, and 1326, Vsg is set to Vverify to perform a verification test on the select-gate transistor undergoing the disabled erase operation.

[0169] Voltage signal 1330 represents the voltage Vsg applied to the select-gate transistor that has not undergone a disabled erase operation. During erase pulses 1301, 1302, and 1303, as depicted by lines 1331, 1333, and 1335, Vsg is set to Vsg1. During the time interval between erase pulses, during verification tests performed on the select-gate transistor that has undergone a disabled erase operation, as depicted by lines 1332, 1334, and 1336, Vsg is set to Vread.

[0170] Voltage signal 1340 represents the voltage Vbl of the bit line. During erase pulses 1301, 1302, and 1303, as depicted by graphs 1341, 1343, and 1345 respectively, Vbl is set to float. During the time interval between erase pulses, as depicted by graphs 1342, 1344, and 1346, Vbl is set to a sense voltage such as 0.5V to sense the current in the NAND string.

[0171] When disabling multiple blocks simultaneously, the described voltage signal can be applied to each block concurrently. For example, in Figure 4 On the memory die 400, a disable operation can be performed simultaneously on each of blocks B0-0 to B0-3 and B0-4 to B0-7. When a disable operation is performed simultaneously on a single block of multiple blocks, the described voltage signal can be applied to the single block. For example, in Figure 4 A disable operation can be performed on a single block among blocks B0-0 to B0-3 and B0-4 to B0-7 on the memory die 400. When a disable operation is performed on a single sub-block of a block, the described voltage signal can be applied to the single sub-block. For example, it can be... Figure 7A A disable operation is performed on one of the sub-blocks SB0-SB3 of block BLK0. Because separate Vsgd can be applied to each sub-block, the SGD transistor of the sub-block undergoing the disable operation can receive voltage signal 1320, while the SGD transistors of the remaining sub-blocks of the block that are not disabled can have floating control gate voltages consistent with voltage signal 1340.

[0172] Therefore, it can be understood that in one implementation, the device includes: control circuitry configured to connect to a plurality of memory cells arranged in a NAND string, each NAND string including a first end and a second end and a select gate transistor at the first end of the NAND string; and the circuitry is configured to perform an operation to prevent access to the plurality of memory cells, wherein, in order to perform the operation, the control circuitry is configured to apply an erase bias voltage to the select gate transistor at the first end of the NAND string, and in response to the erase bias voltage, determine whether the threshold voltage of the select gate transistor at the first end of the NAND string increases to be higher than a verification voltage.

[0173] In another implementation, the method includes: applying an erase bias voltage to a first select gate transistor in the NAND string during one or more erase-verify iterations of the operation; and determining, in response to the erase bias voltage, whether the threshold voltage of the first select gate transistor has increased to above a verification voltage during one or more erase-verify iterations.

[0174] In another implementation, the device includes: control circuitry configured to be connected to a plurality of memory cells arranged in a NAND string, the NAND string including a select-gate transistor; and a memory interface connected to circuitry configured to issue commands via the memory interface to perform an operation that irreversibly increases the threshold voltage of the select-gate transistor to a level above a verification voltage, wherein the operation applies a channel-to-gate voltage to the select-gate transistor.

[0175] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations can be made in light of the above teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and with various modifications as suited to the particular intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A memory device, comprising: A control circuit is configured to be connected to a plurality of memory cells arranged in a NAND string, each NAND string including a first end and a second end and a select gate transistor at the first end of the NAND string, and the control circuit is configured to: An operation to prevent access to the plurality of memory cells is performed, wherein, in order to perform the operation, the control circuit is configured to apply a strong erase bias voltage to the select gate transistor at a first end of the NAND string, and in response to the strong erase bias voltage, determine whether the threshold voltage of the select gate transistor at the first end of the NAND string has increased to a level higher than a verification voltage. The verification voltage is greater than the highest programming threshold voltage of the plurality of memory cells.

2. The memory device of claim 1, wherein: Determining whether the threshold voltage of the select gate transistor at the first end of the NAND string increases to be higher than the verification voltage in response to the strong erase bias includes determining whether a minimum number of select gate transistors at the first end of the NAND string have a threshold voltage higher than the verification voltage.

3. The memory device of claim 1, wherein: The application of the strong erase bias and the determination of whether the threshold voltage of the select gate transistor at the first end of the NAND string increases above the verification voltage in response to the strong erase bias are performed in one or more erase-verify iterations of the operation.

4. The memory device of claim 1, wherein: Each NAND string includes a select-gate transistor at a second end of the NAND string; and The control circuit is configured to apply a strong erase bias to the select gate transistor at the second end of the NAND string during the operation.

5. The memory device of claim 1, wherein: In order to apply the strong erase bias voltage to the select gate transistor at the first end of the NAND string, the control circuit is configured to charge the channel of the NAND string to the erase voltage while simultaneously applying a control gate voltage to the select gate transistor at the first end of the NAND string; and The erase voltage exceeds the control gate voltage by at least 15V.

6. The memory device of claim 1, wherein: The first end of the NAND string is the drain end of the NAND string.

7. The memory device of claim 1, wherein: The first end of the NAND string is the source end of the NAND string.

8. The memory device of claim 1, wherein the control circuitry is configured to: The strong erase bias is simultaneously applied to the select gate transistor at the first end of the NAND string in multiple blocks; and Determining whether the threshold voltage of the select gate transistor at the first end of the NAND string increases to be higher than the verification voltage in response to the strong erase bias includes determining whether a minimum number of select gate transistors at the first end of the NAND string in a selected block of the plurality of blocks have a threshold voltage higher than the verification voltage.

9. The memory device of claim 8, wherein: The selected block is a user ROM block; and The remaining blocks among the plurality of blocks include user data blocks.

10. The memory device of claim 1, wherein: The control circuit is configured to simultaneously apply the strong erase bias to the select gate transistor at the first end of the NAND string in a single block; and Determining whether the threshold voltage of the select gate transistor at the first end of the NAND string increases to be higher than the verification voltage in response to the strong erase bias includes determining whether a minimum number of select gate transistors at the first end of the NAND string in the single block have a threshold voltage higher than the verification voltage.

11. The memory device of claim 1, wherein: The control circuit is configured to simultaneously apply the strong erase bias to the select gate transistor at the first end of the NAND string in a single sub-block within the block; and Determining whether the threshold voltage of the select gate transistor at the first end of the NAND string increases to be higher than the verification voltage in response to the strong erase bias includes determining whether a minimum number of select gate transistors at the first end of the NAND string in a single sub-block of the block have a threshold voltage higher than the verification voltage.

12. The memory device of claim 1, wherein: The operation irreversibly increases the threshold voltage of at least a minimum number of the selected gate transistors by at least 2V.

13. A method of operating a memory device, comprising: In one or more erase-verify iterations of the operation, a strong erase bias is applied to the first select gate transistor in the NAND string, and the application of the strong erase bias irreversibly increases the threshold voltage of the select gate transistor by at least 2V. as well as In response to the strong erase bias, determine whether the threshold voltage of the first selected gate transistor has increased to above the verification voltage during the one or more erase-verify iterations; and The verification voltage is greater than the highest programming threshold voltage of the memory cell.

14. The method of claim 13, further comprising: In one or more erase-verify iterations, a strong erase bias is applied to a second select gate transistor in the NAND string, wherein the first select gate transistor is located at a first end of the NAND string and the second select gate transistor is located at a second end of the NAND string.

15. A memory device, comprising: A control circuit is configured to be connected to a plurality of memory cells arranged in a NAND string, the NAND string including a select gate transistor; as well as A memory interface, connected to the control circuit, the control circuit being configured to issue a command via the memory interface to perform an operation that irreversibly increases the threshold voltage of the select gate transistor to a level higher than a verification voltage, wherein the operation applies a channel-to-gate voltage of at least 15V to the select gate transistor, and wherein the channel-to-gate voltage is a strong erase bias; and The verification voltage is greater than the highest programming threshold voltage of the plurality of memory cells.

16. The memory device of claim 15, wherein: The NAND strings extend vertically within the stack; and The selected gate transistor is located on top of the stack.

17. The memory device of claim 15, wherein: The NAND strings extend vertically within the stack; and The selected gate transistor is located at the bottom of the stack.

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