A method for manufacturing gate oxide of medium voltage MOS tube

Abstract

The present invention provides a method for manufacturing a medium-voltage MOS tube gate oxide, wherein a medium-voltage MOS tube active region is provided on a substrate; a low-voltage MOS tube active region and a high-voltage MOS tube active region are respectively provided on the substrate on both sides of the medium-voltage MOS tube active region; an oxide layer is provided on the high-voltage MOS tube active region; a hard mask layer is formed on the substrate to cover the oxide layer of the low-voltage MOS tube active region, the medium-voltage MOS tube active region and the high-voltage MOS tube active region; the medium-voltage MOS tube active region is photolithographically opened; according to the region of the medium-voltage MOS tube active region opened by photolithography, the medium-voltage MOS tube active region is etched to form a groove; then the photoresist after photolithography is removed; a gate oxide layer is formed in the groove; the ratio of the thickness of the gate oxide layer to the depth of the groove is 0.54:1; then the hard mask layer is removed. The present invention forms a groove in the medium-voltage oxide region so that the height difference between the gate oxide region after high-temperature oxidation and the surrounding region is close to zero, thereby improving the uniformity of the metal gate height, improving the stability of the metal gate and improving the product yield.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for manufacturing gate oxide of a medium-voltage MOS tube. Background Art

[0002] As device size continues to decrease, for medium and high voltage semiconductor devices of 28 nanometers and below, high-K gate dielectric-metal gate process has become the development direction, and the uniformity of metal gate height is a key factor affecting product reliability and product yield. At present, some processes use the growth method of directly growing the gate oxide layer on the silicon substrate, which causes the height of the active area to be higher than the surrounding area. Such morphology will cause the metal gate in the active area to be lower during the chemical mechanical polishing process in the middle and later stages, or the metal gate in the large-sized graphic area will be polished, thereby damaging the product yield and product reliability.

[0003] Therefore, how to make the medium voltage gate oxide region flat with the surrounding area and thus improve the uniformity of the height of metal gates of different sizes becomes an urgent problem to be solved. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for manufacturing a medium voltage MOS tube gate oxide, which is used to solve the problem in the prior art that the medium voltage gate oxide region is highly inconsistent with the surrounding area, thereby affecting the product yield and reliability.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a medium voltage MOS transistor gate oxide, which comprises at least the following steps:

[0006] Step 1, providing a substrate, on which a medium-voltage MOS tube active region is provided; a low-voltage MOS tube active region and a high-voltage MOS tube active region are respectively provided on the substrate on both sides of the medium-voltage MOS tube active region; an oxide layer is provided on the high-voltage MOS tube active region; a hard mask layer is formed on the substrate to cover the oxide layers of the low-voltage MOS tube active region, the medium-voltage MOS tube active region and the high-voltage MOS tube active region;

[0007] Step 2: photolithography and opening the active area of ​​the medium voltage MOS tube;

[0008] Step 3, etching the medium voltage MOS tube active area to form a groove according to the area of ​​the medium voltage MOS tube active area opened by photolithography; then removing the photoresist after photolithography;

[0009] Step 4: forming a gate oxide layer in the trench; the ratio of the thickness of the gate oxide layer to the depth of the trench is 0.54:1; and then removing the hard mask layer.

[0010] Preferably, the low voltage MOS transistor active region, the medium voltage MOS transistor active region and the high voltage MOS transistor active region in step 1 are isolated by an STI region.

[0011] Preferably, the medium voltage MOS transistor active region in step 1 includes a medium voltage NMOS active region and a medium voltage PMOS active region, and the medium voltage NMOS active region and the medium voltage PMOS active region are isolated from each other by an STI region.

[0012] Preferably, the hard mask layer in step 1 is a silicon nitride film layer.

[0013] Preferably, in step one, the silicon nitride film layer is formed on the substrate by a high-temperature furnace tube growth method.

[0014] Preferably, the thickness of the silicon nitride film layer formed in step 1 is 200 angstroms.

[0015] Preferably, the method for forming the trench in step three comprises: firstly etching away the hard mask layer on the medium voltage MOS tube active area; and then etching the substrate of the medium voltage MOS tube active area to form the trench.

[0016] Preferably, in step three, a dry etching method is used to form a groove in the active area of ​​the medium voltage MOS tube.

[0017] Preferably, in step three, wet and dry etching are used to remove the photoresist.

[0018] Preferably, in step four, a high temperature furnace tube growth method is used to form the gate oxide layer in the trench.

[0019] As described above, the medium voltage MOS tube gate oxide manufacturing method of the present invention has the following beneficial effects: the present invention forms a groove in the medium oxygen region so that the height difference between the gate oxide region after high temperature oxidation and the surrounding area is close to zero, thereby improving the uniformity of the metal gate height, improving the stability of the metal gate and improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It shows a schematic diagram of a substrate structure provided with a medium voltage MOS tube active region in the present invention;

[0021] Figure 2 It shows a schematic diagram of the structure of opening the active area of ​​the medium voltage MOS tube by photolithography in the present invention;

[0022] Figure 3 It is a schematic diagram of the structure after the active area of ​​the medium voltage MOS tube is etched to form a groove in the present invention;

[0023] Figure 4 It is a schematic diagram of the structure after a gate oxide layer is formed in the trench in the present invention;

[0024] Figure 5 It is a flow chart of the method for manufacturing gate oxide of a medium voltage MOS tube of the present invention. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] See also Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0027] The present invention provides a method for manufacturing a medium voltage MOS tube gate oxide, such as Figure 5 As shown, Figure 5 The flowchart of the method for manufacturing the gate oxide of a medium voltage MOS tube of the present invention is shown, and the method at least comprises the following steps:

[0028] Step 1, providing a substrate, on which a medium-voltage MOS tube active region is provided; a low-voltage MOS tube active region and a high-voltage MOS tube active region are respectively provided on the substrate on both sides of the medium-voltage MOS tube active region; an oxide layer is provided on the high-voltage MOS tube active region; a hard mask layer is formed on the substrate to cover the oxide layers of the low-voltage MOS tube active region, the medium-voltage MOS tube active region and the high-voltage MOS tube active region;

[0029] like Figure 1 As shown, Figure 1 It shows a schematic diagram of the substrate structure with a medium-voltage MOS tube active region in the present invention. In step 1, a substrate 01 is provided, and a medium-voltage MOS tube active region (MVPMOS and MVNMOS) is provided on the substrate 01; low-voltage MOS tube active regions (LVPMOS and LVNMOS) and high-voltage MOS tube active regions (HVPMOS and HVNMOS) are respectively provided on the substrate 01 on both sides of the medium-voltage MOS tube active region; an oxide layer 08 is provided on the high-voltage MOS tube active region; a hard mask layer 05 is formed on the substrate 01 to cover the oxide layer 08 of the low-voltage MOS tube active region, the medium-voltage MOS tube active region, and the high-voltage MOS tube active region;

[0030] In the present invention, further, the low voltage MOS transistor active region, the medium voltage MOS transistor active region and the high voltage MOS transistor active region in step 1 of this embodiment are isolated by an STI region.

[0031] In the present invention, the medium voltage MOS transistor active region in step 1 of this embodiment includes a medium voltage NMOS active region 04 and a medium voltage PMOS active region 03, and the medium voltage NMOS active region 04 and the medium voltage PMOS active region 03 are isolated from each other by an STI region.

[0032] In the present invention, further, the hard mask layer 05 in step 1 of this embodiment is a silicon nitride film layer.

[0033] The present invention further comprises that in step 1 of this embodiment, a high-temperature furnace tube growth method is used to form the silicon nitride film layer on the substrate 01.

[0034] According to the present invention, the thickness of the silicon nitride film layer formed in step 1 of this embodiment is 200 angstroms.

[0035] Step 2: Photolithography and opening of the medium voltage MOS tube active area; Figure 2 As shown, Figure 2 The structure schematic diagram of the photolithography opening of the active area of ​​the medium voltage MOS tube in the present invention is shown. In the second step, a photoresist layer is first formed on the hard mask layer, and then exposed and developed to form a Figure 2 The photoresist pattern 06 shown exposes the hard mask layer on the upper surface of the active area of ​​the medium voltage MOS tube.

[0036] Step 3: etching the medium voltage MOS tube active area to form a groove according to the area of ​​the medium voltage MOS tube active area opened by photolithography; then removing the photoresist after photolithography; Figure 3 As shown, Figure 3 The structure schematic diagram after the medium voltage MOS tube active area is etched to form a groove in the present invention. In step three, the medium voltage MOS tube active area is etched to form a groove according to the area of ​​the medium voltage MOS tube active area (medium voltage NMOS active area 04 and medium voltage PMOS active area 03) opened by photolithography; then the photoresist after photolithography is removed to expose the hard mask layer 05.

[0037] The present invention further comprises the method of forming the groove in step three of this embodiment: firstly etching away the hard mask layer on the active area of ​​the medium voltage MOS tube; then etching the substrate of the active area of ​​the medium voltage MOS tube (the active area is part of the substrate) to form the groove.

[0038] According to the present invention, in step three of this embodiment, a dry etching method is used to form a groove in the active area of ​​the medium voltage MOS tube.

[0039] The present invention further adopts wet and dry etching to remove the photoresist in step three of this embodiment.

[0040] Step 4: forming a gate oxide layer in the trench; the ratio of the thickness of the gate oxide layer to the depth of the trench is 0.54:1; and then removing the hard mask layer. Figure 4 As shown, Figure 4 The schematic diagram of the structure after the gate oxide layer is formed in the trench in the present invention is shown. In step 4, a gate oxide layer 07 is formed in the trench; the ratio of the thickness of the gate oxide layer to the depth of the trench is 0.54:1; then the hard mask layer is removed, Figure 4 The height difference between the gate oxide layer 07 formed in the trench and the oxide layer 08 on the active area of ​​the high-voltage MOS tube is close to zero, that is, the height difference between the two is very small.

[0041] In the present invention, further, in step 4 of this embodiment, a high temperature furnace tube growth method is used to form the gate oxide layer 07 in the trench.

[0042] In summary, the present invention forms a groove in the middle oxygen region, so that the height difference between the gate oxide region after high temperature oxidation and the surrounding region is close to zero, thereby improving the uniformity of the metal gate height, improving the stability of the metal gate and improving the product yield. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0043] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a medium voltage MOS tube gate oxide, characterized in that: At least the following steps are included: Step 1, providing a substrate, on which a medium-voltage MOS tube active region is provided; a low-voltage MOS tube active region and a high-voltage MOS tube active region are respectively provided on the substrate on both sides of the medium-voltage MOS tube active region; an oxide layer is provided on the high-voltage MOS tube active region; a hard mask layer is formed on the substrate to cover the oxide layers of the low-voltage MOS tube active region, the medium-voltage MOS tube active region and the high-voltage MOS tube active region; Step 2: photolithography and opening the active area of ​​the medium voltage MOS tube; Step 3, etching the medium voltage MOS transistor active area to form a groove according to the area of ​​the medium voltage MOS transistor active area opened by photolithography; Then remove the photoresist after photolithography; Step 4: forming a gate oxide layer in the trench; the ratio of the thickness of the gate oxide layer to the depth of the trench is 0.54:1; The hard mask layer is then removed.

2. The method for manufacturing a medium voltage MOS transistor gate oxide according to claim 1, characterized in that: The low voltage MOS tube active region, the medium voltage MOS tube active region and the high voltage MOS tube active region in step 1 are isolated by an STI region.

3. The method for manufacturing a medium voltage MOS transistor gate oxide according to claim 1, characterized in that: The medium voltage MOS transistor active region in step 1 includes a medium voltage NMOS active region and a medium voltage PMOS active region, and the medium voltage NMOS active region and the medium voltage PMOS active region are isolated from each other by an STI region.

4. The method for manufacturing a medium voltage MOS transistor gate oxide according to claim 1, characterized in that: The hard mask layer in step 1 is a silicon nitride film layer.

5. The method for manufacturing a medium voltage MOS transistor gate oxide according to claim 4, characterized in that: In step 1, the silicon nitride film layer is formed on the substrate by a high-temperature furnace tube growth method.

6. The method for manufacturing a medium voltage MOS transistor gate oxide according to claim 4, characterized in that: The thickness of the silicon nitride film layer formed in step 1 is 200 angstroms.

7. The method for manufacturing a medium voltage MOS transistor gate oxide according to claim 1, characterized in that: The method for forming the trench in step three includes: firstly etching away the hard mask layer on the active area of ​​the medium voltage MOS tube; and then etching the substrate of the active area of ​​the medium voltage MOS tube to form the trench.

8. The method for manufacturing a medium voltage MOS transistor gate oxide according to claim 1, characterized in that: In step three, a dry etching method is used to form a groove in the active area of ​​the medium voltage MOS tube.

9. The method for manufacturing a medium voltage MOS transistor gate oxide according to claim 1, characterized in that: In step three, wet and dry etching are used to remove the photoresist.

10. The method for manufacturing a medium voltage MOS transistor gate oxide according to claim 1, characterized in that: Step 4: forming the gate oxide layer in the groove by a high temperature furnace tube growth method.

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