Semiconductor structure and method for forming the same

Abstract

The embodiment of the present invention provides a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: providing a substrate, wherein the substrate has a groove, wherein the sidewall of the groove includes a first sub-sidewall and a second sub-sidewall extending upward from the bottom of the groove, wherein the first sub-sidewall is located between the second sub-sidewall and the bottom of the groove; blowing a first precursor to the surface of the substrate at a flow rate lower than a preset value so that the first precursor adheres to the top surface of the substrate and the second sub-sidewall; blowing a second precursor to the surface of the substrate so that the second precursor reacts with the first precursor to generate a dielectric layer; alternately blowing the first precursor and the second precursor to the surface of the substrate to form a multi-layer dielectric layer until the area surrounded by the second sub-sidewall is filled, and the area surrounded by the first sub-sidewall, the dielectric layer and the bottom of the groove forms a gap. The present invention can block the top opening of the groove and form a gap.

Description

Technical Field

[0001] The embodiments of the present invention relate to the semiconductor field, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous advancement of semiconductor technology, the resistance and capacitance delay (RC delay) phenomenon that affects the transmission speed of circuits has gradually become prominent. Currently, the parasitic resistance R can be reduced by adjusting the conductor connection material, but due to process limitations, the parasitic capacitance C cannot be reduced by changing the conductor connection geometry.

[0003] Since the parasitic capacitance C is proportional to the dielectric constant k of the insulating medium in the circuit, if low-k materials are used as the insulating dielectric layer, the parasitic effect in the circuit will be greatly reduced, thereby increasing the signal transmission speed. The dielectric constant of air is close to 1. If air is introduced into the dielectric layer, the dielectric constant k of the dielectric layer can be greatly reduced. Summary of the invention

[0004] The embodiments of the present invention provide a semiconductor structure and a method for forming the same, which can introduce an air gap into a dielectric layer and reduce the dielectric constant k of the dielectric layer.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has a groove, and the sidewall of the groove includes a first sub-sidewall and a second sub-sidewall extending upward from the bottom of the groove, and the first sub-sidewall is located between the second sub-sidewall and the bottom of the groove; blowing a first precursor to the surface of the substrate at a flow rate lower than a preset value so that the first precursor adheres to the top surface of the substrate and the second sub-sidewall; blowing a second precursor to the surface of the substrate so that the second precursor reacts with the first precursor to generate a dielectric layer; and alternately blowing the first precursor and the second precursor to the surface of the substrate to form multiple layers of the dielectric layer until the top opening of the groove is blocked, and the area enclosed by the first sub-sidewall, the dielectric layer and the bottom of the groove constitutes a gap.

[0006] In addition, in the process of forming the plurality of dielectric layers, the first precursor is blown at a flow rate that increases layer by layer. Since the top surface area of ​​the dielectric layer increases continuously in the process of forming the dielectric layer layer by layer, the flow rate of the first precursor needs to be increased layer by layer to ensure that the dielectric layer is continuously stacked in the area surrounded by the second sub-side wall, thereby blocking the top opening of the groove.

[0007] In addition, the substrate surface has polar groups; in the process step of blowing the first precursor, the polar groups react with the first precursor to fix the functional groups of the first precursor. Since the substrate surface has polar groups that can react with the first precursor, in the blowing direction of the first precursor, the first precursor will adhere to the top surface of the substrate and the second sub-side wall that it contacts first, thereby preventing the first precursor from adhering to the first sub-side wall or the bottom of the groove, ensuring that the area surrounded by the first sub-side wall has a lower dielectric constant.

[0008] In addition, the surface of the dielectric layer has polar groups; in the process step of blowing the first precursor, the polar groups react with the first precursor to fix the functional groups of the first precursor. Since the surface of the dielectric layer has polar groups that can fix the first precursor, when the first precursor is blown alternately, the first precursor will preferentially adhere to the surface of the dielectric layer with polar groups, thereby preventing the first precursor from being deposited on the first sub-sidewall or the bottom of the groove.

[0009] Additionally, the polar group includes a hydroxyl group.

[0010] In addition, the material of the dielectric layer includes silicon dioxide, and at least one of the first precursor or the second precursor includes an organic substance containing a silanol group.

[0011] In addition, the silanol group-containing organic substance includes a 3-tert-butylsilanol group.

[0012] In addition, the first precursor includes a metal organic compound with a catalytic effect. Since the 3-tert-butylsilanol group can selectively bind to the metal organic compound, the use of the metal organic compound as the first precursor can ensure that the 3-tert-butylsilanol group as the second precursor is only effectively combined with the first precursor, that is, the dielectric layer is only formed at the attachment position of the first precursor, avoiding the second precursor from being deposited in the area surrounded by the first sub-sidewall, so that the gap area surrounded by the first sub-sidewall has a low K dielectric constant; in addition, the metal organic compound has a catalytic effect, which can accelerate the formation of the dielectric layer and shorten the process cycle.

[0013] In addition, the metal material in the metal organic compound includes at least one of aluminum, lanthanum, zirconium or hafnium.

[0014] In addition, the reaction temperature of the first precursor and the second precursor to form the dielectric layer is 225° C. to 250° C.

[0015] In addition, in a direction perpendicular to the surface of the substrate, the ratio of the height of the first sub-sidewall to the height of the second sub-sidewall is 1 to 9. By controlling the flow rate of the first precursor, the thickness ratio of the first sub-sidewall to the second sub-sidewall is controlled, thereby controlling the dielectric constant of the groove when it is used as a dielectric layer.

[0016] An embodiment of the present invention also provides a semiconductor structure, comprising: a substrate and a groove located in the substrate, the groove sidewall comprising a first sub-sidewall and a second sub-sidewall extending upward from the bottom of the groove, the first sub-sidewall being located between the second sub-sidewall and the bottom of the groove; a multi-layer dielectric layer, the multi-layer dielectric layer blocking the top opening of the groove and being stacked in sequence in the direction of the groove sidewall toward the central axis of the groove; a gap, the gap being composed of the area enclosed by the first sub-sidewall, the bottom of the groove and the multi-layer dielectric layer.

[0017] In addition, the substrate has conductive structures located on two opposite sides of the groove.

[0018] In addition, the multi-layer dielectric layer contains a metal material, and the metal material includes at least one of aluminum, lanthanum, zirconium or hafnium.

[0019] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0020] In the above technical solution, the first precursor is blown at a flow rate lower than a preset value, so that the first precursor only adheres to the top surface of the substrate and the second sub-side wall. In this way, when a multi-layer dielectric layer is formed to block the top opening of the groove, the area enclosed by the first sub-side wall, the bottom of the groove and the multi-layer dielectric layer can form a gap. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0022] Figure 1 , Figure 2 , Figure 4 as well as Figures 11 to 13 A schematic structural diagram corresponding to each step of the method for forming a semiconductor structure provided by an embodiment of the present invention;

[0023] Figure 3 as well as Figures 5 to 10 A schematic diagram of the chemical reaction corresponding to the method for forming a semiconductor structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0025] Figure 1 , Figure 2 , Figure 4 as well as Figures 10 to 12 A schematic structural diagram corresponding to each step of the method for forming a semiconductor structure provided by an embodiment of the present invention; Figure 3 as well as Figures 5 to 9 A schematic diagram of the chemical reaction corresponding to the method for forming a semiconductor structure provided in an embodiment of the present invention.

[0026] refer to Figure 1 A substrate 11 is provided, wherein the substrate 11 has a groove 111 therein, wherein the sidewall of the groove 111 includes a first sub-sidewall A1 and a second sub-sidewall A2 extending upward from the bottom of the groove 111 , and the first sub-sidewall A1 is located between the second sub-sidewall A2 and the bottom of the groove 111 .

[0027] In this embodiment, the substrate 11 has conductive structures 112 located on opposite sides of the groove 111. The conductive structures 112 may be components such as wires and conductive plugs. When the conductive structures 112 are powered on, parasitic capacitance is generated between adjacent conductive structures 112. The magnitude of the parasitic capacitance depends on the dielectric constant k of the dielectric material between the adjacent conductive structures 112. The lower the dielectric constant k, the smaller the parasitic capacitance.

[0028] In this embodiment, the substrate 11 further includes a protective layer 113 located on the sidewall of the conductive structure 112 and an isolation layer 114 located on the top surface of the conductive structure 112. The protective layer 113 is usually a residue left when etching to form the groove 11, so as to prevent the etchant from damaging the conductive structure 112. The area surrounded by the protective layer 113 constitutes the groove 111; the isolation layer 114 mainly acts as an etching stop layer to prevent the etchant from penetrating the isolation layer 114 and damaging the conductive structure 112. The material of the protective layer 113 and the material of the isolation layer 114 can be the same or different.

[0029] It should be noted that this document does not limit the formation method, material, and location of the protective layer 113 and the isolation layer 114. In fact, in other embodiments, there may be no protective layer and isolation layer, that is, the top surface and at least part of the sidewall surface of the conductive structure are exposed.

[0030] In this embodiment, the area surrounded by the second sub-side wall A2 is used to fill the subsequently formed dielectric layer, thereby sealing the top opening of the groove 111, and the area surrounded by the first sub-side wall A1 is used to form a gap, thereby reducing the dielectric constant k of the dielectric layer between adjacent conductive structures 112.

[0031] In this embodiment, in the direction perpendicular to the surface of the substrate 11, the height ratio of the first sub-side wall A1 to the second sub-side wall A2 is 1 to 9, for example, 3, 5 or 7. The thickness ratio is determined by the staff before blowing the first precursor, and the thickness ratio is set to ensure that the dielectric constant k of the dielectric layer between adjacent conductive structures 112 is low, and to consider the process feasibility and structural stability.

[0032] Process feasibility means that during the process of blowing the first precursor, it cannot be guaranteed that the first precursor is only coated on the top surface of the substrate 11, that is, the first precursor will adhere to part of the side wall of the groove 111. Therefore, when setting the thickness ratio, it is necessary to consider the minimum adhesion depth of the first precursor so as to set a reasonable and effective thickness ratio; in addition, structural stability refers to the bearing capacity of the dielectric layer. Since other film layers or structures may be formed on the substrate 11 in the future, in order to avoid the dielectric layer from collapsing due to inability to withstand pressure, thereby affecting the dielectric constant k of the dielectric layer between adjacent conductive structures 112, the dielectric layer needs to have a certain thickness in the direction extending upward from the bottom of the groove 111 so as to meet the preset bearing capacity requirements.

[0033] It should be noted that the technical solution provided in this article is usually applied to grooves 111 with an aspect ratio greater than 1. When the aspect ratio of the groove 111 is less than 1, the blown precursor easily contacts the bottom of the groove 111, resulting in failure to form an ideal gap.

[0034] refer to Figure 2 , blowing the first precursor 12 toward the surface of the substrate 11 at a flow rate lower than a preset value, so that the first precursor 12 adheres to the top surface of the substrate 11 and the second sub-side wall A2.

[0035] The preset value is an ideal value. When the first precursor 12 is blown onto the surface of the substrate 11 at a flow rate greater than or equal to the preset value, the first precursor 12 can cover the top surface of the substrate 11, the second sub-side wall A2, the first sub-side wall A1, and the bottom surface of the groove 111. The first precursor 12 sequentially contacts the top surface of the substrate 11, the second sub-side wall A2, the first sub-side wall A1, and the bottom surface of the groove 111 during the blowing process.

[0036] When the first precursor 12 is blown toward the surface of the substrate 11 at a flow rate lower than a preset value, due to the insufficient amount of the first precursor 12 per unit time, the first precursor 12 will preferentially adhere to the surface of the substrate 11 that it contacts first, i.e., the top surface of the substrate 11 and the second sub-side wall A2.

[0037] refer to Figure 3 , the first precursor 12 (reference Figure 2 ) on the substrate 11 (reference Figure 2 )The first reaction A occurs on the surface.

[0038] In this embodiment, the first precursor 12 includes a metal organic compound having a catalytic effect, specifically trimethylaluminum (CH 3 ) 3 The catalytic effect of the first precursor 12 is mainly used to accelerate the reaction between the first precursor 12 and the second precursor blown subsequently to generate the dielectric layer material.

[0039] The metal material in the metal organic compound includes at least one of aluminum, lanthanum, zirconium or hafnium.

[0040] In this embodiment, the surface of the substrate 11 has polar groups. During the blowing of the first precursor 12, the polar groups react with the first precursor 12 to fix the functional groups of the first precursor 12. Specifically, the surface of the substrate 11 has hydroxyl groups -OH. During the blowing of trimethylaluminum, the methyl -CH 3 It will react with the hydrogen atom -H in the hydroxyl group to produce methane CH 4 , the remaining -CH 3 Al acts as a functional group to connect with the oxygen ions in the original hydroxyl group, providing a catalytic effect for the subsequent dielectric layer reaction.

[0041] Since the surface of the substrate 11 has polar groups that can react with the first precursor 12, in the blowing direction of the first precursor 12, the first precursor 12 will adhere to the top surface of the substrate 11 and the second sub-side wall A2 that are first contacted, thereby avoiding the first precursor 12 from adhering to the first sub-side wall A1 or the bottom of the groove 111, ensuring that the area surrounded by the first sub-side wall A1 has a lower dielectric constant.

[0042] In this embodiment, the polar groups on the surface of the substrate 11 are naturally generated when the substrate 11 is exposed to air or water vapor; in other embodiments, the polar groups may also be formed through certain process steps. In addition, the polar groups are not limited to hydroxyl groups, but may be any polar groups that can react with the first precursor 12 and fix its functional groups; further, the substance attached to the surface of the substrate may not be a polar group, but may be any chemical substance that can react with the first precursor 12 and retain its functional groups.

[0043] In this embodiment, the state of the first precursor 12 is gaseous; in other embodiments, the state of the first precursor may also be liquid. Compared with the gaseous state, the liquid has a smaller intermolecular distance and a more obvious viscosity of fluid movement. Therefore, the liquid first precursor is more likely to adhere to the surface of the substrate after contacting the surface of the substrate, which is beneficial to ensure that the first precursor is only attached to the top surface of the substrate and the second sub-sidewall, so that the area enclosed by the first sub-sidewall has a lower dielectric constant k.

[0044] refer to Figure 4 , blowing the second precursor 13 to the surface of the substrate 11 so that the second precursor 13 and the second precursor 12 (reference Figure 2 ) react to form a dielectric layer 14.

[0045] In this embodiment, the material of the dielectric layer 14 is silicon dioxide, and the silicon source of silicon dioxide includes a silanol group, that is, at least one of the first precursor 12 or the second precursor 13 includes an organic matter containing a silanol group. Silicon dioxide has a relatively low dielectric constant k, and the use of silicon dioxide as the material of the dielectric layer 14 is conducive to ensuring that the area surrounded by the second sub-side wall A2 (the dielectric layer 14 fills the area) has a relatively low dielectric constant k.

[0046] In this embodiment, the material of the second precursor 13 includes 3-tert-butylsilanol group. 3-tert-butylsilanol group can selectively combine with metal organic matter. Using metal organic matter as the first precursor 12 and 3-tert-butylsilanol group as the second precursor 13 can ensure that the second precursor 13 is effectively combined with the first precursor 12 only, that is, the dielectric layer 14 is formed only at the attachment position of the first precursor 12, avoiding the second precursor 13 from attaching to the first sub-side wall A1 or the bottom surface of the groove 111, so that the area surrounded by the first sub-side wall A1 has a lower dielectric constant k.

[0047] refer to Figures 5 to 10 , the first precursor 12 (reference Figure 2 ) and the second precursor 13 (reference Figure 4 ) reaction generates a dielectric layer 14 (reference Figure 4 ), the reaction process mainly includes the second reaction B, the third reaction C, the fourth reaction D, the fifth reaction E, the sixth reaction F and the seventh reaction G.

[0048] The second reaction B and the third reaction C are reactions between the 3-tert-butylsilanol group as a chain macromolecule and the surface material of the substrate 11. The surface material of the substrate 11 will change as the reaction proceeds. The fourth reaction D is a polymerization reaction. The fifth reaction E and the sixth reaction F generate two parallel intermediate compounds. The seventh reaction G generates the final product, silicon dioxide.

[0049] The present application forms a silicon dioxide film layer through the reaction between chain macromolecules, which greatly improves the silicon dioxide film forming efficiency. The silicon dioxide film forming efficiency in the present application is 50 to 100 times that of the silicon dioxide film forming efficiency of the ordinary atomic layer deposition process.

[0050] In this embodiment, the reaction temperature of the first precursor 12 and the second precursor 13 to form the dielectric layer 14 is 225° C. to 250° C., for example, 230° C., 237° C. or 245° C. At this reaction temperature, the first precursor 12 and the second precursor 13 have a higher reaction rate, which is conducive to shortening the process cycle.

[0051] In this embodiment, after forming a dielectric layer 14, a cleaning process is used to remove the excess first precursor 12, the second precursor 13, and various intermediate products generated by the reaction. This prevents the excess unreacted precursors and reaction intermediate products from affecting the formation of the subsequent dielectric layer 14, and avoids affecting the performance parameters of the finally formed multi-layer dielectric layer 14, including the dielectric constant k and the load-bearing capacity.

[0052] In this embodiment, the reaction temperature in the entire process flow is 225° C. to 250° C. from the start of blowing the first precursor 12 to the reaction to form the dielectric layer 14. This is beneficial to improving the reaction rate of the chemical reaction in the process flow, and is beneficial to volatilizing the precursor and the intermediate product into a gaseous state or maintaining a gaseous state, thereby preventing the liquid precursor and the intermediate product from being deposited on the surface of the substrate 11 and affecting the progress of the chemical reaction; in addition, the gaseous precursor and the intermediate product can be effectively removed by passing an inert gas.

[0053] The reaction temperature in the process flow can be adjusted according to the actual materials involved in the reaction and the intermediate products generated by the reaction to achieve the preset purpose.

[0054] refer to Fig.11 and Fig.12 , alternately blowing the first precursor 12 and the second precursor 13 onto the surface of the substrate 11 to form a multi-layer dielectric layer 14 until the top opening of the groove 111 is blocked, and the first sub-side wall A1 (reference Figure 4 ) and the area surrounded by the bottom of the groove 111 and the multi-layer dielectric layer 14 form a gap.

[0055] In this embodiment, the surface of the dielectric layer 14 has polar groups, and in the process of blowing the first precursor 12, the polar groups react with the first precursor 12 to fix the functional groups of the first precursor 12. Since the surface of the dielectric layer 14 has polar groups that can fix the first precursor 12, when the first precursor 12 is blown alternately, the first precursor 12 will adhere to the surface that is first contacted, that is, the top surface and the side wall surface of the dielectric layer 14, thereby preventing the first precursor 12 from adhering to the first sub-side wall A1 or the bottom of the groove 111.

[0056] Accordingly, the polar groups on the surface of the dielectric layer 14 may be naturally generated when exposed to air or water vapor, or may be formed by processing; in addition, the surface of the dielectric layer 14 may also have other substances besides polar groups to fix the functional groups of the first precursor 12 .

[0057] In this embodiment, the first precursor 12 is blown at a gradually increasing flow rate during the process of forming the multi-layer dielectric layer 14. Since the surface area of ​​the dielectric layer 14 gradually increases during the process of forming the multi-layer dielectric layer 14 with the same thickness, the first precursor 12 needs to be blown at a gradually increasing flow rate so that the first precursor 12 can adhere to the side wall of the dielectric layer 14, thereby sealing the top opening of the groove 111.

[0058] In this embodiment, the dielectric layer 14 formed later covers the entire side wall surface of the dielectric layer 14 formed earlier, so that the finally formed multi-layer dielectric layer 14 fills the area surrounded by the second sub-side wall A2. This structure has high structural stability. When subjected to a force from the conductive structure toward the groove 111, the multi-layer dielectric layer 14 will not break due to stress concentration.

[0059] In other embodiments, reference Fig.13 The dielectric layer 24 formed later covers part of the sidewall surface of the dielectric layer 24 formed earlier. In this way, in the process of forming the dielectric layer 24 layer by layer, the first precursor can be blown according to the same flow parameter, which is conducive to reducing the difficulty of the process.

[0060] In this embodiment, the first precursor is blown at a flow rate lower than a preset value, so that the first precursor only adheres to the top surface of the substrate and the second sub-side wall. In this way, when a multi-layer dielectric layer is formed to block the top opening of the groove, the area enclosed by the first sub-side wall, the bottom of the groove and the multi-layer dielectric layer can form a gap.

[0061] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, which can be manufactured using the above-mentioned method for forming a semiconductor structure.

[0062] refer to Fig.12 The semiconductor structure includes: a substrate 11 and a groove 111 located in the substrate 11, the groove 111 includes a first sub-sidewall and a second sub-sidewall extending upward from the bottom of the groove 111, and the first sub-sidewall is located between the second sub-sidewall and the bottom of the groove 111; a multi-layer dielectric layer 14, the multi-layer dielectric layer 14 blocks the top opening of the groove 111, and is stacked in sequence in the direction of the side wall of the groove 111 toward the central axis of the groove 111; a gap, the gap is composed of the area surrounded by the first sub-sidewall, the bottom of the groove 111 and the multi-layer dielectric layer 14.

[0063] In this embodiment, the substrate 11 has conductive structures 112 located on two opposite sides of the groove 111 .

[0064] In this embodiment, the multi-layer dielectric layer 14 includes a metal material, and the metal material includes at least one of aluminum, lanthanum, zirconium or hafnium. The metal material will not affect the dielectric effect of the dielectric layer 14.

[0065] In this embodiment, a new semiconductor structure is provided, which has a multilayer dielectric layer that blocks the top opening of the groove and a gap surrounded by the first sub-side wall, the bottom of the groove and the multilayer dielectric layer. When the gap is introduced into the dielectric layer, the dielectric layer has a lower dielectric constant k.

[0066] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a groove, wherein the sidewall of the groove comprises a first sub-sidewall and a second sub-sidewall extending upward from the bottom of the groove, wherein the first sub-sidewall is located between the second sub-sidewall and the bottom of the groove; Blowing a first precursor toward the surface of the substrate at a flow rate lower than a preset value, so that the first precursor adheres to the top surface of the substrate and the second sub-sidewall; Blowing a second precursor toward the surface of the substrate so that the second precursor reacts with the first precursor to generate a dielectric layer; The first precursor and the second precursor are alternately blown toward the substrate surface to form multiple layers of the dielectric layer until the top opening of the groove is blocked, and the area enclosed by the first sub-side wall, the dielectric layer and the bottom of the groove forms a gap.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the process of forming the plurality of dielectric layers, the first precursor is blown at a flow rate that increases layer by layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The substrate surface has polar groups; in the process step of blowing the first precursor, the polar groups react with the first precursor to fix the functional groups of the first precursor, and the polar groups include hydroxyl groups.

4. The method for forming a semiconductor structure according to claim 1, wherein: The surface of the dielectric layer has polar groups; in the process step of blowing the first precursor, the polar groups react with the first precursor to fix the functional groups of the first precursor, and the polar groups include hydroxyl groups.

5. The method for forming a semiconductor structure according to claim 1, wherein: The material of the dielectric layer includes silicon dioxide, and at least one of the first precursor or the second precursor includes an organic substance containing a silanol group.

6. The method for forming a semiconductor structure according to claim 5, characterized in that: The organic matter containing silanol groups includes 3-tert-butylsilanol groups.

7. The method for forming a semiconductor structure according to claim 1, wherein: The first precursor includes a metal organic compound having a catalytic effect.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: The metal material in the metal organic compound includes at least one of aluminum, lanthanum, zirconium or hafnium.

9. The method for forming a semiconductor structure according to claim 1, wherein: The reaction temperature of the first precursor and the second precursor to form the dielectric layer is 225° C. to 250° C.

10. The method for forming a semiconductor structure according to claim 1, wherein: In a direction perpendicular to the surface of the substrate, a ratio of a height of the first sub-sidewall to a height of the second sub-sidewall is 1-9.

11. A semiconductor structure obtained by the method for forming a semiconductor structure according to any one of claims 1 to 10, characterized in that: include: A substrate and a groove in the substrate, wherein the groove sidewall comprises a first sub-sidewall and a second sub-sidewall extending upward from the bottom of the groove, and the first sub-sidewall is located between the second sub-sidewall and the bottom of the groove; A multi-layer dielectric layer, the multi-layer dielectric layer blocks the top opening of the groove and is stacked in sequence in the direction from the side wall of the groove toward the central axis of the groove; A gap is formed by an area surrounded by the first sub-side wall, the bottom of the groove and the multi-layer dielectric layer.

12. The semiconductor structure according to claim 11, characterized in that: The substrate has conductive structures located on opposite sides of the groove.

13. The semiconductor structure according to claim 12, characterized in that: The multi-layer dielectric layer contains a metal material, and the metal material includes at least one of aluminum, lanthanum, zirconium or hafnium.

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