Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate in which an IO well region and a shallow trench isolation structure are formed; etching the IO well region and a part of the shallow trench isolation structure to form a trench; and filling a gate oxide structure in the trench, wherein the gate oxide structure comprises: a first oxide layer, a second oxide layer and a third oxide layer. The present invention also provides a semiconductor device, comprising: a substrate and a sandwich-type gate oxide structure. By forming a sunken gate oxide structure on the IO well region and a part of the shallow trench isolation structure in the substrate, and adopting a process of sequentially growing the first oxide layer, the second oxide layer and the third oxide layer to obtain the sandwich-type gate oxide structure, the present application improves (reduces) the height of the gate oxide structure in the medium-voltage device while eliminating the corner void defect of the gate oxide structure, thereby improving the performance and reliability of the medium-voltage device.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and particularly relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the size of transistors continues to shrink, HKMG (High-k gate dielectric + metal gate) has gradually replaced the original silicon dioxide insulating layer + polysilicon gate configuration and become the main development direction for the manufacturing process of CMOS devices below 28 nm. Currently, there are Gate-first and Gate-last HKMG technologies. For the Gate-first technology, since the metal gate needs to undergo multiple high-temperature processes, it is easy to damage the metal gate, thus seriously affecting the performance and reliability of the device. In contrast, the Gate-last process can effectively avoid high-temperature processes and effectively ensure the performance and reliability of the device. However, the flatness of the DummyPoly structure has become a key step for the height uniformity of the metal gate. The Gate-last process usually first fabricates the DummyPoly structure, and then removes the DummyPoly structure through the ILD0 CMP (Interlayer Dielectric Chemical Mechanical Polishing) process, dry and / or wet etching processes in subsequent processes and leaves a trench, and finally fills the trench with a metal material to finally form a metal gate.

[0003] In the Gate-last process, since a certain thickness of gate oxide layer needs to be grown on the substrate surface in medium-voltage devices (IO devices), the height deviation of the gate oxide layer of medium-voltage devices is too large compared with that of the gate oxide layers of low-voltage (core) devices and high-voltage devices on the same wafer. This results in too large a height deviation of the metal gate formed on the gate oxide layer of medium-voltage devices compared with the metal gates of low-voltage (core) devices and high-voltage devices on the same wafer. After forming the DummyPoly structure on the gate oxide layer, during the process of performing the ILD0 CMP (Interlayer Dielectric Chemical Mechanical Polishing) process, since all devices on the same wafer are polished simultaneously, the Dummy Poly above the gate oxide layer of medium-voltage devices is over-polished by mistake because it is higher than the Dummy Poly of low-voltage devices. This will affect the formation of the metal gate in subsequent medium-voltage devices and easily lead to device failure. Therefore, someone came up with using a recessed gate oxide to solve the problem of height difference in the gate oxide layer. However, in the recessed gate oxide manufacturing process, due to the existence of a corner (the edge inclination angle of the gate oxide layer) at the junction of the gate oxide layer and the shallow trench isolation structure (STI), voids are likely to appear in the gate oxide layer at the corner position, resulting in a lower coverage ratio of the gate oxide layer at the corner position compared with other areas in the trench. That is to say, there are certain void defects in the gate oxide layer at the corner position, seriously affecting the reliability of the gate oxide layer and thus affecting the normal operation of medium-voltage devices. Summary of the Invention

[0004] This application provides a semiconductor device and a manufacturing method thereof, which can solve the problems of too high height of the gate oxide layer and damage to the gate oxide layer in medium-voltage devices.

[0005] On the one hand, an embodiment of this application provides a manufacturing method of a semiconductor device, including:

[0006] Providing a substrate, in which an IO well region and shallow trench isolation structures located on both sides of the IO well region are formed;

[0007] Using a lithography process to open a part of the surface of the IO well region and the shallow trench isolation structures;

[0008] Etching the IO well region and the shallow trench isolation structures to form trenches; and,

[0009] Forming a gate oxide structure, and filling the trenches with the gate oxide structure;

[0010] Among them, the step of forming the gate oxide structure includes:

[0011] Forming a first oxide layer, and covering the bottom wall of the trenches with the first oxide layer;

[0012] Forming a second oxide layer, and covering the first oxide layer with the second oxide layer;

[0013] Forming a third oxide layer, and covering the surface of the second oxide layer and the remaining surface of the shallow trench isolation structures with the third oxide layer;

[0014] Removing the third oxide layer on the remaining surface of the shallow trench isolation structures.

[0015] Optionally, in the manufacturing method of the semiconductor device, an ISSG process is used to form the first oxide layer with a thickness of .

[0016] Optionally, in the manufacturing method of the semiconductor device, a furnace tube high-temperature oxidation process is used to form the second oxide layer with a thickness of .

[0017] Optionally, in the manufacturing method of the semiconductor device, an ALD process is used to form the third oxide layer with a thickness of .

[0018] Optionally, after removing the third oxide layer on the remaining surface of the shallow trench isolation structures in the manufacturing method of the semiconductor device, the step of forming the gate oxide structure further includes:

[0019] Etch a portion of the thickness of the third oxide layer on the trench so that the upper surface of the remaining thickness of the third oxide layer is flush with the upper surface of the shallow trench isolation structure.

[0020] Optionally, in the method for manufacturing the semiconductor device, the portion of the thickness of the third oxide layer etched on the trench is

[0021] Optionally, in the method for manufacturing the semiconductor device, the size of each of the shallow trench isolation structures opened by the lithography process in width is

[0022] Optionally, in the method for manufacturing the semiconductor device, the materials of the first oxide layer, the second oxide layer, and the third oxide layer are all silicon dioxide.

[0023] On the other hand, an embodiment of the present application further provides a semiconductor device, including:

[0024] A substrate, in which an IO well region and shallow trench isolation structures located on both sides of the IO well region are formed, wherein trenches are formed in the IO well region and a part of the shallow trench isolation structures;

[0025] A gate oxide structure, which fills the trench, and the gate oxide structure includes: a first oxide layer, a second oxide layer, and a third oxide layer stacked in sequence.

[0026] The technical solution of the present application has at least the following advantages:

[0027] The present application improves (reduces) the height of the gate oxide structure in the medium-voltage device by forming a sunken gate oxide structure on the IO well region and a part of the shallow trench isolation structures in the substrate, and eliminates the corner void defect of the gate oxide structure by adopting the process of sequentially growing the first oxide layer, the second oxide layer, and the third oxide layer to obtain a sandwich-type gate oxide structure. Thus, while improving the height of the gate oxide structure in the medium-voltage device, the corner void defect of the gate oxide structure is eliminated, ensuring the integrity of the performance and structure of the gate oxide structure, thereby avoiding the failure of the medium-voltage device, and thus improving the performance and reliability of the medium-voltage device. Description of the Drawings

[0028] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figures 1 - 7 It is a schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present invention;

[0030] 100 - Substrate, 101 - Shallow trench isolation structure, 110 - IO well region, 120 - Core well region, 130 - Photoresist, 131 - Photolithography definition window, 140 - Gate oxide structure, 141 - First oxide layer, 142 - Second oxide layer, 143 - Third oxide layer, 144 - Corner, 200 - Trench. Detailed implementation manners

[0031] Next, the technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0032] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0033] In the description of the present application, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0034] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0035] An embodiment of the present application provides a method for manufacturing a semiconductor device, and the method for manufacturing the semiconductor device includes:

[0036] First step: Provide a substrate, in which an IO well region and shallow trench isolation structures located on both sides of the IO well region are formed;

[0037] Second step: Use a lithography process to open part of the surface of the IO trap region and the shallow trench isolation structure.

[0038] Third step: Etch the IO trap region and the shallow trench isolation structure to form trenches.

[0039] Fourth step: Form a gate oxide structure, and the gate oxide structure fills the trenches.

[0040] Specifically, refer to Figures 1 - 7 , Figures 1 - 7 which is a schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present invention.

[0041] First, refer to Figure 1 , provide a substrate 100, in which an IO trap region 110 and shallow trench isolation structures 101 located on both sides of the IO trap region 110 are formed. Specifically, the substrate 100 can be one of single-crystalline silicon, polycrystalline silicon, and amorphous silicon. The substrate 100 can also be gallium arsenide, silicon-gallium compound, etc. The substrate 100 can also have a silicon-on-insulator or epitaxial layer-on-silicon structure. The substrate 100 can also be other semiconductor materials, which will not be listed one by one here. In this embodiment, the conductive type of the substrate 100 can be P-type. A core trap region 120 can also be formed in the substrate 100, and the IO trap region 110 and the core trap region 120 are isolated by the shallow trench isolation structures 101. The IO trap region 110 is located in a medium-voltage device, and the core trap region 120 is located in a low-voltage device. Because the stress of the shallow trench isolation structure 101 is different from that of the IO trap region 110, the upper surface of the shallow trench isolation structure 101 is slightly higher than the surface of the substrate 100 by a certain height.

[0042] Next, refer to Figure 2 , use a lithography process to open part of the surface of the IO trap region 110 and the shallow trench isolation structure 101. Specifically, coat a layer of photoresist 130 on the surface of the substrate 100, and form a lithography-defined window 131 in the photoresist 130 through exposure and development. As Figure 2 shown, the lithography-defined window 131 opens part of the surface of the IO trap region 110 and the shallow trench isolation structure 101. Among them, the dimensions of the shallow trench isolation structures 101 on both sides of the IO trap region 110 opened by the lithography process can both be

[0043] Then, refer to Figure 3, etch the IO well region 110 and the shallow trench isolation structure 101 to form a trench 200. Specifically, a dry etching process may be used to etch the IO well region 110 and the shallow trench isolation structure 101 under the lithographically defined window 131. The thickness of the etched IO well region 110 and the shallow trench isolation structure 101 may be

[0044] Furthermore, referring to Figures 4 - 7 , form a gate oxide structure 140, and the gate oxide structure 140 fills the trench 200. Specifically, the steps of forming the gate oxide structure 140 include:

[0045] The first step: referring to Figure 4 , form a first oxide layer 141, and the first oxide layer 141 covers the bottom wall of the trench. Specifically, the first oxide layer 141 is formed by an ISSG (in-situ steam generation) process, and the thickness of the first oxide layer 141 may be

[0046] The second step: referring to Figure 5 , form a second oxide layer 142, and the second oxide layer 142 covers the first oxide layer 141. Specifically, the second oxide layer 142 is formed by a furnace high-temperature oxidation (Furnace) process, and the thickness of the second oxide layer 142 may be

[0047] The third step: referring to Figure 6 , form a third oxide layer 143, and the third oxide layer 143 covers the surface of the second oxide layer 142 and the remaining surface of the shallow trench isolation structure 101. Specifically, the third oxide layer 143 may also cover the surface of the core well region 120 and the surface of the remaining substrate 100. In this embodiment, the third oxide layer 143 is formed by an ALD (atomic layer deposition) process, and the thickness of the third oxide layer 143 may be In this embodiment, the materials of the first oxide layer 141, the second oxide layer 142, and the third oxide layer 143 may all be silicon dioxide.

[0048] The fourth step: referring to Figure 7 , remove the third oxide layer 143 on the remaining surface of the shallow trench isolation structure 101. Specifically, this step also includes removing the third oxide layer 143 on the surface of the core well region 120 and the surface of the remaining substrate 100, and only retaining the third oxide layer 143 at the top of the trench 100.

[0049] In the present application, a sunken gate oxide structure 140 is formed on the IO well region 110 and a part of the shallow trench isolation structure 101 in the substrate 100 to improve (reduce) the height of the gate oxide structure 140 in the medium-voltage device, ensuring the integrity of the gate oxide structure 140 of the IO device and the uniformity of the subsequent metal gate height. Further, referring to Figure 7 , the inclined parts on both sides of the gate oxide structure 140 close to the shallow trench isolation structure 101 are corners (angles) 144. When depositing the gate oxide structure 140 in the trench 200, void defects are likely to occur at the position of the corner 144. However, in the present application, the process of sequentially growing the first oxide layer 141, the second oxide layer 142, and the third oxide layer 143 is adopted to obtain the sandwich-like gate oxide structure 140. The present application forms the gate oxide structure 140 in three different processes, which can eliminate the void defects at the corner 144 position of the gate oxide structure. Thus, while improving the height of the gate oxide structure 140 in the medium-voltage device, the present application eliminates the void defects at the corner 144 of the gate oxide structure 140, ensuring the integrity of the performance and structure of the gate oxide structure 140, thereby avoiding the failure of the medium-voltage device and improving the performance and reliability of the medium-voltage device. The inventor's experiment found that the coverage rate of the third oxide layer at the corner 144 position of the gate oxide structure 140 formed by the semiconductor manufacturing method provided by the present invention is increased by at least 20% compared with the oxide coverage rate at the corner position of the gate oxide layer formed in the prior art.

[0050] Preferably, after removing the third oxide layer 143 on the remaining surface of the shallow trench isolation structure 101, the step of forming the gate oxide structure 140 may further include: etching back a part of the thickness of the third oxide layer 143 on the trench 200 so that the upper surface of the remaining thickness of the third oxide layer 143 is flush with the upper surface of the shallow trench isolation structure 101. Specifically, the part of the thickness of the third oxide layer 143 etched on the trench 200 may be

[0051] Based on the same inventive concept, an embodiment of the present application further provides a semiconductor device, including: a substrate 100 and a gate oxide structure 140. Among them, an IO well region 110 and shallow trench isolation structures 101 located on both sides of the IO well region 110 are formed in the substrate 100. Among them, a trench 200 is formed in the IO well region 110 and the part of the shallow trench isolation structure 101; the gate oxide structure 140 fills the trench 200, and the gate oxide structure 140 includes: a first oxide layer 141, a second oxide layer 142, and a third oxide layer 143 stacked in sequence.

[0052] Obviously, the above embodiments are merely examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a substrate, in which an IO well region and shallow trench isolation structures located on both sides of the IO well region are formed; Using a lithography process to open the surface of the IO well region and part of the surface of the shallow trench isolation structures; Etching the IO well region and the shallow trench isolation structures to form trenches; And Forming a gate oxide structure, the gate oxide structure filling the trenches; Wherein, the step of forming the gate oxide structure includes: Forming a first oxide layer by ISSG process, the first oxide layer covering the bottom wall of the trenches; Forming a second oxide layer by furnace high-temperature oxidation process, the second oxide layer covering the first oxide layer; Forming a third oxide layer by ALD process, the third oxide layer covering the surface of the second oxide layer and the remaining surface of the shallow trench isolation structures; Removing the third oxide layer on the remaining surface of the shallow trench isolation structures.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Forming the first oxide layer with a thickness of 15 Å - 35 Å by ISSG process.

3. The manufacturing method of the semiconductor device according to claim 1, wherein, Forming the second oxide layer with a thickness of 130 Å - 170 Å by furnace high-temperature oxidation process.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Forming the third oxide layer with a thickness of 40 Å - 60 Å by ALD process.

5. The manufacturing method of the semiconductor device according to claim 1, characterized in that, After removing the third oxide layer on the remaining surface of the shallow trench isolation structures, the step of forming the gate oxide structure further includes: Etching a part of the thickness of the third oxide layer on the trenches to make the upper surface of the remaining thickness of the third oxide layer flush with the upper surface of the shallow trench isolation structures.

6. The manufacturing method of the semiconductor device according to claim 5, characterized in that, Etching a part of the thickness of the third oxide layer on the trenches to be 30 Å - 40 Å.

7. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The size of each of the shallow trench isolation structures opened by the lithography process in width is 600 Å - 700 Å.

8. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The materials of the first oxide layer, the second oxide layer and the third oxide layer are all silicon dioxide.

9. A semiconductor device prepared by the method for manufacturing a semiconductor device according to any one of claims 1-8, characterized in that, Including: A substrate, in which an IO well region and shallow trench isolation structures located on both sides of the IO well region are formed, wherein, trenches are formed in the IO well region and part of the shallow trench isolation structures; A gate oxide structure, the gate oxide structure filling the trenches, the gate oxide structure including: a first oxide layer, a second oxide layer and a third oxide layer stacked in sequence.

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