Multi-voltage domain device and gate driver integrated circuit

Abstract

The present invention discloses a multi-voltage domain device and a gate driver integrated circuit. The multi-voltage domain device includes a semiconductor layer, which includes a first voltage domain, a second voltage domain, and an isolation region that electrically isolates the first voltage domain and the second voltage domain in a lateral direction. The isolation region includes at least one deep trench isolation barrier. A layer stack is disposed on the semiconductor layer and includes: a stacked insulator layer; a first coil disposed in the stacked insulator layer; and a second coil disposed in the stacked insulator layer and laterally separated from the first coil in a lateral direction. The first coil and the second coil are magnetically coupled to each other in the lateral direction. The first coil includes a terminal vertically disposed above a first region and electrically coupled to the first voltage domain, and the second coil includes a terminal vertically disposed above a second region and electrically coupled to the second voltage domain.

Description

Technical Field

[0001] The present disclosure generally relates to multi-voltage domain devices and gate driver integrated circuits, and more particularly to multi-voltage domain devices and gate driver integrated circuits having semiconductor layers. Background Art

[0002] A high voltage (HV) gate driver circuit may include a low voltage (LV) gate driver for driving a low side transistor switch and a high voltage (HV) gate driver for driving a high side transistor switch. The LV gate driver is disposed in a low voltage domain, while the HV gate driver is disposed in a high voltage domain. In fact, the gate driver further includes a termination region that isolates the high voltage domain from the low voltage domain and may be referred to as an isolation termination region. Thus, the termination region provides a high voltage isolation barrier between the two voltage domains.

[0003] Typically, the HV gate driver receives control signals and other possible communication signals from a circuit located in the low voltage domain. Thus, these signals are sent from the low voltage domain through the termination region to the high voltage domain.

[0004] Signals can be transmitted through a vertical coreless transformer. However, a vertical coreless transformer requires a thick oxide such as interlayer dielectric (ILD) to isolate the vertically opposite sides of the transformer. This also applies to capacitive coupling techniques, in which plates are placed one on top of the other and vertically separated by the ILD. In both cases, the ILD thickness determines the isolation range. Expanding the isolation requires changing the ILD and thus requires changing the manufacturing process, which includes changing a certain minimum number of metal layers to ensure sufficient ILD between the primary and secondary coils and / or requires special back-end-of-line (BEOL) processes. Thus, from a manufacturing perspective, these vertical arrangements for accommodating different isolation levels are costly and inefficient and are not practical for HV gate driver processing.

[0005] Therefore, there may be a need for an improved device with a coreless transformer that is more easily and economically sized according to different voltage isolation requirements. Summary of the Invention

[0006] An embodiment provides a multi-voltage domain device having a semiconductor layer including a first major surface and a second major surface disposed opposite the first major surface. The semiconductor layer includes a first region including a first circuit operating in a first voltage domain; a second region including a second circuit operating in a second voltage domain different from the first voltage domain; and an isolation region electrically isolating the first region and the second region in a lateral direction extending parallel to the first and second major surfaces, wherein the isolation region includes at least one deep trench isolation barrier, each of the deep trench isolation barriers extending perpendicularly from the first major surface to the second major surface. The multi-voltage domain device further includes a layer stack disposed on the first major surface of the semiconductor layer, the layer stack including: a plurality of sub-insulator layers forming a stacked insulator layer; a first coil disposed in the stacked insulator layer; and a second coil disposed in the stacked insulator layer and laterally separated from the first coil in the lateral direction by the stacked insulator layer, wherein the first coil and the second coil are magnetically coupled to each other in the lateral direction, wherein the first coil includes at least two first terminals vertically disposed on the first region and electrically coupled to the first circuit, and wherein the second coil includes at least two second terminals vertically disposed on the second region and electrically coupled to the second circuit.

[0007] An embodiment provides a gate driver integrated circuit having a semiconductor layer including a first major surface and a second major surface disposed opposite the first major surface. The semiconductor layer includes: a high-side region including a first circuit operating in a first voltage domain according to a first pair of power terminals including a first low power terminal and a first high power terminal; a low-side region including a second circuit operating in a second voltage domain lower than the first voltage domain according to a second pair of power terminals including a second low power terminal and a second high power terminal; and an isolation region electrically isolating the high-side region and the low-side region in a lateral direction extending parallel to the first and second major surfaces, wherein the isolation region includes at least one deep trench isolation barrier, each of the deep trench isolation barriers extending perpendicularly from the first major surface to the second major surface. The gate driver integrated circuit further includes a layer stack disposed on the first major surface of the semiconductor layer, the layer stack including: a plurality of sub-insulator layers forming a stacked insulator layer; a first coil disposed in the stacked insulator layer; and a second coil disposed in the stacked insulator layer and laterally separated from the first coil in the lateral direction by the stacked insulator layer, wherein the first coil and the second coil are magnetically coupled to each other in the lateral direction, wherein the first coil includes at least two first terminals vertically disposed on the high-side region and electrically coupled to the first circuit, and wherein the second coil includes at least two second terminals vertically disposed on the low-side region and electrically coupled to the second circuit.

[0008] Embodiments provide a multi-voltage domain device having a semiconductor layer including a first major surface and a second major surface disposed opposite the first major surface. The semiconductor layer includes: a first region including a first circuit operating in a first voltage domain; a second region including a second circuit operating in a second voltage domain different from the first voltage domain; and an isolation region electrically isolating the first region and the second region in a lateral direction extending parallel to the first major surface and the second major surface, wherein the isolation region includes at least one deep trench isolation barrier, and each of the deep trench isolation barriers extends vertically from the first major surface to the second major surface. The multi-voltage domain device further includes: a layer stack disposed on the first major surface of the semiconductor layer, the layer stack including: a plurality of sub-insulator layers forming a stacked insulator layer; a first coil disposed in the stacked insulator layer; and a second coil disposed in the stacked insulator layer and laterally separated from the first coil in the lateral direction by the stacked insulator layer; a third coil disposed in the stacked insulator layer and separated from the first coil and the second coil in the lateral direction by the stacked insulator layer; and a fourth coil disposed in the stacked insulator layer and separated from the first coil, the second coil, and the third coil in the lateral direction by the stacked insulator layer, wherein the first coil and the second coil are magnetically coupled to each other in the lateral direction, wherein the third coil and the fourth coil are magnetically coupled to each other in the lateral direction, wherein the first coil includes at least two first terminals vertically disposed on the first region and electrically coupled to the first circuit, wherein the second coil includes at least two second terminals vertically disposed on the second region and electrically coupled to the second circuit, wherein the third coil includes at least two third terminals vertically disposed on the first region and electrically coupled to the first circuit, and wherein the fourth coil includes at least two fourth terminals vertically disposed on the second region and electrically coupled to the second circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments are described herein with reference to the drawings.

[0010] Figure 1A A top view of a lateral coreless transformer according to one or more embodiments is shown.

[0011] Figure 1B A cross-sectional view taken along cutting line AA of a multi-voltage domain device including the lateral coreless transformer shown in Figure 1A is shown.

[0012] Figure 2 A cross-sectional view of an example variation of a multi-voltage domain device according to one or more embodiments is shown.

[0013] Figure 3A cross-sectional view showing an exemplary variation of a multi-voltage domain device according to one or more embodiments.

[0014] Figure 4 A top view showing an exemplary variation of a multi-voltage domain device according to one or more embodiments.

[0015] Figure 5A A schematic diagram showing a lateral coreless transformer communication system according to one or more embodiments.

[0016] Figure 5B A schematic diagram showing another lateral coreless transformer communication system according to one or more embodiments.

[0017] Figure 6A and Figure 6B A schematic diagram showing another lateral coreless transformer communication system according to one or more embodiments.

[0018] Figure 7 A schematic block diagram showing an energy transfer circuit using a lateral coreless transformer according to one or more embodiments.

[0019] Figure 8 is a schematic block diagram of a power module according to one or more embodiments. Detailed Description

[0020] Hereinafter, details are set forth to provide a more comprehensive explanation of the exemplary embodiments. However, it will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In other cases, well-known structures and devices are shown in block diagram form or in schematic diagrams rather than in detail to avoid obscuring the embodiments. Additionally, unless otherwise specifically stated, the features of the different embodiments described hereinafter may be combined with each other.

[0021] Furthermore, in the following description, equivalent or similar reference numerals are used to denote equivalent or similar elements or elements having equivalent or similar functions. Since the same elements or elements with equivalent functions are given the same reference numerals in the drawings, the repeated description of the elements provided with the same reference numerals may be omitted. Therefore, the descriptions provided for elements having the same or similar reference numerals are interchangeable.

[0022] In this regard, directional terms such as "top", "bottom", "below", "above", "front", "rear", "back", "front portion", "tail portion", etc. may be used with reference to the orientation of the described drawings. Since the components of the embodiments can be positioned in multiple different orientations, the directional terms are for illustrative purposes. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope defined by the claims. Therefore, the following detailed description should not be construed as limiting. The directional terms used in the claims can assist in defining the spatial or positional relationship of one element to another element or feature, and are not limited to a specific orientation.

[0023] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present. Other words used to describe the relationship between elements (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.) should be interpreted in a similar manner.

[0024] In the embodiments described herein or shown in the drawings, any direct electrical connection or coupling (i.e., any connection or coupling without additional intervening elements) can also be achieved by an indirect connection or coupling (i.e., a connection or coupling having one or more additional intervening elements), and vice versa, as long as the general purpose of the connection or coupling, such as transmitting a certain signal or transmitting a certain information, is essentially maintained. Features from different embodiments can be combined to form additional embodiments. For example, unless otherwise stated, changes or modifications described with respect to one of the embodiments can also be applied to other embodiments.

[0025] Without departing from the aspects of the embodiments described herein, the terms "substantially" and "about" can be used herein to account for small manufacturing tolerances that are considered acceptable in the industry (e.g., within 5%). For example, a resistor having an approximate resistance value can actually have a resistance within 5% of that approximate resistance value.

[0026] In the present disclosure, expressions including ordinal numbers such as "first", "second", etc. can modify various elements. However, such elements are not limited by the above expressions. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only for the purpose of distinguishing one element from another. For example, a first box and a second box represent different boxes, although they are both boxes. For example, without departing from the scope of the present disclosure, a first element can be referred to as a second element, and similarly, a second element can also be referred to as a first element.

[0027] Many functions in modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving motors or electric machines, rely on power semiconductor devices. For example, to name just a few, insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes have been used in various applications, including but not limited to switching in power supplies and power converters.

[0028] Power semiconductor devices generally include a semiconductor structure configured to conduct a load current along a load current path between two load terminal structures or load electrodes (e.g., source / emitter and drain / collector) of the device. Additionally, the load current path can be controlled by a control electrode, sometimes referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device to one of a conducting state and a blocking state. The control signal can be a voltage signal or a current signal with a controlled value.

[0029] A power transistor (also referred to as a power switch or transistor switch) is a power semiconductor device that can be used to drive a load current. For example, an IGBT is turned on or off by activating and deactivating its gate terminal. Applying a positive input voltage signal across the gate and emitter will keep the device in the "on" state, while making the input gate signal zero or slightly negative will turn the device to the "off" state. There are a turn-on process for turning on the power transistor and a turn-off process for turning off the power transistor.

[0030] During the turn-on process, a gate driver integrated circuit (IC) can be used to supply (source) a gate current (i.e., turn-on current) to the gate of the power transistor to charge the gate to a sufficient voltage for turning on the device. In particular, the current Io+ is the gate driver output current used to raise (i.e., charge) the gate of the power transistor during the turn-on transient. Thus, the current Io+ is used to turn on the power transistor.

[0031] In contrast, during the turn-off process, the gate driver IC is used to draw (sink) a gate current (i.e., turn-off current) from the gate of the power transistor to fully discharge the gate to turn off the device. The current Io- is the gate driver output current used to discharge the gate of the power transistor during the turn-off transient. Thus, Io- is used to turn off the power transistor.

[0032] According to a pulse width modulation (PWM) scheme, voltage pulses can be output from the gate driver IC as control signals. Thus, during a PWM period for controlling a power transistor, the control signal can be switched between a turn-on voltage level and a turn-off voltage level. This in turn charges and discharges the gate voltage to turn on and turn off the power transistor, respectively.

[0033] In particular, the gate of a power transistor is a capacitive load, and when initiating a switching event, the turn-on current (i.e., the gate-source current) and the turn-off current (i.e., the gate-drain current) are specified as the initial currents. During the turn-off event, after a short period of time (a time shorter than the PWM period), the gate current decreases and reaches zero when the gate reaches 0V. During the turn-on event, after a short period of time (a time shorter than the PWM period), the gate current decreases and reaches zero when the gate reaches the high-side supply level.

[0034] The transistor may include an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET) (e.g., Si MOSFET or SiC MOSFET). Although the IGBT may be used as an example in the following embodiments, it should be understood that the MOSFET may replace the IGBT, and vice versa, the IGBT may replace the MOSFET. In this case, in any of the examples described herein, when the MOSFET replaces the IGBT, the drain of the MOSFET may replace the collector of the IGBT, the source of the MOSFET may replace the emitter of the IGBT, and the drain-source voltage VDS of the MOSFET may replace the collector-emitter voltage VCE of the IGBT. Thus, any IGBT module may be replaced by a MOSFET module, and vice versa, any MOSFET module may be replaced by an IGBT module.

[0035] The specific embodiments described in this specification belong to but are not limited to power semiconductor devices that can be used within a power converter or a power supply. Thus, in an embodiment, the power semiconductor device may be configured to carry a load current to be provided to a load and / or provided by a power supply, respectively. For example, the semiconductor device may include one or more power semiconductor units such as a monolithically integrated diode unit and / or a monolithically integrated transistor unit. Such a diode unit and / or such a transistor unit may be integrated in a power semiconductor module.

[0036] Power semiconductor devices including transistors appropriately connected to form a half-bridge are commonly used in the field of power electronics. For example, a half-bridge may be used to drive a motor or a switched-mode power supply.

[0037] For example, a multiphase inverter is configured to provide multiphase power by supplying a multiphase load (e.g., a three-phase motor). For example, three-phase power includes three symmetric sine waves that are 120 electrical degrees out of phase with each other. In a symmetric three-phase power system, three conductors each carry an alternating current (AC) having the same frequency and voltage amplitude with respect to a common reference but having a phase difference of one-third of a period. Due to the phase difference, the voltage on any conductor reaches its peak one-third of a period later than one of the other conductors and one-third of a period earlier than the remaining conductor. This phase delay provides a constant power transfer for a balanced linear load. This also makes it possible to generate a rotating magnetic field in a motor.

[0038] In a three-phase system supplying a balanced linear load, the sum of the instantaneous currents in the three conductors is zero. In other words, the current in each conductor is equal in magnitude to the sum of the currents in the other two conductors but opposite in sign. The return path for the current in any phase conductor is the other two phase conductors. The instantaneous currents generate a current space vector.

[0039] A three-phase inverter includes three inverter legs, one inverter leg for each of the three phases, and each inverter leg is connected in parallel to a direct current (DC) voltage source. Each inverter leg includes a pair of power transistors arranged, for example, in a half-bridge configuration for converting DC to AC. In other words, each inverter leg includes two complementary transistors (i.e., a high-side transistor and a low-side transistor) connected in series that conduct and turn off complementary to each other to drive the phase load.

[0040] Figure 1A A top view of a lateral coreless transformer 100 according to one or more embodiments is shown. Figure 1B A cross-sectional view taken along cut line AA of a multi-voltage domain device 101 including the Figure 1A lateral coreless transformer 100 shown in is shown.

[0041] The multi-voltage domain device 101 includes a stack of a semiconductor layer, an isolation layer, and a metal layer. Specifically, the lateral coreless transformer 100 may be formed on a silicon-on-insulator (SOI) wafer, where a buried oxide (BOX) layer 2 is formed in the SOI wafer, and the SOI wafer includes a semiconductor substrate 1 and a semiconductor layer 3 disposed on opposite sides of the BOX layer 2. The BOX layer 2 may alternatively be referred to as a wafer insulator layer. Note that other types of semiconductor substrate / insulator layer structures may also be used.

[0042] The semiconductor layer 3 forming the functional circuit components and devices may be further formed on the BOX layer 2. The back-end-of-line (BEOL) layer stack 4 includes metal layers (e.g., M1, M2, and M3) formed in a stacked insulator layer 9 (e.g., an oxide layer). Specifically, the metal layers are alternated with one or more insulator sub-layers in the vertical direction to form the BEOL layer stack 4. The BEOL layer stack 4 may be formed on the semiconductor layer 3. It should be noted that the BOX layer 2 and the stacked insulator layer 9 may be made of the same or different insulating materials.

[0043] Multiple metal layers, such as M1, M2, and M3, are deposited within the BEOL layer stack 4 to form the coils of the laterally coreless transformer 100. The metal layers are vertically separated (isolated) from each other in the z-direction by one or more insulator sub-layers of the stacked insulator layer 9, except that a metal or conductive structure segment is provided in the sub-insulator layer between two metal layers. The metal segment or conductive structure segment electrically couples the two metal layers together, thereby providing an electrical path between the two metal layers, and thus a continuous coil can be formed. Therefore, it can be said that the coil is formed by vertically overlapping metal layers. The minimum number of metal layers is one, however, there is no real limit to the total number of metal layers as long as it is actually manufacturable.

[0044] In addition, as will be discussed in more detail below, the metal layers of different coil structures are laterally separated (isolated) from each other in the x-direction by the stacked insulator material 9 of the BEOL layer stack 4.

[0045] The multi-voltage domain device 101 includes a first voltage domain (e.g., voltage domain A), which is laterally isolated from a second voltage domain (e.g., voltage domain B) by an isolation region or termination region including a plurality of deep trench isolation (DTI) barriers 5. Each of the DTI barriers 5 extends vertically from the main surface of the semiconductor layer 3 to the BOX layer 2. Each DTI barrier 5 is a trench partially filled with an insulating material that is the same as or different from the insulating material used for the BOX layer 2, and is defined by the semiconductor material of the semiconductor layer 3 forming its sidewalls. The DTI should be constructed in such a way that it actually defines the isolation region within the layer 3 to provide lateral isolation within the semiconductor layer 3. Therefore, the minimum number of DTI is one. The DTI barrier may be partially filled with an insulator material and polysilicon to fill the trench.

[0046] The lateral dimension Dl of the isolation region 5 is defined by the outer sidewall of the outermost DTI barrier 5a and the inner sidewall of the innermost DTI barrier 5b. The number and lateral dimension of the DTI barriers 5 can be adjusted based on the desired isolation level required to isolate the first voltage domain (e.g., voltage domain A) from the second voltage domain (e.g., voltage domain B).

[0047] For example, voltage domain A can be a low voltage (LV) domain or a medium voltage (MV) domain, while voltage domain B can be a high voltage (HV) domain. The LV domain is an area including low voltage devices, the MV domain is an area including medium voltage devices, and the HV domain is an area including high voltage devices. For example, low voltage devices can be powered from 0V to 5V, medium voltage devices can be powered from 0V to 30V, and high voltage devices can be powered above 100V (e.g., 120V to 160V or higher). The voltage domains are not limited to these voltage ranges, but instead are intended to provide an example of an implementation. However, the general principle of different voltage domain levels at different voltage grades remains the same. Thus, a higher level of isolation may be required when voltage domain A is an LV domain compared to when voltage domain A is an MV domain, because the voltage difference between the LV domain and the HV domain is greater than the voltage difference between the MV domain and the HV domain.

[0048] The lateral coreless transformer 100 is formed in the BEOL layer stack 4 (i.e., within the stacked insulator layer 9) and includes two metal coils 6 and 7 formed on opposite lateral sides of the isolation region via metal layers M1, M2, and M3. Specifically, coil 6 is disposed in the edge region of voltage domain A and coil 7 is disposed in the edge region of voltage domain B. For example, coil 6 can surround the inner periphery of voltage domain A and coil 7 can surround the outer periphery of voltage domain B such that their wires face each other laterally. In other words, coils 6 and 7 can be concentric coils. The DTI barrier 5 constituting the isolation region can laterally surround voltage domain B to laterally separate the two voltage domains. Thus, coils 6 and 7 and the isolation region can form a concentric structure.

[0049] In addition, coils 6 and 7 are laterally separated (isolated) from each other in the x - direction by the stacked insulator material 9 of the BEOL layer stack 4. Each metal layer of coils 6, 7 is conductively coupled to an adjacent metal layer through a metal via or other metal structure formed in a sub - insulator layer located between two adjacent metal layers.

[0050] Thus, the metal layers M1 and M2 of coil 6 are conductively coupled together and the metal layers M2 and M3 of coil 6 are conductively coupled together such that coil 6 is a continuous conductive structure, whereby coil 6 extends from terminal 6a to terminal 6b. It can be seen that the two terminals 6a and 6b of coil 6 are arranged diagonally with respect to each other and can each be coupled to a respective voltage pad (not shown). The metal wires of coil 6 vertically spiral through the BEOL layer stack 4.

[0051] The coil terminals 6a and 6b have opposite potentials (e.g., Vp+ and Vp-), and each is coupled to an electrical contact (e.g., a pad or a wire) located in the first voltage domain (e.g., voltage domain A). The electrical contact can be coupled to a corresponding terminal of a communication circuit located in voltage domain A, and each terminal is configured to energize the coil 6 for data transmission or receive (i.e., sample) data transmission from the coil 6. Alternatively, the coil terminals 6a and 6b can be directly coupled to the corresponding terminals of a communication circuit located in voltage domain A.

[0052] Similarly, the metal layers M1 and M2 of the coil 7 are conductively coupled together, and the metal layers M2 and M3 of the coil 7 are conductively coupled together, such that the coil 7 is a continuous conductive structure, whereby the coil 7 extends from the terminal 7a to the terminal 7b. It can be seen that the two terminals 7a and 7b of the coil 7 are arranged diagonally with respect to each other and can each be coupled to a corresponding voltage pad (not shown). The wires of the coil 7 vertically wind through the BEOL layer stack 4.

[0053] The coil terminals 7a and 7b have opposite potentials (e.g., Vs+ and Vs-), and each is coupled to an electrical contact (e.g., a pad or a wire) located in the first voltage domain (e.g., voltage domain B). The electrical contact can be coupled to a corresponding terminal of a communication circuit located in voltage domain B, and each terminal is configured to energize the coil 7 for data transmission or receive (i.e., sample) data transmission from the coil 7. Alternatively, the coil terminals 7a and 7b can be directly coupled to the corresponding terminals of a communication circuit located in voltage domain B.

[0054] According to the lateral arrangement of the coils 6 and 7, when implementing different levels of isolation, the number of sub-insulator layers of the BEOL layer stack 4 that define the thickness of the interlayer dielectric (ILD) does not need to be modified, which is required for vertical coreless transformers. Therefore, there is no need to vertically change the manufacturing process to accommodate different isolation ranges for different multi-voltage domain devices and technologies. Instead, only the lateral spacing will require different lateral geometries within the already predefined layer in which the metal structure of the coil is formed laterally to achieve different isolation ranges in the same manufacturing process. Additionally, in the case of DTI-based isolation, the lateral spacing is directly defined by the DTI barrier region. Further, the lateral oxide region defined by the dimension D2 in the BEOL layer stack 4 is used to isolate the signal transmission channels and does not expose the HV terminals to the passivation / molding compound, which may be the case for vertical coreless transformers or vertical capacitive coupling solutions.

[0055] Figure 2A cross-sectional view of an example variation of a multi-voltage domain device 101 in accordance with one or more embodiments is shown. In particular, a lower inductive (magnetic) coupling can be achieved by forming a single coil on each side of an isolation region (i.e., DTI barrier 5). A higher inductive (magnetic) coupling can be achieved by forming two or more coils on each side of the isolation region. Additionally, a lower voltage isolation can be achieved by reducing the number of DTI barriers, thereby reducing the lateral dimensions D1 and D2. In contrast, a higher voltage isolation can be achieved by increasing the number of DTI barriers, thereby increasing the lateral dimensions D1 and D2.

[0056] Further, in some cases, at least one of the coils 6, 7 can partially or fully straddle the isolation region 5 to achieve better magnetic coupling between the coils 6 and 7. This coil is referred to as a "cross-over" coil. However, the terminals of the cross-over coil (e.g., terminals 6a, 6b or terminals 7a, 7b) remain entirely within the designated voltage domain of the coil. This allows for maintaining a desired degree of isolation between the voltage domains while achieving better magnetic coupling between the coils.

[0057] For example, one or more metal layers of coil 7 can partially extend laterally from voltage domain B into the isolation region 5 such that a portion of coil 7 perpendicularly overlaps one or more DTI barriers. However, its terminals 7a and 7b remain laterally within voltage domain B. Thus, coil 7 has no direct electrical contact with voltage domain A and remains isolated from voltage domain A.

[0058] Additionally or alternatively, one or more metal layers of coil 6 can partially extend laterally from voltage domain A into the isolation region 5 such that a portion of coil 6 perpendicularly overlaps one or more DTI barriers. However, its terminals 6a and 6b remain laterally within voltage domain A. Thus, coil 6 has no direct electrical contact with voltage domain B and remains isolated from voltage domain B.

[0059] Note that both coils 6 and 7 may partially straddle / span over the isolation region 5. This will allow for maintaining a higher degree of isolation between the voltage domains while achieving better magnetic coupling between the coils.

[0060] Alternatively, one or more metal layers of coil 7 can extend completely across the isolation region 5 laterally from voltage domain B into voltage domain A such that a portion of coil 7 is laterally within voltage domain A. However, the terminals 7a and 7b of coil 7 remain laterally within voltage domain B. Thus, coil 7 has no direct electrical contact with voltage domain A and remains isolated from voltage domain A. Here, coil 6 remains entirely within the boundaries of voltage domain A.

[0061] Alternatively, one or more metal layers of coil 6 can extend completely across isolation region 5 laterally from voltage domain A into voltage domain B such that a portion of coil 6 is laterally within voltage domain B. However, its terminals 6a and 6b remain laterally within voltage domain A. Thus, coil 6 has no direct electrical contact with voltage domain B and remains isolated from voltage domain B. Here, coil 7 remains entirely within the boundaries of voltage domain B.

[0062] Figure 3 A cross-sectional view showing an example variation of a multi-voltage domain device 101 in accordance with one or more embodiments is shown. Here, each voltage domain includes two coils (i.e., two windings), the two coils including a primary coil 6-1, 7-1 and a secondary coil 6-2, 7-2, respectively. Additionally, primary coil 7-1 has a shielding wall 8 disposed in a sub-isolation layer between adjacent metal layers of coil 7-1. Shielding wall 8 is coupled to the adjacent metal layers of coil 7-1. Shielding wall 8 may be useful in certain applications in which two voltage domains vary with fast transients (dV / dt). In such cases, parasitic coupling between the two sides of the coreless transformer may cause false signals to be detected, thereby endangering the common mode transient immunity (CMTI) of the system.

[0063] The lateral coreless transformer 100 allows for the creation of shielding walls that will intercept electric field induced noise. These shielding walls can be created using virtual open-ended coils placed between the two sides of the lateral coreless transformer, particularly on the receiver side (i.e., the HV side). The virtual coils are connected together through vias to maximize the shielding effect, thereby creating a metal shielding wall between two laterally separated transformer coils. For example, the metal layers (i.e., windings) of the virtual open-ended coil (shielding wall 8) can be perpendicularly interleaved with the metal layers (i.e., windings) of coil 7-1, as Figure 3 shown. Proper biasing of shielding wall 8 to a low impedance node will solve this task without significantly affecting the coupling characteristics of the transformer.

[0064] Figure 4 A top view showing an example variation of a multi-voltage domain device 101 in accordance with one or more embodiments is shown. Here, the multi-voltage domain device 101 is a monolithic device including four voltage domains (domains A, B, C, and D), the four domains being isolated from each other by their respective isolation regions (i.e., DTI barrier regions 5). Thus, three lateral coreless transformers 100A, 100B, and 100C are provided. Domains A, B, and C can operate at the same voltage level (e.g., HV level), or at least two of the three domains A, B, and C can operate at different voltage levels. Domain D can be at a low voltage level or a medium voltage level.

[0065] Multiple lateral coreless transformers can be constructed monolithically on a single die / waf er, and such an arrangement can enable a monolithic multiphase arrangement, such as but not limited to a so-called three-phase gate driver.

[0066] Figure 5A FIG. 5 shows a schematic diagram of a lateral coreless transformer communication system 500A according to one or more embodiments. The lateral coreless transformer communication system 500A includes a lateral coreless transformer 100, which includes coils 6 and 7, a first voltage domain representing the outer side (e.g., voltage domain A), a second voltage domain representing the inner side (e.g., voltage domain B), and an isolation region 5 including one or more DTI barriers. Here, each of the coils 6 and 7 partially overlaps with the isolation region 5. However, as described above, the lateral spacing between the coils 6 and 7 can be such that neither of the coils 6 and 7 extends into / above the isolation region 5. It can be appreciated from this figure that both the terminals 6a and 6b are completely within the voltage domain A. Similarly, both the terminals 7a and 7b are completely within the voltage domain B. Each terminal is coupled to a communication circuit located within its designated voltage domain.

[0067] In particular, the voltage domain A includes a communication circuit 50 electrically coupled to the terminals 6a and 6b of the coil 6. Similarly, the voltage domain B includes a communication circuit 51 electrically coupled to the terminals 7a and 7b of the coil 7. In one case, the communication circuit 50 can be a transmitter configured to apply a communication signal in the form of a modulated electrical signal to the coil 6. For example, the transmitter can apply a pulsed carrier signal, a single unipolar or bipolar pulse, or multiple unipolar or bipolar pulses, or a modulated carrier signal to the coil 6. The communication circuit 51 is located on the other side of the transformer, and the communication circuit 51 can be a receiver configured to receive a signal from the coil 7 to decode the received signal, such as a carrier detector, a pulse edge detector, or a demodulator. Alternatively, the communication circuit 51 can be a transmitter and the communication circuit 50 can be a receiver. Alternatively, the communication circuits 50 and 51 can both include transmitter and receiver circuits for two-way communication. The latter arrangement can be configured to switch between the transmission directions in a time-alternating manner to enable two-way communication.

[0068] Depending on the required performance (speed, accuracy) and the coupling characteristics of the transformer, 1-bit on-off (keying) information or multi-bit information can be transmitted in this arrangement. The expected coupling characteristics depend on the physical size of the transformer.

[0069] Accordingly, the lateral coreless transformer 100 includes two sides located in two different voltage domains. The lateral coreless transformer 100 is constructed in such a way as to withstand sufficient voltage and achieve electrical isolation between the two domains while providing magnetic coupling between the two sides of the transformer. This coupling can be utilized via the terminals of the transformer. Additionally, depending on the selected usage scenario, either side can operate as the primary side or the secondary side of the transformer 100. Thus, energy and signals can then be transmitted in either direction. The communication circuit around the transformer 100 can be constructed to exchange between the two transmission directions at any time for two-way communication.

[0070] Further implementations may include one or more additional terminals (multiple taps) on either side of the transformer 100. For example, Figure 5B FIG. shows a schematic diagram of a lateral coreless transformer communication system 500B according to one or more embodiments. Here, the coil 6 includes an additional terminal 6c disposed between the end terminals 6a and 6b and coupled to the communication circuit 50. The additional terminal 6c is entirely disposed within the first voltage domain (e.g., voltage domain A) to maintain electrical isolation. The additional terminal 6c can be used to create a center-tapped transformer as shown, or to create another type of multi-tapped transformer. For the center-tapped configuration, the additional terminal 6c can be connected to the ground potential of its corresponding voltage domain.

[0071] Figure 6A and Figure 6B FIGS. show schematic diagrams of lateral coreless transformer communication systems 600A and 600B according to one or more embodiments, respectively.

[0072] The lateral coreless transformer communication systems 600A and 600B include a lateral coreless transformer 100, which includes coils 6 and 7, a first voltage domain (e.g., voltage domain A) representing the outer side, a second voltage domain (e.g., voltage domain B) representing the inner side, and an isolation region 5 including one or more DTI barriers.

[0073] Here, each of the coils 6 and 7 partially overlaps with the isolation region 5. However, as described above, the lateral spacing between the coils 6 and 7 can be such that neither coil 6 nor coil 7 extends onto / above the isolation region 5. It can be understood from this figure that both the terminals 6a and 6b are entirely within the voltage domain A. Similarly, both the terminals 7a and 7b are entirely within the voltage domain B. Each terminal is coupled to a communication circuit located within its corresponding voltage domain.

[0074] Specifically, voltage domain A includes communication circuits 60a or 60b electrically coupled to terminals 6a and 6b of coil 6. Similarly, voltage domain B includes communication circuit 61 electrically coupled to terminals 7a and 7b of coil 7. In one case, communication circuit 60 can be a transmitter configured to apply a communication signal by modifying the impedance of the input circuit, for example, by selectively shorting the terminals of transmitter coil 6 via switch SW or by selectively connecting tuning impedance Z or simple capacitor C via switch SW. Communication circuit 61 is located on the other side of the transformer. Communication circuit 61 can be a receiver configured to read the impedance on the secondary side and detect the status of transmitters 60a, 60b. This type of configuration can be attractive because it does not require energy on the transmitter side except for controlling switch SW. This type of communication can be used for monolithic isolated opto-emulator gate drivers, but is not limited thereto.

[0075] It should also be understood that communication circuits 60a, 60b can be exchanged with communication circuit 61 such that communication from voltage domain B to voltage domain A can be achieved. Alternatively, communication circuits 60a, 60b and 61 can each include transmitter and receiver circuits for two-way communication. The latter arrangement can be configured to switch between transmission directions in a time-interleaved manner to enable two-way communication.

[0076] Figure 7 A schematic block diagram of an energy transfer circuit 700 using a lateral coreless transformer 100 according to one or more embodiments is shown. Lateral coreless transformer 100 is used to transfer energy or power between two voltage domains in a DC-DC converter application. Energy transfer circuit 700 includes a power supply 70, a driver 71, and a voltage converter 72 electrically coupled to a load.

[0077] On the primary side (e.g., voltage domain A), driver 71 operates in a push-pull mode, flyback mode, or other DC-DC converter mode. Thus, driver 71 includes an appropriate push-pull converter circuit, flyback converter circuit, etc. to supply energy to coil 6 according to the power conversion scheme.

[0078] On the receiver side (e.g., voltage domain B), voltage converter 72 can be a voltage rectifier or voltage multiplier coupled to coil 7. Voltage converter 72 receives the transferred energy received by coil 7 and further converts this energy into the supply voltage required by the load.

[0079] This configuration can be used, for example, to support the DC operation of a bootstrap mode gate driver or to transfer sufficient energy for a low-frequency gate driver (e.g., solid-state relay type), but is not limited thereto.

[0080] Figure 8Schematic block diagram of a power circuit 800 according to one or more embodiments. The power circuit 800 includes a single-phase drive stage 10 (i.e., an inverter leg) and a monolithic gate driver system 20 electrically coupled to the single-phase drive stage 10. However, the single-phase drive stage can be extended to a multi-phase drive state by adding additional inverter legs. Alternatively, it may also be the case that only one high-side switch (i.e., a single high-side gate driver) is driven from a low-voltage domain.

[0081] The single-phase drive stage 10 includes a low-side transistor 11 and a high-side transistor 12 that are controlled to supply a load current ILOAD to one phase of a load (not shown). Freewheeling diodes D1 and D2 coupled to their respective power transistors 11 and 12 are also shown.

[0082] The gate driver system 20 is a high-voltage (HV) gate driver system. The gate driver system 20 includes a low-side (LS) gate driver 21 for driving the low-side transistor switch 11 and a high-side (HS) gate driver 22 for driving the high-side transistor switch 12. As will be described later, the LS gate driver 21 and the HS gate driver 22 are in different voltage domains of the gate driver system 20. In addition, the gate driver system 20 itself is a monolithic device, where each region is formed on the same semiconductor substrate (i.e., substrate 1).

[0083] Both gate drivers 21 and 22 perform gate driving of their respective power transistors 11 and 12 based on digital PWM signals LIN and HIN received from a microcontroller unit (MCU). The PWM signals are control signals received from the MCU at the PWM logic unit 35 of the gate driver 20. The PWM logic unit 35 receives the LIN and HIN signals from the MCU and ensures signal integrity to correctly drive the power bridge. Finally, the corresponding PWM control signals are passed to the corresponding low-side gate driver 21 and high-side gate driver 22, where the PWM signal HIN is sent to the high-side gate driver 22. Then, the low-side gate driver 21 and the high-side gate driver 22 perform gate driving.

[0084] Both gate drivers 21 and 22 respectively include separate pre-driver circuits 26 and 27 and buffers 33 and 34. The pre-driver circuits 26 and 27 are configured to receive a PWM signal and control the on / off states of corresponding first current sources (e.g., source-type FETs) for generating current Io+ based on the PWM signal. Additionally, the pre-driver circuits 26 and 27 are configured to receive a PWM signal and control the on / off states of corresponding second current sources (e.g., drain-type FETs) for generating current Io- based on the PWM signal. The corresponding current sources are provided in the buffers 33 and 34. Thus, the buffers 33 and 34 can each include a pair of complementary FETs for generating an on-current Io+ and an off-current Io- for their respective power transistors 11 and 12. Each of the pre-driver circuits 26 and 27 can also command its respective buffer 33 or 34 to use a certain current capability.

[0085] The low-side gate driver 21 is arranged in a low-side area defined by a medium-voltage domain or a low-voltage domain, while the high-side gate driver is arranged in a high-side area defined by a high-voltage domain. In fact, the gate driver system 20 further includes an isolation area 5 that isolates different voltage domains from each other and can be referred to as an isolation termination area. According to the above-described embodiment, the isolation area 5 includes one or more DTI barriers. Thus, the isolation area 5 provides a voltage isolation barrier between two or more voltage domains.

[0086] The gate driver system 20 can be configured to receive a PWM control signal from the MCU and turn on or off the corresponding transistors 11 and 12 according to the received PWM control signal. For example, during the turn-on process of the corresponding transistor 11 or 12, the gate driver system 20 can be used to provide a (source) gate current Io+ to the gate of the corresponding transistor 11 / 12 to charge the gate. In contrast, during the turn-off process, the gate driver system 20 can be used to draw a (drain) gate current from the gate of the transistor 11 / 12 to discharge the gate.

[0087] Thus, the MCU is electrically coupled to the gate driver system 20 for transmitting information signals and control signals HIN and LIN therebetween, and the gate driver system 20 is electrically coupled to the inverter leg 10 for driving its power transistors.

[0088] Specifically, the MCU is configured to generate PWM control signals LIN and HIN for controlling transistors 11 and 12 respectively and send these control signals to the LV domain 43. For example, the gate driver system 20 is configured to receive instructions from the MCU to drive a load phase (i.e., an inverter leg) connected to voltage VS using the PWM control signals. These PWM control signals are received by the gate driver system 20 at the LV domain 43 (i.e., at the input pins HIN and LIN) and passed through an appropriate logic unit (e.g., the PWM logic unit 35) to the corresponding pre-driver circuits 26 and 27. Buffers 33 and 34 are configured to receive the PWM control signals and drive the corresponding power transistors 11 and 12 via the output terminals HO and LO of the gate driver system 20.

[0089] In Figure 8 In the example shown, there are four regions, including: a high-side region defined by the HV domain 41, a low-side region defined by the medium voltage (MV) domain 42 or the medium voltage domain, a low voltage region defined by the LV domain 43, and a termination region 5. Since the gate driver system 20 is a monolithic device, the four regions 5, 41, 42, and 43 are monolithically constructed into a single integrated circuit. In a monolithic solution, the termination region (i.e., the isolation region 5) within the die is used to isolate different voltage domains. Here, transformers 100-1 and 100-2 can be used to send electrical signals between different voltage domains.

[0090] The LV domain 43 is a region that includes low voltage devices, the MV domain 42 is a region that includes medium voltage devices, and the HV domain 41 is a region that includes high voltage devices. For example, the low voltage devices can be supplied with 0V to 5V, the medium voltage devices can be supplied with 0V to 30V, and the high voltage devices can be supplied with more than 100V (e.g., 120V to 160V). The voltage domains are not limited to these voltage ranges but are intended to provide an example of an implementation. However, the general principle for different voltage domain levels at different voltage ratings remains the same.

[0091] The isolation region 5 is represented by a dashed line between different voltage domains. The isolation region 5 isolates different voltage domains from each other. Thus, the isolation region 5 provides a voltage isolation barrier between different voltage domains. The isolation region 5 can be a single continuous region or can include two or more regions for separating various voltage domains.

[0092] The gate driver system 20 itself is a monolithic device, where each region is formed on the same semiconductor substrate (i.e., substrate 1).

[0093] Communication between voltage domains is achieved through lateral coreless transformers 100-1 and 100-2, which have features equivalent to those described above for the lateral coreless transformer 100. A communication circuit (e.g., communication circuits 50 and 51, 60a and 61, or 60b and 61) can be incorporated into the PWM logic unit 35 and the pre-drivers 26 and 27, where the pre-drivers 26 and 27 are coupled to the lateral coreless transformers 100-1 and 100-2. Each of the lateral coreless transformers 100-1 and 100-2 includes at least two coils (e.g., coils 6 and 7).

[0094] In one example, the LV domain 43 provides information from the PWM logic unit 35 to the gate driver 22 in the other voltage domain 41 and the gate driver 21 in the other voltage domain 42 via the lateral coreless transformers 100-1 and 100-2, respectively. Thus, the transformer 100-1 is configured to send an electrical signal (e.g., a PWM control signal) from the PWM logic unit 35 to the gate driver 22 (i.e., from the first voltage domain to the second voltage domain). Additionally, the transformer 100-2 is configured to send an electrical signal (e.g., a PWM control signal) from the PWM logic unit 35 to the gate driver 21 (i.e., from the first voltage domain to the third voltage domain).

[0095] It should also be understood that the corresponding components of the MV domain 42 and the LV domain 43 can be combined into the same voltage domain (e.g., the LV domain) such that they are integrated in the same area of the die. Thus, only the transformer 100-1 is required for transmission between two existing voltage domains (e.g., the LV domain 43 and the HV domain 41).

[0096] Although Figure 8 an example including three isolated voltage domains is shown, some embodiments can have a configuration where there is no isolation between the MV domain 42 and the LV domain 43. In other words, there can be no Figure 8 portion of the isolation region 5 shown between the MV domain 42 and the LV domain 43. In this case, to isolate the HV domain 41 from the other voltage domains 42 and 43, the isolation region 5 remains between the HV domain 41 and the other voltage domains 42 and 43.

[0097] Additionally, some embodiments may have a configuration in which the LV domain 43 is entirely disposed within the MV domain 42. In this case, in order to isolate the LV domain 43 from the MV domain 42, the LV domain 43 may be a voltage island completely surrounded by the isolation region 5. Additionally, in order to isolate the HV domain 41 from the MV domain 42, the isolation region 5 remains between the HV domain 41 and the MV voltage domain 42. Thus, the LV domain 43 is isolated from the MV domain 42, and the HV domain 41 is isolated from the MV domain 42. Of course, the LV domain 43 and the HV domain 41 are also isolated from each other by two separate isolation regions 5.

[0098] As described herein, VB refers to the high-side floating power supply voltage terminal; VS refers to the high-side floating ground voltage terminal; VDD or VCC refers to the low-side fixed power supply voltage terminal and the logic fixed power supply voltage terminal; VSS or VEE refers to the low-side ground voltage terminal; HO refers to the high-side floating output voltage terminal; LO refers to the low-side output voltage terminal; DC+ refers to the DC link positive electrode; DC- refers to the DC link negative electrode; and HIN and LIN refer to the pins for receiving the logic input voltage (i.e., control signal) from the MCU.

[0099] In one example, the gate driver system 20 may operate in a common-mode manner at 130V with a floating power supply having a maximum operating range of 30V. In this example, VB operates at a maximum value of 160V, VS operates at a maximum value of 130V, VCC operates at 30V, and VSS operates at 0V. Specifically, when the transistor 12 is turned on (and the transistor 11 is turned off), VS is equal to DC+, and when the transistor 11 is turned on (and the transistor 12 is turned off), VS is equal to DC-. In both cases, due to the bootstrap capacitor 24, VB remains at a voltage substantially 30V higher than VS. The bootstrap diode 25 can be used to charge the bootstrap capacitor 24 via an electrical coupling to VCC. The bootstrap diode 25 may be external to the gate driver system 20 or integrated within the gate driver system 20. The bootstrap diode 25 may have a low resistivity to charge the bootstrap capacitor 24 quickly. Thus, in the case where DC+ is 130V (equal to the common-mode voltage), the low-side (external) power supply voltage supplying VCC can be set to 30V, and the high-side power supply voltage terminal VB can operate at a maximum voltage of 160V. DC- is connected to ground / VSS, but this is not necessary.

[0100] In another example, the gate driver system 20 can operate in a 1500V common-mode manner with a floating power supply having a maximum operating range of 35V. In this example, VB operates at a maximum of 1535V, VS operates at a maximum of 1500V, VCC operates at 35V, and VSS operates at 0V. In particular, when transistor 12 is turned on (and transistor 11 is turned off), VS is equal to DC+, and when transistor 11 is turned on (and transistor 12 is turned off), VS is equal to DC-. In both cases, due to the bootstrap capacitor 24, VB remains at a voltage substantially 35V higher than VS. Thus, in the case where DC+ is 1500V (equal to the common-mode voltage), the low-side (external) power supply voltage supplying VCC can be set to 35V, and the high-side power supply voltage terminal VB can operate at a maximum voltage of 1535V. DC- is connected to ground / VSS, but this is not necessary.

[0101] It will be understood that the common-mode voltage and the maximum operating range of the floating power supply are configurable and can be set to different voltages provided in the above two examples, including a common-mode voltage between 130V and 1500V, less than 30V, or greater than 1500V.

[0102] The above voltages are set such that the high-side voltage domain operates in a higher voltage or power domain compared to the low-side voltage domain. Additionally, the medium voltage or power domain is set at an intermediate level between the HV domain and the LV domain.

[0103] The HV domain 41 includes a pre-driver circuit 27 and a buffer 34 coupled to VS and VB.

[0104] The LV domain 43 includes a PWM logic unit 35 and a transmitter circuit that sends communication signals to other voltage domains.

[0105] The MV domain 42 includes a pre-driver circuit 26 and a buffer 33. The MV domain 42 also includes a power management unit (PMU) 37 powered by VSS and VCC. The PMU 37 is a microcontroller that manages and regulates power functions. For starters, the PMU 37 converts the medium power supply voltage (i.e., VCC) to a low power supply voltage (e.g., 5V) that is supplied to the LV domain 43. In particular, the PMU 37 supplies this low power supply voltage to the PWM logic unit 35. The PWM logic unit 35 uses the low power supply voltage to perform its functions. Secondly, the PMU 37 is configured to monitor for faults and turn off the power supply to the PWM logic unit 35 in the event of an occurrence. By turning off the power supply to the PWM logic unit 35, the PWM logic unit 35 is disabled and the high-side transistor 12 is turned off.

[0106] As combined with Figure 7The energy transfer between the described voltage domains can be achieved by the lateral coreless transformer 100-3, which has the same characteristics as those described above for the lateral coreless transformer 100. The lateral coreless transformer 100-3 serves as a DC-DC converter to transfer energy from the MV domain 42 to the HV domain 41, such that power is provided through VCC and this power is delivered to VB via the lateral coreless transformer 100-3.

[0107] Due to the low amount of electric power transferred by the lateral coreless transformer 100-3, the lateral coreless transformer 100-3 can be used to support a bootstrap operation driver to achieve a permanently-on high side, also known as a 100% duty cycle operation that cannot be managed solely by the bootstrap diode 25, because the bootstrap diode 25 operates in a blocking mode at least part of the time. That is, when the bootstrap diode 25 is in the blocking mode (i.e., the voltage in the HV domain is higher than the voltage in the LV domain), the bootstrap diode 25 does not transfer energy. Therefore, by transferring sufficient energy to maintain the operation of the HV domain circuit (i.e., the HS gate driver 22), the lateral coreless transformer 100-3 can be used to support the bootstrap diode 25, while this solution will still rely on the bootstrap diode 25 to transfer the most important part of the energy required by the HV domain circuit to drive the relevant load. In this case, the lateral coreless transformer 100-3 is electrically coupled in parallel to the bootstrap diode 25 between VCC and VB.

[0108] Therefore, depending on the rated voltage of the HV domain 41, the lateral coreless transformer 100-3 can be used alone or in combination with the bootstrap diode to deliver power to VB. In other words, the bootstrap diode 25 can be optional in some cases.

[0109] Although various embodiments have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention that will achieve some of the advantages of the concepts disclosed herein. For example, although the above embodiments are directed to transmitters using coreless transformers (i.e., inductive coupling transmission), the transformers 60 and 61 can be replaced with different types of transmitters, including capacitive transmitters that use capacitive coupling for data transmission. Therefore, other transmitter types can be used, and it will be apparent to those skilled in the art that other components performing the same or similar functions can be appropriately replaced. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present invention. It should be mentioned that the features explained with reference to specific figures can be combined with the features of other figures, even in those cases where it is not explicitly mentioned. Such modifications to the overall inventive concept are intended to be covered by the appended claims and their legal equivalents.

[0110] In addition, the appended claims are hereby incorporated into the detailed description, where each claim can independently serve as a separate exemplary embodiment. Although each claim can independently serve as a separate exemplary embodiment, it should be noted that although a dependent claim may refer to a specific combination with one or more other claims in the claims, other exemplary embodiments may also include a combination of the dependent claim with the subject matter of each other independent claim or dependent claim. Such combinations are presented herein unless a specific combination is not intended. In addition, even if a claim does not directly depend on an independent claim, the features of that claim are intended to be included in any other independent claim.

[0111] It should also be noted that the methods disclosed in the specification or claims can be implemented by a device having means for performing each of the respective actions of these methods. For example, the techniques described in this disclosure can be implemented at least in part in hardware, software, firmware, or any combination thereof (including any combination of a computer program on a non-transitory computer-readable recording medium, a computing system, and an integrated circuit). For example, aspects of the described techniques can be implemented within one or more processors, which include one or more microprocessors, DSPs, ASICs, or any other equivalent integrated or discrete logic circuitry, and any combination of such components.

[0112] In addition, it should be understood that the disclosure of a plurality of actions or functions in the specification or claims may not be construed as being in a specified order. Thus, unless such actions or functions are non-interchangeable for technical reasons, the disclosure of a plurality of actions or functions does not limit these actions or functions to a particular order. In addition, in some embodiments, a single action may include or may be decomposed into multiple sub-actions. Unless explicitly excluded, these sub-actions may be included and are part of the disclosure of that single action.

Claims

1. A multi-voltage domain device, comprising: A semiconductor layer, which includes a first main surface and a second main surface disposed opposite to the first main surface, wherein the semiconductor layer includes: A first region, which includes a first circuit operating in a first voltage domain, A second region, which includes a second circuit operating in a second voltage domain different from the first voltage domain, and An isolation region, which electrically isolates the first region and the second region in a lateral direction extending parallel to the first main surface and the second main surface, Wherein the isolation region includes at least one deep trench isolation barrier, and each deep trench isolation barrier in the deep trench isolation barriers extends vertically from the first main surface to the second main surface; and A layer stack, which is disposed on the first main surface of the semiconductor layer, and the layer stack includes: a plurality of sub-insulator layers, which form a stacked insulator layer; a first coil, which is disposed in the stacked insulator layer; and a second coil, which is disposed in the stacked insulator layer and is laterally separated from the first coil in the lateral direction by the stacked insulator layer, Wherein the first coil and the second coil are magnetically coupled to each other in the lateral direction, Wherein the first coil includes at least two first terminals vertically disposed above the first region and electrically coupled to the first circuit, and Wherein the second coil includes at least two second terminals vertically disposed above the second region and electrically coupled to the second circuit.

2. The multi-voltage domain device according to claim 1, wherein, The first coil and the second coil are configured to transmit a communication signal between the first circuit and the second circuit across the isolation region via magnetic coupling therebetween.

3. The multi-voltage domain device according to claim 1, wherein: The first circuit includes a transmitter, which is configured to generate a communication signal and transmit the communication signal to the first coil, and The second circuit includes a receiver, which is configured to receive the communication signal from the second coil, wherein the communication signal is transmitted across the isolation region via magnetic coupling between the first coil and the second coil.

4. The multi-voltage domain device according to claim 1, wherein: The first region includes a first edge region surrounding the isolation region, The second region includes a second edge region surrounded by the isolation region, such that the first edge region and the second edge region are laterally separated, The first coil is vertically disposed above the first edge region, The second coil is vertically disposed above the second edge region, and The first coil surrounds the second coil.

5. The multi-voltage domain device according to claim 4, wherein: The first coil is constrained within the vertical extension range of the first edge region, and The second coil is constrained within the vertical extension range of the second edge region.

6. The multi-voltage domain device according to claim 4, wherein The first coil and the second coil are concentric coils.

7. The multi-voltage domain device according to claim 6, wherein, The isolation region is concentric with respect to the first coil and the second coil.

8. The multi-voltage domain device according to claim 1, wherein, The minimum lateral spacing between the first coil and the second coil is equal to or greater than the maximum lateral dimension of the isolation region.

9. The multi-voltage domain device according to claim 1, wherein: The first coil is entirely disposed within a first region defined by the vertical extent of the first area of the layer stack, and The second coil is entirely disposed within a second region defined by the vertical extent of the second area of the layer stack.

10. The multi-voltage domain device according to claim 1, wherein: The first coil is entirely disposed within a first region defined by the vertical extent of the first area of the layer stack, and The second coil extends from a second region defined by the vertical extent of the second area of the layer stack and further extends partially above the isolation region in the lateral direction.

11. The multi-voltage domain device according to claim 1, wherein: The first coil extends from a first region defined by the vertical extent of the first area of the layer stack and further extends partially above the isolation region in the lateral direction, and The second coil extends from a second region defined by the vertical extent of the second area of the layer stack and further extends partially above the isolation region in the lateral direction.

12. The multi-voltage domain device according to claim 1, wherein: The first coil is entirely disposed within a first region defined by the vertical extent of the first area of the layer stack, and The second coil extends from a second region defined by the vertical extent of the second area of the layer stack and further extends laterally above the isolation region into the first region defined by the vertical extent of the first area of the layer stack.

13. The multi-voltage domain device according to claim 1, wherein, The layer stack further comprises: A third coil disposed within the stacked insulator layer and laterally separated from the first coil and the second coil, A fourth coil disposed within the stacked insulator layer and laterally separated from the first coil, the second coil, and the third coil, Wherein the third coil comprises at least two third terminals disposed vertically above the first area and electrically coupled to the first circuit, and Wherein the fourth coil comprises at least two fourth terminals disposed vertically above the second area and electrically coupled to the second circuit.

14. The multi-voltage domain device according to claim 13, wherein: The layer stack further comprises an end-open dummy coil, the end-open dummy coil comprising windings that are vertically interleaved with the windings of the second coil to form a shielding wall configured to block an electric field, and The second coil is disposed laterally between the first coil and the fourth coil, and The first coil is disposed laterally between the third coil and the second coil.

15. The multi-voltage domain device according to claim 14, wherein: The third coil is entirely disposed within a first region defined by the vertical extent of the first area of the layer stack, and The fourth coil is entirely disposed within a second region of the layer stack defined by the vertical extent of the second region.

16. The multi-voltage domain device according to claim 1, further comprising: A wafer insulator layer including a third major surface; Wherein, a second major surface of the semiconductor layer is disposed on the third major surface of the wafer insulator layer, and each of the at least one deep trench isolation barrier extends vertically from the first major surface to the third major surface.

17. The multi-voltage domain device according to claim 16, further comprising: A silicon-on-insulator wafer including the semiconductor layer and the wafer insulator layer.

18. The multi-voltage domain device according to claim 1, wherein, The multi-voltage domain device is a monolithic device.

19. The multi-voltage domain device according to claim 1, wherein The first coil and the second coil are configured to transfer power from the first circuit to the second circuit across the isolation region via magnetic coupling therebetween to operate the second circuit.

20. The multi-voltage domain device according to claim 1, further comprising: A bootstrap capacitor configured to supply main power corresponding to the second voltage domain to the second circuit; And A bootstrap diode coupled to a voltage source of the first circuit and the bootstrap capacitor and coupled between the voltage source of the first circuit and the bootstrap capacitor, wherein the bootstrap diode is configured to charge the bootstrap capacitor to provide the main power, Wherein, the first coil and the second coil are coupled to the voltage source of the first circuit and the bootstrap capacitor and coupled between the voltage source of the first circuit and the bootstrap capacitor, and the first coil and the second coil are in parallel with the bootstrap diode and are configured to transfer supplementary power from the first circuit to the second circuit across the isolation region to supply power to the second circuit.

21. The multi-voltage domain device according to claim 20, wherein, The main power and the supplementary power enable the second circuit to operate with a 100% duty cycle.

22. A gate driver integrated circuit, comprising: A semiconductor layer including a first major surface and a second major surface disposed opposite to the first major surface, wherein the semiconductor layer includes: A high-side region including a first circuit operating in a first voltage domain through a first pair of power terminals including a first low power terminal and a first high power terminal; A low-side region including a second circuit operating in a second voltage domain lower than the first voltage domain through a second pair of power terminals including a second low power terminal and a second high power terminal; and An isolation region electrically isolating the high-side region and the low-side region in a lateral direction extending parallel to the first major surface and the second major surface, Wherein, the isolation region includes at least one deep trench isolation barrier, and each of the deep trench isolation barriers extends vertically from the first major surface to the second major surface; and A layer stack is disposed on a first main surface of the semiconductor layer. The layer stack includes: a plurality of sub-insulator layers that form a stacked insulator layer; a first coil disposed in the stacked insulator layer; and a second coil disposed in the stacked insulator layer and laterally separated from the first coil in the lateral direction by the stacked insulator layer, wherein the first coil and the second coil are magnetically coupled to each other in the lateral direction, wherein the first coil includes at least two first terminals that are vertically disposed above the high-side region and electrically coupled to the first circuit, and wherein the second coil includes at least two second terminals that are vertically disposed above the low-side region and electrically coupled to the second circuit.

23. A multi-voltage domain device, comprising: A semiconductor layer including a first main surface and a second main surface disposed opposite to the first main surface. The semiconductor layer includes: A first region including a first circuit operating in a first voltage domain, A second region including a second circuit operating in a second voltage domain different from the first voltage domain, and An isolation region that electrically isolates the first region and the second region in a lateral direction extending parallel to the first main surface and the second main surface, wherein the isolation region includes at least one deep trench isolation barrier, and each deep trench isolation barrier in the deep trench isolation barriers extends vertically from the first main surface to the second main surface; and A layer stack is disposed on the first main surface of the semiconductor layer. The layer stack includes: a plurality of sub-insulator layers that form a stacked insulator layer; a first coil disposed in the stacked insulator layer; a second coil disposed in the stacked insulator layer and laterally separated from the first coil in the lateral direction by the stacked insulator layer; a third coil disposed in the stacked insulator layer and separated from the first coil and the second coil in the lateral direction by the stacked insulator layer; and a fourth coil disposed in the stacked insulator layer and separated from the first coil, the second coil, and the third coil in the lateral direction by the stacked insulator layer, wherein the first coil and the second coil are magnetically coupled to each other in the lateral direction, wherein the third coil and the fourth coil are magnetically coupled to each other in the lateral direction, wherein the first coil includes at least two first terminals that are vertically disposed above the first region and electrically coupled to the first circuit, wherein the second coil includes at least two second terminals that are vertically disposed above the second region and electrically coupled to the second circuit, wherein the third coil includes at least two third terminals that are vertically disposed above the first region and electrically coupled to the first circuit, and wherein the fourth coil includes at least two fourth terminals that are vertically disposed above the second region and electrically coupled to the second circuit.

24. The multi-voltage domain device according to claim 23, wherein: The first coil and the second coil are configured to transmit communication signals between the first circuit and the second circuit across the isolation region via magnetic coupling therebetween, and the third coil and the fourth coil are configured to transfer power from the first circuit to the second circuit across the isolation region via magnetic coupling therebetween to operate the second circuit.

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