Method of forming memory and three-dimensional memory

Abstract

This application provides a method for forming a memory and a three-dimensional memory. The method includes: providing a substrate, the substrate including a substrate and a stacked structure, the stacked structure being located on an exposed surface of the substrate, the stacked structure including alternating sacrificial layers and insulating dielectric layers; forming a patterned mask layer on the exposed surface of the stacked structure, the patterned mask layer including a slit region and an edge region at least on one side of the slit region, the slit region including a plurality of channels extending to the surface of the stacked structure, and the edge region including a first groove and / or a hole; etching the stacked structure using the patterned mask layer as a mask to form a plurality of gate line slits; and removing the patterned mask layer. This method for forming a memory effectively alleviates problems such as etching stoppage and tilting of the gate line slits at the edges, ensuring good etching effect of the gate line slits at the plane edges, thereby ensuring good overall device performance.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a method for forming a memory and a three-dimensional memory. Background Technology

[0002] In 3D NAND manufacturing processes, such as Figure 1 As shown, each die includes four plane regions. The gate lines at the plane edge have a severe loading effect during the etching process, which often leads to abnormal stops and tilting problems during the etching process of the gate line slits. This results in poor gate line slit performance and thus affects device performance.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] This application provides a method for forming a memory and a three-dimensional memory to solve the problem of poor etching effect of gate line slits at the edge of a plane.

[0005] According to one aspect of the present invention, a method for forming a memory is provided, comprising: providing a substrate, the substrate including a substrate and a stacked structure, the stacked structure being located on an exposed surface of the substrate, the stacked structure including alternating sacrificial layers and insulating dielectric layers; forming a patterned mask layer on the exposed surface of the stacked structure, the patterned mask layer including a slit region and an edge region located at least on one side of the slit region, the slit region including a plurality of channels extending through to the surface of the stacked structure, the edge region including a first groove and / or a hole; etching the stacked structure using the patterned mask layer as a mask to form a plurality of gate line slits; and removing the patterned mask layer.

[0006] Optionally, the critical dimension of the first groove is smaller than the critical dimension of the channel, and the critical dimension of the hole is smaller than the critical dimension of the channel.

[0007] Optionally, the key dimensions of each of the channels are the same.

[0008] Optionally, there are multiple slit areas and multiple edge areas, with some of the edge areas located between two adjacent slit areas and the other edge areas located at the edges of the slit areas.

[0009] Optionally, forming a patterned mask layer on the exposed surface of the stacked structure includes: sequentially forming a mask material layer and a photoresist layer on the exposed surface of the stacked structure; removing a portion of the photoresist layer to form a plurality of first openings and at least one second opening penetrating to the surface of the mask material layer on the surface of the photoresist layer, the remaining photoresist layer being a photoresist portion; etching the mask material layer using the photoresist portion as a mask to form the patterned mask layer, wherein the first opening corresponds to the channel, the second opening corresponds to the first groove and / or hole; and removing the photoresist portion.

[0010] Optionally, forming a mask material layer on the exposed surface of the stacked structure includes: forming a first sub-mask material layer on the exposed surface of the stacked structure; and forming a second sub-mask material layer on the exposed surface of the first sub-mask material layer.

[0011] Optionally, the material of the first sub-mask layer includes carbon, and the material of the second sub-mask layer includes silicon oxynitride.

[0012] Optionally, after etching the stacked structure using the patterned mask layer as a mask to form multiple gate line slits, the method for forming the memory further includes: replacing all the sacrificial layers with multiple conductive layers to form a stacked structure, the stacked structure including the conductive layers and the insulating dielectric layer arranged alternately.

[0013] Optionally, replacing all the sacrificial layers with multiple conductive layers includes: removing each of the sacrificial layers with phosphoric acid to form multiple second grooves; and filling the second grooves with a conductive material to form the conductive layer.

[0014] According to another aspect of the present invention, a three-dimensional memory is also provided, the three-dimensional memory including a substrate and a plurality of gate line slits, wherein the substrate includes a substrate and a stacked structure, the stacked structure being located on an exposed surface of the substrate, the stacked structure including alternately disposed sacrificial layers and insulating dielectric layers; each of the gate line slits is located in the substrate, the gate line slits penetrating the stacked structure to the surface of the substrate, the gate line slits having the same depth, the aperture of the gate line slit located in a first region being a first aperture, the aperture of the gate line slit located at the edge of a second region being a second aperture, the absolute value of the difference between the first aperture and the second aperture being less than or equal to 1 nm, the first region being the edge of the substrate, and the second region being the region of the substrate excluding the first region.

[0015] According to an embodiment of the present invention, in the method for forming the memory, the patterned mask layer includes a slit region and an edge region located at least on one side of the slit region. The slit region includes a plurality of channels extending to the surface of the stacked structure, and the edge region includes a first groove and / or a hole, i.e., including three cases, the first being, such as... Figure 9 As shown, the edge region includes a first groove; the second type, as... Figure 10 As shown, the edge region includes holes; the third type, such as... Figure 11 As shown, the edge region includes a first groove and a hole. Using the patterned mask layer as a mask, the stacked structure is etched to obtain multiple gate line slits, each corresponding to a channel. The memory formation method of this application, by forming a first groove and / or a hole in the edge region—that is, setting the first groove and / or a hole on the outer edge of the gate line slits at the edge—makes the etching environment of the gate line slits at the edge similar to that of the gate line slits at the non-edge (i.e., internal) areas during the etching process. This ensures that the structure of the etched gate line slits at the edge is essentially consistent with that of the internal gate line slits, guaranteeing that the critical dimensions of the gate line slits at the edge meet the corresponding process requirements. This mitigates the impact of etching byproducts on the etching of the gate line slits at the edge, alleviates the load effect, and effectively mitigates problems such as etching stoppage and tilting of the gate line slits at the edge. This ensures a better etching effect for the gate line slits at the plane edge, thereby guaranteeing better overall device performance. Furthermore, since the etching does not proceed downwards from the first groove and the hole during the etching of the layer structure, meaning that the first groove and the hole do not form a pattern, the influence of the first groove and the hole on downstream processes is avoided. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 This shows a top view of the grain structure in the 3D NAND fabrication process;

[0018] Figure 2 A schematic flowchart illustrating the method for forming a memory according to an embodiment of this application is shown.

[0019] Figures 3 to 8 The diagram shows a schematic representation of the structure formed by the method of forming the memory according to this application after different process steps;

[0020] Figures 9 to 11 Top views of the graphical mask layers according to embodiments of this application are shown respectively.

[0021] The above figures include the following reference numerals:

[0022] 100. Substrate; 101. Sacrificial layer; 102. Insulating dielectric layer; 103. Channel; 104. First groove; 105. Hole; 106. Gate line slit; 107. First opening; 108. Second opening; 109. Mask material layer; 110. Conductive layer; 200. Slit region; 201. Edge region. Detailed Implementation

[0023] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0024] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0029] In one typical embodiment of this application, a method for forming a memory and a three-dimensional memory are provided.

[0030] According to an embodiment of this application, a method for forming a memory is provided.

[0031] Figure 2 This is a flowchart of a method for forming a memory according to an embodiment of this application. For example... Figure 2 As shown, the method includes the following steps:

[0032] Step S101, as follows Figure 3 As shown, a substrate is provided, the substrate including a substrate 100 and a stacked structure, the stacked structure being located on the exposed surface of the substrate 100, the stacked structure including an alternately disposed sacrificial layer 101 and an insulating dielectric layer 102.

[0033] Step S102: A patterned mask layer is formed on the exposed surface of the aforementioned stacked structure. The patterned mask layer includes a slit region and an edge region located at least on one side of the slit region. The slit region includes a plurality of channels 103 extending through the surface of the stacked structure. The edge region includes a first groove 104 and / or a hole 105, resulting in... Figure 5 The structure shown;

[0034] Step S103, as follows Figure 6 As shown, using the above-mentioned patterned mask layer as a mask, the above-mentioned stacked structure is etched to form a plurality of gate line slits 106.

[0035] Step S104: Remove the above patterned mask layer to obtain the following result. Figure 7 The three-dimensional memory shown.

[0036] In the above-described method for forming the memory, the patterned mask layer includes a slit region and an edge region located at least on one side of the slit region. The slit region includes a plurality of channels extending to the surface of the stacked structure. The edge region includes a first groove and / or a hole, i.e., it includes three cases, the first being, such as... Figure 9 As shown, the aforementioned edge region includes a first groove; the second type, as... Figure 10 As shown, the aforementioned edge area includes holes; the third type, such as... Figure 11As shown, the aforementioned edge region includes a first groove and a hole. Using the aforementioned patterned mask layer as a mask, the aforementioned stacked structure is etched to obtain multiple gate line slits, each corresponding to one of the aforementioned channels. The method for forming the aforementioned memory in this application, by forming the first groove and / or hole in the aforementioned edge region—that is, by setting the first groove and / or hole on the outer edge of the gate line slit at the edge—makes the etching environment of the gate line slit at the edge similar to that of the gate line slits at the non-edge (i.e., internal) areas during the etching process. This ensures that the structure of the etched gate line slits at the edge is essentially consistent with that of the internal gate line slits, guaranteeing that the critical dimensions of the gate line slits at the edge can meet the corresponding process requirements. This mitigates the influence of etching byproducts on the etching of the gate line slits at the edge, alleviates the load effect, and effectively mitigates problems such as etching stoppage and tilting of the gate line slits at the edge. This ensures a better etching effect for the gate line slits at the plane edge, thereby guaranteeing better overall device performance. Furthermore, since the etching of the above-mentioned layer structure does not proceed downwards from the first groove and the above-mentioned hole, that is, the first groove and the above-mentioned hole will not form a pattern, the influence of the first groove and the hole on the downstream process is avoided.

[0037] It should be noted that the aforementioned edge region corresponds to the area in the plane edge of the aforementioned memory where no gate line slits are provided.

[0038] Specifically, the etching environment of the gate line slits at the edge and the gate line slits at the inside is similar during the etching process, which refers to the following aspects: First, the presence of the first groove and / or hole makes the height difference of the patterned mask layer between the edge region and the slit region relatively small, thus ensuring that the amount of etching reactants entering the gate line slits at the inside and the gate line slits at the edge is basically the same during the etching process; Second, based on the consistent height of the patterned mask layer, the amount of etching by-products discharged from the gate line slits at the inside and the gate line slits at the edge during the etching process is also roughly the same, thus making the influence of etching by-products on the etching of the gate line slits at the inside and the gate line slits at the edge basically the same.

[0039] According to a specific embodiment of this application, the critical dimension of the first groove is smaller than the critical dimension of the channel, and the critical dimension of the hole is smaller than the critical dimension of the channel. Thus, the first groove and the hole do not penetrate to the surface of the stacked structure, thereby ensuring that the subsequent formation of multiple gate line slits does not affect the stacked structure corresponding to the edge region. In other words, the first groove and the hole do not form a pattern in the stacked structure, further avoiding any impact on downstream processes.

[0040] To mitigate the loading effect of gate line slits at the plane edge, some process parameters are sacrificed by designing the critical dimensions of the gate line slits at the edge to differ from those inside the plane. This restricts the process settings for each gate line. However, in another specific embodiment of this application, using the aforementioned formation method, the critical dimensions of each channel are identical. This eliminates the need to consider the loading effect, allowing for more stringent process settings and ensuring better process performance in 3D NAND fabrication. Specifically, the aforementioned critical dimensions include hole depth, opening diameter, and bottom diameter.

[0041] To further ensure a better mitigation of the load effect and to further ensure better overall device performance, in another specific embodiment of this application, such as... Figures 9 to 11 As shown, there are multiple slit regions 200, each slit region 200 including multiple channels 103. There are multiple edge regions 201, some of which include multiple first grooves 104, some of which include multiple holes 105, and some of which include multiple first grooves 104 and multiple holes 105. Some of the edge regions 201 are located between two adjacent slit regions 200, while the other edge regions 201 are located at the edges of the slit regions 200. In a more specific embodiment, the edge regions surround the slit regions, that is, the edges of the slit regions are all provided with edge regions. This can further alleviate the load effect and further avoid the problem of poor etching effect of the gate line slits at the edges.

[0042] In practical applications, those skilled in the art can provide multiple channels and / or multiple holes in each of the aforementioned edge areas, so that all the channels and / or all the holes surround the aforementioned slit area.

[0043] The patterned mask layer of this application can be formed using any feasible method in the prior art. Those skilled in the art can determine a suitable method to form the patterned mask layer of this application based on the actual situation. To form the patterned mask layer more simply and quickly, according to another specific embodiment of this application, a patterned mask layer is formed on the exposed surface of the above-mentioned stacked structure, including: as... Figure 4 and Figure 5As shown, a mask material layer and a photoresist layer are sequentially formed on the exposed surface of the above-mentioned stacked structure; a portion of the photoresist layer is removed to form a plurality of first openings 107 and at least one second opening 108 extending through to the surface of the mask material layer on the surface of the photoresist layer, and the remaining photoresist layer is a photoresist portion; the mask material layer 109 is etched using the photoresist portion as a mask to form the above-mentioned patterned mask layer, wherein the first opening 107 corresponds to the above-mentioned channel 103, and the second opening 108 corresponds to the above-mentioned first groove 104 and / or hole 105; the above-mentioned photoresist portion is removed.

[0044] Specifically, the critical dimension of the first opening is larger than that of the second opening. Thus, during the etching of the mask material layer downward through the first and second openings, more etching reactants enter the first opening than the second opening. Furthermore, during the etching process, the amount of reaction byproducts discharged from the channel is greater than that discharged from the first groove and the hole. This ensures that the mask material layer is not etched through when the first groove and the hole are formed, but can be etched through when the channel is formed.

[0045] According to another specific embodiment of this application, forming a mask material layer on the exposed surface of the above-mentioned stacked structure includes: forming a first sub-mask material layer on the exposed surface of the above-mentioned stacked structure; and forming a second sub-mask material layer on the exposed surface of the first sub-mask material layer. Of course, the mask material layer of this application is not limited to the above-described forming method, but may also be formed by other methods. Those skilled in the art can select appropriate materials and processes according to actual conditions to form the mask material layer of this application.

[0046] To form a more stable mask material layer and ensure better photolithography and etching effects, in one specific embodiment of this application, the material of the first sub-mask layer includes carbon, and the material of the second sub-mask layer includes silicon oxynitride. In a more specific embodiment, the first sub-mask layer is a carbon layer, and the second sub-mask layer is a silicon oxynitride layer.

[0047] There are many methods for forming the photoresist layer described above in this application. Those skilled in the art can choose an appropriate method to form the photoresist layer described above in this application based on the actual situation.

[0048] In practical applications, a substrate is provided, including: providing a substrate; and alternately disposing sacrificial layers and insulating dielectric layers on the exposed surface of the substrate to form a stacked structure.

[0049] It should be noted that each step in the above-described substrate formation embodiments can be implemented using feasible methods in the prior art. The substrate in the above-described substrate can be selected according to the actual needs of the device, and may include a silicon substrate, a germanium substrate, a silicon-germanium composite, an SOI (Silicon on Insulator) substrate, or a GOI (Germanium on Insulator) substrate. In other embodiments, the substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Sand-Germanium on Silicon). Of course, it may also be other substrates feasible in the prior art.

[0050] In one specific embodiment, after etching the stacked structure using the patterned mask layer as a mask to form multiple gate line slits, the method for forming the memory further includes: replacing all the sacrificial layers with multiple conductive layers to form a stacked structure, wherein the stacked structure includes alternately arranged conductive layers 110 and insulating dielectric layers 102, resulting in... Figure 8 The structure shown.

[0051] According to another specific embodiment of this application, replacing all of the above-mentioned sacrificial layers with multiple conductive layers includes: removing each of the above-mentioned sacrificial layers with phosphoric acid to form multiple second grooves; filling the second grooves with conductive material to form the above-mentioned conductive layers.

[0052] In other embodiments, the alternatingly stacked conductive layer and insulating dielectric layer can be directly deposited on the substrate without a gate replacement process.

[0053] In practical applications, the sacrificial layer and the insulating dielectric layer can be made of conventional materials available in the prior art. In another specific embodiment of this application, the sacrificial layer is a silicon nitride layer, the insulating dielectric layer is a silicon oxide layer, and the conductive layer is made of tungsten.

[0054] In one specific embodiment, during the etching process to form the gate line slit, the sacrificial layer and the insulating dielectric layer have a dry etching selectivity of almost 1:1. When the sacrificial layer parallel to the substrate direction is replaced with a conductive layer, the sacrificial layer and the insulating dielectric layer have a high wet etching selectivity, for example, 30:1 or even higher. The number of layers in the stacked structure can be determined according to specific needs.

[0055] These structural layers can be formed by one or more of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and / or other known crystal growth processes.

[0056] It should also be noted that the three-dimensional memory in this application can be a memory or a storage unit of a memory.

[0057] The aforementioned stacked structure of this application can be formed by a single stacking and a single etching, or by multiple stackings and multiple etchings.

[0058] According to another aspect of the present invention, a three-dimensional memory is also provided, wherein the three-dimensional memory is manufactured using any of the above-described memory forming methods.

[0059] The aforementioned three-dimensional memory is fabricated using any of the aforementioned memory formation methods. These methods involve forming a first groove and / or hole in the edge region, specifically, setting the first groove and / or hole at the outer edge of the gate line slit. This ensures that the etching environment of the gate line slit at the edge is similar to that of the gate line slits outside the edge (i.e., inside) during etching. This results in the etched gate line slits at the edge having a structure substantially consistent with the internal gate line slits, guaranteeing that the critical dimensions of the gate line slits at the edge meet the corresponding process requirements. This mitigates the impact of etching byproducts on the etching of the gate line slits at the edge, alleviates the loading effect, and effectively mitigates problems such as etching stoppage and tilting of the gate line slits at the edge. This ensures a good etching effect for the gate line slits at the plane edge, thereby guaranteeing good overall device performance. Furthermore, since etching does not proceed downwards from the first groove and hole during the etching of the aforementioned layer structure, the first groove and hole do not form patterns, thus avoiding the influence of the first groove and hole on downstream processes.

[0060] According to another typical embodiment of this application, a three-dimensional memory is also provided. The three-dimensional memory includes a substrate and a plurality of gate line slits. The substrate includes a substrate and a stacked structure. The stacked structure is located on the exposed surface of the substrate. The stacked structure includes alternately disposed sacrificial layers and insulating dielectric layers. Each of the gate line slits is located in the substrate and penetrates the stacked structure to the surface of the substrate. The gate line slits have the same depth. The aperture of the gate line slit located in a first region is a first aperture. The aperture of the gate line slit located at the edge of a second region is a second aperture. The absolute value of the difference between the first aperture and the second aperture is less than or equal to 1 nm. The first region is the edge of the substrate, and the second region is the region of the substrate other than the first region.

[0061] The aforementioned three-dimensional memory includes a substrate and a plurality of gate line slits located in the substrate. The depth of each gate line slit is the same. The absolute value of the difference between the aperture of the gate line slit located in the first region and the aperture of the gate line slit located in the second region is less than or equal to 1 nm. That is, the difference between the aperture of the gate line slit located at the edge of the substrate and the aperture of the gate line slit located inside the substrate is small. This ensures good consistency of the gate line slits of the three-dimensional memory, thereby ensuring good overall device performance.

[0062] In practical applications, the absolute value of the difference between the first aperture and the second aperture is not limited to less than or equal to 1 nm. Those skilled in the art can adjust the process parameters according to actual needs to make the first aperture and the second aperture basically consistent, such as making the absolute value of the difference between the first aperture and the second aperture 2 nm.

[0063] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0064] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0065] 1) In the memory formation method described above in this application, the patterned mask layer includes a slit region and an edge region located at least on one side of the slit region. The slit region includes a plurality of channels extending through to the surface of the stacked structure. The edge region includes a first groove and / or a hole, i.e., there are three cases: first, the edge region includes a first groove; second, the edge region includes a hole; third, the edge region includes a first groove and a hole. Using the patterned mask layer as a mask, the stacked structure is etched to obtain a plurality of gate line slits, and the gate line slits correspond one-to-one with the channels. The method for forming the memory described in this application involves forming a first groove and / or hole in the edge region. Specifically, the first groove and / or hole are provided at the outer edge of the gate line slit at the edge. This ensures that the etching environment of the gate line slit at the edge is similar to that of the gate line slit at the non-edge (i.e., internal) area during etching. This results in the gate line slit at the edge having a structure substantially consistent with the internal gate line slit, guaranteeing that the critical dimensions of the gate line slit at the edge meet the corresponding process requirements. This mitigates the impact of etching byproducts on the etching of the gate line slit at the edge, alleviates the load effect, and effectively mitigates problems such as etching stoppage and tilting of the gate line slit at the edge. This ensures a good etching effect for the gate line slit at the plane edge, thereby guaranteeing good overall device performance. Furthermore, since etching does not proceed downwards from the first groove and hole during the etching of the layer structure, the first groove and hole do not form patterns, thus avoiding the influence of the first groove and hole on downstream processes.

[0066] 2) The three-dimensional memory described in this application is fabricated by any of the aforementioned memory formation methods. These methods involve forming a first groove and / or hole in the edge region, i.e., setting the first groove and / or hole at the outer edge of the gate line slit at the edge. This ensures that the etching environment of the gate line slit at the edge is similar to that of the gate line slit at the non-edge (i.e., internal) region during etching. This results in the etched gate line slit at the edge having a structure substantially consistent with the internal gate line slit, guaranteeing that the critical dimensions of the gate line slit at the edge meet the corresponding process requirements. This mitigates the impact of etching byproducts on the etching of the gate line slit at the edge, alleviates the load effect, and effectively mitigates problems such as etching stoppage and tilting of the gate line slit at the edge. This ensures a good etching effect for the gate line slit at the plane edge, thereby guaranteeing good overall device performance. Furthermore, since etching does not proceed downwards from the first groove and hole during the etching of the aforementioned layer structure, i.e., the first groove and hole do not form patterns, this avoids the influence of the first groove and hole on downstream processes.

[0067] 3) The three-dimensional memory described above in this application includes a substrate and a plurality of gate line slits located in the substrate. The depth of each gate line slit is the same. The absolute value of the difference between the aperture of the gate line slit located in the first region and the aperture of the gate line slit located in the second region is less than or equal to 1 nm. That is, the difference between the aperture of the gate line slit located at the edge of the substrate and the aperture of the gate line slit located inside the substrate is small. This ensures that the consistency of each gate line slit of the three-dimensional memory is good, thereby ensuring that the overall performance of the device is good.

[0068] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for forming a memory, characterized in that, include: A substrate is provided, the substrate including a substrate and a stacked structure located on an exposed surface of the substrate, the stacked structure including alternating sacrificial layers and insulating dielectric layers; A patterned mask layer is formed on the exposed surface of the stacked structure. The patterned mask layer includes a slit region and an edge region located at least on one side of the slit region. The slit region includes a plurality of channels extending through the surface of the stacked structure. The edge region includes a first groove and / or a hole. Using the patterned mask layer as a mask, the stacked structure is etched to form multiple gate line slits; Remove the patterned mask layer; There are multiple slit areas and multiple edge areas. Some of the edge areas are located between two adjacent slit areas, while the other edge areas are located at the edges of the slit areas.

2. The method according to claim 1, characterized in that, The critical dimension of the first groove is smaller than the critical dimension of the channel, and the critical dimension of the hole is smaller than the critical dimension of the channel.

3. The method according to claim 1, characterized in that, The key dimensions of all the channels are the same.

4. The method according to claim 1, characterized in that, A patterned mask layer is formed on the exposed surface of the stacked structure, including: A mask material layer and a photoresist layer are sequentially formed on the exposed surface of the stacked structure; A portion of the photoresist layer is removed to form a plurality of first openings and at least one second opening extending through to the surface of the mask material layer on the surface of the photoresist layer, and the remaining photoresist layer is the photoresist portion. The photoresist portion is used as a mask to etch the mask material layer to form the patterned mask layer, wherein the first opening corresponds to the channel and the second opening corresponds to the first groove and / or hole; Remove the photoresist portion.

5. The method according to claim 4, characterized in that, A masking material layer is formed on the exposed surface of the stacked structure, comprising: A first sub-mask material layer is formed on the exposed surface of the stacked structure; A second sub-mask material layer is formed on the exposed surface of the first sub-mask material layer.

6. The method according to claim 5, characterized in that, The material of the first sub-mask layer includes carbon, and the material of the second sub-mask layer includes silicon oxynitride.

7. The method according to claim 1, characterized in that, After etching the stacked structure using the patterned mask layer as a mask to form multiple gate line slits, the method for forming the memory further includes: Multiple conductive layers replace all the sacrificial layers to form a stacked structure, the stacked structure comprising alternating conductive layers and insulating dielectric layers.

8. The method according to claim 7, characterized in that, Replacing all the sacrificial layers with multiple conductive layers includes: Phosphoric acid is used to remove each of the sacrificial layers, forming multiple second grooves; The conductive layer is formed by filling the second groove with conductive material.

9. A three-dimensional memory, characterized in that, Manufactured using any one of the memory forming methods of claims 1 to 8, comprising: A substrate includes a substrate and a stacked structure located on an exposed surface of the substrate, the stacked structure including alternating sacrificial layers and insulating dielectric layers; Multiple gate line slits are located in the substrate, and the gate line slits penetrate the stacked structure to the surface of the substrate. The depth of each gate line slit is the same. The aperture of the gate line slit located in the first region is the first aperture, and the aperture of the gate line slit located at the edge of the second region is the second aperture. The absolute value of the difference between the first aperture and the second aperture is less than or equal to 1 nm. The first region is the edge of the substrate, and the second region is the region of the substrate other than the first region.

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