Bias current feedback loop for low noise amplifier low gain mode and low noise amplifier

Abstract

The present invention discloses a bias current feedback loop for a low-gain mode of a low-noise amplifier. The low-noise amplifier includes a cascode transistor and a main transistor, including an operational amplifier, an output end of which is electrically connected to the gate of the cascode transistor; a resistor, one end of which is electrically connected to the gate of the main transistor; a first transistor, a gate of which is electrically connected to the other end of the resistor, and a source of which is grounded; a second transistor, a gate of which is electrically connected to the gate of the cascode transistor, and a source of which is electrically connected to the drain of the first transistor; a first current-voltage conversion module, an input end of which is electrically connected to the drain of the second transistor, and an output end of which is electrically connected to the in-phase input end of the operational amplifier; a second current-voltage conversion module; and a first reference current source. It can reduce current consumption in a low-gain mode, has high input reference linearity, and is not prone to input mismatch problems. A low-noise amplifier is also disclosed.

Description

Technical Field

[0001] The present invention relates to a bias current feedback loop of a low noise amplifier and the low noise amplifier, and in particular to a bias current feedback loop and the low noise amplifier used in a low gain mode of the low noise amplifier. Background Art

[0002] The design of low noise amplifier (LNA) is a very important part of wireless receiver (RX) chip design. Figure 1 The noise, linearity and frequency response performance of the LNA play a decisive role in the entire RX. The LNA current consumption, especially for those applications that are sensitive to current consumption, such as the Internet of Things, can account for 30-40% of the entire RX.

[0003] In order to accommodate input signals or interference with a large dynamic range, the LNA needs to work under different gain conditions to balance noise and linearity performance. In low gain mode, compared with high gain, in addition to improved linearity, saving current consumption is also an important indicator.

[0004] The current consumption of the LNA in low-gain mode will vary greatly under various process, power supply voltage and temperature (PVT) variations. How to reduce this variation is also an important issue.

[0005] Figure 2 The design presented here is an existing LNA. Because the low gain of this LNA is achieved by reducing the load impedance rather than the bias current, the current consumption is not reduced at low gains. Also, because the input transistors (Q1 and Q2) do not change their operating state in the low-gain mode, the input referred linearity of the LNA cannot be further improved as the gain is gradually reduced and the linearity of Q1 and Q2 begins to dominate. Figure 3 Another existing LNA design is presented, and its problems are similar to Figure 2 The same problem is presented for LNA design. Figure 4 What is presented is another existing LNA design. When two LNAs with different gains are connected in parallel to achieve high / low gain in ping-pong mode, the input impedance of the LNA changes, which will cause either input matching failure when working at low gain, or extremely difficult matching design in the chip.

[0006] Therefore, it is desirable to seek a technical solution to at least alleviate the above problems. Summary of the invention

[0007] The object of the present invention is to provide a bias current feedback loop for a low-gain mode of a low-noise amplifier, which is applied to a low-noise amplifier. The low-noise amplifier can reduce current consumption in the low-gain mode, improve input reference linearity, and easily avoid input mismatch problems in the low-gain mode. A low-noise amplifier is also provided. The low-noise amplifier can reduce current consumption in the low-gain mode, improve input reference linearity, and is not prone to input mismatch problems in the low-gain mode.

[0008] The technical solution of the present invention for achieving the above-mentioned object is as follows:

[0009] A bias current feedback loop for a low-gain mode of a low-noise amplifier, wherein the low-noise amplifier adopts a cascode structure, the low-noise amplifier comprises a cascode transistor and a main transistor, and the bias current feedback loop comprises:

[0010] an operational amplifier having an output electrically connected to the gate of the cascode transistor;

[0011] a resistor having one end electrically connected to the gate of the main transistor;

[0012] A first transistor, whose gate is electrically connected to the other end of the resistor and whose source is grounded, wherein a bias voltage is inputted from the gate;

[0013] a second transistor having a gate electrically connected to the gate of the cascode transistor and a source electrically connected to the drain of the first transistor;

[0014] A first current-to-voltage conversion module, an input end of which is electrically connected to the drain of the second transistor, and an output end of which is electrically connected to the non-inverting input end of the operational amplifier;

[0015] A second current-to-voltage conversion module, an output terminal of which is electrically connected to an inverting input terminal of the operational amplifier;

[0016] A first reference current source, an output end of which is electrically connected to an input end of the second current-voltage conversion module;

[0017] The first transistor and the second transistor correspond to the mirror main transistor and the cascode transistor in turn, and the ratio of the DC bias current is 1:N, where N is a positive number.

[0018] The gate of the second transistor is electrically connected to the gate of the cascode transistor through a first switch tube; the source of the first switch tube is electrically connected to the gate of the cascode transistor, the drain of the first switch tube is electrically connected to the gate of the second transistor, and the gate of the first switch tube inputs a first control signal.

[0019] Also includes:

[0020] The second switch tube has a source electrically connected to the positive electrode of the power supply, a drain electrically connected to the gate of the cascode transistor, and a gate inputting the first control signal.

[0021] The first current-voltage conversion module includes a third transistor; the drain of the third transistor is electrically connected to its gate, the drain serves as the input end of the first current-voltage conversion module, the gate serves as the output end of the first current-voltage conversion module, and the source is electrically connected to the positive electrode of the power supply.

[0022] The second current-voltage conversion module includes a fourth transistor; the drain of the fourth transistor is electrically connected to its gate, its drain serves as the input end of the second current-voltage conversion module, its gate serves as the output end of the second current-voltage conversion module, and its source is electrically connected to the positive electrode of the power supply.

[0023] The first reference current source comprises:

[0024] a fifth transistor, whose source is electrically connected to the positive electrode of the power supply and whose gate is electrically connected to its drain;

[0025] a second reference current source, an output terminal of which is electrically connected to the drain of the fifth transistor;

[0026] a sixth transistor, whose source is electrically connected to the positive electrode of the power supply, and whose gate is electrically connected to the gate of the fifth transistor;

[0027] a seventh transistor, whose source is grounded, whose gate is electrically connected to its drain, and whose drain is electrically connected to the drain of the sixth transistor;

[0028] A reference current sub-unit includes an eighth transistor and a ninth transistor, wherein the drain of the eighth transistor is electrically connected to the input terminal of the second current-voltage conversion module, the gate of the eighth transistor is electrically connected to the second control signal input terminal, the source of the eighth transistor is electrically connected to the drain of the ninth transistor, the source of the ninth transistor is grounded, and the gate of the ninth transistor is electrically connected to the gate of the seventh transistor.

[0029] There are a plurality of reference current sub-units, and the gate of the eighth transistor of each reference current sub-unit is electrically connected to a different second control signal input terminal.

[0030] The operational amplifier comprises:

[0031] a tenth transistor, whose source is electrically connected to the positive electrode of the power supply and whose gate is electrically connected to the gate of the fifth transistor;

[0032] an eleventh transistor, whose source is electrically connected to the drain of the tenth transistor and whose gate serves as a non-inverting input terminal of the operational amplifier;

[0033] a twelfth transistor, whose source is electrically connected to the drain of the tenth transistor and whose gate serves as an inverting input terminal of the operational amplifier;

[0034] a thirteenth transistor, whose drain is electrically connected to its gate and the drain of the eleventh transistor, and whose source is grounded;

[0035] a fourteenth transistor, a drain of which is electrically connected to the drain of the twelfth transistor, a gate of which is electrically connected to the gate of the thirteenth transistor, and a source of which is grounded;

[0036] The drain of the fourteenth crystal serves as the output terminal of the operational amplifier.

[0037] Also includes:

[0038] a third reference current source, an output terminal of which is electrically connected to the gate of the first transistor;

[0039] a fifteenth transistor, having a drain electrically connected to its gate and the gate of the first transistor, and having a source grounded;

[0040] A capacitor has one end connected to the ground and the other end electrically connected to the gate of the fifteenth transistor.

[0041] A low noise amplifier comprises the bias current feedback loop for the low gain mode of the low noise amplifier.

[0042] The beneficial technical effects of the present invention are:

[0043] 1. Different from the existing method of achieving low gain by reducing output impedance while keeping the current consumption of LNA unchanged, the bias current feedback loop of the present invention reduces the current consumption of LNA when it is in low gain mode compared with when it is in high gain mode. This is very helpful for applications that are sensitive to current consumption, such as the Internet of Things.

[0044] 2. Due to the role of the bias current feedback loop in the present invention, the current consumption of the LNA in low gain mode is fixed, equal to N times the first reference current. Under PVT changes, the change in current consumption is very small. This is extremely beneficial to the working stability of the product.

[0045] 3. Through the bias current feedback loop of the present invention, the input matching of the LNA in the low gain mode is basically the same as that in the high gain mode. The reason is that the transistor at the input end is still in the on state, so the capacitive reactance presented to the RF input port does not change significantly, and the input mismatch problem is not easy to occur in the low gain mode.

[0046] 4. With Figure 2 , 3Unlike the existing LNA designs presented, the input-referred linearity of the LNA in low-gain mode can be improved by the bias current feedback loop of the present invention, because the main transistor is now operating in the triode region, which is a better linear region than the saturation region in high gain. Since the input signal or interference of the LNA is quite large when operating at low gain, the improvement of linearity is very significant. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 The figure is a block diagram of a typical existing wireless receiver.

[0048] Figure 2 The following is a circuit diagram for an existing LNA low-gain mode design.

[0049] Figure 3 The following is a circuit diagram for another existing LNA low-gain mode design.

[0050] Figure 4 The following is a circuit diagram of another existing LNA low-gain mode design.

[0051] Figure 5 FIG. 4 is a schematic diagram of a bias current feedback loop for LNA low gain mode according to the present invention.

[0052] Figure 6 FIG. 4 is a schematic diagram of a preferred bias current feedback loop for LNA low gain mode according to the present invention. DETAILED DESCRIPTION

[0053] The examples given below are specific descriptions of the present invention. It is necessary to point out that the following examples are only used to further illustrate the present invention and cannot be understood as limiting the scope of protection of the present invention.

[0054] Figure 5An embodiment of a bias current feedback loop for a low-gain mode of a low-noise amplifier is exemplarily shown in many embodiments of the present invention. Among them, the low-noise amplifier adopts a cascode structure, and the low-noise amplifier includes a cascode transistor M2 and a main transistor M1. The gate of the main transistor M1 is electrically connected to one end of the first inductor L1, the radio frequency input signal RFin is input from the other end of the first inductor L1, and the source of the main transistor M1 is grounded through the second inductor L2. The source of the cascode transistor M2 is electrically connected to the drain of the main transistor M1, the drain of the cascode transistor M2 is electrically connected to the positive electrode of the power supply through the radio frequency choke circuit Z1, and the radio frequency output signal RFout is output from the drain of the cascode transistor M2. The bias current feedback loop for the low-gain mode of the low-noise amplifier includes an operational amplifier 1, a resistor R, a first transistor M3, a second transistor M4, a first current-voltage conversion module 2, a second current-voltage conversion module 3, and a first reference current source Iref.

[0055] The output terminal of the operational amplifier 1 is electrically connected to the gate of the cascode transistor M2.

[0056] One end of the resistor R is electrically connected to the gate of the main transistor M1 .

[0057] The gate of the first transistor M3 is electrically connected to the other end of the resistor R, and the source of the first transistor M3 is grounded, wherein the bias voltage Vbias is input from the gate of the first transistor M3.

[0058] A gate of the second transistor M4 is electrically connected to the gate of the cascode transistor M2 , and a source of the second transistor M4 is electrically connected to the drain of the first transistor M3 .

[0059] The input end of the first current-voltage conversion module 2 is electrically connected to the drain of the second transistor M4 , and the output end of the first current-voltage conversion module 2 is electrically connected to the non-inverting input end of the operational amplifier 1 .

[0060] The output terminal of the second current-voltage conversion module 3 is electrically connected to the inverting input terminal of the operational amplifier 1 .

[0061] The output terminal of the first reference current source Iref is electrically connected to the input terminal of the second current-voltage conversion module 3 .

[0062] The first transistor M3 and the second transistor M4 correspond to the mirror main transistor M1 and the cascode transistor M2 in turn, and the ratio of the DC bias current is 1:N, where N is a positive number.

[0063] See also Figure 6, the gate of the second transistor M4 is electrically connected to the gate of the cascode transistor M2 through the first switch tube M6. Specifically, the source of the first switch tube M6 is electrically connected to the gate of the cascode transistor M2, the drain of the first switch tube M6 is electrically connected to the gate of the second transistor M4, and the gate of the first switch tube M6 inputs the first control signal Gsw. The first control signal Gsw is a low level when the LNA is in high gain, and a high level when the LNA is in low gain. The bias current feedback loop is closed when the LNA is in high gain, that is, the bias current feedback loop is disconnected from the cascode transistor M2 through the first switch tube M6. The bias current feedback loop is opened when the LNA is in low gain, that is, the bias current feedback loop is electrically connected to the cascode transistor M2 through the first switch tube M6.

[0064] See also Figure 6 The bias current feedback loop of the present invention further includes a second switch tube M7. The source of the second switch tube M7 is electrically connected to the positive electrode of the power supply, the drain of the second switch tube M7 is electrically connected to the gate of the cascode transistor M2, and the gate of the second switch tube M6 inputs the first control signal Gsw. The second switch tube M7 and the third inductor L3 form a radio frequency choke circuit Z1. One end of the third inductor L3 is electrically connected to the positive electrode of the power supply, and the other end thereof is electrically connected to the drain of the second transistor M4.

[0065] See also Figure 6 The first current-voltage conversion module 2 of the bias current feedback loop of the present invention includes a third transistor M8; the drain of the third transistor M8 is electrically connected to the gate of the third transistor M8, the drain of the third transistor M8 serves as the input end of the first current-voltage conversion module 2, the gate of the third transistor M8 serves as the output end of the first current-voltage conversion module 2, and the source of the third transistor M8 is electrically connected to the positive electrode of the power supply. When working at low gain, the first transistor M3 and the second transistor M4 mirror the bias current of the LNA, and the third transistor M8 connected in a diode manner collects this current and realizes the current-to-voltage conversion.

[0066] See also Figure 6 The second current-voltage conversion module 3 of the bias current feedback loop of the present invention includes a fourth transistor M9; the drain of the fourth transistor M9 is electrically connected to the gate of the fourth transistor M9, the drain of the fourth transistor M9 serves as the input end of the second current-voltage conversion module 3, the gate of the fourth transistor M9 serves as the output end of the second current-voltage conversion module 3, and the source of the fourth transistor M9 is electrically connected to the positive electrode of the power supply. When working at low gain, the fourth transistor M9 connected in a diode manner realizes the conversion of the first reference current Iref, that is, the conversion of current to voltage.

[0067] See also Figure 6 The first reference current source Iref of the bias current feedback loop of the present invention includes a fifth transistor M15, a second reference current source Ibias2, a sixth transistor M16, a seventh transistor M17, and a reference current sub-unit.

[0068] The source of the fifth transistor M15 is electrically connected to the positive electrode of the power supply, and the gate thereof is electrically connected to the drain thereof. The output terminal of the second reference current source Ibias2 is electrically connected to the drain of the fifth transistor M15. The source of the sixth transistor M16 is electrically connected to the positive electrode of the power supply, and the gate of the sixth transistor M16 is electrically connected to the gate of the fifth transistor M15. The source of the seventh transistor M17 is grounded, the gate of the seventh transistor M17 is electrically connected to the drain of the seventh transistor M17, and the drain of the seventh transistor M17 is electrically connected to the drain of the sixth transistor M16.

[0069] The reference current sub-unit includes an eighth transistor M18 and a ninth transistor M19, wherein the drain of the eighth transistor M18 is electrically connected to the input end of the second current-voltage conversion module 3, the gate of the eighth transistor M18 is electrically connected to the second control signal input end, the source of the eighth transistor M18 is electrically connected to the drain of the ninth transistor M19, the source of the ninth transistor M19 is grounded, and the gate of the ninth transistor M19 is electrically connected to the gate of the seventh transistor M17.

[0070] In some embodiments, there are multiple reference current sub-units, and the gate of the eighth transistor M18 of each reference current sub-unit is electrically connected to different second control signal input terminals. For example, there are n+1 reference current sub-units, and the corresponding different second control signal input terminals are Vctrl <0> 、Vctrl <1> 、……、Vctrl <n>The gate of the eighth transistor M18 of the first reference current sub-unit is connected to the second control signal input terminal Vctrl <0> The gate of the eighth transistor M18 of the second reference current subunit is electrically connected to the second control signal input terminal Vctrl <1> Electrical connection, and so on. Through the second control signal input terminal Vctrl <0> 、Vctrl <1> 、……、Vctrl <n>Control, the first reference current Iref is equal to the sum of the mirror currents of n+1 reference current sub-units, when given to each second control signal input terminal Vctrl <0> 、Vctrl <1> 、……、Vctrl <n>Different signals, such as those given to each second control signal input terminal Vctrl through program control <0> 、Vctrl <1> 、……、Vctrl <n>Different signals obtain different first reference currents Iref, thereby obtaining different LNA low gains. n is a natural number.

[0071] See also Figure 6 The operational amplifier 1 of the bias current feedback loop of the present invention includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14.

[0072] The source of the tenth transistor M10 is electrically connected to the positive electrode of the power supply, and the gate thereof is electrically connected to the gate of the fifth transistor M15. The source of the eleventh transistor M11 is electrically connected to the drain of the tenth transistor M10, and the gate thereof serves as the non-inverting input terminal of the operational amplifier 1. The source of the twelfth transistor M12 is electrically connected to the drain of the tenth transistor M10, and the gate thereof serves as the inverting input terminal of the operational amplifier 1. The drain of the thirteenth transistor M13 is electrically connected to the gate of the thirteenth transistor M13 and the drain of the eleventh transistor M11, and the source of the thirteenth transistor M13 is grounded. The drain of the fourteenth transistor M14 is electrically connected to the drain of the twelfth transistor M12, the gate thereof is electrically connected to the gate of the thirteenth transistor M13, and the source thereof is grounded. The drain of the fourteenth transistor M14 serves as the output terminal of the operational amplifier 1. When the feedback loop starts to work, the operational amplifier 1 ensures that the signals of the two input terminals (non-inverting input terminal and inverting input terminal) are consistent, that is, one Nth of the LNA bias current is equal to the first reference current Iref.

[0073] See also Figure 6 The bias current feedback loop of the present invention further includes a third reference current source Ibias1, a fifteenth transistor M5, and a capacitor C.

[0074] The output end of the third reference current source Ibias1 is electrically connected to the gate of the first transistor M3. The drain of the fifteenth transistor M5 is electrically connected to the gate of the fifteenth transistor M5 and the gate of the first transistor M3, and the source of the fifteenth transistor M5 is grounded. One end of the capacitor C is grounded, and the other end thereof is electrically connected to the gate of the fifteenth transistor M5. The normal or high gain bias voltage Vbias is formed by the fifteenth transistor M5, the third reference current source Ibias1 and the corresponding resistor and capacitor connected in a diode manner.

[0075] Figure 5 An embodiment of a low noise amplifier among many embodiments of the present invention is exemplified. Figure 6 This is a preferred embodiment of the bias current feedback loop for the low gain mode of the LNA of the present invention. The low noise amplifier includes the above-mentioned bias current feedback loop for the low gain mode of the low noise amplifier.

[0076] It should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0077] The present invention has been described in detail above with reference to the embodiments, which are illustrative rather than restrictive. Changes and modifications without departing from the overall concept of the present invention are within the protection scope of the present invention.< / n> < / n> < / n> < / n>

Claims

1. A bias current feedback loop for a low-gain mode of a low-noise amplifier, the low-noise amplifier adopts a cascode structure, the low-noise amplifier comprises a common-gate transistor and a main transistor, the gate of the main transistor is electrically connected to one end of a first inductor, a radio frequency input signal is input from the other end of the first inductor, the source of the main transistor is grounded through a second inductor, the source of the common-gate transistor is electrically connected to the drain of the main transistor, and the drain of the common-gate transistor is electrically connected to the positive electrode of a power supply through a radio frequency choke circuit, characterized in that: The bias current feedback loop includes: an operational amplifier having an output terminal electrically connected to the gate of the common-gate transistor; a resistor having one end electrically connected to the gate of the main transistor; A first transistor, whose gate is electrically connected to the other end of the resistor, whose source is grounded, and whose gate is input with a bias voltage; a second transistor having a gate electrically connected to the gate of the common-gate transistor and a source electrically connected to the drain of the first transistor; A first current-to-voltage conversion module, an input end of which is electrically connected to the drain of the second transistor, and an output end of which is electrically connected to the non-inverting input end of the operational amplifier; A second current-to-voltage conversion module, an output terminal of which is electrically connected to an inverting input terminal of the operational amplifier; A first reference current source, an output end of which is electrically connected to an input end of the second current-voltage conversion module; The ratio of the DC bias currents of the first transistor and the second transistor corresponding to the mirror main transistor and the common gate transistor is 1:N, where N is a positive number; The gate of the second transistor is electrically connected to the gate of the common-gate transistor through a first switch tube; the source of the first switch tube is electrically connected to the gate of the common-gate transistor, the drain of the first switch tube is electrically connected to the gate of the second transistor, and the gate of the first switch tube inputs a first control signal; Also includes: The second switch tube has a source electrically connected to the positive electrode of the power supply, a drain electrically connected to the gate of the common-gate transistor, and a gate inputting the first control signal.

2. The bias current feedback loop for low gain mode of a low noise amplifier according to claim 1, characterized in that: The first current-voltage conversion module includes a third transistor; the drain of the third transistor is electrically connected to its gate, the drain serves as the input end of the first current-voltage conversion module, the gate serves as the output end of the first current-voltage conversion module, and the source is electrically connected to the positive electrode of the power supply.

3. The bias current feedback loop for low gain mode of a low noise amplifier according to claim 1, characterized in that: The second current-voltage conversion module includes a fourth transistor; the drain of the fourth transistor is electrically connected to its gate, its drain serves as the input end of the second current-voltage conversion module, its gate serves as the output end of the second current-voltage conversion module, and its source is electrically connected to the positive electrode of the power supply.

4. The bias current feedback loop for low gain mode of a low noise amplifier according to claim 1, characterized in that: The first reference current source comprises: a fifth transistor, whose source is electrically connected to the positive electrode of the power supply and whose gate is electrically connected to its drain; a second reference current source, an output terminal of which is electrically connected to the drain of the fifth transistor; a sixth transistor, whose source is electrically connected to the positive electrode of the power supply, and whose gate is electrically connected to the gate of the fifth transistor; a seventh transistor, whose source is grounded, whose gate is electrically connected to its drain, and whose drain is electrically connected to the drain of the sixth transistor; A reference current sub-unit includes an eighth transistor and a ninth transistor, wherein the drain of the eighth transistor is electrically connected to the input terminal of the second current-voltage conversion module, the gate of the eighth transistor is electrically connected to the second control signal input terminal, the source of the eighth transistor is electrically connected to the drain of the ninth transistor, the source of the ninth transistor is grounded, and the gate of the ninth transistor is electrically connected to the gate of the seventh transistor.

5. The bias current feedback loop for low gain mode of a low noise amplifier according to claim 4, characterized in that: There are a plurality of reference current sub-units, and the gate of the eighth transistor of each reference current sub-unit is electrically connected to a different second control signal input terminal.

6. The bias current feedback loop for low gain mode of a low noise amplifier according to claim 4, characterized in that: The operational amplifier comprises: a tenth transistor, whose source is electrically connected to the positive electrode of the power supply and whose gate is electrically connected to the gate of the fifth transistor; an eleventh transistor, whose source is electrically connected to the drain of the tenth transistor and whose gate serves as a non-inverting input terminal of the operational amplifier; a twelfth transistor, whose source is electrically connected to the drain of the tenth transistor and whose gate serves as an inverting input terminal of the operational amplifier; a thirteenth transistor, whose drain is electrically connected to its gate and the drain of the eleventh transistor, and whose source is grounded; a fourteenth transistor, a drain of which is electrically connected to the drain of the twelfth transistor, a gate of which is electrically connected to the gate of the thirteenth transistor, and a source of which is grounded; The drain of the fourteenth crystal serves as the output terminal of the operational amplifier.

7. The bias current feedback loop for low gain mode of a low noise amplifier according to claim 1, characterized in that: Also includes: a third reference current source, an output terminal of which is electrically connected to the gate of the first transistor; a fifteenth transistor, having a drain electrically connected to its gate and the gate of the first transistor, and having a source grounded; A capacitor has one end connected to the ground and the other end electrically connected to the gate of the fifteenth transistor.

8. A low noise amplifier, characterized in that: The invention comprises a bias current feedback loop for a low gain mode of a low noise amplifier as described in any one of claims 1 to 7.

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