UVM verification platform interface rapid configuration method, device, equipment and medium

Abstract

The embodiment of the present invention provides a method, device, equipment and medium for quickly configuring the interface of a UVM verification platform. The method includes: creating a definition file in the package file of the top module and each bottom layer of the UVM verification platform; wherein the UVM verification platform includes a top module and several bottom modules of different levels within the top module; defining a macro function of a connection interface in the definition file of the top module and each bottom module; wherein the macro function is used to encapsulate the macro function for connecting the interface that has been written in the bottom layer of the next level; when it is detected that a DUT needs to be connected to the outside, the connection interface is quickly configured by recursively calling the macro function from the top module to the bottom layer of the next level, so as to realize that the UVM verification platform is connected to the DUT through the configured connection interface. The present invention greatly improves the work efficiency of developers, plays a role in accelerating project progress, thereby ensuring the tape-out time of a chip project.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and medium for rapid interface configuration of a UVM verification platform. Background Art

[0002] Universal Verification Methodology (UVM) is a widely used verification methodology for RTL verification. It's a verification platform based on transaction-level methodology (TLM). Simply put, it's a class library that helps verification developers easily build a configurable and reusable verification environment. This methodology encapsulates many low-level interfaces into objects, allowing developers to use them simply by following syntax rules.

[0003] like Figure 1 As shown, Figure 1 The typical architecture of the existing UVM verification platform is as follows: Figure 1 As you can see, the UVM testbench connects the DUT to the testbench through the interface. At this point, you usually need to complete the following three things in the top module:

[0004] (1) Declare interface

[0005] (2) Connect the interface to the DUT

[0006] (3) Pass the interface to the env environment through set config_db.

[0007] To facilitate understanding of the working principle of the UVM verification platform, the following abstracts the behavioral functions of the RTL design module, such as Figure 2 shown.

[0008] It can be found that each RTL design module consists of the following three parts:

[0009] (1) Input interface, used to obtain external input stimulus, such as Figure 2 data_in

[0010] (2) Behavioral functions, used to perform corresponding logical operations on input stimuli, such as Figure 2 The arithmetic logic inside the module (including combinational and sequential logic circuits)

[0011] (3) Output interface, used to output the result of the operation, such as Figure 2 data_out

[0012] like Figure 3 As shown, the above three abstract parts are usually encapsulated into the following verification environment:

[0013] (1) Encapsulate the interface of the input end data_in into an agent

[0014] (2) Encapsulate the output data_out interface into an agent

[0015] Note that the agent encapsulated above mainly accomplishes two things:

[0016] The monitor in the agent encapsulation component monitors the signal of the sampling interface and encapsulates it into a transaction to pass it to the verification environment for processing by subsequent components

[0017] The driver in the agent encapsulation component gets the interface handle, and then drives the required stimulus transaction to the interface as the input stimulus for subsequent modules

[0018] (3) Encapsulate the above two agents in the env verification environment, write the reference model and some analysis components at this level, and start writing test cases to verify the RTL design module.

[0019] In the top module of the verification platform, you need to declare, connect, and transfer the configuration of the interfaces corresponding to data_in and data_out. Generally, the top module instantiation includes two modules: rtl_inst_top, which is used to instantiate the RTL design, and env_inst_top, which is used to declare, connect, and transfer the configuration of all interfaces. Figure 3 The RTL design module has only one level, which is the simplest case, but if it is like Figure 4 What about in the middle?

[0020] At this point, in the top module of the verification platform, it is necessary to declare, connect, and configure all interfaces encapsulated by the underlying agents, which is a bit troublesome.

[0021] For more complex RTL designs, such as a complex chip consisting of hundreds or thousands of submodules, the corresponding interfaces would also reach hundreds or thousands. This means that interfaces would need to be declared at least a thousand times in the top-level environment. In this case, if the top-level module of the verification platform were to continue declaring, connecting, and configuring all interfaces encapsulated by the underlying agents, things would become very difficult. The path hierarchy and code statements would become very lengthy and complex, prone to errors, and even nearly impossible to complete. Summary of the Invention

[0022] In view of this, the object of the present invention is to provide a method, device, equipment and medium for rapid interface configuration of a UVM verification platform to improve the above-mentioned problems.

[0023] An embodiment of the present invention provides a method for quickly configuring an interface of a UVM verification platform, comprising:

[0024] Create definition files in the top-level module and each bottom-level package file of the UVM verification platform; wherein the UVM verification platform includes the top-level module and several bottom-level modules of different levels located within the top-level module, and the bottom-level modules of different levels are nested with each other according to their level size;

[0025] The macro functions of the connection interface are defined in the definition files of the top-level module and each bottom-level module; wherein the macro functions are used to encapsulate the macro functions for the connection interface that have been written in the bottom level of the next level;

[0026] When it is detected that the DUT needs to be connected to an external device, the connection interface is quickly configured by recursively calling the macro function from the bottom layer of the top module to the next level, so as to realize that the UVM verification platform is connected to the DUT through the configured connection interface.

[0027] Preferably, it also includes:

[0028] By configuring the script, the two input and output ports of the underlying module can be automatically encapsulated into independent agents.

[0029] Preferably, in the configuration definition file, the current connection interface is declared, and then the connection direction of the connection interface is specified through the is_active parameter to determine whether it needs to be driven to the DUT through the env verification environment through the sequence, that is, whether the agent package corresponding to the interface is in active mode; wherein, when driven by the sequence in the env verification environment, is_active is 1, and when driven by the DUT, is_active is 0.

[0030] Preferably, for the encapsulated macro function, the verification environment of this layer is instantiated at a higher level and includes two usage modes, wherein:

[0031] The first usage mode corresponds to the input port of the underlying module being driven by sequence stimulus;

[0032] The input port of the underlying module corresponding to the second usage mode is driven by the port output port of the preceding module.

[0033] The embodiment of the present invention also provides an interface rapid configuration device for a UVM verification platform, which includes:

[0034] A definition file creation unit is used to create a definition file in the top module of the UVM verification platform and each bottom package file; wherein the UVM verification platform includes a top module and a plurality of bottom modules of different levels located within the top module, and the bottom modules of different levels are nested with each other according to their level size;

[0035] A macro function encapsulation unit is used to define a macro function for connecting an interface in the definition files of the top-level module and each bottom-level module; wherein the macro function is used to encapsulate the macro function for connecting an interface that has been written in the bottom level of the next level;

[0036] The recursive call unit is used to quickly configure the connection interface by recursively calling the macro function from the top module to the bottom layer of the next level when it detects that it needs to be connected to an external DUT, so as to realize that the UVM verification platform is connected to the DUT through the configured connection interface.

[0037] Preferably, it also includes:

[0038] The port encapsulation unit is used to automatically encapsulate the two input and output ports of the bottom module into independent agents by configuring the script.

[0039] Preferably, in the configuration definition file, the current connection interface is declared, and then the connection direction of the connection interface is specified through the is_active parameter to determine whether it needs to be driven to the DUT through the env verification environment through the sequence, that is, whether the agent package corresponding to the interface is in active mode; wherein, when driven by the sequence in the env verification environment, is_active is 1, and when driven by the DUT, is_active is 0.

[0040] Preferably, for the encapsulated macro function, the verification environment of this layer is instantiated at a higher level and includes two usage modes, wherein:

[0041] The first usage mode corresponds to the input port of the underlying module being driven by sequence stimulus;

[0042] The input port of the underlying module corresponding to the second usage mode is driven by the port output port of the preceding module.

[0043] An embodiment of the present invention further provides an interface rapid configuration device for a UVM verification platform, which includes a memory and a processor. The memory stores a computer program, and the computer program can be executed by the processor to implement the interface rapid configuration method for the UVM verification platform as described above.

[0044] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program. The computer program can be executed by a processor of a device where the computer-readable storage medium is located to implement the above-mentioned UVM verification platform interface rapid configuration method.

[0045] In summary, this embodiment achieves rapid declaration, connection, and configuration transfer of interfaces involved in the verification environment by layering macro functions, making this part of the code reusable. Combined with the use of scripts, it can automate the declaration, connection, and configuration transfer of interfaces involved in the verification environment. This embodiment has at least the following advantages:

[0046] (1) Realizes the rapid declaration, connection and configuration transfer of interfaces involved in complex RTL design, improving the development efficiency of the verification platform

[0047] (2) The code for declaring, connecting, and configuring the verification platform interface can be reused, reducing repetitive development work

[0048] (3) The encapsulated macro function for top-level reuse has only two parameters. When the RTL is not completed when building the verification platform, the instantiation name of the next level added by the DUT needs to be manually specified. The others can be automatically generated according to the script configured at the beginning.

[0049] (4) Standardized the UVM development framework to facilitate team collaboration and project management

[0050] Therefore, this embodiment can greatly improve the work efficiency of developers and accelerate the progress of the project, thereby ensuring the tape-out time of the chip project. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 This is a typical architecture diagram of the UVM verification platform.

[0053] Figure 2 It is an abstract diagram of the RTL design module.

[0054] Figure 3 It is a packaging diagram of the verification environment corresponding to the RTL design module.

[0055] Figure 4 It is a schematic diagram of a more complex RTL design and its corresponding verification environment.

[0056] Figure 5 The present invention is a flowchart of a method for rapidly configuring an interface of a UVM verification platform provided by a first embodiment of the present invention.

[0057] Figure 6 This is a schematic diagram of the macro function call to implement interface declaration, connection and configuration transfer in an embodiment of the present invention.

[0058] Figure 7 It is a code implementation diagram that adds definition files to the package file.

[0059] Figure 8 This is the code implementation diagram of the interface of the input port data_in.

[0060] Figure 9 It is the code implementation diagram of the macro function defined in the define file.

[0061] Figure 10 This is the code implementation diagram of the output port interface and define file.

[0062] Figure 11 Code implementation diagram that encapsulates macro functions for calling by the upper level.

[0063] Figure 12 It is a code implementation diagram of the macro function encapsulated in the top-level module.

[0064] Figure 13 It is a structural diagram of an interface rapid configuration device of a UVM verification platform provided by a second embodiment of the present invention. DETAILED DESCRIPTION

[0065] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0066] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0067] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0068] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0069] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0070] See also Figure 5 The first embodiment of the present invention provides a method for rapidly configuring an interface of a UVM verification platform, which can be executed by a rapid interface configuration device of the UVM verification platform (hereinafter referred to as a rapid configuration device), and in particular, by one or more processors in the rapid configuration device to implement the following steps:

[0071] S101, creating a definition file in the top module of the UVM verification platform and each bottom package file; wherein the UVM verification platform includes a top module and several bottom modules of different levels located within the top module, and the bottom modules of different levels are nested with each other according to their level size.

[0072] In this embodiment, the rapid configuration device can be a computer, a workstation, a server or other terminal device with computing and processing capabilities, wherein, in particular, the rapid configuration device is installed with a UVM verification platform. Figure 1 As shown, the UVM verification platform generally includes the following components:

[0073] Sequencer: All sequencers must be derived from uvm_sequencer.

[0074] Function of sequencer: organize and manage sequence. When driver requests data, it sends sequence_item generated by sequence to driver.

[0075] driver: All drivers must be derived from uvm_driver.

[0076] Driver function: Apply for sequence_item (data packet) from sequencer and drive the information in the packet to the port of DUT according to the bus protocol.

[0077] monitor: All monitors must be derived from uvm_monitor.

[0078] Monitor function: In order to detect interface data, it receives data from the DUT and converts it into a sequence_item at the transaction level and sends it to the scoreboard for comparison.

[0079] agent: All agents must be derived from uvm_agent.

[0080] Agent function: Encapsulates the sequencer, driver, and monitor together. The use of the agent module improves the reusability of the code.

[0081] scoreboard: Generally, scoreboards must be derived from uvm_scoreboard.

[0082] Scoreboard function: Compares the data sent by the reference model and the monitor, and determines whether the DUT is working correctly based on the comparison results.

[0083] env: All envs must be derived from uvm_env.

[0084] The env function encapsulates components on the platform to implement multiple use cases in one environment. When running different use cases, you can simply instantiate the env in it. It can be regarded as a structured container.

[0085] test: All test cases must be derived from uvm_test or its derived classes.

[0086] In this embodiment, the UVM verification platform generally includes a top-level module and several bottom-level modules, and the top-level module and the bottom-level modules are nested with each other according to their hierarchical sizes.

[0087] like Figure 6 As shown, Figure 6 In the example, top_env is the top module (or top verification environment), and the three env verification environments are the bottom modules located at the next level of the top module, and each bottom module of env also includes two bottom modules named agent. Of course, it should be noted that in other embodiments of the present invention, different UVM verification platforms have different hierarchical structures. Figure 6 It should not be understood as limiting the present invention.

[0088] In this embodiment, the definition file (define file) can be added to the package file by Figure 7 The code shown is implemented.

[0089] The above are the class files that are generally needed to encapsulate the interface (i.e. the connection interface) into an agent. You can see that the define file is also included in the package file.

[0090] S102, defining a macro function for the connection interface in the definition files of the top-level module and each bottom-level module; wherein the macro function is used to encapsulate the macro function for the connection interface that has been written in the bottom level of the next level.

[0091] Taking the input port data_in as an example, let's first look at the code implementation of the interface, such as Figure 8 shown.

[0092] Then as Figure 9 As shown, let's look at the macro functions defined in the define file

[0093] Then, if Figure 10 As shown, let's look at the code implementation of the output port interface and define file

[0094] It should be noted that Figure 10 Each interface in the example has only one data member. This is just an example. In reality, an RTL design may have many input and output ports. The input and output ports are separated here, that is, written as independent interfaces and encapsulated into independent agents, for the purpose of later configuration script automation.

[0095] It can be seen that in the define file, this embodiment first declares the current interface, and then specifies the connection direction of the connection interface through the is_active parameter, so as to determine whether it needs to be driven to the DUT through the sequence by the env verification environment, that is, whether the agent encapsulation corresponding to the connection interface is in active mode. Because in the top-level verification environment, it is necessary to clearly know and configure the active mode of the currently existing agent, so as to determine which signals on the interface in the environment are driven by the sequence in the env verification environment (is_active is 1 at this time) and which are driven by the dut (is_active is 0 at this time). The is_active here can be known when the env verification environment is generated by the configuration script, so the parameter setting of the encapsulated macro function can be automatically completed by the script. This is also one of the reasons why if you want to achieve fully automated script configuration, you need to limit the data members in the interface to a single direction. Another reason is to achieve automation of driving and sampling. That is, the two clocking blocks, drive and monitor, in the interface will include all the data members of the interface, and the input and output ports will not be mixed. Then, when these two clocking blocks are used in the driver or monitor later, there is no need to modify the code in the interface and they can be used directly, thereby improving development efficiency.

[0096] S103, when it is detected that it needs to be connected to an external DUT, the connection interface is quickly configured by recursively calling a macro function from the bottom layer of the top module to the next level, so as to realize that the UVM verification platform is connected to the DUT through the configured connection interface.

[0097] First, the agent encapsulation of the input and output ports of the interface needs to be instantiated in the top-level env bottom-level module to establish the env verification environment for the bottom-level module. As before, this embodiment will still declare, connect, and configure the interface in the tb_env_inst_top module.

[0098] It can be seen that in this embodiment, the previously packaged macro function can be directly called, and the calling and parameter setting of the macro function can be automatically completed by the script.

[0099] Then, repeat the above steps to encapsulate and call macro functions layer by layer, thereby realizing the declaration, connection and configuration of the interface in a complex verification environment.

[0100] Specifically, encapsulating macro functions for use at a higher level can be done by Figure 11 The code shown is implemented.

[0101] It can be seen that this embodiment encapsulates two macro functions, corresponding to the two usage modes of the env verification environment of this layer being instantiated at the top level. The input port of the underlying module corresponding to the first usage mode is driven by sequence stimulus, and the input port of the underlying module corresponding to the second usage mode is driven by the output port of the preceding module, usually the preceding RTL module or its corresponding RTL model.

[0102] Generally, all env environments have only the two usage modes described above, as they are driven by either the preceding module or the env environment (sequence stimulus). The top-level module can specify which macro function to use via parameters in the top-level module configuration script, or it can be manually selected and called by the verification personnel. As the developer of the top-level env verification environment, they must be aware of the active mode corresponding to the underlying agent they are instantiating.

[0103] In addition, you can see that the encapsulated macro function reused for the top-level module here has only two parameters. When the RTL is not completed when building the verification platform, the instantiation name of the next level of DUT (sub_path, corresponding to module1, module2 or module3 in RTL, and the instantiation name of the RTL top-level module top_module defaults to dut) needs to be manually specified. The others can be automatically generated according to the script configured at the beginning.

[0104] After establishing the call of the bottom module, we now establish the env verification environment corresponding to the top module (top_env). Similarly, this embodiment will use the macro function encapsulated in the previous step in the tb_env_inst_top module at this level to complete the declaration, connection and configuration transfer of the interface.

[0105] Similarly, you can directly call the previously encapsulated macro function, or of course it can be done automatically by the script.

[0106] From the previous Figure 4It can be seen that the input ports of module1 and module3 will be driven by sequence stimulus, while module2, as the subsequent module of module1, has its input port driven by the output port of module1. Therefore, it should call the macro function sub_module_create_inf instead of sub_module_create_inf_active, that is, it is necessary to pay attention to the usage mode of the internal agent of the reusable verification environment included in the instantiation.

[0107] In the env verification environment corresponding to the top_module layer, the encapsulated macro function is as follows Figure 12 shown.

[0108] That is, by repeating layer-by-layer encapsulation and reuse, the automatic declaration, connection, and configuration transfer of interfaces can be achieved, thereby improving development efficiency and accelerating project progress.

[0109] In summary, this embodiment achieves rapid declaration, connection, and configuration transfer of interfaces involved in the verification environment by layering macro functions, making this part of the code reusable. Combined with the use of scripts, it can automate the declaration, connection, and configuration transfer of interfaces involved in the verification environment. This embodiment has at least the following advantages:

[0110] 1) Realizes the rapid declaration, connection and configuration transfer of interfaces involved in complex RTL design, improving the development efficiency of the verification platform

[0111] 2) The code for declaring, connecting, and configuring the verification platform interface can be reused, reducing repetitive development work.

[0112] (3) The encapsulated macro function for top-level reuse has only two parameters. When the RTL is not completed when building the verification platform, the instantiation name of the next level added by the DUT needs to be manually specified. The others can be automatically generated according to the script configured at the beginning.

[0113] (4) Standardized the UVM development framework to facilitate team collaboration and project management

[0114] Therefore, this embodiment can greatly improve the work efficiency of developers and accelerate the progress of the project, thereby ensuring the tape-out time of the chip project.

[0115] See also Figure 13 The second embodiment of the present invention further provides an interface rapid configuration device for a UVM verification platform, which includes:

[0116] A definition file creation unit 210 is used to create a definition file in the top-level module and each bottom-level package file of the UVM verification platform; wherein the UVM verification platform includes a top-level module and a plurality of bottom-level modules at different levels within the top-level module, and the bottom-level modules at different levels are nested with each other according to their level size;

[0117] The macro function encapsulation unit 220 is used to define the macro function of the connection interface in the definition file of the top-level module and each bottom-level module; wherein the macro function is used to encapsulate the macro function for the connection interface that has been written in the bottom level of the next level;

[0118] The recursive calling unit 230 is used to quickly configure the connection interface by recursively calling the macro function from the top module to the bottom layer of the next level when it detects that it needs to be connected to an external DUT, so as to realize that the UVM verification platform is connected to the DUT through the configured connection interface.

[0119] Preferably, it also includes:

[0120] The port encapsulation unit is used to automatically encapsulate the two input and output ports of the bottom module into independent agents by configuring the script.

[0121] Preferably, in the configuration definition file, the current connection interface is declared, and then the connection direction of the connection interface is specified through the is_active parameter to determine whether it needs to be driven to the DUT through the env verification environment through the sequence, that is, whether the agent package corresponding to the interface is in active mode; wherein, when driven by the sequence in the env verification environment, is_active is 1, and when driven by the DUT, is_active is 0.

[0122] Preferably, for the encapsulated macro function, the verification environment of this layer is instantiated at a higher level and includes two usage modes, wherein:

[0123] The first usage mode corresponds to the input port of the underlying module being driven by sequence stimulus;

[0124] The input port of the underlying module corresponding to the second usage mode is driven by the port output port of the preceding module.

[0125] The third embodiment of the present invention further provides an interface rapid configuration device for a UVM verification platform, which includes a memory and a processor. The memory stores a computer program, and the computer program can be executed by the processor to implement the interface rapid configuration method for the UVM verification platform as described above.

[0126] A fourth embodiment of the present invention further provides a computer-readable storage medium storing a computer program. The computer program can be executed by a processor of a device where the computer-readable storage medium is located to implement the above-mentioned method for rapid interface configuration of the UVM verification platform.

[0127] In the several embodiments provided in the embodiments of the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device and method embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified functions or actions, or can be implemented using a combination of dedicated hardware and computer instructions.

[0128] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0129] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, electronic device, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk. It should be noted that, in this article, the terms "include", "comprising" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements inherent to such a process, method, article or device. Without further constraints, an element defined by the phrase "comprises a..." does not preclude the existence of additional identical elements in the process, method, article or apparatus that includes the element.

[0130] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A UVM verification platform interface rapid configuration method, characterized in that, include: Create definition files in the package files of the top module and each bottom module of the UVM verification platform; wherein the UVM verification platform includes the top module and several bottom modules of different levels located within the top module, and the bottom modules of different levels are nested with each other according to their level size; The macro functions of the connection interface are defined in the definition files of the top-level module and each bottom-level module; wherein the macro functions are used to encapsulate the macro functions for the connection interface that have been written in the bottom level of the next level; When it is detected that the DUT needs to be connected to an external device, the connection interface is quickly configured by recursively calling the macro function from the bottom layer of the top module to the next level, so as to realize that the UVM verification platform is connected to the DUT through the configured connection interface.

2. the interface rapid configuration method of UVM verification platform according to claim 1, is characterized in that, Also includes: By configuring the script, the two input and output ports of the underlying module can be automatically encapsulated into independent agents.

3. the interface rapid configuration method of UVM verification platform according to claim 2, is characterized in that, In the configuration definition file, declare the current connection interface, and then use the is_active parameter to specify the connection direction of the connection interface to determine whether it needs to be driven to the DUT through the env verification environment through the sequence; among them, when driven by the sequence in the env verification environment, is_active is 1, and when driven by the DUT, is_active is 0.

4. the interface rapid configuration method of UVM verification platform according to claim 1, is characterized in that For encapsulated macro functions, the underlying module of the layer is instantiated by the upper-level module, which includes two usage modes: The first usage mode corresponds to the input port of the underlying module being driven by sequence stimulus; The input port of the underlying module corresponding to the second usage mode is driven by the output port of the preceding module.

5. A UVM verification platform interface rapid configuration device, characterized in that, include: A definition file creation unit is used to create a definition file in the package file of the top module and each bottom module of the UVM verification platform; wherein the UVM verification platform includes a top module and a plurality of bottom modules of different levels located within the top module, and the bottom modules of different levels are nested with each other according to their level size; A macro function encapsulation unit is used to define a macro function for connecting an interface in the definition files of the top-level module and each bottom-level module; wherein the macro function is used to encapsulate the macro function for connecting an interface that has been written in the bottom level of the next level; The recursive call unit is used to quickly configure the connection interface by recursively calling the macro function from the top module to the bottom layer of the next level when it detects that it needs to be connected to an external DUT, so as to realize that the UVM verification platform is connected to the DUT through the configured connection interface.

6. The interface rapid configuration device of the UVM verification platform according to claim 5, wherein Also includes: The port encapsulation unit is used to automatically encapsulate the two input and output ports of the bottom module into independent agents by configuring the script.

7. The interface rapid configuration device of the UVM verification platform according to claim 6, wherein In the configuration definition file, declare the current connection interface, and then use the is_active parameter to specify the connection direction of the connection interface to determine whether it needs to be driven to the DUT through the env verification environment through the sequence; among them, when driven by the sequence in the env verification environment, is_active is 1, and when driven by the DUT, is_active is 0.

8. the interface rapid configuration device of UVM verification platform according to claim 5, is characterized in that For encapsulated macro functions, the underlying module of the layer is instantiated by the upper-level module, which includes two usage modes: The first usage mode corresponds to the input port of the underlying module being driven by sequence stimulus; The input port of the underlying module corresponding to the second usage mode is driven by the output port of the preceding module.

9. An interface rapid configuration device for a UVM verification platform, characterized in that, The invention comprises a memory and a processor, wherein a computer program is stored in the memory, and the computer program can be executed by the processor to implement the interface rapid configuration method of the UVM verification platform according to any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that A computer program is stored, and the computer program can be executed by a processor of the device where the computer-readable storage medium is located to implement the interface rapid configuration method of the UVM verification platform according to any one of claims 1 to 4.

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