Electronic device and method for software and hardware collaboration

Abstract

An electronic device includes a remapping hardware, a processor, and a north bridge integrated circuit. The remapping hardware converts a virtual address into a physical address. The processor executes a software for configuring the remapping hardware. The north bridge integrated circuit transmits the physical address to the processor. When the software changes the configuration of the remapping hardware, the remapping hardware outputs a data diversion instruction. When the north bridge integrated circuit receives the data diversion instruction at a first time point, the north bridge integrated circuit puts aside the instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are completed at a second time point, and at the second time point, outputs a response instruction to the remapping hardware. The remapping hardware notifies the processor that the execution of the data diversion instruction has been completed based on the response instruction.

Description

Technical Field

[0001] The invention relates to an electronic device, and more particularly to an electronic device and a method for software and hardware collaboration. Background Art

[0002] With the rise of artificial intelligence (AI), heterogeneous computing and virtualization technologies are becoming increasingly important. The address remapping unit (remapping hardware) related to virtualization technology has become indispensable in computer systems. The two main functions of the address remapping unit are to handle direct memory access remapping (DMA remapping) and interrupt remapping. In order to improve conversion efficiency, the address remapping unit stores the page table contents in the memory into its internal cache.

[0003] When the software needs to reset the system and invalidate the original contents in the cache, due to the change in the mapping relationship, the instructions that have been processed by the remapping unit need to be sent to the processor (CPU) before the state changes (these instructions are executed with the old mapping relationship), and then report the completion of the state transition or the invalidation of the cache. Data draining refers to instructions that have been processed by the remapping unit but are still in the queue of the external device and are waiting for the software to complete the processing. If the execution of the draining instructions is not thorough, it may cause irreversible effects on the system. Summary of the invention

[0004] An electronic device according to an embodiment of the present invention includes a remapping hardware, a processor, and a north bridge integrated circuit. The remapping hardware converts a virtual address into a corresponding physical address. The processor executes a software for configuring the remapping hardware. The north bridge integrated circuit transmits the physical address to the processor. When the software changes the configuration of the remapping hardware, the remapping hardware outputs a data draining instruction. When the north bridge integrated circuit receives the data draining instruction at a first time point, the north bridge integrated circuit puts aside the instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are completed at a second time point, and at the second time point, outputs a response instruction to the remapping hardware. The second time point is later than the first time point. The remapping hardware notifies the processor that the execution of the data draining instruction has been completed based on the response instruction.

[0005] The electronic device as described above further includes an external device that transmits the virtual address to the remapping hardware. When the external device receives the data diversion instruction at a first time point, the external device puts on hold instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are completed at a third time point. At the third time point, the external device outputs a second response instruction to the remapping hardware. The third time point is later than the first time point. The remapping hardware does not notify the processor that the execution of the data diversion instruction has been completed until the response instruction and the second response instruction are received.

[0006] In the electronic device as described above, after the software changes the configuration of the remapping hardware and before the remapping hardware outputs the data drainage instruction, the remapping hardware checks whether there is another data drainage instruction that has not been executed to completion.

[0007] In the electronic device as described above, the north bridge integrated circuit transmits the physical address to the processor through a direct memory access (DMA) instruction, and the processor sends a confirmation instruction back to the north bridge integrated circuit as a response.

[0008] In the electronic device as described above, the north bridge integrated circuit includes a counter. When the north bridge integrated circuit receives a data diversion instruction at a first time point, the north bridge integrated circuit executes the instruction being executed before the first time point, the counter counts the instruction being executed before the first time point, and counts the confirmation instructions from the processor in response to the instruction being executed before the first time point.

[0009] In the electronic device as described above, when the north bridge integrated circuit executes one of the instructions being executed before the first time point, the count of the counter is increased by 1. When the north bridge integrated circuit receives a confirmation instruction from the processor in response to one of the instructions being executed before the first time point, the count of the counter is reduced by 1. When the count of the counter returns to zero, the north bridge integrated circuit outputs a response instruction to the remapping hardware.

[0010] In the electronic device as described above, when the software changes the configuration of the remapping hardware, the processor outputs a configuration instruction to the remapping hardware, so that the remapping hardware outputs data diversion instructions to the north bridge integrated circuit and the external device according to the configuration instruction.

[0011] The electronic device as described above, wherein the remapping hardware includes a cache. The cache includes at least a first sub-cache and a second sub-cache. The first sub-cache and the second sub-cache correspond to the same configuration instruction. The processor notifies the remapping hardware that the configuration instruction has been issued by changing the state of the first sub-cache. The remapping hardware notifies the processor that the data diversion instruction associated with the configuration instruction has been executed by changing the state of the second sub-cache.

[0012] The method for improving the collaborative work of software and hardware according to the embodiment of the present invention is applicable to an electronic device having a remapping hardware, a processor, and a north bridge integrated circuit, wherein the processor executes a software for configuring the remapping hardware; the method comprises: the software changes the configuration of the remapping hardware; the remapping hardware checks whether there is a previous data draining instruction that has not been executed; the remapping hardware outputs a data draining instruction to the north bridge integrated circuit; the north bridge integrated circuit receives the data draining instruction at a first time point; the north bridge integrated circuit puts on hold the instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are executed at a second time point; the north bridge integrated circuit outputs a response instruction to the remapping hardware at the second time point, the second time point being later than the first time point; the remapping hardware notifies the processor that the execution of the data draining instruction has been completed based on the response instruction.

[0013] As described above, when the electronic device also includes an external device, the method also includes: the remapping hardware outputs a data diversion instruction to the external device; the external device receives the data diversion instruction at a first time point; the external device puts on hold instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are completed at a third time point; at the third time point, the external device outputs a second response instruction to the remapping hardware, the third time point being later than the first time point; the remapping hardware does not notify the processor that the execution of the data diversion instruction has been completed until it receives the response instruction and the second response instruction.

[0014] According to the method described above, when the north bridge integrated circuit receives a data diversion instruction at a first time point, the method further includes: the north bridge integrated circuit executes the instruction being executed before the first time point; the north bridge integrated circuit counts the instructions being executed before the first time point; and the north bridge integrated circuit counts a confirmation instruction from the processor in response to the instruction being executed before the first time point.

[0015] According to the method described above, when the north bridge integrated circuit receives a data diversion instruction at a first time point, the method further includes: adding 1 to a count value each time the north bridge integrated circuit executes one of the instructions being executed before the first time point; subtracting 1 from a count value each time the north bridge integrated circuit receives a confirmation instruction from the processor in response to one of the instructions being executed before the first time point; and when the count value returns to zero, the north bridge integrated circuit outputs a response instruction to the remapping hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present invention.

[0017] Figure 2 For the embodiment of the present invention Figure 1A signal timing diagram of the electronic device 100 executing a data draining instruction.

[0018] Figure 3 For the embodiment of the present invention Figure 1 A timing diagram of signals between the remapping hardware 102 and the processor 104 notifying each other via the register.

[0019] Figure 4 For the embodiment of the present invention Figure 1 A timing diagram of signals for the remapping hardware 102 to receive a plurality of configuration instructions from the processor 104.

[0020] Figure 5 For the embodiment of the present invention, it is applicable to Figure 1 Flow chart of a method for improving software and hardware collaboration by remapping hardware 102, processor 104, and north bridge integrated circuit 106.

[0021] Figure 6 The embodiments of the present invention are applicable to Figure 1 The remapping hardware 102, the processor 104, the north bridge integrated circuit 106, and the external device 108 are based on Figure 5 Flowchart of a method for improving software and hardware collaboration.

[0022] Figure 7 For the embodiment of the present invention Figure 5 Detailed flowchart of step S508. DETAILED DESCRIPTION

[0023] The present invention is described with reference to the accompanying drawings, in which the same reference numerals throughout the drawings indicate similar or identical components. The above drawings are not depicted according to the actual scale, and they are only provided for the purpose of illustrating the present invention. Some of the invention's forms are described below as references for the illustrated exemplary applications. This means that many specific details, relationships and methods are described to provide a complete understanding of this invention. However, a person with general knowledge in the relevant field will recognize that this invention can still be implemented without one or more of the specific details or with other methods.

[0024] For other examples, well-known structures or operations are not listed in detail to avoid obscuring the invention. The present invention is not limited by the order of the acts or events described, such as some acts may occur in a different order or simultaneously with other acts or events. In addition, not all acts or events described need to be performed in the same method as the prior invention.

[0025] Figure 1 FIG. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present invention. Figure 1As shown, the electronic device 100 includes a remapping hardware 102, a processor 104, a north bridge integrated circuit 106, and an external device 108. In some embodiments, the remapping hardware 102 can convert a virtual address into a physical address. The remapping hardware 102 includes a cache 110. The cache 110 stores a mapping table that records the correspondence between virtual addresses and physical addresses. In some embodiments, the electronic device 100 can be, for example, a laptop computer, a desktop computer, a tablet computer, a smart mobile device, or a workstation server.

[0026] For example, the external device 108 intends to read data in a memory (not shown) in the electronic device 100. First, the external device 108 outputs a virtual address VA to the remapping hardware 102. The remapping hardware 102 converts the virtual address VA from the external device 108 into a physical address PA according to the mapping table in the cache 110, and transmits the physical address PA back to the external device 108. Next, the external device 108 transmits the physical address PA to the north bridge integrated circuit 106, and the north bridge integrated circuit 106 forwards the physical address PA to the processor 104. Afterwards, the processor 104 transmits the physical address to a memory controller (not shown), so that the memory controller can read the data corresponding to the physical address PA in the memory.

[0027] In some embodiments, the external device 108 intends to write data into the memory of the electronic device 100, and there is no direct interface between the external device 108 and the remapping hardware 102. Therefore, the external device 108 can first output the virtual address VA to the north bridge integrated circuit 106, and the north bridge integrated circuit 106 then transmits the virtual address VA from the external device 108 to the remapping hardware 102. Similarly, the remapping hardware 102 converts the virtual address VA into the physical address PA according to the mapping table in the cache 110. Then, the remapping hardware 102 transmits the physical address PA to the north bridge integrated circuit 106. The north bridge integrated circuit then transmits the physical address PA to the processor 104. Afterwards, the processor 104 transmits the physical address PA to the memory controller, so that the memory controller can write the data into the physical address PA of the memory.

[0028] The processor 104 executes a software for configuring the remapping hardware 102. In some embodiments, when the software changes the configuration of the remapping hardware 102, the processor 104 outputs a configuration instruction 160 to the remapping hardware 102, so that the remapping hardware 102 correspondingly outputs a data draining instruction (e.g., data draining instructions 120, 130) to components connected thereto, such as the northbridge integrated circuit 106 and the external device 108.

[0029] When the northbridge integrated circuit 106 receives the data diversion instruction 120 from the remapping hardware 102 at a first time point, the northbridge integrated circuit 106 will put on hold the instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are completed at a second time point. The second time point is later than the first time point. Similarly, when the external device 108 receives the data diversion instruction 130 from the remapping hardware 102 at a first time point, the external device 108 will put on hold the instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are completed at a third time point. The third time point is later than the first time point.

[0030] In some embodiments, when the northbridge integrated circuit 106 completes the instruction being executed before the first time point at the second time point, the northbridge integrated circuit 106 outputs a response instruction 122 to the remapping hardware 102. Similarly, when the external device 108 completes the instruction being executed before the first time point at the third time point, the external device 108 outputs a response instruction 132 to the remapping hardware 102.

[0031] After receiving the response instruction 122 and the response instruction 132, the remapping hardware 102 notifies the processor 104 that the execution of the data diversion instructions 120 and 130 has been completed. Afterwards, the remapping hardware 102 can update the correspondence between the virtual address and the physical address recorded in the mapping table in the cache 110 for executing instructions according to the new configuration of the software. When the mapping table in the cache 110 has been updated, the north bridge integrated circuit 106 and the external device 108 can continue to execute the instructions that have not been executed after the first time point.

[0032] In short, the remapping hardware 102 can only notify the processor 104 that the execution of the data diversion instructions of all components has been completed after collecting the response instructions (such as the response instructions 122 and 132) replied by all the components connected to it.

[0033] Since the north bridge integrated circuit 106 and the external device 108 can only execute one data diversion instruction at the same time, after the software changes the configuration of the remapping hardware 102, and before the remapping hardware 102 outputs a new data diversion instruction, the remapping hardware 102 will check whether there is another data diversion instruction that has not been executed. In other words, the remapping hardware 102 will check whether it has received response instructions from all components to determine whether there is another data diversion instruction that has not been executed. When the remapping hardware 102 has received response instructions from all components, the remapping hardware 102 determines that another data diversion instruction has been completed, and confirms that there is no other data diversion instruction that has not been completed. After that, the remapping hardware 102 will output a new data diversion instruction to the north bridge integrated circuit 106 and the external device 108.

[0034] In some embodiments, when the northbridge integrated circuit 106 receives the data drainage instruction 120 from the remapping hardware 102 at a first time point, the northbridge integrated circuit 106 executes the instruction that was being executed before the first time point. For example, the northbridge integrated circuit 106 is transmitting the physical address to the processor 104 via a direct memory access (DMA) instruction 140 before the first time point, and the processor 104 sends a confirmation instruction 142 back to the northbridge integrated circuit 106 in response.

[0035] Similarly, when the external device 108 receives the data flow instruction 130 from the remapping hardware 102 at the first time point, the external device 108 executes the instruction that was being executed before the first time point. For example, the external device 108 is transmitting the physical address to the processor 104 (through the transfer of the north bridge integrated circuit 106) through a direct memory access (DMA) instruction 150 before the first time point, and the processor 104 sends a confirmation instruction 152 back to the external device 108 as a response. In some embodiments, the direct memory access instruction 140, 150 can be a DMA read instruction, or a DMA write instruction, but the present invention is not limited thereto.

[0036] In some embodiments, the northbridge integrated circuit 106 includes a counter 114. When the northbridge integrated circuit 106 receives the data drainage instruction 120 at a first time point, the counter 114 counts the instructions being executed before the first time point (e.g., the direct memory access instruction 140), and counts the confirmation instructions (e.g., the confirmation instruction 142) from the processor 104 in response to the instructions being executed before the first time point.

[0037] Specifically, assuming that the number of instructions being executed by the northbridge integrated circuit 106 before the first time point is 10, each time the northbridge integrated circuit 106 continues to execute one of the 10 instructions, the count value of the counter 114 increases by 1. Each time the northbridge integrated circuit 106 receives a confirmation instruction from the processor 104 in response to one of the 10 instructions, the count value of the counter 114 decreases by 1. When the count value of the counter 114 returns to zero, the northbridge integrated circuit 106 outputs a response instruction 122 to the remapping hardware 102.

[0038] Similarly, in some embodiments, the external device 108 includes a counter 116. When the external device 108 receives the data drainage instruction 130 at a first time point, the counter 116 counts the instructions being executed before the first time point, and counts the confirmation instructions from the processor 104 in response to the instructions being executed before the first time point.

[0039] Similarly, assuming that the external device 108 is executing 5 instructions before the first time point, each time the external device 108 continues to execute one of the 5 instructions, the count value of the counter 116 increases by 1. Each time the external device 108 receives a confirmation instruction from the processor 104 in response to one of the 5 instructions, the count value of the counter 116 decreases by 1. When the count value of the counter 116 returns to zero, the external device 108 outputs a response instruction 132 to the remapping hardware 102. In some embodiments, the external device 108 is a Peripheral Component Interconnect Express (PCI-e) device, but the present invention is not limited thereto.

[0040] Figure 2 For the embodiment of the present invention Figure 1 The electronic device 100 of FIG. 1 is a signal timing diagram for executing a data draining instruction. Figure 1 and Figure 2 When the software changes the configuration of the remapping hardware 102, the processor 104 outputs the configuration instruction 160 to the remapping hardware 102. The remapping hardware 102 receives the configuration instruction 160 from the processor 104 at time point t1, driving the remapping hardware 102 to correspondingly output the data diversion instruction 120 to the north bridge integrated circuit 106 at time point t1, and output the data diversion instruction 130 to the external device 108. The remapping hardware 102 receives the response instruction 122 from the north bridge integrated circuit 106 at time point t2, and learns that the north bridge integrated circuit 106 has completed the execution of the data diversion instruction 120. Therefore, the remapping hardware 102 changes the voltage of the data diversion instruction 120 from a high level to a low level, indicating that the execution of the data diversion instruction 120 has been completed.

[0041] Similarly, the remapping hardware 102 receives the response instruction 132 from the external device 108 at time point t3, and learns that the external device 108 has completed the execution of the data diversion instruction 130. Therefore, the remapping hardware 102 changes the voltage of the data diversion instruction 130 from a high level to a low level, indicating that the execution of the data diversion instruction 130 has been completed. The north bridge integrated circuit 106 executes the data diversion procedure between time point t1 and time point t2. The external device 108 executes the data diversion procedure between time point t1 and time point t3.

[0042] Since the remapping hardware 102 must wait for the Northbridge IC 106 and the external device 108 to complete the data diversion process (i.e., receive the response instruction 122 and the response instruction 132) before notifying the processor 104, the electronic device 100 executes the data diversion process (i.e., Figure 2 The period of draining_process) is from time point t1 to time point t3.

[0043] In some embodiments, the processor 104 outputs configuration instructions 160 to the remapping hardware 102 in response to the reconfiguration of the remapping hardware 102 by software. The configuration instructions 160 may include a DMA remapping function on / off instruction, a DMA protection memory check function on / off instruction, an input / output translation lookaside buffer (IOTLB) cache invalidation instruction, an interrupt remapping function on / off instruction, and an interrupt remapping entry cache (IREC) cache invalidation instruction.

[0044] In other words, as long as the remapping hardware 102 receives the above-mentioned DMA remapping function on / off instruction, DMA protection memory check function on / off instruction, IOTLB cache invalidation instruction, interrupt remapping function on / off instruction, and IREC cache invalidation instruction from the processor 104, the remapping hardware 102 will correspondingly issue a data diversion instruction 120 to the north bridge integrated circuit 106 and a data diversion instruction 130 to the external device 108.

[0045] Figure 3 For the embodiment of the present invention Figure 1 The remapping hardware 102 and the processor 104 use the buffer to notify each other. Figure 1 and Figure 3 , the remapping hardware 102 further includes a buffer 112. In some embodiments, the buffer 112 includes a sub-buffer TE and a sub-buffer TES (not shown). The sub-buffer TE and the sub-buffer TES correspond to the DMA remapping function on / off instruction. The processor 104 informs the remapping hardware 102 that its DMA remapping function on / off instruction has been issued by changing the state of the sub-buffer TE. The remapping hardware 102 informs the processor 104 that the data drainage instruction associated with the DMA remapping function on / off instruction has been executed by changing the state of the sub-buffer TES.

[0046] For example, if Figure 3As shown, the processor 104 changes the state of the sub-register TE from a low level to a high level at time point t4, that is, the processor 104 transmits a DMA remapping function start instruction to the remapping hardware 102 at time point t4. The remapping hardware 102 reads the sub-register TE and learns that its state has changed, so it sends a data draining instruction (such as data draining instructions 120, 130) to the north bridge integrated circuit 106 and the external device 108 at time point t5. The north bridge integrated circuit 106 and the external device 108 perform the data draining program between time point t5 and time point t6. The remapping hardware 102 has received a response instruction (such as response instruction 122, 132) from the north bridge integrated circuit 106 and the external device 108 at time point t6, so the voltage of the data draining program draining_process changes from a high level to a low level at time point t6. At the same time, the remapping hardware 102 changes the state of the sub-register TES from a low level to a high level at time point t6. The processor 104 reads the sub-register TES and learns that its status has changed, so that the software knows at time point t6 that the data drainage instruction associated with the DMA remapping function enable instruction has been executed.

[0047] Similarly, if Figure 3 As shown, the processor 104 changes the state of the sub-register TE from a high level to a low level at time point t7, that is, the processor 104 transmits a DMA remapping function shutdown instruction to the remapping hardware 102 at time point t7. The remapping hardware 102 reads the sub-register TE and learns that its state has changed, so it sends a data draining instruction to the north bridge integrated circuit 106 and the external device 108 at time point t8. The north bridge integrated circuit 106 and the external device 108 execute the data draining program between time point t8 and time point t9. The remapping hardware 102 has received the response instruction from the north bridge integrated circuit 106 and the external device 108 at time point t9, so the voltage of the data draining program draining_process changes from a high level to a low level at time point t9. At the same time, the remapping hardware 102 changes the state of the sub-register TES from a high level to a low level at time point t9. The processor 104 reads the sub-register TES and learns that its status has changed, so that the software knows at time point t9 that the data drainage instruction associated with the DMA remapping function disabling instruction has been executed.

[0048] In some embodiments, the buffer 112 includes a sub-buffer EPM and a sub-buffer PRS (not shown). When the configuration instruction 160 is a DMA protection memory check function on / off instruction, the processor 104 notifies the remapping hardware 102 that the DMA protection memory check function on / off instruction has been issued by changing the state of the sub-buffer EPM. The remapping hardware 102 notifies the processor 104 that the data drainage instruction associated with the DMA protection memory check function on / off instruction has been executed by changing the state of the sub-buffer PRS.

[0049] In some embodiments, when the configuration instruction 160 is an IOTLB cache invalidation instruction, the processor 104 directly transmits an IOTLB invalidation instruction to the remapping hardware 102, so that the remapping hardware 102 correspondingly sends a data drainage instruction to the north bridge integrated circuit 106 and the external device 108. The remapping hardware 102 directly transmits an interrupt event to the processor 104, so that the software knows that the data drainage instruction associated with the IOTLB cache invalidation instruction has been executed.

[0050] In some embodiments, the register 112 includes a sub-register IRE and a sub-register IRES (not shown). When the configuration instruction 160 is an interrupt remapping function on / off instruction, the processor 104 notifies the remapping hardware 102 that the interrupt remapping function on / off instruction has been issued by changing the state of the sub-register IRE. The remapping hardware 102 notifies the processor 104 that the data drainage instruction associated with the interrupt remapping function on / off has been executed by changing the state of the sub-register IRES.

[0051] In some embodiments, when the configuration instruction 160 is an IREC cache invalidation instruction, the processor 104 directly transmits an IREC invalidation instruction to the remapping hardware 102, so that the remapping hardware 102 correspondingly sends a data drain instruction to the northbridge integrated circuit 106 and the external device 108. The remapping hardware 102 directly transmits an interrupt event to the processor 104, so that the software knows that the data drain instruction associated with the IREC invalidation instruction has been executed.

[0052] Figure 4 For the embodiment of the present invention Figure 1 The remapping hardware 102 receives a plurality of configuration instructions from the processor 104. Figure 1 and Figure 4, the remapping hardware 102 receives the configuration instruction 160_1 from the processor 104 at time point t10, and accordingly outputs the data draining instruction to the north bridge integrated circuit 106 and the external device 108, so that the north bridge integrated circuit 106 and the external device 108 start to execute the data draining program at time point t10 (that is, the voltage of draining_process changes from a low level to a high level at time point t10).

[0053] Next, the remapping hardware 102 receives another configuration instruction 160_2 from the processor 104 at time point t11, and receives another configuration instruction 160_3 from the processor 104 at time point t12. Figure 4 As shown, since at time point t11 ​​and time point t12, the north bridge integrated circuit 106 and the external device 108 are still executing the data diversion program corresponding to the configuration instruction 160_1, the remapping hardware 102 detects that there are still unfinished data diversion instructions. Therefore, the remapping hardware 102 can only wait for the data diversion program corresponding to the configuration instruction 160_1 to be completed, and then transmit the data diversion instruction corresponding to the configuration instruction 160_2 to the north bridge integrated circuit 106 and the external device 108 at time point t13.

[0054] When the data diversion program corresponding to the configuration instruction 160_2 is completed, the remapping hardware 102 will then send the data diversion instruction corresponding to the configuration instruction 160_3 to the north bridge integrated circuit 106 and the external device 108. In short, the north bridge integrated circuit 106 and the external device 108 can only execute the operation of one data diversion instruction at a time.

[0055] Figure 5 For the embodiment of the present invention, it is applicable to Figure 1 Flow chart of a method for improving the coordination of software and hardware by remapping hardware 102, processor 104, and north bridge integrated circuit 106. Figure 5 As shown, in step S500, the software (i.e., the processor 104) first changes the configuration of the remapping hardware. In step S502, the remapping hardware 102 checks that there is no previous data drainage instruction that has not been executed. Then, in step S504, the remapping hardware 102 outputs a data drainage instruction (e.g., data drainage instruction 120) to the north bridge integrated circuit 106. In step S506, the north bridge integrated circuit 106 receives the data drainage instruction at a first time point.

[0056] Furthermore, in step S508, the northbridge integrated circuit 106 puts on hold the instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are completed at a second time point. In step S510, the northbridge integrated circuit 106 outputs a response instruction (e.g., response instruction 122) to the remapping hardware 102 at the second time point, the second time point being later than the first time point. Finally, in step S512, the remapping hardware notifies the processor 104 that the execution of the data diversion instruction has been completed according to the response instruction.

[0057] Figure 6 The embodiments of the present invention are applicable to Figure 1 The remapping hardware 102, the processor 104, the north bridge integrated circuit 106, and the external device 108 are based on Figure 5 A flowchart of a method for improving the collaboration between software and hardware. Figure 6 As shown, the method for improving the cooperation between software and hardware of the present invention includes Figure 5 The steps S500-S510 further include, in step S600, the remapping hardware 102 outputs a data diversion instruction (eg, the data diversion instruction 130) to the external device 108. In step S602, the external device 108 receives the data diversion instruction at a first time point.

[0058] In step S604, the external device 108 puts on hold the instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are completed at a third time point. Next, in step S606, at the third time point, the external device 108 outputs a second response instruction (e.g., response instruction 132) to the remapping hardware 102, and the third time point is later than the first time point. Finally, in step S608, the remapping hardware 102 does not notify the processor 104 that the execution of the data diversion instruction has been completed until the response instruction and the second response instruction are received.

[0059] Figure 7 For the embodiment of the present invention Figure 5 The detailed flow chart of step S508 is shown in FIG. Figure 7 As shown, in step S700, the north bridge integrated circuit 106 executes the instruction being executed before the first time point. In step S702, the north bridge integrated circuit 106 counts the instructions being executed before the first time point. In step S704, when the north bridge integrated circuit 106 executes one of the instructions being executed before the first time point, the count value is increased by 1.

[0060] Next, in step S706, the northbridge integrated circuit 106 counts a confirmation instruction from the processor 104 in response to the instruction being executed before the first time point. In step S708, when the northbridge integrated circuit 106 receives a confirmation instruction from the processor 104 in response to one of the instructions being executed before the first time point, the count value is reduced by 1. Finally, in step S710, when the count value returns to zero, the northbridge integrated circuit 106 outputs a response instruction (e.g., response instruction 122) to the remapping hardware 102.

[0061] The electronic device and method for improving the collaborative work of software and hardware of the present invention increase the reliability of IO virtualization hardware and can protect the system data to a certain extent. When the IOV device faces the virtualization software changing the system state or modifying the page table content, the hardware can make a smoother transition. The data draining program executed by the present invention has the following advantages: 1. It does not affect the performance of other normal functions; 2. It is a complete data draining process without missing any instructions; 3. It adds confirmation instructions (such as confirmation instructions 142 and 152) for the processor to respond to DMA instructions, which are used to confirm whether the data draining program is completed. The processor in the prior art does not respond to DMA instructions, but directly transfers the DMA instructions (for example, to the memory controller).

[0062] 4. The data diversion procedure between the remapping hardware and the north bridge integrated circuit (or external device) is completed by a handshake signal (for example, the data diversion instruction 120 corresponds to the response instruction 122, and the data diversion instruction 130 corresponds to the response instruction 132); 5. The remapping hardware only issues specific data diversion instructions at specific times (for example, when the configuration instruction 160 is a DMA remapping function on / off instruction, a DMA protection memory check function on / off instruction, an IOTLB cache invalidation instruction, an interrupt remapping function on / off instruction, or an IREC cache invalidation instruction).

[0063] Although the embodiments of the present invention are described above, it should be understood that what is presented above is only an example, not a limitation. Many changes to the above exemplary embodiments can be implemented without violating the spirit and scope of the invention according to this embodiment. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above. More specifically, the scope of the present invention should be defined by the following claims and their equivalents.

[0064] Although the invention has been illustrated and described above with reference to one or more implementations, equivalent changes and modifications will occur to others familiar with the art based on the above specification and drawings. In addition, although a particular feature of an embodiment of the invention has been demonstrated with reference to one of the multiple implementations, the feature may be combined with one or more other features as may be desirable and useful for any known or particular application.

[0065] Unless otherwise defined, all terms (including technical or scientific terms) used herein are generally understood by those having ordinary skill in the art to which the above invention belongs. We should further understand that the above terms, as defined in commonly used dictionaries, should be interpreted as having the same meaning in the context of the relevant art. Unless otherwise explicitly defined herein, the above terms are not to be interpreted as having an idealized or overly formal meaning.

Claims

1. An electronic device, comprising: A remapping hardware that converts virtual addresses into corresponding physical addresses; a processor, executing software for configuring the remapping hardware; a north bridge integrated circuit that transmits the physical address to the processor; When the software changes the configuration of the remapping hardware, the remapping hardware outputs a data diversion instruction; When the north bridge integrated circuit receives the data diversion instruction at a first time point, the north bridge integrated circuit suspends instructions that have not been executed after the first time point until the instructions that are being executed before the first time point are completed at a second time point, and outputs a response instruction to the remapping hardware at the second time point; the second time point is later than the first time point; The remapping hardware notifies the processor that the execution of the data diversion instruction has been completed according to the response instruction.

2. The electronic device as claimed in claim 1, further comprising: an external device that transmits the virtual address to the remapping hardware; When the external device receives the data diversion instruction at the first time point, the external device puts on hold instructions that have not been executed after the first time point until the instructions that were being executed before the first time point are completed at a third time point; At the third time point, the external device outputs a second response instruction to the remapping hardware; the third time point is later than the first time point; The remapping hardware does not notify the processor that the execution of the data diversion instruction has been completed until the response instruction and the second response instruction are received.

3. The electronic device according to claim 1, wherein: After the software changes the configuration of the remapping hardware, before the remapping hardware outputs the data drainage instruction, the remapping hardware checks whether there is another data drainage instruction that has not been executed completely.

4. The electronic device according to claim 1, wherein: The north bridge integrated circuit transmits the physical address to the processor through a direct memory access instruction, and the processor sends back a confirmation instruction to the north bridge integrated circuit as a response.

5. The electronic device as claimed in claim 4, wherein: The north bridge integrated circuit includes a counter; when the north bridge integrated circuit receives the data drainage instruction at the first time point, the north bridge integrated circuit executes the instruction being executed before the first time point, the counter counts the instructions being executed before the first time point, and counts the confirmation instructions from the processor in response to the instructions being executed before the first time point.

6. The electronic device as claimed in claim 5, wherein: Each time the north bridge integrated circuit executes one of the instructions being executed before the first time point, the count of the counter is increased by 1; each time the north bridge integrated circuit receives the confirmation instruction from the processor in response to one of the instructions being executed before the first time point, the count of the counter is reduced by 1; when the count of the counter returns to zero, the north bridge integrated circuit outputs the response instruction to the remapping hardware.

7. The electronic device as claimed in claim 2, wherein: When the software changes the configuration of the remapping hardware, the processor outputs a configuration instruction to the remapping hardware, so that the remapping hardware correspondingly outputs the data diversion instruction to the north bridge integrated circuit and the external device according to the configuration instruction.

8. The electronic device as claimed in claim 7, wherein: The remapping hardware includes a cache; the cache includes at least a first sub-cache and a second sub-cache, wherein the first sub-cache and the second sub-cache correspond to the same configuration instruction; the processor informs the remapping hardware that the configuration instruction has been issued by changing the state of the first sub-cache; the remapping hardware informs the processor that the data drainage instruction associated with the configuration instruction has been executed by changing the state of the second sub-cache.

9. A method for collaborative work of software and hardware, applicable to an electronic device having a remapping hardware, a processor, and a north bridge integrated circuit, wherein the processor executes a software for configuring the remapping hardware; the method comprising: The software changes the configuration of the remapping hardware; The remapping hardware checks that there is no previous data drain instruction that has not yet been executed to completion; The remapping hardware outputs a data diversion instruction to the north bridge integrated circuit; The north bridge integrated circuit receives the data diversion instruction at a first time point; The north bridge integrated circuit suspends the instructions that have not been executed after the first time point until the instructions that are being executed before the first time point are completed at a second time point; The north bridge integrated circuit outputs a response instruction to the remapping hardware at the second time point; wherein the second time point is later than the first time point; The remapping hardware notifies the processor that the execution of the data diversion instruction has been completed according to the response instruction.

10. The method of claim 9, wherein: When the electronic device further includes an external device, the method further includes: The remapping hardware outputs the data diversion instruction to the external device; The external device receives the data diversion instruction at the first time point; The external device suspends the instructions that have not been executed after the first time point until the instructions that are being executed before the first time point are completed at a third time point; At the third time point, the external device outputs a second response instruction to the remapping hardware; the third time point is later than the first time point; The remapping hardware does not notify the processor that the execution of the data diversion instruction has been completed until the response instruction and the second response instruction are received.

11. The method of claim 9, wherein: When the north bridge integrated circuit receives the data diversion instruction at the first time point, the method further includes: The north bridge integrated circuit executes the instruction being executed before the first time point; The north bridge integrated circuit counts the instructions being executed before the first time point; The north bridge integrated circuit counts a confirmation instruction from the processor in response to the instruction being executed before the first time point.

12. The method of claim 11, wherein: When the north bridge integrated circuit receives the data diversion instruction at the first time point, the method further includes: When the north bridge integrated circuit executes each of the instructions being executed before the first time point, the count value is increased by 1; When the north bridge integrated circuit receives the confirmation instruction from the processor in response to one of the instructions being executed before the first time point, the count value is reduced by 1; When the count value returns to zero, the north bridge integrated circuit outputs the response instruction to the remapping hardware.

Images