Semiconductor device and semiconductor memory device

Abstract

The present application discloses a semiconductor device and a semiconductor memory device. A semiconductor device includes a sudden power detection circuit, a power-on reset circuit, and a driving circuit. The sudden power detection circuit is configured to detect a voltage level of an external power supply voltage and generate a sudden power detection signal. The power-on reset circuit is configured to detect the voltage level of the external power supply voltage based on a reset reference voltage and generate a power-on reset signal. The driving circuit is configured to perform a sudden power-off operation and a power-on reset operation.

Description

Technical Field

[0001] Various embodiments generally relate to semiconductor devices and semiconductor memory devices, and more particularly, to semiconductor devices and semiconductor memory devices related to performing a sudden power-off operation and a power-on reset operation. Background Art

[0002] Generally, a semiconductor device performs circuit operations by using an internal power voltage generated based on an external power voltage. Similarly, a semiconductor memory device including a volatile memory device and a non-volatile memory device also performs circuit operations by using an internal power voltage generated based on an external power voltage.

[0003] In addition, a volatile memory device has an advantage in high data processing speed, which is a speed for storing external data therein or outputting internal data to the outside. However, a disadvantage of the volatile memory device is that it needs to continuously receive an external power voltage when processing data. On the other hand, a non-volatile memory device has a disadvantage in slow data processing speed. However, an advantage of the non-volatile memory device is that it retains data previously stored therein even without supplying an external power voltage.

[0004] The non-volatile memory device performs a programming operation to store data in a memory cell, and performs a read operation to output the data stored in the memory cell. In addition, the non-volatile memory device performs an erase operation to erase the data stored in the memory cell before the programming operation. As described above, the non-volatile memory device can retain data previously stored therein even without supplying an external power voltage. However, when the external power voltage is not stably supplied during the programming operation, the read operation, or the erase operation, the data stored in the memory cell may be damaged.

[0005] Specifically, during the programming operation, the read operation, or the erase operation, the non-volatile memory device applies a high voltage to a word line, a bit line, and a source line. Therefore, when the external power voltage is not stably supplied during the programming operation, the read operation, or the erase operation, the voltage level of the high voltage applied to the corresponding line may be undesirably reduced. In this case, due to the influence of the undesirably reduced voltage level of the high voltage, the data distribution of the memory cell connected to the corresponding line is changed. The change in the data distribution of the memory cell means a change in the data stored in the memory cell. In addition, the change in the data stored in the memory cell means that the reliability of the data cannot be guaranteed. Summary of the Invention

[0006] In an embodiment, a semiconductor device may include: a sudden power detection circuit that is enabled based on an enable signal and is configured to detect a voltage level of an external power supply voltage and generate a sudden power detection signal; a power-on reset circuit that is configured to set a reset reference voltage for a power-on reset operation based on the enable signal and a power-on reset signal, detect the voltage level of the external power supply voltage according to the reset reference voltage, and generate a power-on reset signal; and a drive circuit that is configured to perform a sudden power-off operation based on the sudden power detection signal and perform a power-on reset operation based on the power-on reset signal.

[0007] In an embodiment, a semiconductor memory device may include: a sudden power detection circuit that is enabled based on an enable signal and is configured to detect a voltage level of an external power supply voltage and generate a sudden power detection signal; a power-on reset circuit that is configured to set a reset reference voltage for a power-on reset operation based on the enable signal and a power-on reset signal, detect the voltage level of the external power supply voltage according to the reset reference voltage, and generate a power-on reset signal; and a discharge circuit that is configured to perform a discharge operation on a line connected to a memory cell based on the sudden power detection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a configuration of a semiconductor device according to an embodiment.

[0009] Figure 2 is an illustration Figure 1 of a circuit diagram of a configuration of the sudden power detection circuit.

[0010] Figure 3 is an illustration Figure 1 of a circuit diagram of a configuration of the power-on reset circuit.

[0011] Figure 4 is an illustration Figure 1 of an operation timing diagram of the semiconductor device.

[0012] Figure 5 is a block diagram illustrating a partial configuration of a semiconductor device according to an embodiment.

[0013] Figure 6 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment. DETAILED DESCRIPTION

[0014] The description of the present disclosure is only about embodiments of structural description and / or functional description. The scope of the rights of the present disclosure should not be construed as limited to the embodiments described in the specification. That is to say, since the embodiments can be modified in various ways and can have various forms, the scope of the rights of the present disclosure should be understood to include equivalent forms that can achieve the technical spirit. In addition, the objectives or effects proposed in the present disclosure do not mean that a specific embodiment should include all objectives or effects or only include such effects. Therefore, the scope of the rights of the present disclosure should not be understood as being limited by it.

[0015] The meaning of the terms described in this application should be understood as follows.

[0016] Terms such as "first" and "second" are used to distinguish one element from another, and the scope of the present disclosure should not be limited by these terms. For example, the first element can be named the second element. Similarly, the second element can be named the first element.

[0017] Unless otherwise clearly indicated in the context, the singular representation should be understood to include the plural representation. Terms such as "including" or "having" should be understood to mean the presence of a set of characteristics, quantities, steps, operations, elements, components, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other characteristics, quantities, steps, operations, elements, components, or combinations thereof.

[0018] In each step, for the convenience of description, symbols (for example, a, b, and c) are used, and these symbols do not describe the order of the steps. Unless a specific order is clearly described in the context, the steps can be executed in an order different from the order described in the context. That is to say, the steps can be executed according to the described order, can be executed substantially simultaneously with the described order, or can be executed in the order opposite to the described order.

[0019] Unless otherwise defined, all terms used herein (including technical or scientific terms) have the same meaning as commonly understood by those skilled in the art. Unless clearly defined in the application, terms defined in a common dictionary should be interpreted as having the same meaning as in the context of the related art and should not be interpreted as having an ideal or overly formal meaning.

[0020] Various embodiments may relate to providing a semiconductor device and a semiconductor memory device capable of stably controlling a sudden power-off operation and a power-on reset operation.

[0021] Various embodiments relate to providing a semiconductor device and a semiconductor memory device capable of stably controlling a power-on reset operation based on the characteristics of a transistor according to changes in process, voltage, and temperature.

[0022] The embodiment has the effect of stably controlling the sudden power-off operation and the power-on reset operation, thereby substantially preventing incorrect operations that may occur during the sudden power-off operation and the power-on reset operation.

[0023] The embodiment has the effect of stably controlling the power-on reset operation even when the characteristics of the transistor change, thereby substantially preventing incorrect operations that may occur during the power-on reset operation.

[0024] The object of the present disclosure is not limited to the above object, and according to the following description, those of ordinary skill in the art to which the present disclosure pertains can clearly understand other objects not described above.

[0025] Figure 1 is a block diagram illustrating the configuration of a semiconductor device according to an embodiment.

[0026] Referring to Figure 1 , the semiconductor device may include a sudden power detection circuit 100, a power-on reset circuit 200, and a drive circuit 300.

[0027] First, the sudden power detection circuit 100 may be enabled based on an enable signal ENB, and may be configured to detect the voltage level of an external power supply voltage VCC and generate a sudden power detection signal DTVCC. Therefore, the sudden power detection circuit 100 may generate a sudden power detection signal DTVCC that is enabled when the voltage level of the external power supply voltage VCC drops below a set voltage level.

[0028] The enable signal ENB may be a signal for enabling and disabling the sudden power detection circuit 100. The enable signal ENB may enable the sudden power detection circuit 100. In addition, the enable signal ENB may be disabled when the sudden power-off operation has been completed, and the sudden power detection circuit 100 may be disabled. For example, the enable signal ENB may be enabled during a sudden voltage drop or power-off period of the external power supply voltage VCC. The period of the enable signal ENB will be described again in Figure 4 .

[0029] Next, the power-on reset circuit 200 may be configured to set a reset reference voltage for the power-on reset operation based on the enable signal ENB and a power-on reset signal POR. In addition, the power-on reset circuit 200 may be configured to detect the voltage level of the external power supply voltage VCC according to the reset reference voltage, and generate a power-on reset signal POR. Therefore, the power-on reset circuit 200 may detect the voltage level of the external power supply voltage VCC according to the reset reference voltage set based on the enable signal ENB and the power-on reset signal POR, and generate a power-on reset signal POR.

[0030] As will be described later, the power-on reset circuit 200 can set a first reset reference voltage corresponding to a disable time point of the power-on reset signal POR based on the enable signal ENB and the power-on reset signal POR during a power-on period of the external power supply voltage VCC. In addition, the power-on reset circuit 200 can set a second reset reference voltage corresponding to an enable time point of the power-on reset signal POR based on the enable signal ENB during a power-down period of the external power supply voltage VCC. Here, the power-on reset circuit 200 can set the voltage level of the first reset reference voltage corresponding to the power-on period and the voltage level of the second reset reference voltage corresponding to the power-down period to be different from each other. This will be described again in Figure 4 as follows.

[0031] Next, the driving circuit 300 can be configured to perform a sudden power-off operation based on the sudden power detection signal DTVCC and perform a power-on reset operation based on the power-on reset signal POR. The sudden power-off operation can be a discharging operation for nodes included in the driving circuit 300. In addition, the power-on reset operation can be an initialization operation for the driving circuit 300 or an internal circuit included in the driving circuit 300. For example, the initialization operation can be an initialization operation for a circuit included in the semiconductor device that generates an internal power supply voltage, or an initialization operation for a latch circuit that stores an initial value during a programming operation and a reading operation of data.

[0032] The semiconductor device according to an embodiment can set the first reset reference voltage and the second reset reference voltage of the power-on reset circuit 200 based on the enable signal ENB corresponding to an enable period of the sudden power detection circuit 100, thereby stably controlling the power-on reset operation performed by the power-on reset circuit 200 and the sudden power-off operation performed by the sudden power detection circuit 100.

[0033] Figure 2 is an example Figure 1 of the circuit diagram showing the configuration of the sudden power detection circuit 100.

[0034] Referring to Figure 2 , the sudden power detection circuit 100 can include a voltage dividing circuit 110 and a voltage comparison circuit 120.

[0035] First, the voltage dividing circuit 110 can be configured to generate a divided voltage V_D obtained by dividing the voltage level of the external power supply voltage VCC based on the enable signal ENB.

[0036] The voltage dividing circuit 110 may include a first PMOS transistor P1 and first to fourth resistors R1 to R4. The first PMOS transistor P1 and the first to fourth resistors R1 to R4 are connected in series between a voltage terminal to which an external power supply voltage VCC is applied and a voltage terminal to which a ground power supply voltage VSS is applied. The first PMOS transistor P1 may receive an enable signal ENB through its gate, and the second resistor R2 and the third resistor R3 may be connected to a common node for outputting a divided voltage V_D.

[0037] Next, the voltage comparison circuit 120 may be configured to compare the divided voltage V_D and a sudden power reference voltage V_SPO, and generate a sudden power detection signal DTVCC.

[0038] The voltage comparison circuit 120 may receive the sudden power reference voltage V_SPO through its (+) terminal, receive the divided voltage V_D through its (-) terminal, and output the sudden power detection signal DTVCC. As will be described below with reference to Figure 4 The sudden power reference voltage V_SPO may have a voltage level between the voltage level of a first reset reference voltage and the voltage level of a second reset reference voltage.

[0039] Figure 3 is an illustration Figure 1 of the configuration of the power-on reset circuit 200.

[0040] Referring to Figure 3 the power-on reset circuit 200 may include a voltage detection circuit 210 and a signal output circuit 220.

[0041] First, the voltage detection circuit 210 may be configured to set a reset reference voltage based on the enable signal ENB and the power-on reset signal POR. In addition, the voltage detection circuit 210 may be configured to detect the external power supply voltage VCC based on the set reset reference voltage. The voltage detection circuit 210 may include a resistance adjustment circuit 211 and a voltage sensing circuit 212.

[0042] The resistance adjustment circuit 211 may be configured to adjust a resistance value for the voltage drop of the external power supply voltage VCC based on the enable signal ENB and the power-on reset signal POR.

[0043] The resistance adjustment circuit 211 may include a fifth resistor R5 to an eighth resistor R8, and the fifth resistor R5 to the eighth resistor R8 are connected in series to a voltage terminal to which an external power supply voltage VCC is applied. In addition, the resistance adjustment circuit 211 may include a second PMOS transistor P2 and a third PMOS transistor P3, and the second PMOS transistor P2 and the third PMOS transistor P3 are connected in series to a voltage terminal to which an external power supply voltage VCC is applied. The gate of the second PMOS transistor P2 may receive an enable signal ENB, and the gate of the third PMOS transistor P3 may receive a power-on reset signal POR. A resistor circuit including the fifth resistor R5 and the sixth resistor R6 and a transistor circuit including the second PMOS transistor P2 and the third PMOS transistor P3 may be connected in parallel.

[0044] For example, the second PMOS transistor P2 may be turned on or off based on the enable signal ENB, and the third PMOS transistor P3 may be turned on or off based on the power-on reset signal POR. Therefore, when the enable signal ENB or the power-on reset signal POR becomes logic "high", the second PMOS transistor P2 or the third PMOS transistor P3 may be turned off. Therefore, a voltage drop of the external power supply voltage VCC may occur due to the resistance values of the fifth resistor R5 to the eighth resistor R8. In addition, when both the enable signal ENB and the power-on reset signal POR become logic "low", the second PMOS transistor P2 and the third PMOS transistor P3 may be turned on. Therefore, the external power supply voltage VCC may be bypassed through the second PMOS transistor P2 and the third PMOS transistor P3. Therefore, a voltage drop of the external power supply voltage VCC may occur due to the resistance values of the seventh resistor R7 and the eighth resistor R8 rather than the fifth resistor R5 and the sixth resistor R6. With such a configuration, the resistance adjustment circuit 211 may adjust the resistance value for the voltage drop of the external power supply voltage VCC based on the enable signal ENB and the power-on reset signal POR.

[0045] Next, the voltage sensing circuit 212 may be configured to sense the external power supply voltage VCC whose resistance value has been decreased by the resistance adjustment circuit 211 based on a reset reference voltage.

[0046] The voltage sensing circuit 212 may include a ninth resistor R9 and a first NMOS transistor N1. The ninth resistor R9 and the first NMOS transistor N1 are connected in series between the resistance adjustment circuit 211 and a voltage terminal to which a ground power supply voltage VSS is applied. A first node ND1 may be commonly connected between the eighth resistor R8 and the ninth resistor R9, and the first NMOS transistor N1 may be connected in a diode type. In addition, the voltage sensing circuit 212 may include a second NMOS transistor N2 connected between a second node ND2 and a voltage terminal to which a ground power supply voltage VSS is applied. The gate of the second NMOS transistor N2 may be connected to the first node ND1.

[0047] For example, the voltage sensing circuit 212 may output the output voltage of the resistance adjustment circuit 211 to the first node ND1 as a sensed voltage. The second NMOS transistor N2 may be turned on or off based on the sensed voltage output from the first node ND1. When the second NMOS transistor N2 is turned on, the second node ND2 may be driven by the ground power supply voltage VSS. However, when the second NMOS transistor N2 is turned off, the second node ND2 may be driven to the level of the voltage output from the load circuit 221 described below. With such a configuration, the voltage sensing circuit 212 may determine the voltage level for driving the second node ND2 based on the sensed voltage.

[0048] As a reference, when assuming that the threshold voltage of the second NMOS transistor N2 is constant, the voltage level of the sensed voltage corresponding to the reference at which the second NMOS transistor N2 may be turned on or off may be constant. In this case, the voltage level of the external power supply voltage VCC at which the second NMOS transistor N2 may be turned on or off may be changed according to the resistance value adjusted by the resistance adjustment circuit 211. Therefore, the reset reference voltage of the semiconductor device according to the embodiment may refer to the voltage level of the external power supply voltage VCC at which the second NMOS transistor N2 may be turned on or off.

[0049] In addition, the signal output circuit 220 may be configured to output a power-on reset signal POR based on the output signal of the voltage detection circuit 210. The signal output circuit 220 may include a load circuit 221 and an output circuit 222.

[0050] First, the load circuit 221 may be configured to receive the external power supply voltage VCC and transfer the external power supply voltage VCC to the second node ND2.

[0051] The loading circuit 221 may include a tenth resistor R10 to a thirteenth resistor R13, and the tenth resistor R10 to the thirteenth resistor R13 are connected between a voltage terminal to which an external power supply voltage VCC is applied and a second node ND2. Accordingly, the loading circuit 221 may reduce the external power supply voltage VCC and transmit the reduced external power supply voltage VCC to the second node ND2.

[0052] Next, the output circuit 222 may be configured to output a power-on reset signal POR based on the voltage level of the second node ND2.

[0053] The output circuit 222 may include a first inverter circuit INV1 that receives the output voltage of the second node ND2 and a second inverter circuit INV2 that receives the output signal of the first inverter circuit INV1 and outputs the power-on reset signal POR. As described above, the voltage level of the second node ND2 may be determined based on the output signals of the voltage sensing circuit 212 and the loading circuit 221. Accordingly, the output circuit 222 may output the power-on reset signal POR based on the output signals of the voltage sensing circuit 212 and the loading circuit 221.

[0054] Figure 4 is an illustration Figure 1 of the operation timing of the semiconductor device.

[0055] Referring to Figures 1 to 4 , the voltage level of the external power supply voltage VCC may gradually increase during the power-on period. Since the voltage obtained by reducing the external power supply voltage VCC is transmitted to Figure 3 the second node ND2, the voltage level of the second node ND2 may also increase. Accordingly, the power-on reset signal POR may become logic "high". Thus, Figure 1 the driving circuit 300 of

[0056] the semiconductor device may perform a power-on reset operation based on the power-on reset signal POR. That is, the driving circuit 300 may perform an initialization operation based on the power-on reset signal POR.

[0056] Then, when the voltage level of the external power supply voltage VCC increases to a voltage level "A", at Figure 3The voltage level of the sensed voltage generated at the first node ND1 can also increase according to the external power supply voltage VCC. At this time, since the power-on reset signal POR is logic "high", the third PMOS transistor P3 can be cut off. Therefore, the resistance adjustment circuit 211 can reflect the resistance values of the fifth resistor R5 to the eighth resistor R8 in the external power supply voltage VCC. In other words, the sensed voltage generated at the first node ND1 can have a voltage level that decreases by reflecting the resistance values of the fifth resistor R5 to the eighth resistor R8 in the external power supply voltage VCC. Then, the second NMOS transistor N2 can be turned on according to the sensed voltage generated at the first node ND1. Therefore, the second node ND2 can be driven by the ground power supply voltage VSS. Therefore, the power-on reset signal POR can change from logic "high" to logic "low". For ease of description, the voltage level "A" when the power-on reset signal POR is disabled can be defined as the "first reset reference voltage".

[0057] In addition, during the power-down period, the voltage level of the external power supply voltage VCC can gradually decrease. The power-down period can be in a sudden power-off state, and the enable signal ENB can change from logic "high" to logic "low". Figure 2 The sudden power detection circuit 100 can be enabled based on the enable signal ENB having logic "low". Then, since the divided voltage V_D is a voltage obtained by dividing the external power supply voltage VCC, the voltage level of the divided voltage V_D can also decrease. At this time, since both the enable signal ENB and the power-on reset signal POR are logic "low", Figure 3 both the second PMOS transistor P2 and the third PMOS transistor P3 can be turned on. Therefore, Figure 3 the sensed voltage generated at the first node ND1 can have a voltage level in which the fifth resistor R5 and the sixth resistor R6 are not reflected in the external power supply voltage VCC. Therefore, even if the voltage level of the external power supply voltage VCC is reduced to below the voltage level "A" which is the first reset reference voltage, the second NMOS transistor N2 can basically remain in the on state. That is, the power-on reset signal POR does not change from logic "low" to logic "high".

[0058] In addition, the external power supply voltage VCC can be reduced from the voltage level "A" to the voltage level "B". Figure 2 The sudden power reference voltage V_SPO can have a voltage level corresponding to the voltage level "B". Therefore, when the voltage level of the external power supply voltage VCC is reduced to below the voltage level "B", the sudden power detection signal DTVCC can change from logic "low" to logic "high". Figure 1The driving circuit 300 can perform a sudden power-off operation based on the sudden power detection signal DTVCC. That is, the driving circuit 300 can perform a discharge operation of the node based on the sudden power detection signal DTVCC.

[0059] Then, when Figure 1 the sudden power-off operation performed by the sudden power detection circuit 100 is completed, the enable signal ENB can change from logic "low" to logic "high". In addition, based on the enable signal ENB, the sudden power detection signal DTVCC can change from logic "high" to logic "low". At this time, Figure 3 the second PMOS transistor P2 of can be turned off based on the enable signal ENB. Therefore, the sensed voltage generated at the first node ND1 can have a voltage level that decreases by reflecting the resistance values of the fifth resistor R5 to the eighth resistor R8 to the external power supply voltage VCC. Therefore, the second NMOS transistor N2 can be turned off, and the power-on reset signal POR can change from logic "low" to logic "high". Figure 1 The driving circuit 300 of can perform a power-on reset operation based on the power-on reset signal POR. For ease of description, the voltage level "C" at the time when the power-on reset signal POR is enabled can be defined as the "second reset reference voltage".

[0060] From Figure 4 the timing diagram of, it can be seen that the voltage level "A" as the first reset reference voltage and the voltage level "C" as the second reset reference voltage can be different from each other. That is, the voltage level "A" as the first reset reference voltage can be higher than the voltage level "C" as the second reset reference voltage. In addition, the voltage level "B" corresponding to the sudden power reference voltage V_SPO can have a voltage level between the voltage level "A" as the first reset reference voltage and the voltage level "C" as the second reset reference voltage.

[0061] In addition, from Figure 4 the timing diagram of, it can be seen that during the period when the external power supply voltage VCC increases to the voltage level "A" as the first reset reference voltage and during the period when the external power supply voltage VCC decreases to be lower than the voltage level "C" as the second reset reference voltage, the power-on reset signal POR can be logic "high". In addition, the enable period of the power-on reset signal POR and the enable period of the sudden power detection signal DTVCC may not overlap with each other. In other words, the period of the sudden power-off operation performed based on the sudden power detection signal DTVCC and the period of the power-on reset operation performed based on the power-on reset signal POR may not overlap with each other. That is, the semiconductor device according to the embodiment can basically prevent the power-on reset operation from being performed during the period of the sudden power-off operation. Therefore, the semiconductor device can stably ensure the sudden power-off operation and the power-on reset operation.

[0062] Figure 5 is a block diagram illustrating a partial configuration of a semiconductor device according to an embodiment.

[0063] Before the description, generally, in a semiconductor device, characteristics of transistors provided therein may change according to a process, a voltage, a process, voltage, and temperature (PVT) skew based on the process, voltage, and temperature. Thus, the semiconductor device according to the embodiment may stably control a power-on reset operation by adjusting a reset reference voltage according to the PVT skew.

[0064] Referring to Figure 5 , the semiconductor device may include a skew adjustment circuit 213 configured to adjust a reset reference voltage based on first to third skew control signals C_S, C_T, and C_F that are skew control signals corresponding to the PVT skew. The skew adjustment circuit 213 may be a component added to the Figure 3 configuration. Thus, components corresponding to each other in Figure 3 and Figure 5 may be denoted by substantially the same reference numerals.

[0065] The skew adjustment circuit 213 may be configured to selectively control a resistance path of an external power supply voltage VCC based on the first to third skew control signals C_S, C_T, and C_F. The skew adjustment circuit 213 may include a first path bypass circuit 213_1, a second path bypass circuit 213_2, and a third path bypass circuit 213_3.

[0066] First, the first path bypass circuit 213_1 may be configured to select a resistance path through which the external power supply voltage VCC bypasses a fifth resistor R5 and a sixth resistor R6 based on the first skew control signal C_S. The first path bypass circuit 213_1 may include a fourth NMOS transistor N4 connected between a drain terminal of a third PMOS transistor P3 and a third node ND3. A gate of the fourth NMOS transistor N4 may be connected to the first skew control signal C_S. Thus, the fourth NMOS transistor N4 may be turned on or off based on the first skew control signal C_S. The first skew control signal C_S may be a signal that is enabled when a transistor has a "slow" characteristic according to the PVT skew. Thus, when a transistor has a "slow" characteristic according to the PVT skew, the first path bypass circuit 213_1 may turn on the fourth NMOS transistor N4, thereby forming a resistance path through which the external power supply voltage VCC bypasses the fifth resistor R5 and the sixth resistor R6.

[0067] Next, the second path bypass circuit 213_2 can be configured to select a resistance path through which an external power supply voltage VCC bypasses a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7 based on a second skew control signal C_T. The second path bypass circuit 213_2 can include a fifth NMOS transistor N5 connected between the drain terminal of a third PMOS transistor P3 and a fourth node ND4. The gate of the fifth NMOS transistor N5 can be connected to the second skew control signal C_T. The second skew control signal C_T can be a signal that is enabled when the transistor has "TYPICAL" characteristics according to PVT skew. Therefore, when the transistor has "typical" characteristics, the second path bypass circuit 213_2 can turn on the fifth NMOS transistor N5, thereby forming a resistance path through which the external power supply voltage VCC bypasses the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7.

[0068] Next, the third path bypass circuit 213_3 can be configured to select a resistance path through which an external power supply voltage VCC bypasses a fifth resistor R5 to an eighth resistor R8 based on a third skew control signal C_F. The third path bypass circuit 213_3 can include a sixth NMOS transistor N6 connected between the drain terminal of the third PMOS transistor P3 and a fifth node ND5. The gate of the sixth NMOS transistor N6 can be connected to the third skew control signal C_F, which is enabled when the transistor has "FAST" characteristics according to PVT skew. When the transistor has "fast" characteristics, the third path bypass circuit 213_3 can form a resistance path through which the external power supply voltage VCC bypasses the fifth resistor R5 to the eighth resistor R8.

[0069] As described above, the skew adjustment circuit 213 can be composed of, for example, three NMOS transistors (i.e., a fourth NMOS transistor N4 to a sixth NMOS transistor N6). In addition, considering the voltage drop of the transmitted signal, the skew adjustment circuit 213 can also be composed of three PMOS transistors.

[0070] In short, the skew adjustment circuit 213 can adjust the number of resistors reflected in the external power supply voltage VCC by selecting a resistance path according to PVT skew. The fact of adjusting the number of resistors reflected in the external power supply voltage VCC means that the reset reference voltage can be adjusted. That is, the skew adjustment circuit 213 can adjust the reset reference voltage by adjusting the resistance path according to PVT skew. Therefore, even in the presence of PVT skew, the semiconductor device according to the embodiment can stably generate a power-on reset signal POR.

[0071] Figure 6is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment.

[0072] Referring to Figure 6 , the semiconductor memory device may include a sudden power detection circuit 100A, a power-on reset circuit 200A, and a discharge circuit 300A.

[0073] First, the sudden power detection circuit 100A may be enabled based on an enable signal ENB, and may be configured to detect a voltage level of an external power supply voltage VCC and generate a sudden power detection signal DTVCC. Accordingly, the sudden power detection circuit 100A may generate the sudden power detection signal DTVCC that is enabled when the voltage level of the external power supply voltage VCC drops below a set voltage level.

[0074] Next, the power-on reset circuit 200A may be configured to set a reset reference voltage for a power-on reset operation based on the enable signal ENB. In addition, the power-on reset circuit 200A may be configured to detect the voltage level of the external power supply voltage VCC according to the reset reference voltage and generate a power-on reset signal POR. Accordingly, the power-on reset circuit 200A may detect the voltage level of the external power supply voltage VCC according to the reset reference voltage set based on the enable signal ENB and generate the power-on reset signal POR.

[0075] The sudden power detection circuit 100A and the power-on reset circuit 200A may respectively correspond to Figure 1 the sudden power detection circuit 100 and the power-on reset circuit 200 of Figures 1 to 5 . Since the sudden power detection circuit 100A and the power-on reset circuit 200A have been described with reference to

[0076] Next, the discharge circuit 300A may be configured to perform a discharge operation on at least one of a word line WL, a bit line BL, and a source line SL which are lines connected to memory cells based on the sudden power detection signal DTVCC.

[0077] In the semiconductor memory device according to an embodiment, an enable period of the sudden power detection signal DTVCC for a sudden power-off operation and an enable period of the power-on reset signal POR for a power-on reset operation may not overlap with each other. Accordingly, during the sudden power-off operation, a stable discharge operation on the word line WL, the bit line BL, and the source line SL may be ensured based on the sudden power detection signal DTVCC.

[0078] In addition, the semiconductor memory device according to an embodiment may include a memory cell array circuit 400A, a voltage supply circuit 500A, and a page buffer circuit 600A.

[0079] First, the memory cell array circuit 400A may include a plurality of memory cells (not shown) connected to word lines WL, bit lines BL, and source lines SL and storing data. Next, the voltage supply circuit 500A may be configured to supply corresponding internal power supply voltages to the word lines WL, bit lines BL, and source lines SL according to a programming operation, a read operation, and an erase operation. Next, the page buffer circuit 600A may be configured to transmit data to the memory cell array circuit 400A through the bit lines BL or receive the data stored in the memory cell array circuit 400A.

[0080] The voltage supply circuit 500A may perform an initialization operation based on a power-on reset signal POR. The voltage supply circuit 500A may include a plurality of voltage generation circuits (not shown) for generating internal power supply voltages supplied to the word lines WL, bit lines BL, and source lines SL. Accordingly, the plurality of voltage generation circuits may perform an initialization operation based on the power-on reset signal POR. In addition, the page buffer circuit 600A may perform an initialization operation based on the power-on reset signal POR. The page buffer circuit 600A may include a plurality of latch circuits. Among the plurality of latch circuits, an initial value may be set before performing a programming operation and a read operation. Accordingly, the plurality of latch circuits may perform an initialization operation of setting an initial value based on the power-on reset signal POR.

[0081] The semiconductor memory device according to an embodiment may stably control a sudden power-off operation and a power-on reset operation, thereby substantially preventing malfunction that may occur during the sudden power-off operation and the power-on reset operation.

[0082] The effects of the present disclosure are not limited to the above effects, and according to the above description, other effects not described above may be clearly understood by those of ordinary skill in the art to which the present disclosure pertains.

[0083] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0084] Cross-reference to related applications

[0085] This application claims priority to Korean Patent Application No. 10-2020-0090325, filed on Jul. 21, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A sudden power detection circuit, the sudden power detection circuit being enabled based on an enable signal and configured to detect a voltage level of an external power supply voltage and generate a sudden power detection signal; A power-on reset circuit, the power-on reset circuit being configured to set a reset reference voltage for a power-on reset operation based on the enable signal and a power-on reset signal, detect a voltage level of the external power supply voltage according to the reset reference voltage, and generate the power-on reset signal; And A drive circuit, the drive circuit being configured to perform a sudden power-off operation based on the sudden power detection signal and perform the power-on reset operation based on the power-on reset signal.

2. The semiconductor device according to claim 1, wherein, The sudden power-off operation includes a discharge operation for a node in the drive circuit, and the power-on reset operation includes an initialization operation for the drive circuit.

3. The semiconductor device according to claim 1, wherein, The reset reference voltage includes a first reset reference voltage corresponding to a power-on period of the external power supply voltage and a second reset reference voltage corresponding to a power-off period of the external power supply voltage.

4. The semiconductor device according to claim 3, wherein, The first reset reference voltage and the second reset reference voltage have different voltage levels.

5. The semiconductor device according to claim 3, wherein, The voltage level of the first reset reference voltage is higher than the voltage level of the second reset reference voltage.

6. The semiconductor device according to claim 3, wherein, The sudden power detection circuit includes: A voltage dividing circuit, the voltage dividing circuit being configured to generate a divided voltage by dividing the voltage level of the external power supply voltage based on the enable signal; and A voltage comparison circuit, the voltage comparison circuit being configured to compare the divided voltage with a sudden power reference voltage and generate the sudden power detection signal.

7. The semiconductor device according to claim 6, wherein, The voltage level of the sudden power reference voltage corresponds to a voltage level between the voltage level of the first reset reference voltage and the voltage level of the second reset reference voltage.

8. The semiconductor device according to claim 1, wherein, The power-on reset circuit includes: A voltage detection circuit, the voltage detection circuit being configured to set the reset reference voltage based on the enable signal and the power-on reset signal, and detect the external power supply voltage based on the set reset reference voltage; and A signal output circuit, the signal output circuit being configured to output the power-on reset signal based on an output signal of the voltage detection circuit.

9. The semiconductor device according to claim 8, wherein, The voltage detection circuit includes: A resistance adjustment circuit, the resistance adjustment circuit being configured to adjust a resistance value for a voltage drop of the external power supply voltage based on the enable signal and the power-on reset signal; and A voltage sensing circuit, the voltage sensing circuit being configured to sense the external power supply voltage that drops through the resistance value adjusted by the resistance adjustment circuit based on the reset reference voltage.

10. The semiconductor device according to claim 8, wherein, The signal output circuit includes: A loading circuit, the loading circuit being configured to receive the external power supply voltage; and An output circuit, the output circuit being configured to output the power-on reset signal based on an output signal of the loading circuit and an output signal of the voltage detection circuit.

11. The semiconductor device according to claim 1, wherein, The power-on reset circuit further includes: A skew adjustment circuit, the skew adjustment circuit being configured to further receive a skew control signal corresponding to process, voltage, temperature (PVT) skew, and to adjust the reset reference voltage based on the skew control signal.

12. The semiconductor device according to claim 11, wherein, The skew adjustment circuit selectively controls a resistance path of the external power supply voltage based on the skew control signal.

13. A semiconductor memory device, the semiconductor memory device comprising: A sudden power detection circuit, the sudden power detection circuit being enabled based on an enable signal and being configured to detect a voltage level of an external power supply voltage and generate a sudden power detection signal; A power-on reset circuit, the power-on reset circuit being configured to set a reset reference voltage for a power-on reset operation based on the enable signal and a power-on reset signal, to detect a voltage level of the external power supply voltage according to the reset reference voltage, and to generate the power-on reset signal; And A discharge circuit, the discharge circuit being configured to perform a discharge operation on a line connected to a memory cell based on the sudden power detection signal.

14. The semiconductor memory device according to claim 13, the semiconductor memory device further comprising: A memory cell array circuit, the memory cell array circuit including a plurality of memory cells connected to a word line, a bit line, and a source line and being configured to store data, wherein the discharge circuit performs the discharge operation on at least one of the word line, the bit line, and the source line based on the sudden power detection signal.

15. The semiconductor memory device according to claim 14, the semiconductor memory device further comprising: A voltage supply circuit, the voltage supply circuit being configured to supply an internal power supply voltage to the word line, the bit line, and the source line; And A page buffer circuit, the page buffer circuit being configured to transmit data to and receive data from the memory cell array circuit through the bit line, wherein at least one of the voltage supply circuit and the page buffer circuit is initialized based on the power-on reset signal.

16. The semiconductor memory device according to claim 13, wherein, The reset reference voltage includes a first reset reference voltage corresponding to a power-up period of the external power supply voltage and a second reset reference voltage corresponding to a power-down period of the external power supply voltage.

17. The semiconductor memory device according to claim 16, wherein, The first reset reference voltage and the second reset reference voltage have different voltage levels.

18. The semiconductor memory device according to claim 16, wherein, The voltage level of the first reset reference voltage is higher than the voltage level of the second reset reference voltage.

19. The semiconductor memory device according to claim 13, wherein, The power-on reset circuit includes: A voltage detection circuit, the voltage detection circuit being configured to set the reset reference voltage based on the enable signal and the power-on reset signal, and to detect the external power supply voltage based on the set reset reference voltage; and A signal output circuit, the signal output circuit being configured to output the power-on reset signal based on an output signal of the voltage detection circuit.

20. The semiconductor memory device according to claim 19, wherein, The voltage detection circuit includes: A resistance adjustment circuit, the resistance adjustment circuit being configured to adjust a resistance value for a voltage drop of the external power supply voltage based on the enable signal and the power-on reset signal; and A voltage sensing circuit configured to sense the external power supply voltage that has decreased through a resistance value adjusted by the resistance adjustment circuit based on the reset reference voltage.

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