Control Method of a Storage Device

Abstract

The present invention relates to a control method for a memory device. The control method for the memory device includes: operating the memory device in a partially depleted silicon-on-insulator state; applying a first control voltage to a control gate of the memory device to form a potential well in a floating body region; reducing a potential barrier between a source region and a sub-source region, injecting electrons into the floating body region, such that a potential of the floating body region is reduced, and performing a write "1" operation; increasing the potential barrier between the source region and the sub-source region, such that the potential of the floating body region remains unchanged, and performing a write "0" operation. The control method for the memory device provided by the present invention can, by forming a potential barrier structure between the source region and the sub-source region, realize dual storage sites in the same memory device without changing a vertical structure of the memory device, and increase a storage bit number of the memory device.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly to a control method for a storage device. Background Art

[0002] A storage device is a type of device that can store a large amount of binary information. Since a large amount of data needs to be stored during the operation of a computer and other digital systems, the memory has become an indispensable component of the computer and these other digital systems.

[0003] Since the amount of data that a computer needs to process is increasing, it is required that the storage device has a larger storage capacity. Therefore, the storage capacity is the most important indicator for measuring the performance of the storage device. Summary of the Invention

[0004] Based on this, in view of the technical problems in the above background art, it is necessary to provide a control method for a storage device that can increase the storage bits of the storage device.

[0005] According to some embodiments, a first aspect of the present invention provides a control method for a storage device, where the storage device includes: a gate, a source region, a drain region, a sub-source region, and a floating body region; wherein

[0006] The gate includes a control gate and a floating gate stacked vertically and spaced apart;

[0007] The source region and the drain region are respectively located on opposite sides of the gate;

[0008] The sub-source region is located within the source region;

[0009] The floating body region is located between the source region and the drain region;

[0010] The control method includes the following steps:

[0011] Make the storage device operate in a partially depleted silicon-on-insulator state;

[0012] Apply a first control voltage to the control gate of the storage device to form a potential well in the floating body region;

[0013] Reduce the potential barrier between the source region and the sub-source region, inject electrons into the floating body region, so that the electric potential of the floating body region decreases, and perform a write "1" operation;

[0014] Increase the potential barrier between the source region and the sub-source region, so that the electric potential of the floating body region remains unchanged, and perform a write "0" operation.

[0015] The control method of the storage device provided by the above embodiments enables the storage device to exhibit the floating body effect by operating the storage device in the partially depleted silicon on insulator (PDSOI) state; a potential well is formed in the floating body region to form a barrier structure between the source region and the sub-source region; by forming a barrier structure between the source region and the sub-source region, the control method of the storage device can control the potential of the floating body region through the barrier structure between the source region and the sub-source region to perform the operation of writing "1" or writing "0"; by forming a barrier structure between the source region and the sub-source region, a dual storage site can be realized in the same storage device without changing the vertical structure of the storage device, increasing the storage bits of the storage device.

[0016] In one embodiment, before performing the write "1" operation and the write "0" operation, the following steps are further included:

[0017] Erase the data that has been written.

[0018] The control method of the storage device provided by the above embodiments erases the data that has been written before performing the write "1" or write "0" operation, so that the state of the storage device is "0" before each write operation.

[0019] In one embodiment, the source region is connected to the first write bit line, the sub-source region is connected to the second write bit line, the gate is connected to the word line, and the drain region is connected to the read bit line; the first control voltage is applied to the control gate via the word line.

[0020] The control method of the storage device provided by the above embodiments enables the storage device to write data through the first write bit line and / or the second write bit line by connecting the first write bit line to the source region and the second write bit line to the sub-source region; by forming a barrier structure between the source region and the sub-source region, a dual storage site can be realized in the same storage device without changing the vertical structure of the storage device, increasing the storage bits of the storage device.

[0021] In one embodiment, the method further includes the following steps:

[0022] Reduce the voltage of the first write bit line to form a barrier between the sub-source region and the floating body region and ensure that there is a barrier between the floating body region and the drain region to perform the data holding operation of the storage device.

[0023] In one embodiment, during the process of performing the holding operation, the following steps are further included:

[0024] Periodically refresh the data written to the storage device.

[0025] The control method of the storage device provided by the above embodiment avoids the generation and / or recombination of carriers in the potential well in the floating body region by periodically refreshing the data written to the storage device.

[0026] In one embodiment, the method further includes the following steps:

[0027] Set the control voltage applied to the control gate to zero and read the read current on the read bit line to perform a read operation.

[0028] In one embodiment, during the process of performing the read operation, the read current is a direct current.

[0029] In one embodiment, during the process of performing the read operation, the difference between the read current when reading "1" and the read current when reading "0" is greater than 100 μA / μm.

[0030] The control method of the storage device provided by the above embodiment makes it easier to distinguish between writing "1" data and writing "0" data because the difference between the read current when reading "1" and the read current when reading "0" is greater than 100 μA / μm.

[0031] In one embodiment, the written data is stored in the floating gate and the floating body region.

[0032] In one embodiment, the method further includes the following steps:

[0033] Apply a second control voltage to the control gate to clear the stored charge in the floating body region;

[0034] Wherein, the second control voltage is greater than the first control voltage.

[0035] The control method of the storage device provided by the above embodiment avoids the problems of reduced erase / write times and increased time while increasing the storage bits of the storage device by applying a second control voltage to the control gate to retain the stored charge in the floating gate when clearing the stored charge in the floating body region of the storage device.

[0036] In one embodiment, the method further includes the following steps:

[0037] Apply a third control voltage to the control gate to clear the stored charge in the floating gate and the floating body region;

[0038] Wherein, the third control voltage is greater than the second control voltage. Description of the Drawings

[0039] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0040] Figure 1 Schematic diagram of the structure of a storage device in the control method of a storage device provided in one embodiment of the present application;

[0041] Figure 2 Flow chart of the control method of a storage device provided in one embodiment of the present application;

[0042] Figure 3 Circuit schematic diagram of a storage device in the control method of a storage device provided in one embodiment of the present application.

[0043] Explanation of reference numerals:

[0044] 1. Gate; 101. Control gate; 102. Floating gate; 103. Floating gate dielectric layer; 104. Control gate dielectric layer; 2. Source region; 3. Drain region; 4. Sub-source region; 5. Floating body region; 6. Substrate; 7. Buried oxide layer. Detailed implementation manners

[0045] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant accompanying drawings. Embodiments of the present application are shown in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0047] It can be understood that the terms "first", "second", "third", etc. used in the present application can be used herein to describe various parameters, but these parameters are not limited by these terms. These terms are only used to distinguish one parameter from another. For example, without departing from the scope of the present application, the first control voltage can be called the second control voltage, and similarly, the second control voltage can be called the first control voltage. Both the first control voltage and the second control voltage are control voltages, but they are not the same control voltage.

[0048] It can be understood that in the following embodiments, "connection" should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0049] As used herein, the terms "comprising", "including" or "having", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0050] Currently, storage devices are developing towards the direction of multi-level cells, that is, each storage cell stores more than one storage site, aiming to increase the storage capacity.

[0051] For the partially depleted silicon on insulator (PDSOI) technology, during normal operation, the drain potential is relatively high. When electrons in the inversion channel move from the source to the drain, they are accelerated by the electric field. When they move close to the drain-body junction, since the electric field is the strongest at this time, the electrons gain extra energy and collide with the atoms on the lattice to form electron-hole pairs; the electrons move fast and are accelerated to the drain in a very short time; however, the holes move relatively slowly and move slowly along the direction of the electric field to low-potential regions such as the sub-source region and the source region. The holes that move to the sub-source region are easily recombined with the electrons provided by the source, while when they move to the sub-source region, the holes accumulate slowly in the sub-source region due to the floating potential, which directly affects the threshold voltage of the MOS transistor, thus changing the performance of the MOS transistor. Therefore, when the storage device operates in the PDSOI state, the floating body effect can be exhibited.

[0052] Please refer to Figure 1 and Figure 2 , according to some embodiments, the present invention provides a control method for a storage device. As Figure 1 shown, the storage device may include a gate 1, a source region 2, a drain region 3, a sub-source region 4, and a floating body region 5; wherein the gate 1 includes a control gate 101 and a floating gate 102 stacked with a gap therebetween; the source region 2 and the drain region 3 are respectively located on opposite sides of the gate 1; the sub-source region 4 is located within the source region 2; and the floating body region 5 is located between the source region 2 and the drain region 3.

[0053] Please combine Figure 1 with Figure 2 , the control method of the storage device may include the following steps:

[0054] S1: Operate the memory device in the partially depleted silicon on insulator (PDSOI) state;

[0055] S2: Apply a first control voltage to the control gate 101 of the memory device to form a potential well in the floating body region 5;

[0056] S3: Reduce the potential barrier between the source region 2 and the sub-source region 4, inject electrons into the floating body region 5, so that the electric potential of the floating body region 5 decreases, and perform the write "1" operation; or

[0057] S4: Increase the potential barrier between the source region 2 and the sub-source region 4, so that the electric potential of the floating body region 5 remains unchanged, and perform the write "0" operation.

[0058] The control method of the memory device provided by the above embodiments enables the memory device to exhibit the floating body effect by operating the memory device in the PDSOI state; a potential well is formed in the floating body region, so that a potential barrier structure is formed between the source region and the sub-source region; by forming a potential barrier structure between the source region and the sub-source region, the control method of the memory device can control the electric potential of the floating body region through the potential barrier structure between the source region and the sub-source region, and perform the write "1" or write "0" operation; by forming a potential barrier structure between the source region and the sub-source region, a dual storage site can be realized in the same memory device without changing the vertical structure of the memory device, increasing the storage bits of the memory device.

[0059] It should be noted that "0" and "1" can be used to represent the presence or absence of charge, and "0" and "1" can be distinguished by different channel threshold voltages.

[0060] Specifically, in one example, the memory device can be operated in the PDSOI state by adjusting the forward gate voltage and / or the back gate voltage of the memory device.

[0061] Specifically, in one of the embodiments, the data written to the memory device is stored in the floating gate 102 and the floating body region 5.

[0062] In one example, the floating gate 102 may include, but is not limited to, a polysilicon floating gate, a metal floating gate, or a floating gate structure of other materials, and the present application does not limit the material of the floating gate 102; specifically, in one of the embodiments, the floating gate 102 may include a polysilicon floating gate or a metal floating gate.

[0063] In the control method of the storage device provided in the above embodiments, the storage window performance of the storage device can be improved by using a metal floating gate; or a polysilicon floating gate can be used to increase the storage window while reducing the operating voltage required for the storage device, achieving high-density storage and improving the charge retention characteristics.

[0064] Further, in one example, an insulating layer may be provided between the floating gate 102 and the floating body region 5.

[0065] As described above, the data written to the storage device can be stored in the floating gate 102 and the floating body region 5. In the control method of the storage device provided in the above embodiments, since there is an insulating layer between the floating gate 102 and the floating body region 5, the stored data in the floating gate 102 and the floating body region 5 are prevented from affecting each other, improving the reliability and stability of the operation of the storage device.

[0066] In one of the embodiments, before steps S3 and S4, a step of erasing the data that has been written is further included.

[0067] In the control method of the storage device provided in the above embodiments, by erasing the data that has been written before performing the operation of writing "1" or writing "0", the state of the storage device is "0" every time before performing the write operation.

[0068] In one of the embodiments, the circuit schematic diagram of the storage device is as Figure 3 shown, the source region 2 is connected to the first write bit line WBL1, the sub-source region 4 is connected to the second write bit line WBL2, the gate 1 is connected to the word line WL, and the drain region 3 is connected to the read bit line RBL; a first control voltage is applied to the control gate 101 via the word line WL.

[0069] In the control method of the storage device provided in the above embodiments, by connecting the first write bit line WBL1 to the source region 2 and the second write bit line WBL2 to the sub-source region 4, the storage device can write data through the first write bit line WBL1 and / or the second write bit line WBL2; by forming a barrier structure between the source region and the sub-source region, a dual storage site can be realized in the same storage device without changing the vertical structure of the storage device, increasing the number of storage bits of the storage device.

[0070] Specifically, in the process of performing the write "1" operation, the control method of the storage device may include the following steps:

[0071] Reduce the barrier between the second write bit line WBL2 and the first write bit line WBL1, so that electrons are injected into the floating body region 5 through the second write bit line WBL2, and the potential of the floating body region 5 is reduced, and the write "1" operation is performed.

[0072] Specifically, during the process of performing the write "0" operation, the control method of the storage device may include the following steps:

[0073] Increase the barrier between the second write bit line WBL2 and the first write bit line WBL1, keep the potential of the floating body region 5 unchanged, and perform the write "0" operation.

[0074] Based on the above embodiments, the present invention also provides an embodiment, which relates to the situation of performing a holding operation on the data written in the storage device; in this embodiment, the control method of the storage device may further include the following steps:

[0075] Reduce the voltage of the first write bit line WBL1 to form a barrier between the secondary source region 4 and the floating body region 5, and ensure that there is a barrier between the floating body region 5 and the drain region 3 to perform the holding operation of the data written in the storage device.

[0076] Specifically, during the process of performing the holding operation, the control method of the storage device may include the following steps:

[0077] Reduce the voltage of the first write bit line WBL1 to form a barrier between the second write bit line WBL2 and the floating body region 5; at the same time, since there is also a barrier between the floating body region 5 and the read bit line RBL, the storage charge in the secondary source region 4 can be prevented from diffusing, and the holding operation of the data written in the storage device can be realized.

[0078] In one of the embodiments, during the process of performing the holding operation of the data written in the storage device, the data written in the storage device can also be refreshed regularly.

[0079] The control method of the storage device provided in the above embodiments can avoid the generation and / or recombination of carriers in the potential well in the floating body region 5 by refreshing the data written in the storage device regularly.

[0080] The present invention also provides an embodiment, which relates to the situation of performing a read operation on the data written in the storage device; in this embodiment, the control method of the storage device may further include the following steps:

[0081] Set the control voltage applied on the control gate 101 to zero, and read the read current on the read bit line RBL to perform the read operation.

[0082] Specifically, during the process of performing the read operation, the control method of the storage device may include the following steps:

[0083] Via the word line WL, set the control voltage applied on the control gate 101 to zero, and read the read current on the read bit line RBL, then the data stored in the floating gate 102 and the floating body region 5 can be obtained.

[0084] In one embodiment, when performing a read operation on a memory device after writing data, the read current can be a direct current.

[0085] In one embodiment, when performing a read operation on a memory device after writing data, the difference between the read current when reading "1" and the read current when reading "0" can be greater than 100 μA / μm.

[0086] For the control method of the memory device provided in the above embodiment, since the difference between the read current when reading "1" and the read current when reading "0" is greater than 100 μA / μm, it is easier to distinguish between writing "1" data and writing "0" data.

[0087] During the actual use of the memory device, the user will also clear some or all of the written data in the memory device according to their own usage requirements. Then the following embodiments relate to the situation of performing a clear operation on the written data.

[0088] In one example, the control method of the memory device may further include the following steps:

[0089] Apply a second control voltage to the control gate 101 to clear the stored charge in the floating body region 5; wherein, the second control voltage is greater than the first control voltage.

[0090] For the control method of the memory device provided in the above embodiment, by applying a second control voltage to the control gate 101, when clearing the stored charge in the floating body region 5 of the memory device, the stored charge in the floating gate 102 is retained, avoiding the problems of a decrease in the erase / write cycle count and an increase in time while increasing the storage bit count of the memory device.

[0091] Based on the above embodiment, the control method of the memory device may include the following steps:

[0092] Increase the potential of the word line WL to clear the stored charge in the floating body region 5.

[0093] In another example, the control method of the memory device may further include the following steps:

[0094] Apply a third control voltage to the control gate 101 to clear the stored charge in the floating gate 102 and the floating body region 5; wherein, the third control voltage is greater than the second control voltage.

[0095] Based on the above embodiment, the control method of the memory device may include the following steps:

[0096] Increase the potential of the word line WL to a higher level to clear the stored charge in the floating gate 102 and the floating body region 5.

[0097] The following provides a detailed description of the control method for the storage device provided by a possible implementation manner of the present application in conjunction with Table 1:

[0098] Referring to Table 1, in one embodiment, before each write operation is performed, the state of the storage device needs to be "0"; during the process of the storage device performing the write operation, the control method of the storage device may include the following steps:

[0099] Apply a first control voltage of 5V to the control gate 101 via the word line WL to form a potential well in the floating body region 5;

[0100] Reduce the potential barrier between the second write bit line WBL2 and the first write bit line WBL1, so that electrons are injected into the floating body region 5 through the second write bit line WBL2. At this time, the voltage on the first write bit line WBL1 is 3V, and the voltage on the second write bit line WBL2 changes from the original 3.7V to 3V, and the electric potential of the floating body region 5 decreases, and the write "1" operation is performed;

[0101] Increase the potential barrier between the second write bit line WBL2 and the first write bit line WBL1, and the electric potential of the floating body region 5 remains unchanged, and the write "0" operation is performed.

[0102] In one example, during the process of the memory performing the hold operation, the control method of the storage device may include the following steps:

[0103] Reduce the voltage of the first write bit line WBL1. At this time, the voltage of the first write bit line WBL1 is -1.5V, so as to form a potential barrier between the second write bit line WBL2 and the floating body region 5; at the same time, since there is also a potential barrier between the floating body region 5 and the read bit line RBL, the stored charges in the secondary source region 4 can be prevented from diffusing, and the hold operation of the data written in the storage device is realized.

[0104] In one example, during the process of the memory performing the read operation, the control method of the storage device may include the following steps:

[0105] Set the control voltage applied to the control gate 101 to zero via the word line WL. At this time, the voltage applied to the word line WL is 0V, and the read current on the read bit line RBL is read to obtain the data stored in the floating gate 102 and the floating body region 5.

[0106] In one example, during the process of the memory performing the erase operation, the control method of the storage device may include the following steps:

[0107] Increase the electric potential of the word line WL. At this time, the voltage applied to the word line WL is 0V, so as to erase the stored charges in the floating body region 5.

[0108] The potential of the word line WL is increased to a higher level, and at this time, the voltage applied to the word line WL is -5V to erase the stored charges in the floating gate 102 and the floating body region 5.

[0109] Table 1 Voltage examples when performing write, hold, read, and / or erase operations in the control method of the memory device provided by an example of the present invention

[0110]

[0111] Optionally, in one embodiment, as Figure 1 shown, the memory device may further include a substrate 6, a buried oxide layer 7, and a top semiconductor layer stacked in sequence from bottom to top ( Figure 1 not marked in); the source region 2, the drain region 3, the secondary source region 4, and the floating body region 5 are all located in the top semiconductor layer; the gate 1 is located on the surface of the top semiconductor layer away from the buried oxide layer 7.

[0112] Optionally, in one embodiment, as Figure 1 shown, the gate 1 may further include a floating gate dielectric layer 103 and a control gate dielectric layer 104; specifically, the floating gate dielectric layer 103 is located on the surface of the top semiconductor layer away from the buried oxide layer 7, the floating gate 102 is located on the surface of the floating gate dielectric layer 103 away from the top semiconductor layer, the control gate dielectric layer 104 is located on the surface of the floating gate 102 away from the floating gate dielectric layer 103, and the control gate 101 is located on the surface of the control gate dielectric layer 104 away from the floating gate 102; that is, the gate 1 may include the floating gate dielectric layer 103, the floating gate 102, the control gate dielectric layer 104, and the control gate 101 stacked in sequence from bottom to top.

[0113] It should be understood that although Figure 2 the steps in the flowchart of Figure 2 are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover,

[0114] In the description of this specification, the description referring to terms such as "one embodiment", "an example", "another example", etc. means that the specific features, structures, materials, or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0115] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0116] The above-described embodiments only express several implementation manners of the present invention, and the description thereof is relatively specific and detailed. However, it should not be construed as a limitation to the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A control method for a storage device, characterized in that, The storage device includes: a gate, a source region, a drain region, a secondary source region, and a floating body region; wherein the gate includes a control gate and a floating gate stacked vertically with a gap therebetween; the source region and the drain region are respectively located on opposite sides of the gate; the secondary source region is located within the source region; the floating body region is located between the source region and the drain region; the control method includes the following steps: operating the storage device in a partially depleted silicon-on-insulator state; applying a first control voltage to the control gate of the storage device to form a potential well in the floating body region; reducing the potential barrier between the source region and the secondary source region, injecting electrons into the floating body region, and causing the electric potential of the floating body region to decrease to perform a write "1" operation; increasing the potential barrier between the source region and the secondary source region to keep the electric potential of the floating body region unchanged to perform a write "0" operation.

2. The control method of the storage device according to claim 1, characterized in that Before performing the write "1" operation and the write "0" operation, the following steps are further included: erasing the data that has been written.

3. The control method of the storage device according to claim 1, characterized in that The source region is connected to a first write bit line, the secondary source region is connected to a second write bit line, the gate is connected to a word line, and the drain region is connected to a read bit line; the first control voltage is applied to the control gate via the word line.

4. The control method of the storage device according to claim 3, wherein The method further includes the following steps: reducing the voltage of the first write bit line to form a potential barrier between the secondary source region and the floating body region and ensuring that there is a potential barrier between the floating body region and the drain region to perform the holding operation of writing data to the storage device.

5. The control method of the storage device according to claim 4, characterized in that, During the process of performing the holding operation, the following steps are further included: periodically refreshing the data written to the storage device.

6. The control method of the storage device according to claim 3, characterized in that, The method further includes the following steps: setting the control voltage applied to the control gate to zero and reading the read current on the read bit line to perform a read operation.

7. The control method of the storage device according to claim 6, characterized in that, During the process of performing the read operation, the read current is a direct current.

8. The control method of the storage device according to claim 7, wherein, During the process of performing the read operation, the difference between the read current when reading "1" and the read current when reading "0" is greater than 100 μA / μm.

9. The control method of the storage device according to claim 1, characterized in that, The written data is stored in the floating gate and the floating body region.

10. The control method of the storage device according to claim 9, wherein, The method further includes the following steps: applying a second control voltage to the control gate to clear the stored charge in the floating body region; wherein the second control voltage is greater than the first control voltage.

11. The control method of a storage device according to claim 10, characterized in that, The method further includes the following steps: applying a third control voltage to the control gate to clear the stored charge in the floating gate and the floating body region; wherein the third control voltage is greater than the second control voltage.

Images