Method for manufacturing silicon carbide epitaxial wafer

Abstract

A method for manufacturing a silicon carbide epitaxial wafer suitable for suppressing the generation of triangular defects is provided. The method for manufacturing a silicon carbide epitaxial wafer comprises: an etching process, in which the surface of a silicon carbide substrate is etched at a first temperature using an etching gas containing H2; a flattening process, in which the surface etched in the etching process is flattened at a second temperature using a gas containing H2 gas, a first Si supply gas, and a first C supply gas; and an epitaxial layer growth process, in which epitaxial growth is performed at a third temperature on the surface flattened by the flattening process using a gas containing a second Si supply gas and a second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a silicon carbide epitaxial wafer. Background Art

[0002] Silicon carbide has a larger band gap than silicon and exhibits superior physical properties such as dielectric breakdown field strength, saturation electron velocity, and thermal conductivity, resulting in excellent properties as a material for semiconductor devices. In particular, semiconductor devices using silicon carbide can significantly reduce power loss and miniaturize semiconductor devices, thereby achieving energy savings during power conversion. Consequently, silicon carbide is attracting attention as a semiconductor material for achieving a low-carbon society, such as by enhancing the performance of electric vehicles and the functionality of solar cell systems.

[0003] To manufacture a semiconductor device using silicon carbide, first, a silicon carbide epitaxial growth device is used on a silicon carbide substrate by thermal chemical vapor deposition (CVD).

[0004] The chemical vapor deposition method (CVM) allows epitaxial growth of films with highly precisely controlled impurity concentrations. For example, a silicon carbide epitaxial layer can be made n-type by adding nitrogen to the epitaxial growth gas. A wafer with a silicon carbide epitaxial layer formed on a silicon carbide substrate is called a silicon carbide epitaxial wafer. Silicon carbide epitaxial wafers that have undergone further processing, such as forming device regions or performing various other processes, are called silicon carbide semiconductor devices.

[0005] Patent Document 1 discloses a method for manufacturing a silicon carbide semiconductor device. Patent Document 1 states that the method described in Patent Document 1 can suppress the occurrence of surface defects such as step coalescence in a silicon carbide epitaxial layer.

[0006] Patent Document 1: Japanese Patent No. 6012841

[0007] One of the defects generated in the silicon carbide epitaxial layer is a triangular defect. The method of Patent Document 1 can suppress surface defects, but does not particularly consider suppressing the generation of triangular defects. Summary of the Invention

[0008] The present invention has been made to solve such a problem, and an object of the present invention is to provide a method for manufacturing a silicon carbide epitaxial wafer suitable for suppressing the occurrence of triangular defects.

[0009] The method for manufacturing a silicon carbide epitaxial wafer of the present invention comprises: an etching step of etching the surface of a silicon carbide substrate at a first temperature using an etching gas containing H2; a flattening step of flattening the surface etched in the etching step at a second temperature using a gas containing H2 gas, a first Si supply gas, and a first C supply gas; and

[0010] An epitaxial layer growth process is carried out on the surface flattened by a planarization process by epitaxially growing at a third temperature using a gas containing a second Si supply gas and a second C supply gas, and the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1 > T2 > T3.

[0011] Effects of the Invention

[0012] The method for manufacturing a silicon carbide epitaxial wafer of the present invention has: an etching process of etching the surface of a silicon carbide substrate at a first temperature using an etching gas containing H2; a planarization process of planarizing the surface etched in the etching process at a second temperature using a gas containing H2 gas, a first Si supply gas, and a first C supply gas; and

[0013] An epitaxial layer growth process is carried out on the surface flattened by a planarization process by epitaxially growing at a third temperature using a gas containing a second Si supply gas and a second C supply gas, and the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1 > T2 > T3.

[0014] Thereby, the method for manufacturing a silicon carbide epitaxial wafer of the present invention is a method for manufacturing a silicon carbide epitaxial wafer suitable for suppressing the generation of triangular defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a silicon carbide epitaxial growth apparatus according to an embodiment.

[0016] Figure 2 is a schematic cross-sectional view of a silicon carbide epitaxial wafer.

[0017] Figure 3 is a flowchart of a method for manufacturing a silicon carbide epitaxial wafer according to an embodiment.

[0018] Figure 4 is a graph showing the triangular defect density of silicon carbide epitaxial wafers manufactured by an embodiment and Comparative Example 1, respectively.

[0019] Figure 5 is a graph showing the effect of the planarization process when the planarization time and the planarization temperature are changed. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] <A. Embodiment>

[0021] <A-1. Structure of Silicon Carbide Epitaxial Growth Apparatus>

[0022] First, the structure of a silicon carbide epitaxial growth apparatus 100, which is a silicon carbide epitaxial growth apparatus according to the present embodiment, will be described.

[0023] Figure 1 1 is a schematic cross-sectional view of a growth furnace 10 that is a main component of the silicon carbide epitaxial growth apparatus according to the embodiment. Next, the growth furnace 10 will be described.

[0024] The growth furnace 10 includes a susceptor 5 , a wafer holder 3 , a rotation table 2 , and an induction heating coil 4 .

[0025] Growth gas, carrier gas, etching gas and other gases such as Figure 1 The gas is supplied to or discharged from the susceptor 5 as shown by arrow A. Therefore, the susceptor 5 is always filled with new growth gas, carrier gas, etching gas, etc.

[0026] When forming an epitaxial growth layer on the silicon carbide substrate 1, SiH4 gas containing silicon atoms or C3H8 gas containing carbon atoms is used as a growth gas, and a gas containing H2 is used as a carrier gas. The silicon carbide epitaxial growth apparatus 100 can set the growth temperature to a range of 1450°C or higher and 1700°C or lower, and the growth pressure to a range of 1×10 3 Pa and less than or equal to 5×10 4 Pa range. Nitrogen gas for N-type doping can be supplied simultaneously with the growth gas as needed. Furthermore, organometallic materials containing Al, B, or Be can be supplied for P-type doping. Furthermore, HCl, chlorosilane, and the like can be used to increase the growth rate.

[0027] The wafer holder 3 is disk-shaped. A plurality of wafer grooves 31 are formed on the surface of the wafer holder 3 to accommodate the silicon carbide substrate 1. The plurality of wafer grooves 31 are formed by forming a plurality of countersunk holes in the surface of the wafer holder 3. The wafer holder 3 is placed on the turntable 2 and rotates together with the turntable 2, for example, at a constant speed, when forming an epitaxial growth layer on the silicon carbide substrate 1.

[0028] The induction heating coil 4 is wound around the outer periphery of the susceptor 5. The wafer holder 3, susceptor 5, and turntable 2 are inductively heated by supplying power to the induction heating coil 4. When the wafer holder 3, susceptor 5, and turntable 2 are inductively heated, the entire interior of the susceptor 5 is heated by heat conduction and heat radiation.

[0029] In this embodiment, graphite coated with silicon carbide is used for the wafer holder 3, the turntable 2, and the susceptor 5. This is because, when forming an epitaxial growth layer on the silicon carbide substrate 1, the silicon carbide substrate 1 is heated to, for example, approximately 1450°C or higher, and the substrate must be able to withstand this temperature.

[0030] Here, consider the case where the wafer stage 3, the rotating table 2, and the base 5 are made of only graphite. In this case, during the film formation process of the epitaxial growth layer, graphite may generate dust. If the epitaxial growth layer is formed while dust-like graphite particles are falling on the silicon carbide substrate 1, crystal growth will be abnormal starting from the location where the particles land, and crystal defects will occur in the epitaxial growth layer. Therefore, in order to suppress the dusting of graphite, it is preferable to coat the graphite with silicon carbide.

[0031] The graphite coated with silicon carbide suppresses the dusting of graphite through the silicon carbide film. In addition, the diffusion of metal impurities from the graphite is also suppressed. Metal impurities not only cause crystal defects in the epitaxial growth layer but also affect the electrical characteristics of semiconductor devices. Therefore, it is preferable that metal impurities do not diffuse. Therefore, for the wafer stage 3, the rotating table 2, and the base 5, it is preferable to use graphite coated with silicon carbide. For the coating formed of silicon carbide, a silicon carbide material produced by the CVD method or the sintering method can also be used. The coating of graphite can also be performed using TaC (tantalum carbide) instead of silicon carbide. In addition, a carbon coating formed by CVD can also be applied to the graphite.

[0032] <A-2. Structure of Silicon Carbide Epitaxial Wafer>

[0033] Figure 2 It is a schematic cross-sectional view of the silicon carbide epitaxial wafer 20 manufactured by the manufacturing method of the silicon carbide epitaxial wafer according to the present embodiment.

[0034] The silicon carbide epitaxial wafer 20 manufactured in the present embodiment has a silicon carbide substrate 1 and a silicon carbide epitaxial layer 12 formed on the silicon carbide substrate 1.

[0035] The silicon carbide substrate 1 is an N-type low-resistance silicon carbide substrate. The silicon carbide epitaxial layer 12 has the same conductivity type as the silicon carbide substrate 1, specifically, N-type. The silicon carbide substrate 1 is a silicon carbide substrate 1 having a tilt angle inclined at an angle of less than about 5 degrees from the (0001) plane toward the <11-20> direction.

[0036] The preferred structure of the silicon carbide epitaxial wafer 20 will be described.

[0037] A silicon carbide semiconductor device manufactured by subjecting a silicon carbide epitaxial wafer 20 to various processes is referred to as a silicon carbide semiconductor device 21. If defects in the silicon carbide epitaxial wafer 20 are caused by defects during the growth of the silicon carbide substrate 1 and the silicon carbide epitaxial layer 12, localized areas where high voltage cannot be maintained may appear in the silicon carbide semiconductor device 21, causing leakage current to occur. If leakage current occurs in the silicon carbide semiconductor device 21, the silicon carbide semiconductor device 21 is likely to be defective. Therefore, if the density of such areas where high voltage cannot be maintained increases, the yield rate during the manufacture of the silicon carbide semiconductor device 21 decreases. Typical examples of defects that reduce the yield rate are defects caused by a lack of crystallographic uniformity in the silicon carbide epitaxial wafer 20, for example, defects caused by localized imperfections in the periodicity of the atomic arrangement in the crystal along the crystal growth direction. Carrot defects and triangle defects, which occur during silicon carbide epitaxial growth, are known as examples of such defects that cause leakage current in conjunction with stacking faults.

[0038] Even when the ratio of Si to C is 1:1, the stoichiometric composition is the same, and the lattice is a hexagonal close-packed structure, there are different crystal types (polytypes) with different periodicity of atomic arrangement along the c-axis, and the physical properties are determined by this periodicity. Currently, the most attractive type from the perspective of device applications is the type called 4H type. In order to epitaxially grow the same crystal type, the surface of the silicon carbide substrate is usually set to a surface tilted relative to a certain plane orientation of the crystal, for example, it is processed to have a surface tilted 8° or 4° from the (0001) plane to the <11-20> direction.

[0039] The silicon carbide substrate 1 is processed into a wafer shape by slicing, grinding and polishing based on a silicon carbide ingot, and then the surface damage layer of the silicon carbide substrate 1 is removed through multi-stage mechanical polishing, chemical mechanical polishing (CMP), H2 etching, etc.

[0040] If a processing damage layer remains on the surface of the silicon carbide substrate 1, surface defects, primarily triangular defects, often occur when the silicon carbide epitaxial layer is formed. Furthermore, because step flow growth is hindered, step coalescence is likely to occur, increasing surface roughness. Furthermore, even if the surface of the silicon carbide substrate 1 is flat at the nanometer level, processing damage, known as latent damage, may exist near the surface of the silicon carbide substrate 1. These latent damages are generally not accompanied by surface irregularities, or if they exist, they are so small that they cannot be identified using an optical microscope. However, the presence of these latent damages near the surface of the silicon carbide substrate 1 can serve as a starting point for the generation of surface defects, primarily triangular defects, and step coalescence during epitaxial growth.

[0041] In addition, in the manufacturing process of a silicon carbide ingot, if the crystal growth conditions deviate from the desired conditions, particles called inclusions enter the interior of the ingot. If inclusions are present on the surface of the silicon carbide substrate 1, surface defects mainly in the form of triangular defects are generated starting from them during epitaxial growth, thus resulting in a decrease in the device yield.

[0042] Thus, since potential damage and inclusions can cause triangular defects, in the method for manufacturing a silicon carbide epitaxial wafer according to the present embodiment, as will be described later, the potential damage and inclusions are removed by H2 etching. It is preferably completely removed. If the silicon carbide substrate 1 containing potential damage and inclusions is etched with H2 gas or the like, the potential damage and inclusions that cause disorder in the crystal structure are easily etched, thus forming depressions, and these depressions can be confirmed by an optical microscope. If the subsequent <A-3-3. Epitaxial layer growth process> is directly performed on the surface having such depressions, triangular defects starting from the depressions are generated. In the method for manufacturing a silicon carbide epitaxial wafer according to the present embodiment, in order to reduce the triangular defects starting from the depressions, after performing the planarization process described in the <A-3-2. Planarization process> described later, the epitaxial layer growth process described in the <A-3-3. Epitaxial layer growth process> is performed to form the silicon carbide epitaxial layer 12.

[0043] <A-3. Method for manufacturing a silicon carbide epitaxial wafer>

[0044] The method for manufacturing a silicon carbide epitaxial wafer according to the present embodiment will be described.

[0045] In the method for manufacturing a silicon carbide epitaxial wafer according to the present embodiment, a silicon carbide epitaxial growth apparatus 100 is used. Figure 3 It is a flowchart of the method for manufacturing a silicon carbide epitaxial wafer according to the present embodiment.

[0046] First, a silicon carbide substrate 1 is prepared, and the silicon carbide substrate 1 is placed in the wafer slot 31 of the wafer carrier 3 outside the base 5. Then, the wafer carrier 3 on which the silicon carbide substrate 1 is placed is placed on the rotating table 2 provided inside the base 5 (silicon carbide substrate loading process, step S1).

[0047] After step S1, an H2 gas etching process (step S2), a planarization process (step S3), and an epitaxial layer growth process (step S4) are sequentially performed. Then, in the epitaxial layer growth process of step S4, the silicon carbide epitaxial wafer 20 having the silicon carbide epitaxial layer 12 formed on the silicon carbide substrate 1 is taken out from the base 5 (silicon carbide epitaxial wafer unloading process, step S5).

[0048] Next, the H2 gas etching process (step S2), the planarization process (step S3), and the epitaxial layer growth process (step S4) will be described in detail separately.

[0049] <A-3-1. H2 Gas Etching Process>

[0050] In the H2 gas etching process of step S2, after step S1, the pressure inside the susceptor 5 is reduced to a desired pressure, and then the silicon carbide substrate 1 is heated. The heating is performed by supplying power to the induction heating coil 4 wound around the outer periphery of the susceptor 5. By supplying power to the induction heating coil 4, the susceptor 5, the rotating table 2, and the wafer holder 3 are inductively heated. Moreover, the silicon carbide substrate 1 is heated by the radiant heat from the inner wall of the susceptor 5 etc. (also including the side part of the rotating table 2 in the case where the rotating table 2 has a U-shaped shape) and the conduction heat from the wafer holder 3. When the silicon carbide substrate 1 reaches the target temperature, H2 gas is supplied into the susceptor 5 to perform H2 gas etching.

[0051] In the H2 gas etching, a gas containing H2 gas, preferably only H2 gas is allowed to flow through the growth furnace 10. For example, the pressure of the growth furnace 10 is adjusted to be greater than or equal to 5×10 3 Pa and less than or equal to 5×10 4 Pa, and the temperature of the silicon carbide substrate 1 is set to be greater than or equal to 1650°C and less than or equal to 1750°C. In the present embodiment, H2 gas etching was performed at 9×10 3 Pa and 1670°C.

[0052] In order to reduce surface defects such as triangular defects generated during epitaxial growth, it is preferable to completely remove latent damage and inclusions. By setting the etching temperature to be greater than or equal to 1650°C, the etching rate increases, the time required to remove latent damage and inclusions becomes shorter, and from the viewpoint of productivity, it is more preferable to set the etching temperature to be greater than or equal to 1650°C. In addition, when the etching temperature is less than or equal to 1750°C, the etching of the silicon carbide product attached to the furnace wall of the growth furnace 10 is promoted, and the frequency of silicon carbide particles falling onto the silicon carbide substrate 1 is low.

[0053] The latent damage and inclusions existing on the surface of the silicon carbide substrate 1 become brittle due to the disorder of the crystal structure, and thus are easily etched by the heated H2 gas. At the positions on the surface of the silicon carbide substrate 1 where latent damage and inclusions originally existed, depressions remain after etching. The depth of the depressions is, for example, greater than or equal to 0.05μm and less than or equal to about 0.5μm, but is affected by the size of the latent damage and inclusions or the etching conditions.

[0054] The etching treatment time was 9×10 3Under conditions such as Pa and 1670 °C, for example, it is greater than or equal to 5 minutes and less than or equal to 30 minutes. When the etching time is longer than 5 minutes, large potential damages and inclusions can be removed better. In addition, since the etching time is not too long, over-etching can be prevented and productivity can be improved.

[0055] Preferred H2 gas etching conditions. In particular, the preferred etching treatment time and pressure vary depending on the crystal state, surface unevenness state, etc. of the silicon carbide substrate 1. If the potential damages and inclusions can be reduced to the target quantity, the H2 gas etching conditions are not limited to the range described in this embodiment.

[0056] <A-3-2. Planarization treatment process>

[0057] As described above, through the H2 gas etching process described in <A-3-1. H2 gas etching>, the potential damages and inclusions existing in the silicon carbide substrate 1 can be removed, and ideally, they can be completely removed. However, since the potential damages and inclusions are more easily etched compared to other regions, local depressions remain on the surface at the parts originally having potential damages and inclusions. If a silicon carbide epitaxial layer is formed on the surface having depressions after etching through the H2 gas etching process, and the depressions are not filled by epitaxial growth but remain, abnormal growth is caused starting from the depressions and it changes to triangular defects. By performing the epitaxial layer growth process of step S4 after the process of planarizing the depressions by the planarization treatment process of step S3, the generation of triangular defects can be suppressed. The planarization treatment process of step S3 has the same treatment conditions as the epitaxial layer growth process of step S4 in this embodiment except for the treatment temperature and treatment time. It not only planarizes the depressions but also causes epitaxial growth, and the silicon carbide epitaxial layer 12 is regarded as including the region formed in the planarization treatment process of step S3. However, as described below, since it is performed with the aim of planarizing the depressions compared to the epitaxial layer growth process of step S4, it is called planarization treatment. [[ID=ll]]

[0058] The planarization treatment of step S3 is performed under the following conditions: The carrier gas, i.e., H2 gas, the Si supply gas, i.e., SiH4 gas, the C supply gas, i.e., C3H8 gas, and the N2 gas for supplying nitrogen atoms as a dopant are supplied into the growth furnace 10, and the pressure of the growth furnace 10 is adjusted to be greater than or equal to 1×10 3 Pa and less than or equal to 5×10 4 Pa, and the silicon carbide substrate 1 is heated at a temperature greater than or equal to 1550 °C and less than or equal to 1680 °C. The preferred treatment time is, for example, greater than or equal to 5 minutes and less than or equal to 50 minutes. In this embodiment, at 1×10 4Pa was subjected to planarization treatment for 30 minutes under the treatment conditions of 1600 °C.

[0059] Since the treatment temperature of the planarization treatment in step S3 is lower than the treatment temperature of the H2 gas etching process in step S2, the effect of etching the recess by H2 gas is suppressed.

[0060] If the treatment temperature of the planarization treatment is increased, the energy imparted to the atoms of the material gas reaching the silicon carbide substrate becomes larger, and the migration of the atoms of the decomposed material gas, that is, the movement of the decomposed material gas on the surface of the silicon carbide substrate 1 becomes active. Due to the active migration, the atoms of the material gas also reach the recessed part of the surface of the silicon carbide substrate 1, and the planarization effect of the recess becomes higher. Therefore, the planarization treatment can be performed in a shorter time and the productivity becomes higher. Therefore, the treatment temperature of the planarization treatment in step S3 is made higher than the growth treatment temperature of the epitaxial layer growth process in step S4, and more preferably, it is set to be greater than or equal to 1550 °C.

[0061] If the temperature is increased, the migration becomes active. On the other hand, the etching by the carrier gas, that is, H2 gas, also becomes active. Therefore, if the temperature is too high, the effect of making the recess more easily planarized by increasing the temperature of the planarization treatment will be lost. Therefore, it is preferable to set the treatment temperature of the planarization treatment in step S3 to be less than or equal to 1680 °C.

[0062] By performing the epitaxial layer growth process of step S4 after the planarization treatment process of step S3, compared with the case where the epitaxial layer growth process is performed without planarization treatment, the triangular defects starting from the recess can be suppressed (refer to <B. Comparative Example 1> and <E. Evaluation Results>).

[0063] The preferred planarization treatment conditions in the planarization treatment process of step S3 described in this embodiment may vary depending on the conditions of H2 gas etching, or the crystal state, surface unevenness state, etc. of the silicon carbide substrate 1. In addition, the planarization treatment conditions are not limited to the range described in this embodiment.

[0064] <A-3-3. Epitaxial Layer Growth Process>

[0065] Next, the epitaxial layer growth process of step S4 is performed under the same gas conditions as the planarization treatment process of step S3 except for the treatment temperature and treatment time. That is, on the surface planarized by the planarization treatment process of step S3, epitaxial growth is performed using the same type of gas as in the planarization treatment process of step S3 under the same pressure to form the silicon carbide epitaxial layer 12.

[0066] The processing temperature of the epitaxial layer growth process in step S4 is lower than the processing temperature of the planarization process in step S3 aimed at planarizing the recesses.

[0067] Preferably, the processing temperature of the epitaxial layer growth process in step S4 is greater than or equal to 1450°C and less than or equal to 1600°C.

[0068] By lowering the processing temperature of the epitaxial layer growth process in step S4, the epitaxial layer growth process will not be too rapid. Therefore, defects, unevenness, etc., which remain after the flattening of the depressions in the silicon carbide substrate 1, are less likely to remain on the surface of the silicon carbide epitaxial layer 12. Furthermore, the generation of triangular defects caused by defects, unevenness, and unevenness remaining after flattening can be easily suppressed. Therefore, the processing temperature of the epitaxial layer growth process in step S4 is lower than the processing temperature of the flattening process in step S3, and is more preferably set to be less than or equal to 1600°C. Unevenness remaining after flattening refers to, for example, step coalescence, and is different from depressions formed at traces of potential damage or inclusions during the H2 gas etching process, which are formed by expansion.

[0069] To improve the thermal decomposition efficiency of the material gas and to improve the epitaxial growth rate and the in-plane carrier concentration variation of the silicon carbide epitaxial layer 12, it is preferable to increase the temperature. Therefore, the processing temperature of the epitaxial layer growth process in step S4 is preferably set to 1450°C or higher.

[0070] In this embodiment, the epitaxial layer growth process of step S4 is performed at 1500° C. for 3 hours.

[0071] In this embodiment, the primary focus is on maintaining continuity by using the same gas conditions as those used for the planarization process, excluding the process temperature, as the epitaxial layer growth conditions in step S4. This minimizes fluctuations in the gas flow within the growth reactor 10 and minimizes the effects of dusting. However, the epitaxial layer growth conditions in step S4 are not limited to the ranges exemplified in this embodiment. Triangular defects can be suppressed by ensuring that the process temperature T2 of the planarization process in step S3 and the process temperature T3 of the epitaxial layer growth process in step S4 are greater than T3.

[0072] As described above, the method for manufacturing a silicon carbide epitaxial wafer according to this embodiment includes: an H2 etching step (step S2) in which the surface of the silicon carbide substrate is etched using an etching gas containing H2; a planarization step (step S3) in which the surface etched in the etching step (step S2) is planarized using a gas containing H2 gas, SiH4 gas (Si supply gas), and C3H8 gas (C supply gas); and an epitaxial layer growth step (step S4) in which epitaxial growth is performed on the surface planarized in the planarization step (step S3) using a gas containing SiH4 gas (Si supply gas) and C3H8 gas (C supply gas). Furthermore, the processing temperature T1 of the H2 etching step (step S2), the processing temperature T2 of the planarization step (step S3), and the processing temperature T3 of the epitaxial layer growth step (step S4) satisfy the following relationship: T1>T2>T3. By setting T1 > T2, potential damage and inclusions can be efficiently removed in the H2 etching process of step S2, thereby suppressing triangular defects caused by potential damage and inclusions. Furthermore, by flattening the depressions in the planarization process of step S3, triangular defects caused by depressions can be suppressed. Furthermore, by setting T2 > T3, triangular defects caused by depressions and defects and unevenness remaining after planarization can be suppressed. Thus, the method for manufacturing a silicon carbide epitaxial wafer of this embodiment is suitable for suppressing the occurrence of triangular defects.

[0073] The degree to which the concavities are flattened in the planarization process of step S3 depends on the degree of atomic migration of the material gas, which in turn depends on temperature. In this embodiment, the Si supply gas (first Si supply gas) and C supply gas (first C supply gas) used in the planarization process of step S3, and the Si supply gas (second Si supply gas) and C supply gas (second C supply gas) used in the epitaxial layer growth process of step S4 are the same Si supply gas and C supply gas, respectively. However, different Si supply gases and C supply gases may also be used. In this case, by setting T2 > T3, the degree of migration can be controlled, thereby suppressing triangular defects caused by concavities, defects remaining after planarization, triangular defects caused by unevenness, and step coalescence. By setting the first Si supply gas and the second Si supply gas to be the same Si supply gas, and setting the first C supply gas and the second C supply gas to be the same C supply gas, it is possible to suppress airflow fluctuations within the growth furnace 10 during the transition from the planarization process of step S3 to the epitaxial layer growth process of step S4, thereby suppressing dusting within the growth furnace 10.

[0074] The Si supply gas can be any one of SiH2Cl2, SiHCl3, and SiCl4, for example. In addition to C3H8, hydrocarbon gases such as C2H2 can also be used as the C supply gas, for example.

[0075] <A - 4. Effect>

[0076] The processing temperature T1 of the H2 etching process in step S2, the processing temperature T2 of the planarization process in step S3, and the processing temperature T3 of the epitaxial layer growth process in step S4 satisfy T1 > T2 > T3. Thus, the method for manufacturing a silicon carbide epitaxial wafer according to the present embodiment is a method for manufacturing a silicon carbide epitaxial wafer suitable for suppressing the generation of triangular defects.

[0077] The first Si supply gas and the second Si supply gas are the same Si supply gas, and the first C supply gas and the second C supply gas are the same C supply gas. Thus, it is possible to suppress the change in the gas flow in the growth furnace 10 when transitioning from the planarization process in step S3 to the epitaxial layer growth process in step S4, and to suppress the dust formation in the growth furnace 10.

[0078] In the method for manufacturing a silicon carbide epitaxial wafer according to the present embodiment, the processing temperature T1 of the H2 etching process in step S2 is greater than or equal to 1650 °C and less than or equal to 1750 °C, the processing temperature T2 of the planarization process in step S3 is greater than or equal to 1550 °C and less than or equal to 1680 °C, and the processing temperature T3 of the epitaxial layer growth process in step S4 is greater than or equal to 1450 °C and less than or equal to 1600 °C. With these conditions, it is possible to more efficiently manufacture a silicon carbide epitaxial wafer with suppressed triangular defects.

[0079] <A - 5. Variation>

[0080] After forming the silicon carbide epitaxial layer 12 by the processing up to the epitaxial layer growth process in step S4, the processing temperature can be increased to perform other epitaxial growth, and another epitaxial layer (assumed to be the silicon carbide epitaxial layer 13) can be formed on the surface of the silicon carbide epitaxial layer 12. That is, a silicon carbide epitaxial wafer having a plurality of epitaxial layers formed on the silicon carbide substrate 1 can also be formed by forming the silicon carbide epitaxial layer 13 or by further performing other epitaxial growth on the silicon carbide epitaxial layer 13.

[0081] In the epitaxial layer growth process of step S4, by performing epitaxial layer growth at a temperature lower than the temperature that is preferable from the perspective of the growth rate, it is difficult for defects, unevenness, etc. remaining after planarization in the planarization process of step S3 to remain due to epitaxial growth. However, since the epitaxial layer growth process of step S4 is not ideal from the perspective of the growth rate of the epitaxial layer, from the perspective of productivity, it is preferable to increase the processing temperature after the epitaxial layer growth process of step S4 to increase the growth rate.

[0082] That is, the depression is planarized in the planarization process of step S3, the defects, unevenness, etc. remaining after the depression is planarized are reduced in the epitaxial layer growth process of step S4, and then epitaxial growth different from the epitaxial layer growth process of step S4 is performed at a high growth rate. Thus, it is possible to efficiently manufacture a silicon carbide epitaxial wafer with reduced triangular defects, unevenness, etc.

[0083] <B. Comparative Example 1>

[0084] In Comparative Example 1, the planarization process of step S3 in the process of the flowchart described in <A-3. Method for Manufacturing Silicon Carbide Epitaxial Wafer> of the embodiment is not performed, and steps S1, S2, S4, and S5 are sequentially performed to manufacture a silicon carbide epitaxial wafer. The processing conditions of the H2 gas etching process of step S2 and the epitaxial layer growth process of step S4 in this comparative example are the same as the processing conditions in the embodiment. Figure 3

[0085] <C. Comparative Example 2>

[0086] In Comparative Example 2, the processing temperature of the H2 gas etching process of step S2 is changed to 1600°C, which is the same as the temperature of the planarization process of step S3, and the process of the flowchart described in <A-3. Method for Manufacturing Silicon Carbide Epitaxial Wafer> of the embodiment is performed to manufacture a silicon carbide epitaxial wafer. Other conditions such as gas flow rate and pressure in the processing conditions of the H2 gas etching process of step S2 except for the processing temperature are the same as those of the H2 gas etching process of step S2 in the embodiment. The processing conditions of the planarization process of step S3 and the epitaxial layer growth process of step S4 in this comparative example are the same as the processing conditions in the embodiment. Figure 3

[0087] <D. Comparative Example 3>

[0088] In Comparative Example 3, the processing temperature of the epitaxial layer growth process of step S4 is changed to 1600°C, which is the same as the processing temperature of the planarization process of step S3, and the process of the flowchart described in <A-3. Method for Manufacturing Silicon Carbide Epitaxial Wafer> of the embodiment is performed. Figure 3 ​The processing of the flowchart was carried out to fabricate a silicon carbide epitaxial wafer. Other conditions such as gas flow rate and pressure other than the processing temperature in the conditions of the epitaxial layer growth process in step S4 are the same as those in the embodiment. The processing conditions of the H2 gas etching process in step S2 and the planarization process in step S3 in this comparative example are the same as the processing conditions in the embodiment respectively.

[0089] <E. Evaluation Results>

[0090] The silicon carbide epitaxial wafers fabricated through the embodiment and Comparative Examples 1 to 3 were taken out from the growth furnace 10, and the number of triangular defects on the surface of the epitaxial growth layer of the silicon carbide epitaxial wafer (the main surface on the opposite side of the epitaxial growth layer from the silicon carbide substrate 1) was evaluated using an optical surface defect evaluation device.

[0091] Figure 4 is a graph comparing the number of triangular defects on the surface of the epitaxial growth layer between the embodiment and Comparative Example 1. For each of the embodiment and Comparative Example 1, multiple silicon carbide epitaxial wafers were fabricated, and Figure 4 the results of each of these multiple silicon carbide epitaxial wafers were plotted as points. Additionally, in Figure 4 the average value of the number of triangular defects on the surface of the epitaxial growth layer of the multiple silicon carbide epitaxial wafers fabricated through the embodiment and the average value of the number of triangular defects on the surface of the epitaxial growth layer of the multiple silicon carbide epitaxial wafers fabricated through Comparative Example 1 are respectively shown by horizontal lines. The vertical axis is scaled such that the average value of the number of triangular defects on the surface of the epitaxial growth layer of the multiple silicon carbide epitaxial wafers fabricated through the embodiment is set to 1.

[0092] As Figure 4 shown, in the embodiment, through the planarization process, the number of triangular defects is clearly reduced compared to Comparative Example 1. In the embodiment, a silicon carbide epitaxial wafer with a low defect density where the triangular defect density is less than or equal to 0.1 per cm 2 was obtained.

[0093] Furthermore, compared with Comparative Examples 2 and 3, the embodiment has fewer triangular defects.

[0094] In Comparative Example 2, the processing temperature of the H2 gas etching in step S2 is the same as the processing temperature of the planarization process in step S3, which is 1600 °C. In contrast, in the embodiment, the processing temperature of the H2 gas etching in step S2 is higher than 1600 °C of the planarization process in step S3. Therefore, it is considered that in the embodiment, compared with Comparative Example 2, potential damage and inclusions existing on the surface of the silicon carbide substrate 1 can be removed more efficiently, and the triangular defects caused by the potential damage and inclusions are reduced.

[0095] In Comparative Example 3, the processing temperature of the epitaxial layer growth process in Step S4 is the same as the processing temperature of the planarization process in Step S3. In contrast, in the embodiment, the processing temperature of the epitaxial layer growth process in Step S4 is lower than the processing temperature of the planarization process in Step S3. Therefore, it is considered that in the embodiment, compared with Comparative Example 3, it is more difficult for other defects and irregularities remaining after planarizing the recess by the planarization process in Step S3 to remain due to epitaxial growth, and the triangular defects caused by these other defects and irregularities are reduced. That is, by making the processing temperature T2 of the planarization process in Step S3 and the processing temperature T3 of the epitaxial layer growth process in Step S4 satisfy T2 > T3, triangular defects caused by the recess can be efficiently reduced, and also triangular defects caused by reasons other than the recess can be reduced.

[0096] Figure 5 It is a graph showing the tendency of the reduction effect of triangular defects in the planarization process when the planarization processing time and the planarization processing temperature are changed. The reduction effect of triangular defects indicates the degree of reduction of triangular defects when the planarization process is performed compared to when it is not performed. Among them, in both the case where the planarization process is performed and the case where it is not performed, the H2 etching process and the epitaxial layer growth process are performed under the same conditions, and T1 > T2 > T3.

[0097] Figure 5 It shows that the higher the temperature T2 of the planarization process, the shorter the processing time of the planarization process can be. On the contrary, when the temperature of the planarization process is low, the processing time of the planarization process needs to be extended. The reason is considered to be that the migration of atoms of the material gas is more active at higher temperatures. According to the experimental results, a higher reduction effect of triangular defects is obtained when the processing temperature T2 [°C] and the processing time t [minutes] of the planarization satisfy T2 ≥ -34.1 ln(t) + 1687. For a temperature T2 outside the range where the preferred planarization processing temperature in <A-3-2. Planarization process> is greater than or equal to 1550 °C and less than or equal to 1680 °C, there is also a processing time t that satisfies T2 ≥ -34.1 ln(t) + 1687. However, as described in <A-3-2. Planarization process>, it is more preferable that T2 is greater than or equal to 1550 °C and less than or equal to 1680 °C.

[0098] In addition, the respective embodiments can be freely combined, and each embodiment can be appropriately deformed or omitted.

[0099] Description of reference numerals

[0100] 1 silicon carbide substrate, 2 rotation stage, 3 wafer holder, 4 induction heating coil, 5 susceptor, 10 growth furnace, 12 silicon carbide epitaxial layer, 20 silicon carbide epitaxial wafer, 21 silicon carbide semiconductor device, 31 wafer tank, 100 silicon carbide epitaxial growth device.

Claims

1. A method for manufacturing a silicon carbide epitaxial wafer, comprising: an etching step of etching the surface of the silicon carbide substrate at a first temperature using an etching gas containing H2; a planarization treatment step of planarizing the surface etched in the etching step at a second temperature using a gas including H2 gas, a first Si supply gas, and a first C supply gas; and an epitaxial layer growth step of performing epitaxial growth at a third temperature on the surface flattened by the flattening step using a gas including a second Si supply gas and a second C supply gas, The first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.

2. The method for manufacturing a silicon carbide epitaxial wafer according to claim 1, wherein: The first Si supply gas and the second Si supply gas are the same Si supply gas, The first C supply gas and the second C supply gas are the same C supply gas.

3. The method for manufacturing a silicon carbide epitaxial wafer according to claim 1 or 2, wherein: The first Si supply gas is SiH4 gas, The first C supply gas is C3H8 gas.

4. The method for manufacturing a silicon carbide epitaxial wafer according to any one of claims 1 to 3, wherein: The first temperature is greater than or equal to 1650°C and less than or equal to 1750°C, the second temperature is greater than or equal to 1550°C and less than or equal to 1680°C, and the third temperature is greater than or equal to 1450°C and less than or equal to 1600°C.

5. The method for manufacturing a silicon carbide epitaxial wafer according to any one of claims 1 to 4, wherein: The second temperature T2 and the processing time t of the planarization process satisfy T2≥-34.1ln(t)+1687.

6. The method for manufacturing a silicon carbide epitaxial wafer according to any one of claims 1 to 5, wherein: The density of triangular defects is less than or equal to 0.1 / cm 2 Silicon carbide epitaxial wafers are manufactured.

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