Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The method comprises: providing a wafer having a metal layer formed thereon; forming a first intermetallic dielectric layer on the wafer; heating the first intermetallic dielectric layer; oxidizing the first intermetallic dielectric layer; and forming a second intermetallic dielectric layer on the first intermetallic dielectric layer. According to the method for manufacturing the semiconductor device of the present invention, by heating and oxidizing the first intermetallic dielectric layer, a dense oxide layer is formed at the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer, thereby preventing water vapor corrosion and the diffusion and precipitation of free F ions, thereby avoiding the formation of bubble-like defects at the wafer edge and improving the wafer yield.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] As the feature size of integrated circuits decreases, the critical dimension (CD) between metal interconnects also decreases. In the 0.11um-0.18um inter-metal dielectric (IMD) process, high-density plasma chemical vapor deposition (HDPCVD) is used to form the insulating medium. To reduce the dielectric constant between metal interconnects and increase the transmission rate of the circuit, fluorine-doped silicate glass (FSG) is used as the intermetallic dielectric.

[0003] Typically, the F content of fluorine-doped silicate glass (FSG) is around 4%. F ions exist in two primary states within the glass: bound to Si dangling bonds to form Si-F bonds, and as free F ions. The state of F in FSG is primarily affected by the reaction temperature. Excessively low reaction temperatures can lead to an excess of free F ions in the glass. Because FSG is relatively loose and easily absorbs water vapor, these free F ions precipitate, manifesting as bubble-like defects on the wafer.

[0004] Therefore, it is necessary to propose a new method for manufacturing a semiconductor device to solve the above problems. Summary of the Invention

[0005] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention is not intended to limit the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] providing a wafer having a metal layer formed thereon;

[0008] forming a first intermetallic dielectric layer on the wafer;

[0009] performing a heat treatment on the first intermetallic dielectric layer;

[0010] performing an oxidation treatment on the first intermetallic dielectric layer;

[0011] A second intermetal dielectric layer is formed on the first intermetal dielectric layer.

[0012] Furthermore, the first intermetal dielectric layer includes fluorine-doped silicon glass, and the second intermetal dielectric layer includes fluorine-doped silicon glass.

[0013] Furthermore, the first intermetallic dielectric layer is formed by high-density plasma chemical vapor deposition, and the second intermetallic dielectric layer is formed by plasma enhanced chemical vapor deposition.

[0014] Furthermore, the temperature range of the heating treatment is 380°C-400°C.

[0015] Furthermore, the oxidation treatment includes oxygen plasma treatment.

[0016] Furthermore, before forming the first intermetallic dielectric layer on the wafer, the method further includes: forming a first diffusion barrier layer on the metal layer.

[0017] Furthermore, after forming the second intermetal dielectric layer on the first intermetal dielectric layer, the method further includes: forming a second diffusion barrier layer on the second intermetal dielectric layer.

[0018] Furthermore, the first diffusion barrier layer includes silicon-rich oxide, and the second diffusion barrier layer includes silicon-rich oxide.

[0019] Furthermore, the metal layer includes aluminum-copper alloy.

[0020] The present invention provides a semiconductor device, comprising:

[0021] a wafer having a metal layer formed thereon;

[0022] A first intermetallic dielectric layer is formed on the wafer after being heated and oxidized;

[0023] A second intermetal dielectric layer is formed on the first intermetal dielectric layer.

[0024] According to the method for manufacturing a semiconductor device of the present invention, a dense oxide layer is formed at the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer by heating and oxidizing the first intermetallic dielectric layer, thereby avoiding water vapor corrosion and the diffusion and precipitation of free F ions, thereby avoiding the generation of bubble-shaped defects at the edge of the wafer and improving the yield of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following drawings of the present invention are incorporated herein as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and the description thereof is used to explain the principle of the present invention.

[0026] In the attached figure:

[0027] Figure 1A is a schematic diagram of wafer test results including qualified chips and unqualified chips;

[0028] Figure 1 B is a scanning electron microscope image of a cross section of a defective chip of the wafer;

[0029] Figure 1 C shows the wafer test results including qualified chips and unqualified chips before forming fluorine-doped silicon glass using high-density plasma chemical vapor deposition;

[0030] Figure 1 D shows the wafer test results including qualified chips and unqualified chips after forming fluorine-doped silicon glass using high-density plasma chemical vapor deposition;

[0031] Figure 1 E and 1F show scanning electron micrographs of the cross section of a defective chip after high-density plasma chemical vapor deposition;

[0032] Figure 2 is a schematic cross-sectional view of the structure of a semiconductor device according to an exemplary embodiment of the present invention;

[0033] Figure 3 is a schematic flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0034] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0035] It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0036] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] In order to fully understand the present invention, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0040] In order to better understand the present invention, first combine Figure 1 A further analysis is conducted on the reasons causing qualified chips and unqualified chips on the wafer.

[0041] In semiconductor back-end of line (BEOL) processes, Al / Cu (0.5%) alloys are often used as the material for integrated circuit leads. Their key features include low resistance, good conductivity, ease of processing, and the ability to meet the design requirements of diverse chip structures. Adding an appropriate amount of Cu to Al also enhances its electromigration resistance. Due to the relatively low melting point of aluminum, during HDPCVD FSG deposition, the HDP process employs a strong bias power to bombard the wafer surface with charged ions to enhance fill capacity. However, ion bombardment raises the wafer surface temperature. Excessively high wafer reaction temperatures can cause deformation or even melting of the Al wire, impacting reliability.

[0042] Therefore, when applying the HDP process, flowing helium (He) gas is introduced to the back of the wafer to prevent the wafer temperature from overheating and causing aluminum melting. The back helium gas is mainly introduced through two circles of densely packed small holes on the wafer tray (E-Chuck tray). The outer circle (Outer) back helium holes are approximately 7mm from the edge of the wafer, and the inner circle (Inner) back helium holes are approximately 15mm from the edge of the wafer. As the back helium gas flows, the heat of the wafer is removed, and the area with the lowest temperature on the entire wafer will be the outer circle back helium area. Because F in FSG mainly has two forms: combining with Si dangling bonds to form Si-F bonds, and free F ions, a large number of free F ions are likely to appear when the reaction temperature is too low. When too many free F ions gather, F precipitation will occur, which will appear as bubble-like defects on the surface of the FSG film on the wafer, causing short circuit risks in subsequent processes.

[0043] Specifically, Figure 1 The defective chip shown in A, located at the edge of the wafer, is short-circuited, meaning that the wires are interconnected at a certain location. Using a scanning electron microscope (SEM) to analyze the cross-section of the defective chip, bubbles were observed in the short-circuit area. Figure 1 As shown in Figure B, the failure mechanism of the unqualified chip may be that bubbles may appear in the lower layer of the intermetal dielectric layer (IMD). After the subsequent etching to form a via (Via), the via is connected to the bubble, which then causes W to be injected during the tungsten (W) deposition process, resulting in a short circuit.

[0044] further, Figure 1C and 1D show the wafer test results of qualified and unqualified chips before and after high-density plasma chemical vapor deposition to form fluorine-doped silicon glass, respectively. It can be seen that after the high-density plasma chemical vapor deposition step to form fluorine-doped silicon glass, the number of unqualified chips increased significantly. For the above unqualified chips, the cross-section was analyzed using an electron scanning microscope (SEM), and typical egg roll-shaped bubbles (such as Figure 1 E) and the edge bubbling bubbles after typical high-density plasma chemical vapor deposition (as shown in Figure 1 F).

[0045] In view of the above problems, the present invention provides a method for manufacturing a semiconductor device, such as Figure 2 and Figure 3 As shown, including:

[0046] Step S310: providing a wafer 200 , on which a metal layer 210 is formed;

[0047] Step S320: forming a first intermetallic dielectric layer 221 on the wafer 200;

[0048] Step S330: performing a heat treatment on the first intermetallic dielectric layer 221;

[0049] Step S340: performing oxidation treatment on the first intermetallic dielectric layer 221;

[0050] Step S350 : forming a second intermetal dielectric layer 222 on the first intermetal dielectric layer 221 .

[0051] First, step S310 is performed: providing a wafer 200 , on which a metal layer 210 is formed.

[0052] Exemplarily, the wafer 200 includes a silicon substrate, which may be at least one of the following materials: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In one embodiment, the silicon substrate may be a silicon substrate implanted with P-type or N-type impurity ions, and its specific doping concentration is not limited by this embodiment.

[0053] Exemplarily, the wafer 200 further includes an isolation structure, which is a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure. The isolation structure divides the silicon substrate into different active regions, in which various semiconductor devices, such as NMOS and PMOS, can be formed. Various well structures are also formed in the silicon substrate, but are omitted in the figure for simplicity.

[0054] Illustratively, a metal interconnect structure is formed above the active area, comprising a multi-layer intermetallic dielectric structure and a multi-layer interconnect metal layer within the intermetallic dielectric structure. The interconnect metal structure typically includes trenches and vias, which form a connection path from bottom to top to connect the electrodes of the semiconductor devices in the active area to the pads located at the top of the metal interconnect structure. In this embodiment, the metal layer 210 is any layer of the multi-layer interconnect metal layer in the metal interconnect structure.

[0055] For example, the metal layer 210 comprises an aluminum-copper alloy containing approximately 0.5% copper. Al / Cu (0.5%) alloys are commonly used as materials for integrated circuit leads. Their main characteristics include low resistance, good conductivity, ease of processing, and the ability to meet the design requirements of chips with different structures. Adding an appropriate amount of Cu to Al can also enhance its anti-electromigration properties.

[0056] For example, the metal layer 210 may be formed by one of low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD), and selective epitaxial growth (SEG) such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In this embodiment, physical vapor deposition (PVD) is preferred.

[0057] Further, the metal layer 210 is etched to form an interconnection path. The method for etching the metal layer 210 can be dry etching or wet etching. Exemplarily, the dry etching process includes but is not limited to reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method can also be used, or more than one etching method can also be used. The source gas of the dry etching can include HBr and / or CF4 gas.

[0058] Next, the step of forming a first diffusion barrier layer 231 on the metal layer 210 is performed.

[0059] Exemplarily, the first diffusion barrier layer 231 includes a silicon rich oxide (SRO) layer.

[0060] Exemplarily, the preparation of the SRO layer is roughly the same as that of conventional silicon oxide, and both can be prepared by chemical vapor deposition (CVD) using a gas mixture containing silane (SiH4), oxygen (O2) and a rare gas such as argon (Ar) as a preparation gas. Wherein, since the silicon content of SRO is greater than that of conventional silicon oxide, the ratio of SiH4 and O2 is set to be higher than the ratio used to form conventional silicon oxide. In addition, another silane gas such as disilane (Si2H6) gas and tetraethoxysilane (TEOS) gas can be used to replace the monosilane gas. Oxygen-containing gases such as nitrous oxide (N2O) gas or ozone (O3) can also be used to replace oxygen. As an example, when the SRO layer is formed by CVD, the power is 180W-220W, the pressure in the chamber is 2.6Torr-3.0Torr, the SiH4 gas flow rate used is 140sccm-160sccm, the N2O gas flow rate is 2400sccm, the deposition time lasts 4s-5s, and the deposited film thickness is 2.5-3.0.

[0061] Using silicon-rich oxide as the first diffusion barrier layer 231 can capture F ions, thereby preventing F ions in the subsequently formed first intermetallic dielectric layer 221 from diffusing into the metal layer 210 .

[0062] Next, step S320 is performed: forming a first intermetallic dielectric layer 221 on the wafer 200 .

[0063] Exemplarily, an intermetallic dielectric structure is formed between adjacent interconnected metal layers, and the intermetallic dielectric structure is a stacked structure. In this embodiment, the intermetallic dielectric structure includes at least a first intermetallic dielectric layer 221 and a second intermetallic dielectric layer 222. Furthermore, the intermetallic dielectric structure also includes a first diffusion barrier layer 231 located between the first intermetallic dielectric layer 221 and the interconnected metal layer (i.e., metal layer 210), and a second diffusion barrier layer 232 located between the second intermetallic dielectric layer 222 and the interconnected metal layer.

[0064] Exemplarily, a first intermetallic dielectric layer 221 is formed on the first diffusion barrier layer 231 , wherein the first intermetallic dielectric layer comprises fluorine-doped silicon glass (FSG). Furthermore, the F content in the FSG is approximately 4%.

[0065] Exemplarily, the first intermetallic dielectric layer 221 is formed by high-density plasma chemical vapor deposition (HDPCVD).

[0066] Exemplarily, the fluorine-doped silicate glass (FSG) is formed by reacting silicon tetrafluoride (SiF4) / silane (SiH4) gas with an oxidant in a chemical vapor deposition (CVD) process chamber. Simultaneously, radio frequency power (RF Power) is applied to the reaction gas in the process chamber to form a high-density plasma. As an example, when HDPCVD is used to form FSG, the power parameters include: RF bias (RF Bias) = ​​3000W-3300W, side RF (RF Side) = 3300W-3500W, top RF (RF Top) = 1200W-1400W; the back helium gas pressure (independent helium control, IHC) is about 5.8 Torr for the inner circle (Inner) and about 8.6 Torr for the outer circle (Outer); the pressure in the chamber is 4mTorr-6mTorr; the SiH4 gas flow rate used is 30sccm-34sccm, the silicon tetrafluoride gas flow rate is 20sccm-25sccm, and the O2 gas flow rate is 65sccm-75sccm; the deposited film thickness is

[0067] At the same time, flowing He (helium) gas is introduced to the back of wafer 200 to prevent the wafer from overheating and potentially melting aluminum. The back helium gas is introduced primarily through two closely spaced holes on the wafer tray (E-Chuck). The outer ring of holes is approximately 7 mm from the wafer edge, while the inner ring is approximately 15 mm from the wafer edge.

[0068] As an example, the HDPFSG deposition process includes the following stages: wafer loading into the processing chamber, plasma ignition, preheating, reaction gas introduction, pre-deposition of a protective film, main deposition, bias off, and wafer removal from the processing chamber. The bias off stage primarily involves turning off the bias power and reaction gases such as SiH4. After the bias off stage and before the wafer is removed from the processing chamber, a treatment process for the first intermetallic dielectric layer 221 is added, as described below.

[0069] Next, step S330 is performed: heating the first intermetal dielectric layer 221 .

[0070] Illustratively, the temperature range of the heating treatment is 380° C.-400° C., and the time range of the heating treatment is 10s-20s.

[0071] Furthermore, the power parameters during the heat treatment process include: RF bias (RF Bias) = ​​0W, side RF (RF Side) = 3500W-4000W, and top RF (RF Top) = 2500W-3000W. The pressure range during the heat treatment process is 4mTorr-6mTorr. The back helium gas pressure (IHC) range during the heat treatment process is 2.2Torr-2.4Torr for the inner ring (Inner) and 3.6Torr-4.0Torr for the outer ring (Outer). During the heat treatment process, the argon (Ar) gas flow rate is 100sccm-120sccm, and the oxygen (O2) gas flow rate is 120sccm-130sccm.

[0072] By heating the first IMD layer 221, the relatively large amount of free F contained in the first IMD layer 221, particularly in the portion facing away from the helium cryosphere, can be volatilized at a relatively high temperature, thereby preventing the free F from precipitating at the interface between the first IMD layer 221 and the underlying first diffusion barrier layer 231. This prevents bubble-like defects between the first IMD layer 221 and the first diffusion barrier layer 231. Furthermore, the heat treatment only volatilizes the free F in the first IMD layer 221 without affecting the stable F element in the first IMD layer 221, thereby preventing a change in the dielectric constant of the first IMD layer 221.

[0073] Next, step S340 is performed: performing an oxidation process on the first intermetal dielectric layer 221 .

[0074] Exemplarily, the oxidation treatment includes oxygen plasma treatment to form a dense oxide layer on the surface of the first intermetallic dielectric layer 221 .

[0075] Exemplarily, the oxidation treatment time ranges from 16s to 20s. The power parameters during the oxidation treatment include: RF bias (RF Bias) = ​​0W, side RF (RF Side) = 4600W-4800W, top RF (RF Top) = 4600W-4800W. The pressure range during the oxidation treatment is 4mTorr-6mTorr. The back helium gas pressure (IHC) during the oxidation treatment ranges from 4.4Torr-4.8Torr for the inner ring (Inner) and 7.5Torr-7.9Torr for the outer ring (Outer); the gas power of oxygen (O2) during the heating treatment is 220sccm-240sccm.

[0076] Due to the presence of fluorine in the fluorine-doped silicate glass deposited by HDP, the microstructure of FSG presents loose and multi-surrounding pores, so it has a relatively strong ability to adsorb water vapor. There is a waiting time between the formation of the first intermetal dielectric layer 221 and the start of the formation of the second intermetal dielectric layer 222. At this time, the water vapor in the environment enters the first intermetal dielectric layer 221 and combines with the F ions to easily form HF, which will corrode the first intermetal dielectric layer 221 and the metal layer 210. When too much water is absorbed, bubble-shaped defects may be formed at the interface between the first diffusion barrier layer 231 and the first intermetal dielectric layer 221, affecting the yield. In addition, the F in the subsequently formed second intermetal dielectric layer 222 will also diffuse to the first intermetal dielectric layer 221 below, resulting in F precipitation and defects.

[0077] Oxygen treatment dissociates O2 through a larger side source power. After oxygen plasma treatment, the Si dangling bonds at the interface of the first intermetal dielectric layer 221 are oxidized to form a dense oxide layer. This dense oxide layer has two functions: (1) preventing the first intermetal dielectric layer 221 from absorbing water vapor in the environment during the process gap, causing HF corrosion; (2) preventing the free F from diffusing between the second intermetal dielectric layer 222 and the first intermetal dielectric layer 221, causing F precipitation, especially forming bubble-like defects at the edge of the wafer.

[0078] Next, step S350 is performed: forming a second intermetal dielectric layer 222 on the first intermetal dielectric layer 221 .

[0079] Exemplarily, the second IMD layer 222 includes fluorine-doped silicon glass (FSG).

[0080] For example, the second intermetallic dielectric layer 222 is formed by plasma enhanced chemical vapor deposition (PECVD). As an example, when PECVD is used, the power is 900W-1400W, the temperature in the chamber is heated to 300°C-500°C, the SiH4 gas flow rate is 250sccm-280sccm, the SiF4 gas flow rate is 650sccm-750sccm, the N2O gas flow rate is 9000sccm-11000sccm, the N2 gas flow rate is 2000sccm-3000sccm, and the deposited film thickness is 10000sccm.

[0081] Exemplarily, the fluorine-doped silicate glass (FSG) is formed by reacting silicon tetrafluoride (SiF 4 ) / silane (SiH 4 ) gas with an oxidant in a chemical vapor deposition (CVD) process chamber to form fluorine-doped silicate glass (FSG).

[0082] Next, the step of performing chemical mechanical polishing on the second intermetallic dielectric layer 222 is performed.

[0083] For example, chemical-mechanical planarization (CMP) can be used to obtain a relatively perfect surface while ensuring material removal efficiency, thereby obtaining a wafer with good flatness.

[0084] Next, the step of forming a second diffusion barrier layer 232 on the second intermetal dielectric layer 222 is performed.

[0085] Exemplarily, the second diffusion barrier layer 232 includes a silicon rich oxide (SRO) layer.

[0086] Exemplarily, the preparation of the SRO layer is roughly the same as that of conventional silicon oxide, and both can be prepared by chemical vapor deposition (CVD) using a gas mixture of silane (SiH4), oxygen (O2) and a rare gas such as argon (Ar) as a preparation gas. Wherein, since the silicon content of SRO is greater than that of conventional silicon oxide, the ratio of SiH4 and O2 is set to be higher than the ratio used to form conventional silicon oxide. In addition, another silane gas such as disilane (Si2H6) gas and tetraethoxysilane (TEOS) gas can be used to replace the monosilane gas. Oxygen-containing gases such as nitrous oxide (N2O) gas or ozone (O3) can also be used to replace oxygen. As an example, when the SRO layer is formed by CVD, the power is 180W-220W, the pressure in the chamber is 2.6Torr-3.0Torr, the SiH4 gas flow rate used is 140sccm-160sccm, the N2O gas flow rate is 2400sccm, the deposition time lasts 4s-5s, and the deposited film thickness is 2.5-3.0.

[0087] Using silicon-rich oxide as the second diffusion barrier layer 232 can capture F ions, thereby preventing F ions in the second intermetallic dielectric layer 222 from diffusing to the upper interconnect metal layer.

[0088] Furthermore, this embodiment further includes repeating the above steps of forming the metal layer and the intermetallic dielectric structure to form a metal interconnect structure.

[0089] The present invention provides a semiconductor device, such as Figure 2 Shown, including:

[0090] A wafer 200 having a metal layer 210 formed thereon;

[0091] A first intermetallic dielectric layer 221 that is heated and oxidized is formed on the wafer 200;

[0092] A second intermetal dielectric layer 222 is formed on the first intermetal dielectric layer 221 .

[0093] Exemplarily, the wafer 200 includes a silicon substrate, which may be at least one of the following materials: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In one embodiment, the silicon substrate may be a silicon substrate implanted with P-type or N-type impurity ions, and its specific doping concentration is not limited by this embodiment.

[0094] Exemplarily, the wafer 200 further includes an isolation structure, which is a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure. The isolation structure divides the silicon substrate into different active regions, in which various semiconductor devices, such as NMOS and PMOS, can be formed. Various well structures are also formed in the silicon substrate, but are omitted in the figure for simplicity.

[0095] Illustratively, a metal interconnect structure is formed above the active area, comprising a multi-layer intermetallic dielectric structure and a multi-layer interconnect metal layer within the intermetallic dielectric structure. The interconnect metal structure typically includes trenches and vias, which form a connection path from bottom to top to connect the electrodes of the semiconductor devices in the active area to the pads located at the top of the metal interconnect structure. In this embodiment, the metal layer 210 is any layer of the multi-layer interconnect metal layer in the metal interconnect structure.

[0096] For example, the metal layer 210 comprises an aluminum-copper alloy containing approximately 0.5% copper. Al / Cu (0.5%) alloys are commonly used as materials for integrated circuit leads. Their main characteristics include low resistance, good conductivity, ease of processing, and the ability to meet the design requirements of chips with different structures. Adding an appropriate amount of Cu to Al can also enhance its anti-electromigration properties.

[0097] Exemplarily, a first diffusion barrier layer 231 is formed on the metal layer 210 .

[0098] Exemplarily, the first diffusion barrier layer 231 includes a silicon rich oxide (SRO) layer.

[0099] Using silicon-rich oxide as the first diffusion barrier layer 231 can capture F ions, thereby preventing F ions in the subsequently formed first intermetallic dielectric layer 221 from diffusing into the metal layer 210 .

[0100] Exemplarily, a first intermetallic dielectric layer 221 is formed on the wafer 200 .

[0101] Exemplarily, an intermetallic dielectric structure is formed between adjacent interconnected metal layers, and the intermetallic dielectric structure is a stacked structure. In this embodiment, the intermetallic dielectric structure includes at least a first intermetallic dielectric layer 221 and a second intermetallic dielectric layer 222. Furthermore, the intermetallic dielectric structure also includes a first diffusion barrier layer 231 located between the first intermetallic dielectric layer 221 and the interconnected metal layer (i.e., metal layer 210), and a second diffusion barrier layer 232 located between the second intermetallic dielectric layer 222 and the interconnected metal layer.

[0102] Exemplarily, the first intermetallic dielectric layer comprises fluorine-doped silicate glass (FSG), and further, the F content in the FSG is approximately 4%.

[0103] Exemplarily, the first intermetallic dielectric layer 221 is formed using high-density plasma chemical vapor deposition (HDPCVD). The first intermetallic dielectric layer 221 is subjected to a heat treatment at a temperature ranging from 380°C to 400°C for a time ranging from 10s to 20s. The first intermetallic dielectric layer 221 is also subjected to an oxidation treatment, including an oxygen plasma treatment, to form a dense oxide layer on the surface of the first intermetallic dielectric layer 221.

[0104] Exemplarily, a second intermetal dielectric layer 222 is further formed on the first intermetal dielectric layer 221. The second intermetal dielectric layer 222 includes fluorine-doped silicon glass (FSG).

[0105] Furthermore, a second diffusion barrier layer 232 is formed on the second intermetal dielectric layer 222. The second diffusion barrier layer 232 includes a silicon rich oxide (SRO) layer.

[0106] Using silicon-rich oxide as the second diffusion barrier layer 232 can capture F ions, thereby preventing F ions in the second intermetallic dielectric layer 222 from diffusing to the upper interconnect metal layer.

[0107] According to the method for manufacturing a semiconductor device of the present invention, a dense oxide layer is formed at the interface between the first intermetallic dielectric layer and the second intermetallic dielectric layer by heating and oxidizing the first intermetallic dielectric layer, thereby avoiding water vapor corrosion and the diffusion and precipitation of free F ions, thereby avoiding the generation of bubble-shaped defects at the edge of the wafer and improving the yield of the wafer.

[0108] The present invention has been described through the above-described embodiments. However, it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments and that various variations and modifications may be made based on the teachings of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a wafer, on which a metal layer is formed, wherein the metal layer comprises an aluminum-copper alloy; While forming a first intermetallic dielectric layer on the wafer using high-density plasma chemical vapor deposition, flowing helium gas is introduced into the back of the wafer to prevent the temperature of the wafer from being too high, thereby causing aluminum melting; performing a heat treatment on the first intermetallic dielectric layer; performing an oxidation treatment on the first intermetallic dielectric layer; forming a second intermetallic dielectric layer on the first intermetallic dielectric layer by plasma enhanced chemical vapor deposition; The first intermetal dielectric layer includes fluorine-doped silicon glass, and the second intermetal dielectric layer includes fluorine-doped silicon glass.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The temperature range of the heating treatment is 380°C-400°C.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The oxidation treatment includes oxygen plasma treatment.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming a first intermetallic dielectric layer on the wafer, the method further includes: A first diffusion barrier layer is formed on the metal layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: After forming a second intermetal dielectric layer on the first intermetal dielectric layer, the method further includes: A second diffusion barrier layer is formed on the second intermetal dielectric layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The first diffusion barrier layer includes a silicon-rich oxide, and the second diffusion barrier layer includes a silicon-rich oxide.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The metal layer includes an aluminum-copper alloy.

8. A semiconductor device, characterized in that: include: a wafer having a metal layer formed thereon, the metal layer comprising an aluminum-copper alloy; A first intermetallic dielectric layer is formed on the wafer after being heated and oxidized. While forming the first intermetallic dielectric layer using high-density plasma chemical vapor deposition, flowing helium gas is introduced into the back of the wafer to prevent the temperature of the wafer from being too high, thereby preventing aluminum from melting. A second intermetal dielectric layer is formed on the first intermetal dielectric layer; Wherein, a second intermetal dielectric layer is formed on the first intermetal dielectric layer by plasma enhanced chemical vapor deposition, the first intermetal dielectric layer comprises fluorine-doped silicon glass, and the second intermetal dielectric layer comprises fluorine-doped silicon glass.

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