Pixel and display device having the same

Abstract

A pixel and a display device having the pixel are provided. The display device includes a pixel including a first transistor connected between a first node and a second node to generate a drive current; an emission driver supplying an emission control signal; a scan driver supplying a first scan signal to a fourth scan signal in a period in which the emission control signal is supplied; a data driver supplying a data signal; a power supply supplying a voltage of a first power source; and a timing controller controlling a timing of driving of the scan driver, the emission driver, the data driver, and the power supply. The first scan signal controls a timing of supply of the voltage of the first power source to the first node or the second node. The power supply changes a level of the voltage of the first power source in one frame period.

Description

[0001] This application claims priority to and all the benefits of Korean Patent Application No. 10-2020-0091873, filed on July 23, 2020, the contents of which are incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present disclosure relates generally to a pixel and a display apparatus having the same. BACKGROUND

[0003] A display apparatus displays an image by using a control signal applied from the outside.

[0004] A display apparatus includes a plurality of pixels. Each of the pixels includes a plurality of transistors, a light emitting element electrically connected to the transistors, and a capacitor. The transistors are turned on in response to a signal provided through a line and accordingly generate a predetermined driving current. The light emitting element emits light corresponding to the driving current.

[0005] Display apparatuses with low power consumption are being developed to improve the driving efficiency of the display apparatuses. For example, when a still image is displayed, the power consumption of the display apparatus can be reduced by reducing the driving frequency (or data write frequency). In addition, the display apparatus can display an image at various frame frequencies (or driving frequencies) so as to implement image display in various conditions. Accordingly, there is a need for a method capable of improving display quality when a display apparatus is driven by changing the frame frequency. SUMMARY

[0006] The embodiments provide a pixel that effectively prevents (i.e., eliminates) deterioration of display quality due to a change in a hysteresis characteristic of a driving transistor.

[0007] The embodiments also provide a display apparatus including the pixel.

[0008] According to an aspect of the disclosure, a pixel includes a light emitting element, a first transistor connected between a first node and a second node and controlling a driving current supplied to the light emitting element according to a voltage of a third node connected with a gate electrode of a first transistor, a second transistor connected between a data line and the first node and turned on in response to a fourth scan signal, a third transistor connected between the second node and the third node and turned on in response to a second scan signal, a fourth transistor turned on in response to a first scan signal to apply a voltage of a first power supply to the first transistor, a fifth transistor connected between a driving power supply and the first node and turned off in response to an emission control signal, a sixth transistor connected between the second node and a first electrode of the light emitting element and turned off in response to the emission control signal, and a seventh transistor connected between the third node and a second power supply and turned on in response to a third scan signal, wherein a level of the voltage of the first power supply is changed in one frame period.

[0009] One frame period can include a display scan period in which the fourth scan signal is supplied to the second transistor so that a data signal supplied through the data line is written to the first node and the first scan signal is supplied to the fourth transistor, and at least one bias scan period in which the fourth scan signal is not supplied to the second transistor and the first scan signal is supplied to the fourth transistor.

[0010] The first power supply can have a first voltage level in the display scan period and a second voltage level different from the first voltage level in the at least one bias scan period.

[0011] The at least one bias scan period can include a first bias scan period and a second bias scan period after the first bias scan period. The first power supply can have a first voltage level in the display scan period, a second voltage level different from the first voltage level in the first bias scan period, and a third voltage level different from each of the first voltage level and the second voltage level in the second bias scan period.

[0012] The data signal supplied through the data line can have a fourth voltage level in the display scan period and a fifth voltage level different from the fourth voltage level in the at least one bias scan period.

[0013] The data signal supplied through the data line can have a fourth voltage level in the display scan period, a fifth voltage level different from the fourth voltage level in the first bias scan period, and a sixth voltage level different from each of the fourth voltage level and the fifth voltage level in the second bias scan period.

[0014] The pixel can further include an eighth transistor connected between the first electrode of the light emitting element and a third power supply and turned on in response to the first scan signal. The third power supply can have a seventh voltage level in the display scan period and an eighth voltage level different from the seventh voltage level in the at least one bias scan period.

[0015] The pixel can further include an eighth transistor connected between the first electrode of the light emitting element and a third power supply and turned on in response to the first scan signal. The third power supply can have a seventh voltage level in the display scan period, an eighth voltage level different from the seventh voltage level in the first bias scan period, and a ninth voltage level different from each of the seventh voltage level and the eighth voltage level in the second bias scan period.

[0016] One electrode of the fourth transistor can be connected to the first node.

[0017] One electrode of the fourth transistor can be connected to the second node.

[0018] According to another aspect of the present application, there is provided a display device including a pixel, an emission driver, a scan driver, a data driver, a power supply, and a timing controller, the pixel including a first transistor connected between a first node and a second node to generate a drive current, wherein the pixel is connected to a first scan line, a second scan line, a third scan line, a fourth scan line, an emission control line, and a data line, the emission driver supplies an emission control signal to the emission control line, the scan driver supplies first to fourth scan signals to the first to fourth scan lines, respectively, in a period in which the emission control signal is supplied, the data driver supplies a data signal to the data line, the power supply supplies a voltage of a drive power source, a voltage of a first power source, a voltage of a second power source, and a voltage of a third power source to the pixel, and the timing controller controls driving of the scan driver, the emission driver, the data driver, and the power supply, wherein the first scan signal controls timing in which the voltage of the first power source is supplied to the first node or the second node, and wherein the power supply changes a level of the voltage of the first power source in one frame period.

[0019] The pixel can further include a light emitting element, a second transistor connected between the data line and the first node and turned on in response to the fourth scan signal, a third transistor connected between the second node and a third node and turned on in response to the second scan signal, wherein the third node corresponds to a gate electrode of the first transistor, a fourth transistor turned on in response to the first scan signal to apply the voltage of the first power source to the first transistor, a fifth transistor connected between the drive power source and the first node and turned off in response to the emission control signal, a sixth transistor connected between the second node and a first electrode of the light emitting element and turned off in response to the emission control signal, and a seventh transistor connected between the third node and the second power source and turned on in response to the third scan signal.

[0020] One frame period can include a display scan period and at least one bias scan period. In the display scan period, the scan driver can supply the first scan signal through the first scan line and the fourth scan signal through the fourth scan line. In the at least one bias scan period, the scan driver can supply the first scan signal through the first scan line and can not supply the fourth scan signal.

[0021] The power supply can supply the voltage of the first power source having a first voltage level in the display scan period and supply the voltage of the first power source having a second voltage level different from the first voltage level in the at least one bias scan period.

[0022] The at least one bias scan period can include a first bias scan period and a second bias scan period after the first bias scan period. The power supply can supply a voltage of the first power source having a first voltage level in the display scan period, supply a voltage of the first power source having a second voltage level different from the first voltage level in the first bias scan period, and supply a voltage of the first power source having a third voltage level different from each of the first voltage level and the second voltage level in the second bias scan period.

[0023] The data driver can supply a data signal having a fourth voltage level to the data line in the display scan period, and supply a data signal having a fifth voltage level different from the fourth voltage level to the data line in the at least one bias scan period.

[0024] The data driver can supply a data signal having a fourth voltage level to the data line in the display scan period, supply a data signal having a fifth voltage level different from the fourth voltage level to the data line in the first bias scan period, and supply a data signal having a sixth voltage level different from each of the fourth voltage level and the fifth voltage level to the data line in the second bias scan period.

[0025] The pixel can further include an eighth transistor connected between the first electrode of the light emitting element and the third power source and turned on in response to a first scan signal. The power supply can supply a voltage of the third power source having a seventh voltage level in the display scan period, and supply a voltage of the third power source having an eighth voltage level different from the seventh voltage level in the at least one bias scan period.

[0026] The pixel can further include an eighth transistor connected between the first electrode of the light emitting element and the third power source and turned on in response to a first scan signal. The power supply can supply a voltage of the third power source having a seventh voltage level in the display scan period, supply a voltage of the third power source having an eighth voltage level different from the seventh voltage level in the first bias scan period, and supply a voltage of the third power source having a ninth voltage level different from each of the seventh voltage level and the eighth voltage level in the second bias scan period.

[0027] The emission driver can supply an emission control signal in each of a first non-emission period of the display scan period and a second non-emission period of the at least one bias scan period. The scan driver can supply a second scan signal through a second scan line and a third scan signal through a third scan line in the first non-emission period, and can not supply the second scan signal and the third scan signal in the second non-emission period. BRIEF DESCRIPTION OF DRAWINGS

[0028] A more complete understanding of the example embodiments will be afforded to those skilled in the art, as well as a realization of additional aspects and features thereof, upon a reading of the following detailed description of the example embodiments and a review of the associated drawings. The example embodiments are described herein in the context of a display device. However, the example embodiments can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0029] In the drawings, the size of each element can be exaggerated for the purpose of clarity. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements can also be present. Like reference numerals refer to like elements throughout.

[0030] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 is a circuit diagram illustrating an example of a pixel included in the display device illustrated in Figure 1 is a diagram illustrating an example of a scan driver included in the display device illustrated in

[0032] Figure 3 is a circuit diagram illustrating an example of a pixel included in the display device illustrated in Figure 1 is a circuit diagram illustrating an example of a pixel included in the display device illustrated in

[0033] Figure 4 is a timing chart illustrating an example of a signal supplied to the pixel illustrated in Figure 3 is a timing chart illustrating an example of a signal supplied to the pixel illustrated in

[0034] Figure 5 is a timing chart illustrating an example of a signal supplied to the pixel illustrated in Figure 3 is a timing chart illustrating an example of a signal supplied to the pixel illustrated in

[0035] Figure 6A and Figure 6B is a timing chart illustrating an example of a voltage of a first power supply and a data signal supplied to the pixel illustrated in Figure 3 is a timing chart illustrating an example of a voltage of a first power supply and a data signal supplied to the pixel illustrated in

[0036] Figure 7A and Figure 7B is a timing chart illustrating an example of a voltage of a second initialization power supply and a data signal supplied to the pixel illustrated in Figure 3 is a timing chart illustrating an example of a voltage of a first power supply, a voltage of a second initialization power supply, and a data signal supplied to the pixel illustrated in

[0037] Figure 8A and Figure 8B is a timing chart illustrating an example of a voltage of a first power supply, a voltage of a second initialization power supply, and a data signal supplied to the pixel illustrated in Figure 3 is a timing chart illustrating an example of a voltage of a first power supply, a voltage of a second initialization power supply, and a data signal supplied to the pixel illustrated in

[0038] Figure 9A and Figure 9B is a timing chart illustrating an example of a voltage of a first power supply, a voltage of a second initialization power supply, and a data signal supplied to the pixel illustrated in Figure 3The timing diagram shows an instance of the voltage of the first power supply, the voltage of the second initialization power supply, and the data signal of the pixel shown.

[0039] Figure 10 This is a graph showing an example of the brightness of an image displayed by a display device according to related technologies.

[0040] Figure 11 This is a graph illustrating an example of the brightness of an image displayed by a display device according to an embodiment of the present disclosure.

[0041] Figure 12 It shows the supply to Figure 3 The timing diagram shows another instance of the signal of the pixel shown.

[0042] Figure 13 It shows the supply to Figure 3 The timing diagram shows another example of the signal of the pixel shown.

[0043] Figure 14 It is shown that it includes Figure 1 A circuit diagram of another example of a pixel in the display device shown. Detailed Implementation

[0044] This disclosure is applicable to various variations and different shapes, and therefore is described in detail only by way of specific examples. However, the examples are not limited to certain shapes, but are applicable to all variations and equivalent materials as well as substitutions. For better understanding, the included figures are shown in an enlarged manner.

[0045] The same reference numerals throughout the accompanying drawings indicate the same elements. In the drawings, the thickness of certain lines, layers, parts, elements, or features may be enlarged for clarity. It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the "first" element discussed below may also be referred to as the "second" element. Unless the context clearly indicates otherwise, the singular forms used herein are intended to include the plural forms as well.

[0046] It should also be understood that the terms “include” and / or “including” as used in this specification indicate the presence of the stated features, integers, steps, operations, elements and / or components, but do not exclude the presence and / or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0047] Throughout the specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or connected or coupled thereto using one or more intervening elements.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "At least one" should not be construed as limiting "one" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that the terms "comprise", "comprising", "include", "including", or "comprising" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof. Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings

[0049] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0050] Referring to Figure 1 , the display device 1000 can include a pixel unit 100, a scan driver 200, an emission driver 300, a data driver 400, a power supply 500, and a timing controller 600.

[0051] The display device 1000 can display an image at various frame frequencies (e.g., a refresh rate, a driving frequency, or a screen refresh rate) according to a driving condition. The frame frequency is a frequency at which a data voltage is substantially written (or applied) to a driving transistor of a pixel PX within one second. For example, the frame frequency is also referred to as a screen scanning rate or a screen refresh frequency, and indicates a frequency at which a screen is reproduced within one second.

[0052] In an embodiment, an output frequency of the data driver 400 and / or an output frequency of a fourth scan signal supplied to the fourth scan line S4i can be changed according to a frame frequency. For example, the frame frequency for a moving image can be a frequency of about 60 hertz (Hz) or more (e.g., 120 Hz). The fourth scan signal can be supplied to each horizontal line (i.e., a pixel row) 60 times per second.

[0053] In an embodiment, the display device 1000 can adjust the output frequencies of the scan driver 200 and the emission driver 300 and the output frequency of the data driver 400 corresponding to the output frequencies of the scan driver 200 and the emission driver 300. For example, the display device 1000 can display images corresponding to various frame frequencies of 1 Hz to 120 Hz. However, this is merely illustrative, and in another embodiment, the display device 1000 can display images at a frame frequency of 120 Hz or more (e.g., 240 Hz or 480 Hz).

[0054] The display device 1000 can operate at various frame frequencies. In the case of low-frequency driving, it can be possible to view image defects such as flicker due to current leakage in the pixels PX. In addition, according to "change in the bias state of the driving transistor caused by driving at various frame frequencies" and "change in the response speed caused by threshold voltage shift depending on the change in the hysteresis characteristic or the like", it can be possible to view afterimages such as image retention.

[0055] In order to improve image quality, one frame period of the pixels PX can include one display scan period and at least one bias scan period according to the frame frequency. This will be described in detail with reference to FIGS. 2A to 2C. Figure 4 and Figure 5 The operations in the display scan period and the bias scan period will be described in detail.

[0056] The pixel unit 100 can include scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n, emission control lines E1 to En, and data lines D1 to Dm, and include pixels PX connected to the scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n, the emission control lines E1 to En, and the data lines D1 to Dm (m and n are integers greater than 1). Each of the pixels PX can include a driving transistor and a plurality of switching transistors. The pixels PX can be supplied with voltages of a first driving power supply VDD, a second driving power supply VSS, a first power supply VEH, and an initialization power supply Vint from the power supply 500.

[0057] In an embodiment of the disclosure, the signal lines connected to the pixels PX can be differently set according to the circuit structure of the pixels PX.

[0058] The timing controller 600 can be supplied with input image data IRGB and control signals Sync and DE from a host system such as an application processor ("AP") through a predetermined interface.

[0059] The timing controller 600 can generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, a clock signal, etc. The first control signal SCS can be supplied to the scan driver 200, the second control signal ECS can be supplied to the emission driver 300, the third control signal DCS can be supplied to the data driver 400, and the fourth control signal PCS can be supplied to the power supplier 500. The timing controller 600 can rearrange the input image data IRGB, and supply the rearranged image data RGB to the data driver 400.

[0060] The scan driver 200 can receive the first control signal SCS from the timing controller 600, and based on the first control signal SCS, supply a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to first scan lines S11 to S1n, second scan lines S21 to S2n, third scan lines S31 to S3n, and fourth scan lines S41 to S4n, respectively.

[0061] The first scan signal to the fourth scan signal can be set to a gate-on voltage (e.g., a low voltage) corresponding to a type of a transistor to which the corresponding scan signal is supplied. When the scan signal is supplied, the transistor receiving the scan signal can be set to an on state. For example, the gate-on voltage of the scan signal supplied to a P-channel metal oxide semiconductor ("PMOS") transistor can have a logic low level, and the gate-on voltage of the scan signal supplied to an N-channel metal oxide semiconductor ("NMOS") transistor can have a logic high level. Hereinafter, it should be understood that the term "the scan signal is supplied" means that the scan signal is supplied at a logic level at which the transistor controlled by the scan signal is turned on.

[0062] The emission driver 300 can supply an emission control signal to emission control lines E1 to En based on the second control signal ECS. For example, the emission control signal can be sequentially supplied to the emission control lines E1 to En.

[0063] The emission control signal can be set to a gate-off voltage (e.g., a high voltage). The transistor receiving the emission control signal can be turned off when the emission control signal is supplied, and otherwise set to an on state. Hereinafter, it should be understood that the term "the emission control signal is supplied" means that the emission control signal is supplied at a logic level at which the transistor controlled by the emission control signal is turned off.

[0064] For the convenience of description, the following description will be made with the assumption that the display device 100 is a liquid crystal display device. Figure 1Each of the scan driver 200 and the emission driver 300 is shown as a single component in the middle, but the present disclosure according to the present application is not limited thereto. In another embodiment, the scan driver 200 can include a plurality of scan drivers that supply at least one of the first to fourth scan signals, respectively. Also, at least a part of the scan driver 200 and at least a part of the emission driver 300 can be integrated into one driving circuit, one module, or the like.

[0065] The data driver 400 can receive the third control signal DCS and the image data RGB from the timing controller 600. The data driver 400 can convert the image data RGB in a digital form into an analog data signal (i.e., a data voltage). The data driver 400 can supply the data signal to the data lines D1 to Dm according to the third control signal DCS. The data signal supplied to the data lines D1 to Dm can be supplied in synchronization with the fourth scan signal supplied to the fourth scan lines S41 to S4n.

[0066] The power supplier 500 can supply a voltage of a first driving power source VDD and a voltage of a second driving power source VSS for driving the pixel PX to the pixel unit 100. The voltage level of the second driving power source VSS can be lower than the voltage level of the first driving power source VDD. For example, the voltage of the first driving power source VDD can be a positive voltage, and the voltage of the second driving power source VSS can be a negative voltage.

[0067] The power supplier 500 can supply a voltage of a first power source VEH (or a bias power source) and a voltage of an initialization power source Vint to the pixel unit 100. The initialization power source Vint can include a plurality of initialization power sources (e.g., Vint1 and Vint2 shown in the middle) that output a plurality of voltages having different voltage levels. Figure 3

[0068] The first power source VEH can be a power source for supplying a predetermined bias voltage to a source electrode and / or a drain electrode of a driving transistor included in the pixel PX. The first power source VEH can have a positive voltage. However, the voltage level of the first power source VEH according to the present application is not limited thereto. In another embodiment, the voltage level of the first power source VEH can correspond to a negative voltage.

[0069] The initialization power source Vint can be a power source for initializing the pixel PX. For example, the driving transistor and / or the light emitting element included in the pixel PX can be initialized by the voltage of the initialization power source Vint. The voltage of the initialization power source Vint can be a negative voltage.

[0070] ​In this implementation, the power supply 500 can change the voltage level of at least one of the voltage of the first power supply VEH and the voltage of the initialization power supply Vint during a frame period, and supply the changed voltage level to the pixel unit 100. Therefore, the bias state of the driving transistors included in the pixel PX can be controlled.

[0071] Figure 2 It is shown that it includes Figure 1 A diagram showing an example of a scan driver in a display device.

[0072] Reference Figure 1 and Figure 2 The scan driver 200 may include a first scan driver 220, a second scan driver 240, a third scan driver 260, and a fourth scan driver 280.

[0073] The first control signal SCS may include the first scan start signal FLM1 to the fourth scan start signal FLM4. The first scan start signal FLM1 to the fourth scan start signal FLM4 may be supplied to the first scan driver 220, the second scan driver 240, the third scan driver 260 and the fourth scan driver 280 respectively.

[0074] The width (duration) and supply timing of the first scan start signal FLM1 to the fourth scan start signal FLM4 can be determined based on the driving conditions of the pixel PX and the frame frequency. The first scan signal to the fourth scan signal can be output based on the first scan start signal FLM1 to the fourth scan start signal FLM4 respectively. For example, the signal width (i.e., the duration when the signal is on) of at least one of the first scan signal to the fourth scan signal can be different from the signal width of the other scan signals.

[0075] In response to the first scan start signal FLM1, the first scan driver 220 can sequentially supply the first scan signal to the first scan lines S11 to S1n. In response to the second scan start signal FLM2, the second scan driver 240 can sequentially supply the second scan signal to the second scan lines S21 to S2n. In response to the third scan start signal FLM3, the third scan driver 260 can sequentially supply the third scan signal to the third scan lines S31 to S3n. In response to the fourth scan start signal FLM4, the fourth scan driver 280 can sequentially supply the fourth scan signal to the fourth scan lines S41 to S4n.

[0076] Figure 3 It is shown that it includes Figure 1 A circuit diagram of an example of a pixel in the display device shown.

[0077] For ease of description,Figure 3 A pixel PXij (i and j are natural numbers) located on an i-th horizontal line (or i-th pixel row) and connected to a j-th data line Dj is shown in FIG. 1. Figure 3 The pixel PXij shown in FIG. 1 can be substantially the same as the pixel PX shown in FIG. 2. Figure 1 The pixel PX shown in FIG. 2 can be substantially the same as the pixel PX shown in FIG. 1.

[0078] Referring to FIG. 2, Figure 1 and Figure 3 The pixel PXij can include a light emitting element LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.

[0079] A first electrode (i.e., an anode or a cathode) of the light emitting element LD can be connected to the sixth transistor M6 (i.e., a fourth node N4), and a second electrode (i.e., a cathode or an anode) of the light emitting element LD can be connected to the second drive power source VSS. The light emitting element LD can generate light having a predetermined brightness corresponding to an amount of current (i.e., a driving current) supplied from the first transistor M1.

[0080] In an embodiment, the light emitting element LD can be an organic light emitting diode including an organic emission layer. In another embodiment, the light emitting element LD can be an inorganic light emitting element formed of an inorganic material. In another embodiment, the light emitting element LD can be a light emitting element made of a combination of an organic material and an inorganic material. Alternatively, the light emitting element LD can have a form in which a plurality of inorganic light emitting elements are connected in parallel and / or in series between the second drive power source VSS and the sixth transistor M6.

[0081] A first electrode of the first transistor M1 (i.e., a driving transistor) can be connected to a first node N1, and a second electrode of the first transistor M1 can be connected to a second node N2. The first transistor M1 can control an amount of current flowing from the first drive power source VDD to the second drive power source VSS via the light emitting element LD corresponding to a voltage of the third node N3. To this end, the first drive power source VDD can be set to a voltage higher than a voltage of the second drive power source VSS.

[0082] The second transistor M2 can be connected between the j-th data line Dj (hereinafter referred to as a data line Dj) and the first node N1. A gate electrode of the second transistor M2 can be connected to the i-th fourth scan line S4i (hereinafter referred to as a fourth scan line S4i). The second transistor M2 can be turned on when a fourth scan signal is supplied from the fourth scan line S4i to electrically connect the data line Dj and the first node N1.

[0083] The third transistor M3 can be connected between the second electrode (i.e., the second node N2) of the first transistor M1 and the gate electrode (i.e., the third node N3). The gate electrode of the third transistor M3 can be connected to the i-th second scan line S2i (hereinafter referred to as the second scan line S2i). The third transistor M3 can be turned on when a second scan signal is supplied from the second scan line S2i, to electrically connect the second electrode and the gate electrode (i.e., the second node N2 and the third node N3) of the first transistor M1. That is, the timing at which the second electrode (e.g., the drain electrode) of the first transistor M1 and the gate electrode of the first transistor M1 are connected to each other can be controlled by the second scan signal. When the third transistor M3 is turned on, the first transistor M1 can be connected in a diode form.

[0084] The fourth transistor M4 can be turned on in response to a first scan signal supplied from the i-th first scan line S1i (hereinafter referred to as the first scan line S1i), to supply a voltage of the first power supply VEH to the first transistor M1. In an embodiment, the fourth transistor M4 can be connected between the first node N1 (i.e., the first electrode of the first transistor M1) and the first power supply VEH. The timing at which the voltage of the first power supply VEH is supplied to the first node N1 can be controlled by the first scan signal.

[0085] The gate electrode of the fourth transistor M4 can be connected to the first scan line S1i. When the fourth transistor M4 is turned on, the voltage of the first power supply VEH can be supplied to the first node N1. In an embodiment, the voltage of the first power supply VEH can be similar to the voltage of the data signal of the black gray scale. For example, the voltage of the first power supply VEH can be about 5 to 7 volts (V).

[0086] When the fourth transistor M4 is turned on, a predetermined high voltage can be applied to the first electrode (e.g., the source electrode) of the first transistor M1. When the third transistor M3 is in an off state, the first transistor M1 can have an on-bias state (a state in which the first transistor M1 is capable of being turned on) (i.e., is on-biased).

[0087] In an embodiment, the voltage level of the first power supply VEH can be changed in one frame period. For example, the first power supply VEH can have a first voltage level in a display scan period during one frame period, and a second voltage level in a bias scan period during the same frame period. That is, the first power supply VEH can have different voltage levels in the display scan period and the bias scan period. The second voltage level can be higher than the first voltage level. In another example, when one frame period includes one display scan period and a plurality of bias scan periods, the first power supply VEH can have a first voltage level in one display scan period, a second voltage level in a first bias scan period among the bias scan periods, and a third voltage level in a second bias scan period among the bias scan periods (see FIG. 2B). Figure 6B). That is, the first power source VEH can have different voltage levels not only in the display scan period and the bias scan period, but also in the first bias scan period and the second bias scan period among the bias scan period. The third voltage level can be higher than the second voltage level. Accordingly, in low-frequency driving in which the length of one frame period is extended, the voltage level of the first power source VEH that applies the on bias voltage to the first electrode (e.g., the source electrode) of the first transistor M1 is changed so that it is possible to further minimize the deterioration of display quality due to the change in the hysteresis characteristic of the first transistor M1.

[0088] The fifth transistor M5 can be connected between the first driving power source VDD and the first node N1. The gate electrode of the fifth transistor M5 can be connected to the i-th emission control line Ei (hereinafter, referred to as an emission control line Ei). The fifth transistor M5 can be turned off when an emission control signal is supplied to the emission control line Ei, and turned on in other cases.

[0089] The sixth transistor M6 can be connected between the second electrode (i.e., the second node N2) of the first transistor M1 and the first electrode (i.e., the fourth node N4) of the light emitting element LD. The gate electrode of the sixth transistor M6 can be connected to the emission control line Ei. The sixth transistor M6 can be controlled substantially identically to the fifth transistor M5.

[0090] Although the case in which the fifth transistor M5 and the sixth transistor M6 are connected to the same emission control line Ei is shown in Figure 3 , this is merely illustrative, and in another embodiment, the fifth transistor M5 and the sixth transistor M6 can be connected to separate emission control lines to which different emission control signals are supplied, respectively.

[0091] The seventh transistor M7 can be connected between the third node N3 and the first initialization power source Vint1 (in other words, the second power source). The gate electrode of the seventh transistor M7 can be connected to the i-th third scan line S3i (hereinafter, referred to as a third scan line S3i). The seventh transistor M7 can be turned on when a third scan signal is supplied from the third scan line S3i to supply the voltage of the first initialization power source Vint1 to the third node N3. The voltage of the first initialization power source Vint1 can be set to a voltage lower than the voltage of the data signal supplied to the data line Dj.

[0092] Accordingly, when the seventh transistor M7 is turned on, the gate voltage of the first transistor M1 can be initialized to the voltage of the first initialization power source Vint1.

[0093] The eighth transistor M8 can be connected between the first electrode of the light emitting element LD (i.e., the fourth node N4) and the second initialization power source Vint2 (in other words, the third power source). In an embodiment, the gate electrode of the eighth transistor M8 can be connected to the first scan line S1i. The eighth transistor M8 can be turned on when the first scan signal is supplied from the first scan line S1i, to supply the voltage of the second initialization power source Vint2 to the first electrode of the light emitting element LD (i.e., the fourth node N4).

[0094] When the voltage of the second initialization power source Vint2 is supplied to the first electrode of the light emitting element LD, the parasitic capacitor of the light emitting element LD can be discharged. Since the residual voltage charged in the parasitic capacitor is discharged (i.e., eliminated), it is possible to effectively prevent an unintended slight emission. Accordingly, it is possible to improve the black performance of the pixel PXij.

[0095] In an embodiment, the voltage level of the second initialization power source Vint2 can be changed in one frame period. For example, the second initialization power source Vint2 can have a seventh voltage level in a display scan period during one frame period, and an eighth voltage level in a bias scan period during one frame period. That is, the second initialization power source Vint2 can have different voltage levels in the display scan period and the bias scan period (see FIG. 6). Figure 9A ) The eighth voltage level can be lower than the seventh voltage level. In another example, when one frame period includes one display scan period and a plurality of bias scan periods, the second initialization power source Vint2 can have a seventh voltage level in one display scan period, an eighth voltage level in a first bias scan period among the bias scan periods, and a ninth voltage level in a second bias scan period among the bias scan periods. That is, the second initialization power source Vint2 can have different voltage levels not only in the display scan period and the bias scan period, but also in the first bias scan period and the second bias scan period among the bias scan periods (see FIG. 7). Figure 9B ) The ninth voltage level can be lower than the eighth voltage level. Accordingly, in low frequency driving in which the length of one frame period is extended, the voltage level of the second initialization power source Vint2 applied to the first electrode (e.g., anode) of the light emitting element LD is changed, so that the initialization amount of the parasitic capacitor of the light emitting element LD is changed. Accordingly, it is possible to effectively prevent brightness fluctuation due to a change in the hysteresis characteristic of the first transistor M1, and accordingly, it is possible to further minimize the display quality deterioration.

[0096] The first initialization power source Vint1 and the second initialization power source Vint2 can have different voltages. That is, the voltage for initializing the third node N3 and the voltage for initializing the fourth node N4 can be set differently from each other.

[0097] In low-frequency driving in which the length of one frame period is extended, when the voltage of the first initialization power supply Vint1 supplied to the third node N3 is too low, a strong-on bias is applied to the first transistor Ml, and thus the threshold voltage of the first transistor Ml in the corresponding frame period is shifted. This hysteresis characteristic can cause a flicker phenomenon in low-frequency driving. Therefore, in a display device driven at low frequency, it can be desirable that the voltage of the first initialization power supply Vint1 be higher than the voltage of the second drive power supply VSS.

[0098] However, when the voltage of the second initialization power supply Vint2 supplied to the fourth node N4 is higher than a predetermined reference value, the voltage of the parasitic capacitor of the light emitting element LD is not discharged, but can be charged. Therefore, it is desirable that the voltage of the second initialization power supply Vint2 be sufficiently low enough to discharge the voltage of the parasitic capacitor of the light emitting element LD. For example, by taking into account the threshold voltage of the light emitting element LD, the voltage of the second initialization power supply Vint2 can be set to be lower than a value obtained by adding the threshold voltage of the light emitting element LD and the voltage of the second drive power supply VSS.

[0099] However, this is merely illustrative, and the voltage of the first initialization power supply Vint1 and the voltage of the second initialization power supply Vint2 can be set differently. In an example, the voltage of the first initialization power supply Vint1 and the voltage of the second initialization power supply Vint2 can be substantially the same.

[0100] The storage capacitor Cst can be connected between the first drive power supply VDD and the third node N3. The storage capacitor Cst can store the voltage applied to the third node N3.

[0101] The voltage level of the data signal supplied to the data line Dj can change according to the voltage level of the first power supply VEH that changes in one frame period. By the coupling of the parasitic capacitor between the second transistor M2 and the first transistor Ml, even when the voltage level of the first power supply VEH changes, the phenomenon of the voltage level of the voltage applied to the gate electrode of the first transistor Ml (i.e., the third node N3) (i.e., the voltage stored in the storage capacitor Cst) changing can be prevented. Therefore, even in low-frequency driving in which the length of one frame period is extended, the voltage stored in the storage capacitor Cst is constantly maintained during one frame period, so that the pixel PXij can constantly emit light having a luminance corresponding to the data signal of the corresponding frame period during one frame period.

[0102] In addition, the voltage level of the data signal supplied to the data line Dj can be changed based on the voltage level of the second initialization power supply Vint2 which is changed in one frame period. By coupling of the parasitic capacitor between the second transistor M2 and the first transistor Ml, even when the voltage level of the second initialization power supply Vint2 is changed, the phenomenon that the voltage level of the voltage applied to the gate electrode of the first transistor Ml (i.e., the third node N3) (i.e., the voltage stored in the storage capacitor Cst) is changed can be prevented. Therefore, even in low-frequency driving in which the length of one frame period is extended, the voltage stored in the storage capacitor Cst is constantly maintained during one frame period, so that the pixel PXij can constantly emit light having a luminance corresponding to the data signal of the corresponding frame period during one frame period.

[0103] In an embodiment, the first transistor Ml, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can be implemented with a polysilicon semiconductor transistor. For example, the first transistor Ml, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can include a polysilicon semiconductor layer formed by a low-temperature polysilicon ("LTPS") process as an active layer (i.e., a channel). In addition, the first transistor Ml, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can be implemented with a P-type transistor (e.g., a PMOS transistor). Therefore, the gate-on voltage when the first transistor Ml, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are turned on can have a logic low level.

[0104] Since the polysilicon semiconductor transistor has a fast response speed, the polysilicon semiconductor transistor can be applied to a switching element which requires fast switching.

[0105] In an embodiment, the third transistor M3 and the seventh transistor M7 can be implemented with an oxide semiconductor transistor. For example, the third transistor M3 and the seventh transistor M7 can be implemented with an N-type oxide semiconductor transistor (e.g., an NMOS transistor) and include an oxide semiconductor layer as an active layer. Therefore, the gate-on voltage when the third transistor M3 and the seventh transistor M7 are turned on can have a logic high level.

[0106] The oxide semiconductor transistor can be formed by a low-temperature process and has a lower charge mobility than a polysilicon semiconductor transistor. That is, the oxide semiconductor transistor has an excellent off-state current characteristic. Thus, when the third transistor M3 and the seventh transistor M7 are implemented with the oxide semiconductor transistor, a leakage current from the second node N2 according to low-frequency driving can be minimized, and accordingly, display quality can be improved.

[0107] However, the first to eighth transistors M1 to M8 according to the present application are not limited thereto. In another embodiment, at least one of the first to eighth transistors M1 to M8 can be implemented with an oxide semiconductor transistor, or at least one of the third and seventh transistors M3 and M7 can be implemented with a polysilicon semiconductor transistor.

[0108] Figure 4 is a timing chart illustrating an example of signals supplied to the pixel shown in Figure 3 is a timing chart illustrating an example of signals supplied to the pixel shown in Figure 5 is a timing chart illustrating an example of signals supplied to the pixel shown in Figure 3 is a timing chart illustrating an example of signals supplied to the pixel shown in

[0109] Referring to Figure 3 to Figure 5 In a variable-frequency driving in which a frame frequency (i.e., a frequency of a frame period FP) is controlled, one frame period FP can include a display scan period DSP and at least one bias scan period BSP.

[0110] The display scan period DSP can include a first non-emission period NEP1 and a first emission period EP1. The bias scan period BSP can include a second non-emission period NEP2 and a second emission period EP2. Figure 4 The non-emission period NEP and the emission period EP shown in Figure 5 may correspond to the first non-emission period NEP1 and the first emission period EP1 shown in

[0111] The display scan period DSP can include a period in which a data signal actually corresponding to an output image is written (i.e., applied) to the pixel PXij. For example, when a still image is displayed in low-frequency driving, a data signal can be written to the pixel PXij for each display scan period DSP.

[0112] As Figure 5As illustrated in FIG. 1, the emission control signal EMi can be supplied to the emission control line Ei at a first frequency higher than the frame frequency. The third scan signal GIi supplied through the third scan line S3i and the fourth scan signal GWi supplied through the fourth scan line S4i can be supplied at a second frequency lower than the first frequency. For example, the first frequency can be 240 Hz, and the second frequency can be 60 Hz. The frequencies of the third scan signal GIi and the fourth scan signal GWi can be substantially equal to the frame frequency.

[0113] However, this is merely illustrative, and in another embodiment, the second frequency can be 60 Hz or lower. When the second frequency becomes lower or when the difference between the first frequency and the second frequency becomes larger, the number of times the bias scan period BSP repeats in the frame period FP (i.e., the number of bias scan periods) can increase. For example, the frame period FP can include one display scan period DSP and a plurality of consecutive bias scan periods BSP.

[0114] In an embodiment, the second scan signal GCi supplied through the second scan line S2i can be supplied only in the first non-emission period NEP1. The second scan signal GCi can be supplied to the second scan line S2i a plurality of times in the first non-emission period NEP1.

[0115] In an embodiment, the first scan signal GBi supplied through the first scan line S1i can be supplied in the first non-emission period NEP1 and the second non-emission period NEP2. The first scan signal GBi can be supplied to the first scan line S1i a plurality of times in the first non-emission period NEP1. In addition, the first scan signal GBi can be supplied from the first scan line S1i a plurality of times in the second non-emission period NEP2.

[0116] The first scan signal GBi can be a signal for controlling the first transistor M1 to be in the on-bias state. For example, when the fourth transistor M4 is turned on by the first scan signal GBi, the voltage of the first power supply VEH can be supplied to the first node N1. In addition, the first scan signal GBi can be a signal for initializing the light emitting element LD. For example, when the eighth transistor M8 is turned on by the first scan signal GBi, the voltage of the second initialization power supply Vint2 can be supplied to the fourth node N4.

[0117] In the display device according to the embodiment of the disclosure, the voltage of the first power supply VEH can be periodically applied to the first electrode (i.e., the source electrode) of the first transistor M1 through the fourth transistor M4. When the voltage of the first power supply VEH is supplied to the source electrode of the first transistor M1, the first transistor M1 can be in the on-bias state, and the threshold voltage characteristic of the first transistor M1 can change. Thus, it is possible to effectively prevent the first transistor M1 from being deteriorated due to the characteristic of the first transistor M1 being fixed to a certain state in low frequency driving.

[0118] In one embodiment, the voltage level of the first power supply VEH can be changed in one frame period FP. Thus, display quality deterioration due to a change in the hysteresis characteristic of the first transistor Ml can be further minimized. The operation of the pixel PXij according to a change in the voltage level of the first power supply VEH will be described in detail with reference to Figure 6A 、 Figure 6B and Figure 8A to Figure 11 The operation of the pixel PXij according to a change in the voltage level of the first power supply VEH will be described in detail with reference to

[0119] In the display device according to the embodiment of the present disclosure, the voltage of the second initialization power supply Vint2 can be periodically applied to the first electrode (i.e., the anode) of the light-emitting element LD through the eighth transistor M8. When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD, a residual voltage charged in the parasitic capacitor of the light-emitting element LD is discharged (i.e., eliminated), so that an unintended slight emission can be effectively prevented.

[0120] In one embodiment, the voltage level of the second initialization power supply Vint2 can be changed in one frame period FP. Thus, display quality deterioration due to a residual voltage charged in the parasitic capacitor of the light-emitting element LD can be further minimized. The operation of the pixel PXij according to a change in the voltage level of the second initialization power supply Vint2 will be described in detail with reference to Figure 7A to Figure 11 The operation of the pixel PXij according to a change in the voltage level of the second initialization power supply Vint2 will be described in detail with reference to

[0121] Although the case where the first scan signal GBi is supplied in all the non-emission periods NEPi and NEP2 is shown in Figure 5 , the present disclosure according to the present application is not limited thereto. In another embodiment, the first scan signal GBi can be supplied only in some of the second non-emission periods NEP2. For example, the first scan signal GBi can be supplied from the first scan line Sli only in the display scan period DSP and the second bias scan period BSP2 (see FIG. 6) shown in Figure 5

[0122] The period in which the emission control signal EMi has a logic low level can correspond to the emission periods EP, EPi, and EP2, and the period other than the emission periods EP, EPi, and EP2 can correspond to the non-emission periods NEP, NEPi, and NEP2. In the non-emission periods NEP, NEPi, and NEP2, the emission control signal EMi has a logic high level.

[0123] ​The gate-on voltage of the second scan signal GCi and the third scan signal GIi supplied to the third transistor M3 and the seventh transistor M7, respectively, as N-type transistors can have a logic high level. The gate-on voltage of the fourth scan signal GWi and the first scan signal GBi supplied to the second transistor M2, the fourth transistor M4, and the eighth transistor M8, respectively, as P-type transistors can have a logic low level.

[0124] As shown in FIG. 1, Figure 5 In the second non-emission period NEP2, which is a non-emission period of the bias scan period BSP, the first scan signal GBi can be supplied from the first scan line S1i. Accordingly, the voltage of the first power source VEH can be supplied to the first electrode of the first transistor M1 in the second non-emission period NEP2. That is, the on bias can be periodically applied to the first transistor M1 regardless of the frame frequency. In addition, the first scan signal GBi can be supplied through the first scan line S1i multiple times in the second non-emission period NEP2 so as to maintain a stable on bias state. Accordingly, the luminance variation of the first transistor M1 in the frame period FP of the low frequency driving can be minimized. Even in the display scan period DSP, the first scan signal GBi can be supplied through the first scan line S1i multiple times so as to drive the scan driver 200 and simplify the configuration of the display device 1000.

[0125] Hereinafter, the operation of the scan signals GBi, GCi, GIi, and GWi supplied in the display scan period DSP and the pixel PXij will be described in detail with reference to Figure 3 and Figure 4

[0126] During the non-emission period NEP, the emission control signal EMi can be supplied from the emission control line Ei. Accordingly, the fifth transistor M5 and the sixth transistor M6 can be turned off during the non-emission period NEP. The non-emission period NEP can include the first period P1 to the fifth period P5.

[0127] In the first period P1, the scan driver 200 can supply the second scan signal GCi to the second scan line S2i and the first scan signal GBi to the first scan line S1i. In an embodiment, the first scan signal GBi can be supplied after the second scan signal GCi is supplied. Accordingly, in the first period P1, the fourth transistor M4 can be turned on after the third transistor M3 is turned on.

[0128] ​When only the fourth transistor M4 is turned on without the supply of the second scan signal GCi (without the third transistor M3 being turned on), the voltage of the first power source VEH can be supplied to the first node N1 (i.e., the source electrode of the first transistor M1). The voltage of the first power source VEH, which is a high voltage, is applied to the first node N1, so that the first transistor M1 can have an on-bias state. For example, when the voltage of the first power source VEH is about 5 V or more, the first transistor M1 has a source voltage and a drain voltage of about 5 V or more, and the absolute value of the gate-source voltage of the first transistor M1 can increase.

[0129] When a data signal is supplied by the supply of the fourth scan signal GWi in this state, the drive current can be changed unexpectedly due to the influence of the bias state of the first transistor M1, and the image brightness can fluctuate (e.g., an increase in brightness).

[0130] To solve this problem, in an embodiment of the present application, the scan driver 200 can supply the second scan signal GCi earlier than the first scan signal GBi in the first period P1. Accordingly, the third transistor M3 can be turned on earlier than the fourth transistor M4. When the third transistor M3 is turned on, the second node N2 and the third node N3 can be electrically connected to each other. Subsequently, when the fourth transistor M4 is turned on, the voltage of the first power source VEH can be transmitted to the third node N3 through the first node N1. In other words, the voltage difference between the first node N1 and the third node N3 can decrease to the threshold voltage of the first transistor M1. Accordingly, the magnitude of the gate-source voltage of the first transistor M1 can significantly decrease in the first period P1. For example, the first transistor M1 can be set to an off-bias state.

[0131] As described above, to prevent an unexpected increase in brightness due to the supply of the voltage of the first power source VEH before a data signal is written to the pixel PX in the first period P1, the supply of the first scan signal GBi and the second scan signal GCi can be controlled so that the fourth transistor M4 is turned on in a state in which the third transistor M3 is turned on.

[0132] In an embodiment, in the first period P1, the width W1 (i.e., the length of time) of the second scan signal GCi can be greater than the width W2 of the first scan signal GBi. For example, in the first period P1, the third transistor M3 can be turned on earlier than the fourth transistor M4, and turned off after the fourth transistor M4 is turned off.

[0133] However, this is merely illustrative, and in another embodiment, the third transistor M3 can be turned off earlier than the fourth transistor M4.

[0134] The eighth transistor M8 can be turned on in response to the first scan signal GBi, and the voltage of the second initialization power source Vint2 can be supplied to the first electrode (i.e., the fourth node N4) of the light emitting element LD.

[0135] Subsequently, in the second period P2, the scan driver 200 can supply the third scan signal GIi to the third scan line S3i. The seventh transistor M7 can be turned on by the third scan signal GIi. When the seventh transistor M7 is turned on, the voltage of the first initialization power source Vint1 can be supplied to the gate electrode of the first transistor M1. That is, in the second period P2, the gate voltage of the first transistor M1 can be initialized based on the voltage of the first initialization power source Vint1. Accordingly, a strong turn-on bias can be applied to the first transistor M1, and the hysteresis characteristic (i.e., the threshold voltage can be shifted) can be changed.

[0136] Subsequently, in the third period P3, the scan driver 200 can supply the second scan signal GCi to the second scan line S2i. The third transistor M3 can be turned on again in response to the second scan signal GCi. In the third period P3, the scan driver 200 can supply the fourth scan signal GWi to the fourth scan line S4i in correspondence with a part of the second scan signal GCi. The second transistor M2 can be turned on by the fourth scan signal GWi, and the data signal can be provided to the first node N1.

[0137] The first transistor M1 can be connected in a diode form through the turned-on third transistor M3, and can perform a data signal write and a threshold voltage compensation. Since the supply of the second scan signal GCi is maintained even after the supply of the fourth scan signal GWi is suspended, the threshold voltage of the first transistor M1 can be compensated for a sufficient time.

[0138] Subsequently, in the fourth period P4, the scan driver 200 can supply the first scan signal GBi to the first scan line S1i again. Accordingly, the fourth transistor M4 and the eighth transistor M8 can be turned on. When the fourth transistor M4 is turned on, the voltage of the first power source VEH can be supplied to the first node N1.

[0139] The influence of the strong turn-on bias applied in the second period P2 can be eliminated through a data signal write operation and a threshold voltage compensation operation. For example, the voltage difference between the gate voltage and the source voltage (or the voltage difference between the gate voltage and the drain voltage) of the first transistor M1 can be significantly reduced through the threshold voltage compensation in the third period P3. Then, the characteristics of the first transistor M1 can be changed again, and the drive current of the emission period EP can be increased or the excitation of the black gray level can be viewed.

[0140] To prevent this characteristic change, the fourth transistor M4 can be turned on in the fourth time period P4. Therefore, in the fourth time period P4, the voltage of the first power supply VEH is supplied to the source electrode of the first transistor M1, so that the first transistor M1 can be set to the on-biased state.

[0141] Sufficient idle time between the fourth time period P4 and the transmit time period EP is necessary to allow the first transistor M1 to be set to a stable on-bias state before transmission through the operation in the fourth time period P4. Therefore, a fifth time period P5, in which scan signals GBi, GCI, GIi, and GWi are not supplied, can be inserted between the fourth time period P4 and the transmit time period EP.

[0142] In this implementation, the fifth time period P5 may correspond to four or more horizontal time periods. For example, the length of the fifth time period P5 may be approximately 10 μs or more. Therefore, the first transistor M1 can have a stable on-bias state before the emission period EP. Thus, even during repetition... Figure 5 Even during the frame period FP shown, the emitted brightness can be maintained stably.

[0143] In the implementation, the first scan signal GBi, the second scan signal GCi, the third scan signal GIi, and the fourth scan signal GWi can be respectively derived from... Figure 2 The first scan driver 220, the second scan driver 240, the third scan driver 260 and the fourth scan driver 280 shown are supplied.

[0144] Figure 6A and Figure 6B It shows the supply to Figure 3 The timing diagram shows an example of the voltage of the first power supply and the data signal of the pixel shown.

[0145] Reference Figure 3 , Figure 5 and Figure 6A The voltage level of the first power supply VEH can be changed within a frame period FP. For example, the first power supply VEH can have a first voltage level VE1 during the display scan period DSP, and a second voltage level VE2 during at least one bias scan period BSP1 and BSP2. The second voltage level VE2 can be higher than the first voltage level VE1.

[0146] In low-frequency driving, the length of a frame period FP is extended. Specifically, the length of a frame period FP is further extended as the driving frequency decreases. The extent to which the driving current is unintentionally altered by the bias state of the first transistor M1 may become more severe. Therefore, the brightness of the displayed image may fluctuate (e.g., brightness increases).

[0147] In the display device according to the embodiment of the present disclosure, the voltage level of the first power supply VEH is changed in one frame period FP, so that the fluctuation of the image brightness due to the influence of the bias state of the first transistor Ml can be more effectively prevented (i.e., eliminated).

[0148] Specifically, in the low-frequency driving, as the display period is prolonged in one frame period FP, the degree of change of the driving current can become serious. That is, the degree of change of the driving current in the bias scan periods BSPl and BSP2 can become more serious than that in the display scan period DSP. Therefore, although the voltage of the first power supply VEH having the voltage level equal to the voltage level in the display scan period DSP (i.e., the first voltage level VEl) is supplied to the first node Nl in the bias scan periods BSPl and BSP2, the fluctuation of the image brightness due to the influence of the bias state of the first transistor Ml can still occur.

[0149] Therefore, in the display device according to the embodiment of the present disclosure, as Figure 6A shown in FIG. 6, in at least one of the bias scan periods BSPl and BSP2, the voltage of the first power supply VEH having the voltage level higher than the voltage level in the display scan period DSP (i.e., the second voltage level VE2) is supplied to the pixel PXij, so that the fluctuation of the image brightness in the bias scan periods BSPl and BSP2 can be more effectively prevented (i.e., eliminated).

[0150] Referring to Figure 6B , in the embodiment, the voltage level of the first power supply VEH can be changed in the bias scan periods BSPl and BSP2. For example, the first power supply VEH can have the second voltage level VE2 in the first bias scan period BSPl and the third voltage level VE3 in the second bias scan period BSP2. The third voltage level VE3 can be higher than the second voltage level VE2.

[0151] As similarly described with reference to Figure 6A , even in the bias scan periods BSPl and BSP2, as the display period is prolonged, the degree of change of the driving current can become serious. That is, the degree of change of the driving current in the second bias scan period BSP2 can become more serious than that in the first bias scan period BSPl. Therefore, although the voltage of the first power supply VEH having the voltage level equal to the voltage level in the first bias scan period BSPl (i.e., the second voltage level VE2) is supplied to the first node Nl in the second bias scan period BSP2, the fluctuation of the image brightness due to the influence of the bias state of the first transistor Ml can still occur.

[0152] Therefore, in the display device according to the embodiments of this disclosure, such as Figure 6B As shown, during the second bias scan period BSP2, the voltage of the first power supply VEH, which has a higher voltage level than that in the first bias scan period BSP1 (i.e., the third voltage level VE3), is supplied to the pixel PXij, making it possible to more effectively prevent (i.e. eliminate) fluctuations in image brightness during the bias scan periods BSP1 and BSP2 (or the second bias scan period BSP2).

[0153] As the voltage level of the first power supply VEH changes, that is, as the voltage level of the first power supply VEH applied to the first node N1 changes during the bias scan periods BSP1 and BSP2, the voltage applied to the gate electrode of the first transistor M1 (i.e., the third node N3) (i.e., the voltage stored in the storage capacitor Cst) may fluctuate due to the influence of the parasitic capacitor between the first node N1 and the third node N3 (i.e., the parasitic capacitor between the source electrode and the gate electrode of the first transistor M1). (For example, the voltage level of the voltage applied to the third node N3 changes (e.g., increases) correspondingly to the data signal Vdata.)

[0154] In a display device according to an embodiment of the present disclosure, the voltage level of the data signal Vdata supplied from the data line Dj can be changed according to the voltage level of the first power supply VEH, which changes during a frame period FP.

[0155] For example, such as Figure 6A As shown, the display device can supply a data signal Vdata with a fourth voltage level VD1 during the display scan period DSP, and a data signal Vdata with a fifth voltage level VD2 during the bias scan periods BSP1 and BSP2, such that even when the first power supply VEH changes from the first voltage level VE1 to the second voltage level VE2, the voltage applied to the gate electrode of the first transistor M1 does not increase. The fifth voltage level VD2 may be lower than the fourth voltage level VD1.

[0156] Even when the voltage level of the first power supply VEH changes, the coupling between the second transistor M2 and the first transistor M1 via the parasitic capacitor cancels out the increase in voltage of the third node N3 caused by the increase in voltage level of the first power supply VEH and the decrease in voltage of the third node N3 caused by the decrease in voltage level of the data signal Vdata, thus stably maintaining the voltage stored in the storage capacitor Cst. Therefore, during a frame period FP, pixel PXij can constantly emit light with a brightness corresponding to the data signal Vdata supplied in the display scan period DSP of the corresponding frame period FP.

[0157] Similarly, when the voltage level of the first power source VEH is changed again in the second bias scan period BSP2 (i.e., when the voltage of the first power source VEH having a third voltage level V E3 is supplied in the second bias scan period BSP2), the voltage level of the first power source VEH is increased in the second bias scan period BSP2, and thus, the voltage stored in the storage capacitor Cst fluctuates.

[0158] Accordingly, in the display device according to the embodiment of the present disclosure, the voltage level of the data signal Vdata supplied from the data line Dj can be changed in correspondence with the voltage level of the first power source VEH changed in the bias scan periods BSP1 and BSP2.

[0159] For example, as shown in FIG. 6, the display device can supply the data signal Vdata having the fifth voltage level VD2 in the first bias scan period BSP1 and supply the data signal Vdata having the sixth voltage level VD3 in the second bias scan period BSP2, so that the voltage applied to the gate electrode of the first transistor M1 is not increased in correspondence with the change of the first power source VEH from the second voltage level V E2 to the third voltage level V E3. The sixth voltage level VD3 can be lower than the fifth voltage level VD2. Figure 6B

[0160] According to the increase of the voltage of the third node N3 due to the increase of the voltage level of the first power source VEH and the decrease of the voltage of the third node N3 due to the decrease of the voltage level of the data signal Vdata, the voltage stored in the storage capacitor Cst is stably maintained. Accordingly, the pixel PXij can constantly emit light having a luminance corresponding to the data signal Vdata supplied in the display scan period DSP of the corresponding frame period FP during one frame period FP.

[0161] The voltage level of the data signal Vdata changed in the bias scan periods BSP1 and BSP2 (e.g., the fifth voltage level VD2 and / or the sixth voltage level VD3) in correspondence with the voltage level of the first power source VEH changed in the bias scan periods BSP1 and BSP2 (e.g., the second voltage level V E2 and / or the third voltage level V E3) can be experimentally determined by considering circuit design, etc. (e.g., arrangement relationship between transistors, etc.), so that the voltage stored in the storage capacitor Cst can be constantly maintained by the coupling of the parasitic capacitor between the second transistor M2 and the first transistor M1.

[0162] Although in Figure 6A and Figure 6B ​The case where the bias scan period includes two bias scan periods BSP1 and BSP2 has been exemplarily described, but the number of bias scan periods according to the present application is not limited thereto. In another embodiment, for example, the number of bias scan periods can be one or three or more.

[0163] When the number of bias scan periods is three or more, as Figure 6B described in the above, the display apparatus can change the voltage level of the first power VEH for each bias scan period as the length of one frame period FP is extended. In an example, when the number of bias scan periods is three, the display apparatus can supply the voltage of the first power VEH having a second voltage level (for example, VE2) in the first bias scan period (for example, BSP1) as shown in the above, Figure 6B supply the voltage of the first power VEH having a third voltage level (for example, VE3) higher than the second voltage level in the second bias scan period (for example, BSP2) after the first bias scan period, and supply the voltage of the first power VEH having a voltage level higher than the third voltage level in the third bias scan period after the second bias scan period. Figure 6A Figure 6B Figure 6B

[0164] After the bias scan periods BSP1 and BSP2 in one frame period FP are ended, the display apparatus (for example, the display apparatus 1000) can again supply the voltage of the first power VEH having the first voltage level VE1 to the pixels PXij in the display scan period DSP of the next frame period FP. Figure 1

[0165] Figure 7A and Figure 7B is a timing chart showing an example of the voltage of the second initialization power and the data signal supplied to Figure 3 the pixels as shown in the above.

[0166] Referring to Figure 3 , Figure 5 and Figure 7A , the voltage level of the second initialization power Vint2 can be changed in one frame period FP. For example, the second initialization power Vint2 can have a seventh voltage level VI1 in the display scan period DSP and an eighth voltage level VI2 in at least one bias scan period BSP1 and BSP2. The eighth voltage level VI2 can be lower than the seventh voltage level VI1.

[0167] ​​​​The length of a frame period FP increases further as the drive frequency decreases. The extent to which the drive current is unintentionally altered by the bias state of the first transistor M1 may become more severe. As a result, the brightness of the displayed image may fluctuate (e.g., brightness increases).

[0168] In the display device according to an embodiment of the present disclosure, in order to prevent an increase in the brightness of the displayed image, the voltage level of the second initialization power supply Vint2 is changed within a frame period FP, thereby more effectively preventing (i.e., eliminating) fluctuations in image brightness caused by the bias state of the first transistor M1. For example, when the voltage level of the second initialization power supply Vint2 applied to the light-emitting element LD decreases, the initialization amount of the parasitic capacitor of the light-emitting element LD increases, thereby controlling the increase in image brightness. Therefore, the brightness of the displayed image is reduced, making it possible to further minimize fluctuations in image brightness.

[0169] Therefore, in the display device according to the embodiments of this disclosure, such as Figure 7A As shown, during the bias scan periods BSP1 and BSP2, the voltage of the second initialization power supply Vint2, which has a lower voltage level than the voltage level in the display scan period DSP (i.e., the eighth voltage level VI2), is supplied to the light-emitting element LD included in the pixel PXij, so that fluctuations in image brightness during the bias scan periods BSP1 and BSP2 can be prevented (i.e., eliminated) more effectively.

[0170] Reference Figure 7B In this embodiment, the voltage level of the second initialization power supply Vint2 can be changed during the bias scan periods BSP1 and BSP2. For example, the second initialization power supply Vint2 can have an eighth voltage level VI2 during the first bias scan period BSP1 and a ninth voltage level VI3 during the second bias scan period BSP2. The ninth voltage level VI3 can be lower than the eighth voltage level VI2.

[0171] With reference Figure 7A Similarly, even within the bias scan periods BSP1 and BSP2, the degree of change in the drive current can become more significant as the display period is extended. That is, the degree of change in the drive current during the second bias scan period BSP2 can be more significant than the degree of change during the first bias scan period BSP1.

[0172] Therefore, in the display device according to the embodiments of this disclosure, such as Figure 7BAs shown, during the second bias scan period BSP2, the voltage of the second initialization power supply Vint2, which has a lower voltage level than that in the first bias scan period BSP1 (i.e., the ninth voltage level VI3), is supplied to the pixel PXij, making it possible to more effectively prevent (i.e. eliminate) fluctuations in image brightness during the bias scan periods BSP1 and BSP2 (or only the second bias scan period BSP2).

[0173] As the voltage level of the second initialization power supply Vint2 changes, that is, as the voltage level of the second initialization power supply Vint2 decreases during the bias scan periods BSP1 and BSP2, the voltage applied to the gate electrode (i.e., the third node N3) of the first transistor M1 (i.e., the voltage stored in the storage capacitor Cst) can fluctuate due to the influence of the parasitic capacitor between the first node N1 and the third node N3 (i.e., the parasitic capacitor between the source electrode and the gate electrode of the first transistor M1). (For example, the voltage level applied to the third node N3 changes (i.e., decreases) correspondingly to the data signal Vdata.)

[0174] In a display device according to an embodiment of the present disclosure, the voltage level of the data signal Vdata supplied from the data line Dj can be changed in correspondence with the voltage level of the second initialization power supply Vint2, which changes during a frame period FP.

[0175] For example, such as Figure 7A As shown, the display device can supply a data signal Vdata with a tenth voltage level VD4 during the display scan period DSP, and a data signal Vdata with an eleventh voltage level VD5 during the bias scan periods BSP1 and BSP2, such that the voltage applied to the gate electrode of the first transistor M1 does not decrease corresponding to the change of the second initialization power supply Vint2 from the seventh voltage level VI1 to the eighth voltage level VI2. The eleventh voltage level VD5 may be higher than the tenth voltage level VD4.

[0176] Even when the voltage level of the second initialization power supply Vint2 changes, the coupling between the parasitic capacitor between the second transistor M2 and the first transistor M1 cancels out the decrease in the voltage of the third node N3 caused by the decrease in the voltage level of the second initialization power supply Vint2, and the increase in the voltage of the third node N3 caused by the increase in the voltage level of the data signal Vdata, thus stably maintaining the voltage stored in the storage capacitor Cst. Therefore, during a frame period FP, pixel PXij can constantly emit light with a brightness corresponding to the data signal Vdata supplied in the display scan period DSP of the corresponding frame period FP.

[0177] Similarly, when the voltage level of the second initialization power supply Vint2 changes again during the second bias scan period BSP2 (i.e., when the voltage of the second initialization power supply Vint2 with the ninth voltage level VI3 is supplied during the second bias scan period BSP2), the voltage level of the second initialization power supply Vint2 decreases during the second bias scan period BSP2, and therefore, the voltage stored in the storage capacitor Cst may fluctuate.

[0178] Therefore, in the display device according to the embodiments of the present disclosure, the voltage level corresponding to the data signal Vdata supplied from the data line Dj can be changed according to the voltage level of the second initialization power supply Vint2, which changes during the bias scan periods BSP1 and BSP2.

[0179] For example, such as Figure 7B As shown, the display device can supply a data signal Vdata with an eleventh voltage level VD5 during the first bias scan period BSP1, and a data signal Vdata with a twelfth voltage level VD6 during the second bias scan period BSP2, such that the voltage applied to the gate electrode of the first transistor M1 does not decrease corresponding to the change of the second initialization power supply Vint2 from the eighth voltage level VI2 to the ninth voltage level VI3. The twelfth voltage level VD6 may be higher than the eleventh voltage level VD5.

[0180] The decrease in voltage of the third node N3 caused by the decrease in voltage level of the second initialization power supply Vint2 and the increase in voltage of the third node N3 caused by the increase in voltage level of the data signal Vdata cancel each other out, thus stably maintaining the voltage stored in the storage capacitor Cst. Therefore, during a frame period FP, pixel PXij can constantly emit light with a brightness corresponding to the data signal Vdata supplied in the display scan period DSP of the corresponding frame period FP.

[0181] The voltage levels of the data signal Vdata that change during the bias scan periods BSP1 and BSP2 (e.g., eleventh voltage level VD5 and / or twelfth voltage level VD6) corresponding to the voltage levels of the second initialization power supply Vint2 that change during the bias scan periods BSP1 and BSP2 (e.g., eighth voltage level VI2 and / or ninth voltage level VI3) can be experimentally determined by considering circuit design and other factors (e.g., the arrangement of transistors). This allows the voltage stored in the storage capacitor Cst to be maintained constant through the coupling of the parasitic capacitor between the second transistor M2 and the first transistor M1.

[0182] When the number of offset scan periods is 3 or more, as in... Figure 6BAs described in the above, the display device can change the voltage level of the second initialization power Vint2 for each bias scan period as the length of one frame period FP is extended. In an example, when the number of bias scan periods is 3, the display device can supply the second initialization power Vint2 having an eighth voltage level (e.g., VI2) in a first bias scan period (e.g., BSP1) as shown in FIG. 11A. Figure 7B As described in the above, the display device can change the voltage level of the second initialization power Vint2 for each bias scan period as the length of one frame period FP is extended. In an example, when the number of bias scan periods is 3, the display device can supply the second initialization power Vint2 having an eighth voltage level (e.g., VI2) in a first bias scan period (e.g., BSP1) as shown in FIG. 11A. Figure 7B As described in the above, the display device can change the voltage level of the second initialization power Vint2 for each bias scan period as the length of one frame period FP is extended. In an example, when the number of bias scan periods is 3, the display device can supply the second initialization power Vint2 having an eighth voltage level (e.g., VI2) in a first bias scan period (e.g., BSP1) as shown in FIG. 11A. Figure 7B As described in the above, the display device can change the voltage level of the second initialization power Vint2 for each bias scan period as the length of one frame period FP is extended. In an example, when the number of bias scan periods is 3, the display device can supply the second initialization power Vint2 having an eighth voltage level (e.g., VI2) in a first bias scan period (e.g., BSP1) as shown in FIG. 11A. Figure 7B As described in the above, the display device can change the voltage level of the second initialization power Vint2 for each bias scan period as the length of one frame period FP is extended. In an example, when the number of bias scan periods is 3, the display device can supply the second initialization power Vint2 having an eighth voltage level (e.g., VI2) in a first bias scan period (e.g., BSP1) as shown in FIG. 11A.

[0183] Figure 8A and Figure 8B is a timing chart illustrating an example of the voltage of the first power, the voltage of the second initialization power, and the data signal supplied to the pixel as shown in FIG. 10. Figure 3 is a timing chart illustrating an example of the voltage of the first power, the voltage of the second initialization power, and the data signal supplied to the pixel as shown in FIG. 10. Figure 9A and Figure 9B is a timing chart illustrating an example of the voltage of the first power, the voltage of the second initialization power, and the data signal supplied to the pixel as shown in FIG. 10. Figure 3 is a timing chart illustrating an example of the voltage of the first power, the voltage of the second initialization power, and the data signal supplied to the pixel as shown in FIG. 10.

[0184] Referring to Figure 3 , Figure 5 and Figure 8A to Figure 9B , the voltage level of the first power VEH and the voltage level of the second initialization power Vint2 can be changed in one frame period FP.

[0185] For example, as shown in Figure 8A and Figure 9A , the first power VEH can have first voltage levels VE4 and VE7 in the display scan period DSP and second voltage levels VE5 and VE8 higher than the first voltage levels VE4 and VE7 in at least one bias scan period BSP1 and BSP2. Also, the second initialization power Vint2 can have seventh voltage levels VI4 and VI7 in the display scan period DSP and eighth voltage levels VI5 and VI8 lower than the seventh voltage levels VI4 and VI7 in at least one bias scan period BSP1 and BSP2.

[0186] In another example, as shown in Figure 8B and Figure 9BAs shown in FIG. 6, the first power source VEH can have first voltage levels VE4 and VE7 in the display scanning period DSP, second voltage levels VE5 and VE8 higher than the first voltage levels VE4 and VE7 in the first bias scanning period BSP1, and third voltage levels VE6 and VE9 higher than the second voltage levels VE5 and VE8 in the second bias scanning period BSP2. In addition, the second initialization power source Vint2 can have seventh voltage levels VI4 and VI7 in the display scanning period DSP, eighth voltage levels VI5 and VI8 lower than the seventh voltage levels VI4 and VI7 in the first bias scanning period BSP1, and ninth voltage levels VI6 and VI9 lower than the eighth voltage levels VI5 and VI8 in the second bias scanning period BSP2.

[0187] As described with reference to Figure 6A to Figure 7B , by changing the voltage level of the first power source VEH and / or the voltage level of the second initialization power source Vint2, it is possible to more effectively prevent (i.e., eliminate) fluctuations in image brightness due to the influence of the bias state of the first transistor M1.

[0188] This will be described in detail with reference to Figure 3 and Figure 8A When the voltage level of the first power source VEH increases from the first voltage level VE4 to the second voltage level VE5 in the bias scanning periods BSP1 and BSP2, the voltage applied to the gate electrode (i.e., the third node N3) of the first transistor M1 can increase due to the influence of the parasitic capacitor between the first node N1 and the third node N3 (i.e., the parasitic capacitor between the source electrode and the gate electrode of the first transistor M1). In addition, since the voltage level of the second initialization power source Vint2 decreases from the seventh voltage level VI4 to the eighth voltage level VI5 in the bias scanning periods BSP1 and BSP2, the voltage applied to the gate electrode (i.e., the third node N3) of the first transistor M1 can decrease due to the influence of the parasitic capacitor between the fourth node N4 and the third node N3. Accordingly, in the embodiments of the present disclosure, the increase in the voltage of the third node N3 due to the increase in the voltage level of the first power source VEH and the decrease in the voltage of the third node N3 due to the decrease in the voltage level of the second initialization power source Vint2 cancel each other out, making it possible to stably maintain the voltage of the third node N3. Therefore, in the display device according to the embodiments of the present disclosure, during one frame period FP, even when the voltage level of the data signal Vdata does not change, the pixel PXij can constantly emit light having a brightness corresponding to the data signal Vdata supplied in the display scanning period DSP of the corresponding frame period FP.

[0189] However, the present disclosure is not limited thereto. As described with reference to Figure 6A to Figure 7BIn the display device according to an embodiment of the present disclosure, the voltage level of the data signal Vdata can be changed during the bias scan periods BSP1 and BSP2 to effectively prevent the brightness from fluctuating due to changes in the hysteresis characteristics of the first transistor M1 caused by changing the voltage level of the first power supply VEH and the voltage level of the second initialization power supply Vint2, and to prevent the voltage of the third node N3 from fluctuating due to the operation of changing the voltage level of the first power supply VEH and the voltage level of the second initialization power supply Vint2.

[0190] For example, such as Figure 9A As shown, the data signal Vdata may have a fourth voltage level VD7 during the display scan period DSP, and a fifth voltage level VD8 that is higher than the fourth voltage level VD7 during at least one bias scan period BSP1 and BSP2. In another example, as Figure 9B As shown, the data signal Vdata can have a fourth voltage level VD7 during the display scan period DSP, a fifth voltage level VD8 that is higher than the fourth voltage level VD7 during the first bias scan period BSP1, and a sixth voltage level VD9 that is higher than the fifth voltage level VD8 during the second bias scan period BSP2. Therefore, it is possible to more effectively prevent (i.e., eliminate) brightness variations caused by voltage fluctuations at the third node N3.

[0191] Figure 10 This is a graph showing an example of the brightness [unit: nit] of an image displayed by a display device according to related technologies. Figure 11 This is a graph illustrating an example of the brightness of an image displayed by a display device according to an embodiment of the present disclosure.

[0192] Reference Figure 10 and Figure 11 , as reference Figure 3 and Figure 6A to Figure 9B In the display device according to the related technology, as the display period extends within a frame period FP, that is, as the display scan period DSP approaches the offset scan period BSP (see...), Figure 10 The brightness may vary due to changes in the hysteresis characteristics of the first transistor T1 (in...). Figure 10 The brightness changes (e.g., increases) due to the hysteresis of the first transistor T1. On the other hand, in the display device according to an embodiment of this disclosure, the voltage level of the first power supply VEH and / or the voltage level of the second initialization power supply Vint2 changes within a frame period FP, effectively preventing brightness fluctuations due to changes in the hysteresis characteristics of the first transistor T1. Therefore, brightness can be maintained constant throughout a frame period FP (see [reference]). Figure 11 ).

[0193] Figure 12 is a timing chart illustrating another example of signals supplied to the pixel shown in Figure 3 Figure 13 is a timing chart illustrating another example of signals supplied to the pixel shown in Figure 3

[0194] Except for the widths of some of the scan signals and the supply timing being different, Figure 12 and Figure 13 the timing chart shown in Figure 4 is the same as or similar to the timing chart shown in Figure 4 Therefore, components that are the same as or correspond to those in the timing chart shown in

[0195] Referring to Figure 3 , Figure 12 and Figure 13 , the non-emission period NEP of the display scan period can include a first period P1 to a fifth period P5.

[0196] In an embodiment, as shown in Figure 12 , the second period P2 and the third period P3 can partially overlap each other. That is, in a state where the seventh transistor M7 is turned on in response to the third scan signal GIi, the third transistor M3 can be turned on in response to the second scan signal GCi. Since the voltage of the first initialization power Vint1 has been supplied to the third node N3, and the first transistor M1 has been turned on biased, the characteristics of the first transistor M1 according to the signal supply shown in Figure 12 may be similar to the characteristics of the first transistor M1 according to the driving of the third period P3 shown in Figure 4 .

[0197] In an embodiment, as shown in Figure 13 , the supply of the first scan signal GBi can be suspended after the supply of the second scan signal GCi is suspended in the first period P1. In the first period P1, the fourth transistor M4 can be turned on after the third transistor M3 is turned on, and turned off after the third transistor M3 is turned off. Since a voltage similar to the voltage of the first power VEH is supplied to the first node N1, the characteristics of the first transistor M1 in the first period P1 shown in Figure 13 may be similar to the characteristics of the first transistor M1 in the first period P1 shown in Figure 4 .

[0198] As described above, some of the scan signals can be output with a predetermined margin depending on the waveform of the clock signal supplied to the scan driver (200) shown in Figure 1 , the output characteristics of the circuit included in the scan driver (200) shown in Figure 1 , and the like.​​

[0199] Figure 14 is a circuit diagram showing another example of a pixel included in the display device shown in Figure 1

[0200] In addition to the fourth transistor M4, Figure 14 the configuration and operation of the pixel PX'ij shown in FIG. 17 are the same as those of the pixel PXij described with reference to Figure 3 FIG. 16. Therefore, the same or corresponding components as those of the pixel PXij described with reference to Figure 3 FIG. 16 are designated by the same reference numerals, and a repetitive description thereof will be omitted.

[0201] With reference to Figure 14 , the pixel PX'ij can include the light emitting element LD, the first to eighth transistors M1 to M8, and the storage capacitor Cst.

[0202] In an embodiment, one electrode of the fourth transistor M4 can be connected to the second node N2, and the other electrode of the fourth transistor M4 can be connected to the first power supply VEH. The fourth transistor M4 can supply the voltage of the first power supply VEH to the second node N2 in response to the first scan signal supplied from the first scan line S1i. As described above, the voltage for on-bias can be supplied to any one of the source electrode and the drain electrode of the first transistor M1. For example, Figure 3 the pixel PXij shown in FIG. 16 supplies the voltage for on-bias to the source electrode of the first transistor M1, and Figure 14 the pixel PX'ij shown in FIG. 17 supplies the voltage for on-bias to the drain electrode of the first transistor M1.

[0203] According to the present disclosure, a voltage for supplying a bias voltage to a first power supply of a driving transistor and a voltage for supplying an initialization voltage to a second initialization power supply of a light emitting element can be applied to a pixel. The voltage level of the first power supply and / or the voltage level of the second initialization power supply can be changed during one frame period. Therefore, it is possible to effectively prevent (i.e., eliminate) display quality deterioration due to a change in a hysteresis characteristic of the driving transistor.

[0204] Further, according to the present disclosure, when the voltage level of the first power supply and / or the voltage level of the second initialization power supply is changed, a data signal having a voltage level that is changed during one frame period can be applied to the pixel. Therefore, fluctuation in the voltage stored in the storage capacitor is effectively prevented, and thus it is possible to constantly maintain the brightness of a display image.

[0205] ​Exemplary embodiments have been disclosed herein and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, unless otherwise specifically indicated. In some instances, as will be apparent to those of ordinary skill in the art, features, characteristics, and / or elements described in connection with a particular embodiment can be used singly or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Accordingly, one of ordinary skill in the art will recognize that the spirit and scope of the present disclosure are not limited to the specific illustrative embodiments described herein.

Claims

1. A pixel, comprising: Light-emitting elements; A first transistor is connected between a first node and a second node, and the driving current supplied to the light-emitting element is controlled according to the voltage of a third node connected to the gate electrode of the first transistor. The second transistor is connected between the data line and the first node and is turned on in response to the fourth scan signal; A third transistor is connected between the second node and the third node, and is turned on in response to a second scan signal; A fourth transistor, which is turned on in response to a first scan signal to apply the voltage of a first power supply to the first transistor; A fifth transistor is connected between the drive power supply and the first node and is turned off in response to a transmit control signal; A sixth transistor is connected between the second node and the first electrode of the light-emitting element, and is turned off in response to the emission control signal; as well as A seventh transistor, connected between the third node and the second power supply, and turned on in response to a third scan signal. Wherein, the voltage level of the first power source changes within one frame period. The frame time period includes: a display scan time period and at least one offset scan time period. The first power supply has a first voltage level during the display scan period and a second voltage level different from the first voltage level during the at least one bias scan period, the second voltage level being higher than the first voltage level.

2. The pixel according to claim 1, wherein, During the display scan period, the fourth scan signal is supplied to the second transistor such that the data signal supplied through the data line is written to the first node, and the first scan signal is supplied to the fourth transistor. as well as During the at least one bias scan period, the fourth scan signal is not supplied to the second transistor, and the first scan signal is supplied to the fourth transistor.

3. The pixel according to claim 2, wherein, The at least one bias scan period includes a first bias scan period and a second bias scan period following the first bias scan period, and The first power supply has a first voltage level during the display scanning period, a second voltage level different from the first voltage level during the first bias scanning period, and a third voltage level different from each of the first and second voltage levels during the second bias scanning period.

4. The pixel according to claim 2, wherein, The data signal supplied through the data line has a fourth voltage level during the display scan period and a fifth voltage level different from the fourth voltage level during the at least one bias scan period.

5. The pixel according to claim 3, wherein, The data signal supplied via the data line has a fourth voltage level during the display scan period, a fifth voltage level different from the fourth voltage level during the first bias scan period, and a sixth voltage level different from each of the fourth and fifth voltage levels during the second bias scan period.

6. The pixel of claim 2 further comprises an eighth transistor, the eighth transistor being connected between the first electrode of the light-emitting element and the third power supply, and being turned on in response to the first scan signal. in, The third power supply has a seventh voltage level during the display scan period and an eighth voltage level different from the seventh voltage level during the at least one bias scan period.

7. The pixel of claim 3 further comprises an eighth transistor, the eighth transistor being connected between the first electrode of the light-emitting element and the third power supply, and being turned on in response to the first scan signal. in, The third power supply has a seventh voltage level during the display scanning period, an eighth voltage level different from the seventh voltage level during the first bias scanning period, and a ninth voltage level different from each of the seventh and eighth voltage levels during the second bias scanning period.

8. A display device, comprising: A pixel, the pixel including a first transistor connected between a first node and a second node to generate a drive current, the pixel being connected to a first scan line, a second scan line, a third scan line, a fourth scan line, an emit control line, and a data line; A transmit driver that supplies transmit control signals to the transmit control line; A scan driver that, during the period when the transmit control signal is supplied, supplies a first scan signal to a fourth scan signal to the first scan line to the fourth scan line, respectively; A data driver that supplies data signals to the data line; A power supply that supplies the voltage of a drive power supply, the voltage of a first power supply, the voltage of a second power supply, and the voltage of a third power supply to the pixel; as well as A timing controller that controls the driving of the scan driver, the transmit driver, the data driver, and the power supply. Wherein, the first scan signal controls the timing of the voltage of the first power supply being supplied to the first node or the second node, and The power supply changes the voltage level of the first power supply within a frame period. The frame time period includes: a display scan time period and at least one offset scan time period. The first power supply has a first voltage level during the display scan period and a second voltage level different from the first voltage level during the at least one bias scan period, the second voltage level being higher than the first voltage level.

9. The display device according to claim 8, wherein, The pixels also include: Light-emitting elements; The second transistor is connected between the data line and the first node and is turned on in response to the fourth scan signal; A third transistor is connected between the second node and the third node and is turned on in response to the second scan signal, the third node corresponding to the gate electrode of the first transistor; A fourth transistor, which is turned on in response to the first scan signal to apply the voltage of the first power supply to the first transistor; A fifth transistor, which is connected between the drive power supply and the first node, and is turned off in response to the transmit control signal; A sixth transistor, connected between the second node and the first electrode of the light-emitting element, and turned off in response to the emission control signal; and A seventh transistor is connected between the third node and the second power supply and is turned on in response to the third scan signal.

Images