Semiconductor device, method of manufacturing the same, and electronic device

Abstract

The application discloses a semiconductor device, a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors, and aims to solve the undercut problem at the junction of a partition region and a peripheral region. The semiconductor device comprises a substrate, a first transistor and a second transistor formed on the substrate respectively, the first transistor is located in a unit region, and the second transistor is located in a peripheral region; a buffer layer is formed on the first transistor, and the buffer layer covers the unit region and the partition region; a gate stack of the second transistor covers the position of the buffer layer in the partition region and the peripheral region; and a bit line electrically connected with an active region of the first transistor is formed on the buffer layer. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device. The semiconductor device provided by the application is used for the electronic device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, its manufacturing method, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. DRAM has a simple structure; each bit of data requires only one capacitor and one transistor for processing. Furthermore, DRAM has high density and high capacity per unit volume, resulting in lower cost.

[0003] As semiconductor memory devices become highly integrated, the layer stacking structure of the cell region, peripheral region, and the partition region located between the cell region and the peripheral region differs during DRAM manufacturing. Undercutting occurs at the boundary between the partition region and the peripheral region, leading to problems such as short circuits in semiconductor devices. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device, a method for manufacturing the same, and an electronic device, for avoiding undercutting at the boundary between the partition region and the peripheral region.

[0005] To achieve the above objectives, the present invention provides a semiconductor device. The semiconductor device includes:

[0006] The base has a unit region, a peripheral region, and a partition region located between the unit region and the peripheral region;

[0007] A first transistor and a second transistor are respectively formed on a substrate, with the first transistor located in the cell region and the second transistor located in the peripheral region;

[0008] A buffer layer is formed on the first transistor, covering the cell region and the partition region; the gate stack of the second transistor covers the location of the buffer layer in the partition region and the peripheral region.

[0009] And a bit line electrically connected to the active region of the first transistor, the bit line being formed on the buffer layer.

[0010] Compared with existing technologies, the semiconductor device provided by this invention involves forming a buffer layer on a first transistor, where the buffer layer covers both the cell region and the isolation region. The gate stack of the second transistor covers the location of the buffer layer in the isolation region and its peripheral region. A bit line is formed on the buffer layer and electrically connected to the active region of the first transistor. This completely avoids undercutting at the boundary between the isolation region and the peripheral region, thereby preventing short circuits in the semiconductor device and improving its performance.

[0011] The present invention also provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes:

[0012] A substrate is provided, the substrate having a unit region, a peripheral region, and a partition region located between the unit region and the peripheral region;

[0013] A first transistor, a second transistor, and a buffer layer are formed on a substrate; the first transistor is located in a cell region, and the second transistor is located in a peripheral region; the buffer layer is formed on the first transistor, covering both the cell region and the partition region; the gate stack of the second transistor covers the location of the buffer layer in the partition region and the peripheral region.

[0014] Bit lines are formed on the buffer layer and electrically connected to the active region of the first transistor.

[0015] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided by the present invention are the same as those of the semiconductor device described in the above technical solutions, and will not be repeated here.

[0016] The present invention also provides an electronic device, comprising the semiconductor device described above; and / or,

[0017] Electronic devices are communication devices or terminal devices.

[0018] Compared with the prior art, the beneficial effects of the electronic device provided by the present invention are the same as those of the semiconductor device described in the above technical solution, and will not be repeated here. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0020] Figure 1 A layout diagram of a semiconductor device provided in an embodiment of the present invention is shown;

[0021] Figure 2 A schematic diagram of a semiconductor device structure in the prior art is shown;

[0022] Figure 3 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention is shown;

[0023] Figures 4 to 13 This illustrates the various stages along which the semiconductor device is manufactured in embodiments of the present invention. Figure 1 A schematic diagram of a cross-section embodiment of line A-A' in the diagram;

[0024] Figure 14A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0025] Figure label:

[0026] Substrate 100, buffer layer 102, gate stack 103, gate electrode 104, bit line metal layer 106, cell region 108, peripheral region 110, isolation region 112, contact hole 114, bit line node contact 116, gate dielectric layer 118, cap layer 120, first buffer layer 124, second buffer layer 126, mask 128, buffer film 130, gate conductor layer 132, second mask 134. Detailed Implementation

[0027] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0028] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0029] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0031] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0032] Dynamic Random Access Memory (DRAM) is a type of volatile memory that consists of a memory region composed of multiple cell regions and a peripheral region surrounding the cell regions. Each cell region contains a transistor electrically connected to a capacitor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. Each cell region can be located and its data access controlled using word lines (WL) and bit lines (BL) that electrically connect the memory region to each cell region.

[0033] Analysis of the aforementioned semiconductor devices reveals that during DRAM manufacturing, the cell region 108, the peripheral region 110, and the partition region 112 located between the cell region 108 and the peripheral region 110 (in the prior art, the partition region 112 is generally included within the cell region 108; for ease of description later, the partition region 112 and the cell region 108 will be described separately, as follows) Figure 1 The layer stacking structure (as shown) is different, which can easily lead to undercutting problems when wet etching the partition region 112 and the peripheral region 110 (e.g. Figure 2 (as indicated by position I in the diagram), causing a short circuit in the semiconductor device.

[0034] To address the aforementioned problems, embodiments of the present invention provide a semiconductor device, a method for manufacturing the same, and an electronic device. By utilizing a buffer layer formed on a first transistor to cover the gate stack of a second transistor in the partition region and the peripheral region, undercutting at the boundary between the partition region and the peripheral region is avoided, thereby preventing short circuits in the semiconductor device and ensuring its performance.

[0035] For ease of description, the following only describes the differences between the semiconductor devices provided in the embodiments of the present invention and those in the prior art. Other structures not described can be referred to the descriptions in the prior art. Of course, those skilled in the art can also improve other existing semiconductor devices based on the following descriptions of the embodiments of the present invention.

[0036] In response to the above problems, Figure 1 This diagram shows a layout of a semiconductor device provided in an embodiment of the present invention. Figures 3 to 13 It shows along Figure 1 The cross-sectional view taken by line A-A' in the diagram. (See diagram below.) Figure 3 As shown, the semiconductor device includes: a substrate 100, a first transistor, a second transistor, a buffer layer 102, a gate stack 103 of the second transistor, and bit lines.

[0037] like Figure 3 As shown, the substrate 100 has a unit region 108, a peripheral region 110, and a partition region 112 located between the unit region 108 and the peripheral region 110. The substrate 100 can be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate formed by epitaxial growth. The following description uses a silicon substrate as an example.

[0038] The first transistor and the second transistor are respectively formed on the substrate 100. The first transistor is located in the cell region 108, and the second transistor is located in the peripheral region 110. In practical applications, the number of the first transistor and the second transistor can be one or more. When there are multiple first transistors, the multiple first transistors can be arranged in an array in the cell region 108. When there are multiple second transistors, the multiple second transistors are arranged around the first transistor in the peripheral region 110.

[0039] The first transistor within the cell region can be any common type of transistor, such as a bottom-gate transistor, a top-gate transistor, or, of course, a buried channel array transistor (BCAT), but it is not limited to these. The second transistor in the peripheral region can be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0040] like Figure 3As shown, the buffer layer 102 is formed on the first transistor. The buffer layer 102 covers the cell region 108 and the partition region 112. At this time, the substrate 100 of the peripheral region 110 is exposed, which facilitates subsequent deposition, photolithography and etching processes in the peripheral region 110.

[0041] like Figure 3 As shown, bit lines are formed on buffer layer 102 and are electrically connected to the active region of the first transistor.

[0042] like Figure 2 As shown, in practical applications, if the first buffer layer 124 is located between the isolation region 112 and the peripheral region 110 during direct etching (such as wet etching, dry etching, but not limited to these), the via formed by the etching is prone to undercutting (e.g., Figure 2 The above problem can be caused by a short circuit in the semiconductor device (as indicated by the I position in the diagram). When the bit line metal layer 106 is formed on the first buffer layer 124, the above problem can be avoided, thereby further improving the performance of the semiconductor device.

[0043] Therefore, the semiconductor device provided by the embodiments of the present invention can avoid the problem of short circuit in semiconductor devices caused by undercutting in the prior art, which affects the performance of semiconductor devices.

[0044] As one possible implementation, such as Figure 3 and Figure 8 As shown, the buffer layer 102 has a contact hole 114, and the bit line is electrically connected to the active region of the first transistor through a bit line node contact portion 116 subsequently formed in the contact hole 114. It should be understood that the number of contact holes 114 and bit lines can be one or more, depending on the actual situation. One bit line is connected to one first transistor.

[0045] like Figure 3 and Figure 8 As shown, in practical applications, a bit line node contact 116 can be formed within the contact hole 114 in the buffer layer 102, allowing the bit line formed on the buffer layer 102 to be electrically connected to the active region of the first transistor through the bit line node contact 116. Under the control of the word line, the first transistor can be turned on and off. In the on state, it is electrically connected to the gate. Data transmission can be achieved through the bit line and the word line.

[0046] like Figure 3 As shown, as one possible implementation, the buffer layer 102 includes at least one first buffer layer 124 and at least one second buffer layer 126.

[0047] like Figure 3As shown, at least one first buffer layer 124 is formed on the first transistor. The at least one first buffer layer 124 covers the cell region 108 and the partition region 112, exposing the peripheral region 110. At least one second buffer layer 126 is formed on the at least one first buffer layer 124. The gate stack 103 of the second transistor covers at least one second buffer layer 126. When the buffer layer 102 has a contact hole ( Figure 14 (Not shown) When contact holes are formed in the first buffer layer 124 and the second buffer layer 126, the bit line can be electrically connected to the active region of the first transistor through the bit line node contact portion 116 formed in the contact hole.

[0048] The number of the first buffer layer 124 and the second buffer layer 126 can be one or more, depending on the actual situation. When there are multiple first buffer layers 124, the first buffer layer 124 is formed on the first transistor, and the first buffer layer 124 covers the cell region 108 and the isolation region 112. When there are multiple second buffer layers 126, the second buffer layer 126 is formed on the multiple first buffer layers 124.

[0049] In an alternative embodiment, to reduce fabrication complexity, at least one of the aforementioned second buffer layers 126 is formed on at least one first buffer layer 124. The gate stack 103 of the second transistor covers at least one second buffer layer 126. In this case, the cell region 108 is open, and the bit line can be formed only on at least one first buffer layer 124, or it can be formed on both at least one first buffer layer 124 and at least one second buffer layer 126. This reduces the etching of the second buffer layer 126, saving time and materials.

[0050] In another alternative approach, such as Figure 3 As shown, the area of ​​at least one second buffer layer 126 is smaller than the area of ​​at least one first buffer layer 124. In this case, the bit line can be formed only on at least one first buffer layer 124, and the gate stack 103 of the second transistor completely covers at least one second buffer layer 126. Alternatively, the gate stack 103 of the second transistor can also cover a partial area of ​​at least one second buffer layer 126. At least one of the aforementioned second buffer layers 126 is formed on at least one first buffer layer 124. In this case, the cell region 108 is open, and the bit line can be formed only on at least one first buffer layer 124, or it can be formed on at least one first buffer layer 124 and at least one second buffer layer 126. This reduces the etching of the second buffer layer 126, saves time and materials, and lowers the process complexity.

[0051] In another alternative, such as Figure 3As shown, at least one of the aforementioned first buffer layers 124 includes a mask 128 and a buffer film 130. The mask 128 is formed on the first transistor. The buffer film 130 is formed on the mask 128. The mask 128 is an oxide mask. The buffer film 130 is a silicon nitride buffer film. At least one second buffer layer 126 includes an oxide buffer film.

[0052] For example, the mask 128 formed on the first transistor is a hard mask. In the embodiments of the present invention, the mask 128 used is an oxide mask. Of course, the material of the mask 128 can also be selected according to the actual situation, such as silicon nitride, silicon carbide, etc., but is not limited to this. The buffer film 130 is a buffer film such as silicon nitride, silicon carbide, etc. Of course, the material of the buffer film 130 can also be selected according to the actual situation, such as a buffer film made of silicon nitride, silicon carbide, etc. The second buffer layer 126 is an oxide buffer film. Of course, the material of the second buffer layer 126 can also be selected according to the actual situation, such as a buffer film made of silicon nitride, silicon carbide, etc.

[0053] like Figure 3 As shown, in one possible implementation, the semiconductor device further includes a partition structure located in the partition region 112. This partition structure is formed on the substrate 100. A buffer layer 102 covers the partition structure. The gate stack 103 of the second transistor covers a localized area of ​​the partition structure.

[0054] Since the buffer layer 102 covers the isolation structure, and the gate stack 103 of the second transistor covers a local area of ​​the isolation structure, a step difference is avoided at the boundary between the isolation region 112 and the peripheral region 110. This is beneficial for bit line formation without affecting subsequent operations.

[0055] Generally, the cell region 108 where the buried trench array transistor BCAT is located and the partition region 112 located between the cell region 108 and the peripheral region 110 are covered with an insulating film (Spin-on Dielectrics, abbreviated as SOD) between themselves and the substrate 100.

[0056] As one possible implementation, such as Figure 3 As shown, the gate stack 103 of the second transistor includes a gate dielectric layer 118 and a gate electrode 104 of the second transistor. The active region of the second transistor is formed on the surface of the substrate 100, and the gate dielectric layer 118 is formed on the active region of the second transistor. Both the active region and the gate dielectric layer 118 of the second transistor are located in the peripheral region 110. The gate electrode 104 of the second transistor is formed on the gate dielectric layer 118 of the second transistor. The gate electrode 104 of the second transistor is located in the buffer layer 102 at the isolation region 112 and in the peripheral region 110. This arrangement not only makes full use of space but also facilitates subsequent processing.

[0057] This invention also provides a method for manufacturing a semiconductor device. Figure 14 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Figure 14 As shown, the method for manufacturing this semiconductor device includes:

[0058] like Figure 3 As shown, firstly, a substrate 100 is provided. The substrate 100 has a unit region 108, a peripheral region 110, and a partition region 112 located between the unit region 108 and the peripheral region 110. As for the selection of the substrate 100, please refer to the previous text, and it will not be repeated here.

[0059] like Figure 3 As shown, a first transistor, a second transistor, and a buffer layer 102 are then formed on the substrate 100. The first transistor is located in the cell region 108, and the second transistor is located in the peripheral region 110. The buffer layer 102 is formed on the first transistor, covering the cell region 108 and the partition region 112. The gate stack 103 of the second transistor covers the location of the buffer layer 102 in the partition region 112 and the peripheral region 110.

[0060] like Figure 3 As shown, a bit line is then formed on the buffer layer 102. This bit line is electrically connected to the active region of the first transistor.

[0061] like Figure 3 As shown, a bit line metal layer 106 is deposited on the buffer layer 102 to form a bit line. Through contact holes ( Figure 3 The bit line node contact portion 116 (not shown in the figure) forms an electrical connection between the bit line and the active region of the first transistor.

[0062] Compared with the prior art, the semiconductor device manufacturing method provided in the embodiments of the present invention has the same beneficial effects as the semiconductor device provided in the above embodiments, and will not be repeated here.

[0063] As one possible implementation, such as Figure 4 As shown, forming a first transistor, a second transistor, and a buffer layer 102 on the substrate 100 includes:

[0064] like Figure 4 As shown, firstly, active regions of a first transistor and a second transistor are formed on the substrate 100, with the active region of the second transistor located in the peripheral region 110. The first transistor can be a BCAT transistor or similar. The second transistor can be a MOSFET or similar. An isolation structure is formed in the isolation region 112. The isolation structure is formed on the substrate 100.

[0065] Next, a buffer layer 102 is formed on the first transistor. The buffer layer 102 is formed on the partition structure.

[0066] like Figure 4 As shown, a mask 128 for a buried channel array transistor (BACT) is formed on the first transistor and the second transistor, wherein the mask 128 is an oxide mask. A cap layer 120 for the buried channel array transistor (BACT) is formed on the oxide mask, wherein the cap layer 120 is a silicon nitride cap layer. The aforementioned oxide mask and silicon nitride cap layer are located in the cell region 108, the partition region 112, and the peripheral region 110. It is understood that the materials of the mask 128 and the cap layer 120 can be other suitable materials.

[0067] like Figure 4 and Figure 5 As shown, the formed cap layer 120 is removed. In this embodiment of the invention, the cap layer 120 of the buried channel array transistor BACT is removed by sputter etching. It is understood that other practical methods can also be used to remove the cap layer 120.

[0068] Subsequently, silicon nitride is deposited on the oxide mask to form a silicon nitride buffer film. An oxide is then deposited on the silicon nitride buffer film to form an oxide buffer film. The silicon nitride or oxide buffer film can be formed using any of a variety of deposition techniques. For example, low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and other suitable deposition techniques can be used to form the silicon nitride or oxide buffer film.

[0069] In embodiments of the present invention, a silicon nitride buffer film or an oxide buffer film is formed by chemical vapor deposition. It is understood that other practically suitable methods can also be used to form the silicon nitride buffer film or the oxide buffer film.

[0070] like Figure 6 As shown, the buffer layer 102 located in the outer region 110 is graphically represented, exposing the active area of ​​the outer region 110. Figure 6 (Not shown in the image).

[0071] like Figure 6As shown, the buffer layer 102 located in the peripheral region 110 is etched, selectively removing portions of the mask 128, buffer film 130, and second buffer layer 126, namely the oxide mask, silicon nitride buffer film, and oxide buffer film. The above patterning process can employ dry etching or wet etching to etch the buffer layer 102 located in the peripheral region 110. For example, when using dry etching, plasma etching can be utilized. That is, plasma etching or wet etching can be used to selectively remove portions of the oxide mask, silicon nitride buffer film, and oxide buffer film to expose the peripheral region 110, facilitating subsequent deposition, photolithography, and etching processes in the surrounding area. It is understood that other practically suitable methods can also be used to remove portions of the oxide mask, silicon nitride buffer film, and oxide buffer film.

[0072] like Figures 7 to 11 As shown, a gate dielectric layer 118 and a gate electrode 104 of the second transistor are formed on the active region of the second transistor. The gate dielectric layer 118 of the second transistor is formed on the active region of the second transistor and is located in the peripheral region 110.

[0073] As one possible implementation, forming a stacked gate dielectric layer 118 and a gate electrode 104 of the second transistor on the active region of the second transistor includes:

[0074] like Figure 7 As shown, a gate dielectric layer 118 of the second transistor is formed on the active region of the second transistor.

[0075] For example, the active region of the second transistor is formed on the surface of the substrate 100. After the active region of the peripheral region 110 is exposed, an oxide layer 118 is deposited on the active region to form the gate dielectric layer 118. That is, an oxide layer 118 of the second transistor is deposited on the active region of the second transistor. The method of depositing the oxide can be referred to above and will not be repeated here. In the embodiments of the present invention, the oxide layer 118 of the second transistor is formed by atomic layer deposition.

[0076] It should be noted that the above-mentioned gate dielectric layer can be formed in various ways. How the gate dielectric layer is formed is not a key feature of the embodiments of this invention; therefore, it is only briefly described in this specification to enable those skilled in the art to easily implement the embodiments provided by this invention. Those skilled in the art can certainly conceive of other methods for manufacturing the gate dielectric layer.

[0077] like Figure 7As shown, a gate conductor layer 132 is formed on the gate dielectric layer 118 and the buffer layer 102 of the second transistor. The gate conductor layer 132 is located in the cell region 108, the isolation region 112 and the peripheral region 110.

[0078] Doped polysilicon is deposited as gate conductor layer 132 on the gate dielectric layer 118 and buffer layer 102 of the second transistor.

[0079] As one possible implementation, such as Figure 7 As shown, after forming the gate conductor layer 132 on the gate dielectric layer 118 and the buffer layer 102 of the second transistor, and before forming a contact hole through the gate conductor layer 132 and the buffer layer 102, the semiconductor device manufacturing method further includes:

[0080] like Figure 7 As shown, a second mask 134 is formed on the gate conductor layer 132. The second mask 134 is an oxide mask. The second mask 134 covers the cell region 108, the partition region 112, and the peripheral region 110.

[0081] For example, an oxide mask is deposited on the gate conductor layer 132. At this time, the gate conductor layer 132 and the oxide mask are located in the cell region 108, the isolation region 112, and the peripheral region 110. Of course, the materials constituting the gate conductor layer 132 and the second mask 134 can be set according to actual conditions. The method of depositing doped polysilicon and oxide can be referred to the previous text and will not be repeated here.

[0082] like Figure 8 As shown, a through contact hole 114 is formed in the gate conductor layer 132 and the buffer layer 102. The contact hole 114 is used to electrically connect the bit line to the active region of the first transistor.

[0083] For example, the second mask 134, the gate conductor layer 132 and the buffer layer 102 are etched to form a contact hole 114 that penetrates the second mask 134, the gate conductor layer 132 and the buffer layer 102, and the contact hole 114 is located in the cell region 108.

[0084] like Figure 9 As shown, the bit line node contact 116 can be formed in the contact hole 114. The bit line node contact 116 can be formed by forming doped polysilicon filling the contact hole 114 on the second mask 134, the gate conductor layer 132 and the buffer layer 102, and then performing a planarization process (e.g., CMP or etch-back) until the top surfaces of the second mask 134, the gate conductor layer 132 and the buffer layer 102 are exposed.

[0085] As one possible implementation, word lines are formed in the substrate and electrically connected to the gate of the first transistor.

[0086] Because contact holes 114 are formed in the buffer layer 102, the bit lines formed on the buffer layer 102 are electrically connected to the active region of the first transistor through the bit line node contact portion 116 formed by the contact holes 114. Under the control of the word lines, the first transistor can be turned on and off. In the on state, it is electrically connected to the gate. Data transmission can be realized through the bit lines and word lines.

[0087] like Figure 10 and Figure 11 As shown, the gate conductor layer 132 is processed to obtain the gate electrode 104 of the second transistor.

[0088] For example, the oxide mask (second mask 134) formed on the gate conductor layer 132 is removed, and a portion of the gate conductor layer 132 is etched to expose the cell region 108, at which point the gate electrode 104 of the second transistor is obtained.

[0089] like Figure 12 As shown, a portion of the oxide buffer film formed on the silicon nitride buffer film is removed, i.e., the second buffer layer 126 is etched, so that the second buffer layer 126 is formed in a local area of ​​the first buffer layer 124.

[0090] For example, the second buffer layer 126 can be etched using dry etching or wet etching, so that the second buffer layer 126 is formed in a local area of ​​the first buffer layer 124. In this case, the area of ​​the second buffer layer 126 is smaller than the area of ​​the first buffer layer 124. The gate stack 103 of the second transistor completely covers the second buffer layer 126.

[0091] like Figure 13 As shown, a bit line metal layer 106 is deposited on the bit line node contact 116, the buffer film 130, and the gate electrode 104 of the second transistor. The bit line metal layer 106 can subsequently be used to form bit lines.

[0092] This invention also provides an electronic device. The electronic device includes... Figure 3 The semiconductor device shown. The above electronic device can be a communication device or a terminal device.

[0093] As one possible implementation, the electronic device provided in this embodiment of the invention may include, for example, communication devices such as base stations and terminal devices such as mobile phones, tablets, and wearable devices, but is not limited thereto. Further, the electronic device includes smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks. It may also include computers, mobile phones, base stations, servers, etc., but is not limited thereto.

[0094] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0095] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: The substrate has a unit region, a peripheral region, and a partition region located between the unit region and the peripheral region; A first transistor and a second transistor are respectively formed on the substrate, wherein the first transistor is located in the cell region and the second transistor is located in the peripheral region; A buffer layer is formed on the first transistor, the buffer layer covering the cell region and the partition region; the gate stack of the second transistor covers the location of the buffer layer in the partition region and the peripheral region; And a bit line electrically connected to the active region of the first transistor, the bit line being formed on the buffer layer.

2. The semiconductor device according to claim 1, characterized in that, The buffer layer has a contact hole, and the bit line is electrically connected to the active region of the first transistor through the contact hole; The buffer layer includes at least one first buffer layer and at least one second buffer layer; the at least one first buffer layer is formed on the first transistor; the at least one second buffer layer is formed on the at least one first buffer layer; and the gate stack of the second transistor covers the at least one second buffer layer.

3. The semiconductor device according to claim 2, characterized in that, The area of ​​the at least one second buffer layer is smaller than the area of ​​the at least one first buffer layer.

4. The semiconductor device according to claim 2, characterized in that, The at least one first buffer layer includes a mask and a buffer film; the mask is formed on the first transistor; the buffer film is formed on the mask; The mask is an oxide mask; the buffer film is a silicon nitride buffer film; The at least one second buffer layer comprises an oxide buffer film.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor device further includes a partition structure located in the partition region; the partition structure is formed on the substrate; and / or, The gate stack of the second transistor includes a gate dielectric layer of the second transistor and a gate electrode of the second transistor; the gate dielectric layer of the second transistor is formed on the active region of the second transistor; both the active region of the second transistor and the gate dielectric layer of the second transistor are located in the peripheral region; the gate electrode of the second transistor is formed on the gate dielectric layer of the second transistor; the gate electrode of the second transistor is located at the position of the buffer layer in the isolation region and the peripheral region.

6. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate having a unit region, a peripheral region, and a partition region located between the unit region and the peripheral region; A first transistor, a second transistor, and a buffer layer are formed on the substrate; the first transistor is located in the cell region, and the second transistor is located in the peripheral region; the buffer layer is formed on the first transistor, and the buffer layer covers the cell region and the partition region; the gate stack of the second transistor covers the location of the buffer layer in the partition region and the peripheral region. Bit lines are formed on the buffer layer and are electrically connected to the active region of the first transistor.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The formation of the first transistor, the second transistor, and the buffer layer on the substrate includes: Active regions of a first transistor and a second transistor are formed on the substrate, with the active region of the second transistor located in the peripheral region; an isolation structure is formed in the isolation region, the isolation structure being formed on the substrate; A buffer layer is formed on the first transistor; A gate dielectric layer and a gate electrode of the second transistor are formed on the active region of the second transistor. The gate dielectric layer of the second transistor is formed above the active region of the second transistor and is located in the peripheral region.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The formation of the gate dielectric layer and the gate electrode of the second transistor on the active region of the second transistor includes: A gate dielectric layer of the second transistor is formed on the active region of the second transistor; A gate conductor layer is formed on the gate dielectric layer and the buffer layer of the second transistor; the gate conductor layer is located in the cell region, the isolation region and the peripheral region; A contact hole is formed through the gate conductor layer and the buffer layer; the contact hole is used to provide electrical connection between the bit line and the active region of the first transistor; The gate conductor layer is processed to obtain the gate electrode of the second transistor.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, After forming a gate conductor layer on the gate dielectric layer and the buffer layer of the second transistor, and before forming a contact hole through the gate conductor layer and the buffer layer, the method for manufacturing the semiconductor device further includes: A second mask is formed on the gate conductor layer; the second mask is an oxide mask; the second mask covers the cell region, the partition region and the peripheral region.

10. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 5; and / or, The electronic device is a communication device or a terminal device.

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