Layout architecture of discrete-gate trench MOSFETs

Abstract

The present application discloses a layout architecture for a shielded-gate trench MOSFET, comprising: a highly doped substrate of a first polarity and an epitaxial layer of the first polarity grown thereon; a plurality of strip-shaped trenches formed in the epitaxial layer, the plurality of strip-shaped trenches comprising: a plurality of parallel active gate trenches located in an active region; a terminal trench surrounding the periphery of the active region and forming spaced connections with some of the active gate trenches; and a trench guard ring disposed outside the terminal trench. The terminal trench and the outer edges of the unconnected active gate trenches form a mesa of equal width.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and more particularly to the layout architecture of discrete-gate trench MOSFETs. Background Art

[0002] For Gate Shielded Trench MOSFET (also known as discrete gate trench MOSFET, SGT MOSFET), the key to the successful design and fabrication of SGT MOSFET lies in the terminal region design, because the drain-to-source breakdown voltage (BVdss) mainly drops in the mesa region (MESA Region) of the SGT MOSFET.

[0003] In current designs, the trench ends of the active area are disconnected from the trenches in the termination area. To maintain charge balance in the region between the active and termination trenches, a gap must be created. This gap is a key parameter for the SGT MOSFET's breakdown voltage (BVdss), and the spacing is determined by the epitaxial layer (Epi) doping concentration. Any change in the epitaxial layer (Epi) doping concentration will cause a change in the termination area's breakdown voltage (BVdss), making the SGT MOSFET's breakdown voltage (BVdss) unstable. In principle, during the fabrication of a fully charge-balanced SGT MOSFET, the gap distance between the termination area trenches will affect the charge distribution between the active area trench ends and the termination area trenches to a certain extent. This gap distance is generally smaller than the gap distance between the parallel termination area trenches and the active area trenches. However, achieving precise trench spacing is extremely difficult in the SGT MOSFET manufacturing process, especially in the design of the terminal trench corners. It is difficult to achieve the required clearance. This can lead to unstable device functionality and a narrowing or reduction in the applicable range of the breakdown voltage (BVdss). Coupled with the problem of doping concentration variations, the manufactured SGT MOSFET is likely to fail to meet the breakdown voltage (BVdss) range required by the designer, resulting in device malfunction or unusable in the required circuit. Summary of the Invention

[0004] The present application discloses a layout architecture with discrete gate trench MOSFET, comprising: a highly doped substrate comprising a first polarity; an epitaxial layer comprising the first polarity, grown on the highly doped substrate; a plurality of strip trenches formed in the epitaxial layer, the plurality of strip trenches comprising: a plurality of active gate trenches located in an active area and arranged in parallel, the active gate trenches being provided with gate polysilicon and shielding polysilicon; a terminal trench surrounding the periphery of the active area and arranged in a terminal area, the terminal trench being provided with polysilicon, the terminal trench being connected to some of the trenches of the plurality of active gate trenches at intervals in a direction not parallel to the plurality of active gate trenches, and forming the same mesa width as the outer edges of some of the trenches not connected to the plurality of active gate trenches; a plurality of trench guard rings surrounding the periphery of the active area and arranged in the terminal area, the trenches of the plurality of trench guard rings being provided with polysilicon.

[0005] Optionally, the terminal trench is connected to part of the plurality of active gate trenches, and its extended shape is a corrugated shape.

[0006] Optionally, one or more of the plurality of trench protection rings have a shape identical or similar to that of the terminal trench.

[0007] Optionally, a first mesa width is formed between one of the plurality of trench protection rings adjacent to the terminal trench and the terminal trench, and the first mesa width is the same as or different from the mesa width.

[0008] Optionally, a second mesa width is formed between the plurality of trench guard rings, and the second mesa width is the same as or different from the mesa width.

[0009] Optionally, the layout architecture includes an oxide capping layer above the plurality of strip-shaped trenches.

[0010] Optionally, the layout architecture includes a source metal on the oxide capping layer and through an etched trench in the oxide capping layer.

[0011] Optionally, the source metal is disposed in the active area and the terminal area.

[0012] Optionally, the source metal is disposed above the active gate trench and the terminal trench, and does not cover above the multiple trench protection rings so that the multiple trench protection rings form a floating ring structure.

[0013] Optionally, the trench bottoms of the plurality of trench guard rings are all implanted with a trench bottom implant having a second polarity.

[0014] Optionally, the source metal is electrically connected to the polysilicon layer of the floating ring structure.

[0015] Optionally, the highly doped substrate and the epitaxial layer are N-type doped; the source region is N-type doped; the trench bottom implant is P-type doped; the gate polysilicon and the shielding polysilicon are respectively formed by heavily arsenic-doped polysilicon and / or heavily phosphorus-doped polysilicon.

[0016] Optionally, a channel-interrupting trench is provided at the periphery of the terminal region, and the plurality of trench protection rings are located between the active region and the channel-interrupting trench.

[0017] Optionally, the polysilicon in the terminal trench and the gate polysilicon of the multiple active gate trenches connected to the terminal trench are electrically connected.

[0018] Optionally, the end of the active gate trench extends to the terminal region to connect to the trench of the terminal trench, and the end of part of the active gate trench is connected to the terminal trench to uniformly distribute the charge in the terminal region and eliminate the charge imbalance in the terminal region.

[0019] Optionally, the discrete gate trench MOSFET is fully charge balanced, the trench protection ring provides leakage reduction of the saturation drain current (Idss) for the discrete shielded gate unit, and during the breakdown of the reverse biased drain to source breakdown voltage (BVdss) of the discrete shielded gate unit, there is still some voltage drop at the bottom of the trench of the trench protection ring.

[0020] Optionally, the transistor structure formed by the discrete shielded gate unit is a fully charge-balanced discrete gate trench metal oxide semiconductor field effect transistor, and its drain-source breakdown voltage range is between 60V and 300V.

[0021] The present application is applicable to a fully charge-balanced SGT MOSFET, in which a corrugated trench is designed in the terminal region. This corrugated design allows the terminal trench and the portion of the trench not connected to the multiple active gate trenches (i.e., disconnected and unconnected) to maintain the same mesa width (MESA Width) at the corner, thereby maintaining charge balance between the active region and the terminal region, avoiding instability in the breakdown voltage (BVdss) of the SGT MOSFET, and reducing the breakdown voltage (BVdss) falling on the bottom of the trench in the terminal region. Furthermore, by connecting the end of the active gate trench to the terminal trench in the terminal region, the charge distribution in the terminal region is uniformed, effectively eliminating charge imbalance in the terminal region.

[0022] Certain embodiments of the present application have other steps or elements in addition to or instead of those mentioned above. These steps or elements will become apparent to those skilled in the art by reading the following detailed description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a top plan view of a shielded gate trench MOSFET in an embodiment of the present application.

[0024] Figure 2 It is for Figure 1 An exemplary cross section of an SGT structure in the active region.

[0025] Figure 3 and Figure 4 This is to show the alternative embodiment of the present application Figure 1 Example of a top plan view of portion A.

[0026] Figure 5 It means Figure 4 An exemplary cross section of a shielded gate trench MOSFET taken along section line AA'.

[0027] Figure 6 for Figure 5 Figure 2 shows an alternative example of a trench guard ring structure.

[0028] Figure 7 for Figure 6 Figure 2 shows an alternative example of a trench guard ring structure.

[0029] Figure 8 and Figure 9 for Figure 6 and Figure 7 Figure 2 shows an alternative example of a trench guard ring structure.

[0030] Figure 10 Schematic diagram of the boundary of the shielded gate trench MOSFET of this application. DETAILED DESCRIPTION

[0031] The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the present application. It is understood that other embodiments will be apparent based on this disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present application.

[0032] In the following description, numerous specific details are provided to provide a thorough understanding of the present application. However, it will be apparent that the present application can be practiced without these specific details. To avoid obscuring the present application, some well-known circuits, system configurations, and process steps are not disclosed in detail. Similarly, the figures showing embodiments of the system are semi-diagrammatic and not drawn to scale, and in particular, some of the dimensions are exaggerated in the drawn figures for clarity of presentation. Where multiple embodiments having some common features are disclosed and described for clarity and ease of illustration, description, and understanding, similar and similar features will generally be described with similar reference numerals.

[0033] For purposes of this description, the term "horizontal," as used herein, is defined as a plane parallel to the plane of the active surface of the top of the integrated circuit die, regardless of its orientation. The term "vertical" refers to a direction perpendicular to the horizontal just defined. Terms such as "on," "above," "below," "bottom," "top," "side" (as in "sidewall"), "higher," "lower," "upper," "over," and "below" are defined relative to the horizontal plane.

[0034] As used herein, the term "on" means and refers to direct contact between elements without intervening elements. As used herein, the term "processing" includes the deposition, patterning, exposure, development, etching, cleaning and / or removal or trimming of materials required to form the described structure. As used herein, the term "system" means and refers to the method and apparatus of the present application according to the context in which the term is used. As used herein, the term "grown / grows / growing" refers to additional thickness added by means of chemical vapor deposition (CVD) or other deposition processes. The term "center" or "centered" refers to positioning an element so that it is equidistant from the edge of another element.

[0035] It should also be understood that a term or element in the embodiments may be described as a singular instance. It should be understood that the use of the singular is not limited to the singular, but rather can apply to multiple instances of any particular term or element in the application. Multiple instances can be the same or similar, or they can be different.

[0036] It should also be understood that the first and second polarities described below are opposite polarities: when the first polarity is N, the second polarity is P, and when the second polarity is P, the first polarity is N. Furthermore, in the examples described below, when the N polarity is switched to P, the N-type SGT MOSFET becomes a P-type SGT MOSFET, and vice versa.

[0037] Reference Figure 1, which shows a top plan view of a shielded gate trench MOSFET in an embodiment of the present application. The top plan view of shielded gate trench MOSFET 100 depicts integrated circuit die 102 before source and gate metals are applied. Integrated circuit die 102 can include an active region 104 and a termination region 106 surrounding active region 104.

[0038] The active region 104 can be defined as the primary current-carrying region of the integrated circuit die 102. The active region 104 can provide a current path between a source metal (not shown) and a drain metal (not shown), which is applied opposite the source metal. The termination region 106 can provide an isolation space 114 and a gate metal region 116. The isolation space 114 can contain a stripe-shaped gate trench layer 112 that isolates the source metal and the gate metal that can cover the region in the finished device. The isolation space 114 can provide separation between voltages applied to the top of the integrated circuit die 102.

[0039] A gate pad 108 may be formed on the outer edge 109 of the integrated circuit die 102. The gate pad 108 may be an area that provides electrical connections for the stripe-shaped gate trench layer 112. For example, the gate pad 108 is shown as being located at the center of the outer edge 109 of the integrated circuit die 102, but it should be understood that the gate pad 108 may be placed anywhere along the outer edge 109 of the integrated circuit die 102. The active area 104 may include an array of interconnect metal 110 and an array of stripe-shaped gate trench layers 112. The termination region 106 may include the stripe-shaped gate trench layers 112 and may be devoid of interconnect metal 110. Those skilled in the art will understand that the termination region 106 encompasses the outer edge 109 of the integrated circuit die 102 to surround the active area 104. The interconnect metal 110 may provide electrical connections between an array of source implants (not shown), which will be described below.

[0040] As an example, the termination region 106 surrounds the active region 104. The integrated circuit die 102 may include a source contact metal (not shown) applied in the active region 104 and a gate metal (not shown) on the gate liner 108 and around the outer edge 109 of the integrated circuit die 102 with an isolation space 114 therebetween.

[0041] The top plan view of shielded gate trench MOSFET 100 depicts termination region 106, which includes isolation space 114 adjacent active region 104. Termination region 106 may extend to outer edge 109.

[0042] Reference Figures 2 to 4 , which shows an alternative embodiment of the present application Figure 1 For an example of a top plan view of Part A, please also refer to Figure 5 Indicated Figure 4An exemplary cross section of the integrated circuit system 100 taken along the section line AA' is shown in FIG. Figure 1 This is to facilitate understanding of the shielded gate trench MOSFET layout architecture disclosed in this application. The layout architecture of a discrete gate trench MOSFET disclosed in the present application includes: a highly doped substrate 304 having a first polarity; an epitaxial layer 308 having the first polarity and grown on the highly doped substrate 304; a plurality of strip-shaped trenches formed in the epitaxial layer, the plurality of strip-shaped trenches including: a plurality of active gate trenches 310 located in an active region 104 and arranged in parallel, wherein gate polysilicon 318 and shielding polysilicon 314 are arranged in the active gate trenches 310; a terminal trench 411 surrounding the periphery of the active region 104 and arranged in a terminal region 106, wherein polysilicon 414 is arranged in the terminal trench 411, wherein the terminal trench 411 is spaced apart and connected to a portion of the plurality of active gate trenches 310 in a direction not parallel to the plurality of active gate trenches 310, and forms the same mesa width (MESA) as the outer edge of the portion of the trench not connected to the plurality of active gate trenches 310. a plurality of trench protection rings 410 surrounding the periphery of the active area 104 and disposed in the terminal area 106 , wherein polysilicon 414 is disposed in the trenches of the plurality of trench protection rings 410 .

[0043] like Figure 3 and Figure 4 In some embodiments, the direction in which the active gate trenches are arranged in parallel is regarded as the first direction, and the direction orthogonal thereto is regarded as the second direction. The terminal trench 411 is arranged at the junction of the terminal region 106 and the active region 104. With respect to the arrangement of the terminal trench 411 in the second direction, it forms an interval connection with part of the trenches of the plurality of active gate trenches 310 in the form of a disconnected intersection. Moreover, the extended shape formed by the connection between the terminal trench 411 and the active gate trench 310 is a corrugated shape. This corrugated shape design allows the terminal trench 410 and part of the trenches that are not connected to the plurality of active gate trenches 310 (i.e., those that are disconnected and not connected) to maintain the same mesa width (MESA Width) at the corner.

[0044] In some embodiments, the terminal trenches 411 may be arranged in a first direction in a linear shape in parallel with the active gate trenches 310 .

[0045] like Figures 2 to 4 In one embodiment of the present application, in addition to being disposed around the terminal trench 411, the plurality of trench protection rings 410 may also have a shape identical or similar to that of the terminal trench 411. Furthermore, the plurality of trench protection rings 410 may be arranged parallel to the terminal trench.

[0046] In some embodiments, a first mesa width ( W3 ) is formed between one of the plurality of trench protection rings 410 adjacent to the terminal trench 411 and the terminal trench 411 . The first mesa width ( W3 ) is the same as or different from the mesa widths ( W1 , W2 ).

[0047] In some embodiments, a second mesa width ( W4 ) is formed between the plurality of trench protection rings 410 , and the second mesa width ( W4 ) is the same as or different from the mesa widths ( W1 , W2 ).

[0048] like Figure 5 As shown, in one embodiment of the present application, the layout architecture includes an oxide capping layer 332 above the plurality of strip-shaped trenches 310, and a source metal 334 on the oxide capping layer 332 and passing through the etched trenches in the oxide capping layer 332. In some embodiments, the source metal caps the plurality of strip-shaped trenches in the active area and the terminal area.

[0049] or reference Figure 6 , which is Figure 5 In an alternative example of a trench guard ring structure, the source metal 334 is disposed above the active gate trench 310 and the termination trench 411, but does not cover the plurality of trench guard rings 410, thereby forming a floating ring structure 410a. Similarly, the first mesa width (W3) and the second mesa width (W4) may be the same as or different from the mesa widths (W1, W2).

[0050] Further Figure 7 , which is Figure 6 An alternative example of a trench guard ring structure is shown. The bottoms of the trenches of the plurality of trench guard rings 410 (or floating ring structures 410a) are all implanted with a trench bottom implant 417 comprising a second polarity. In some embodiments, the trench bottom implant 417 can also be disposed at Figure 5 The trench protection ring 410 of the structure is located at the bottom of the trench.

[0051] like Figure 8 and Figure 9 , which is Figure 6 and Figure 7 In some embodiments, the source metal 334 is electrically connected to the polysilicon layer 414 of the floating ring structure 410a through wiring, a conductor, or a semiconductor.

[0052] In some embodiments, the polysilicon 414 in the terminal trench 411 and the shielding source polysilicon 314 of the plurality of active gate trenches 310 connected to the terminal trench 411 are electrically connected.

[0053] like Figure 10 As shown in the boundary diagram, in some embodiments, a channel-stopping trench 418 is provided at the edge of the epitaxial layer 308 to block the leakage path of the drain-source breakdown current Idss from the terminal region 106 to the active region 104 .

[0054] like Figures 1 to 9 In some embodiments, the discrete gate trench MOSFET 100 is fully charge balanced, and the trench guard ring 410 provides leakage reduction of the saturation drain current (Idss) for the discrete shielded gate unit 302. During the breakdown of the drain-to-source breakdown voltage (BVdss) of the discrete shielded gate unit 302 under reverse bias, there is still a partial voltage drop at the bottom of the trench 413 in the terminal region of the trench guard ring 410.

[0055] In some embodiments, the termination trench 411 of the active gate trench 310 extends to the termination region 106 to connect to the termination trench 411, and is connected to the trench guard ring 410 of the termination region 106 through the termination trench 411 of the active gate trench 310 to uniformly distribute the charge in the termination region 106 and eliminate the charge imbalance in the termination region 106.

[0056] In some embodiments, the transistor structure formed by the discrete shield gate unit 302 is a fully charge-balanced discrete-gate trench metal-oxide-semiconductor field-effect transistor with a drain-source breakdown voltage ranging from 60V to 300V.

[0057] In some embodiments, the highly doped substrate 304 and the epitaxial layer 308 are N-type doped; the source region 328 is N-type doped, and the second polarity trench bottom implant 417 is P-type doped; the gate polysilicon 318 and the shield polysilicon 314 are respectively formed by heavily arsenic-doped polysilicon and / or heavily phosphorus-doped polysilicon.

[0058] This application is applicable to fully charge-balanced SGT MOSFETs. A corrugated trench guard ring is designed in the terminal region to prevent instability in the SGT MOSFET's breakdown voltage (BVdss) and reduce leakage current between the source and drain. Furthermore, the end of the active gate trench is connected to the terminal region trench to evenly distribute charge in the terminal region, eliminating charge imbalance in the terminal region.

[0059] The resulting methods, processes, apparatus, devices, products and / or systems are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive and effective, and can be implemented by adapting known components for ready, efficient and economical manufacture, application and utilization. Another important aspect of the embodiments of the present application is that they valuablely support and serve the historical trend of reducing costs, simplifying systems and increasing performance.

[0060] These and other valuable aspects of the embodiments of the present application therefore advance the state of the art to at least the next level.

[0061] Although the present application has been described in conjunction with a specific best mode, it should be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore intended to encompass all such alternatives, modifications, and variations that fall within the scope of the included claims. All matter herein set forth or shown in the accompanying drawings is to be interpreted in an illustrative and non-restrictive sense.

Claims

1. A layout architecture of a discrete gate trench MOSFET, characterized in that: include: a highly doped substrate comprising a first polarity; an epitaxial layer comprising the first polarity, grown on the highly doped substrate; A plurality of strip-shaped trenches are formed in the epitaxial layer, the plurality of strip-shaped trenches comprising: A plurality of active gate trenches are located in the active area and are arranged in parallel; a terminal trench surrounding the active area and disposed in the terminal area, wherein polysilicon is disposed in the terminal trench, and the terminal trench is connected to some of the plurality of active gate trenches at intervals in a direction not parallel to the plurality of active gate trenches, and forms the same mesa width as the outer edge of some of the trenches not connected to the plurality of active gate trenches; A plurality of trench protection rings, surrounding the periphery of the active area and arranged in the terminal area, wherein polysilicon is arranged in the trenches of the plurality of trench protection rings; The terminal trench is connected to some trenches of the plurality of active gate trenches, and its extended shape is a corrugated shape; One or more of the plurality of trench protection rings are identical in shape to the terminal trench; the plurality of trench protection rings are arranged in parallel with the terminal trench, and the trench protection rings are extended in a corrugated shape; A first mesa width is formed between one of the plurality of trench protection rings adjacent to the terminal trench and the terminal trench, wherein the first mesa width is the same as or different from the mesa width; A second mesa width is formed between the plurality of trench protection rings, and the second mesa width is the same as or different from the mesa width.

2. The layout architecture of the discrete gate trench MOSFET according to claim 1, wherein: An oxide capping layer is included over the plurality of strip-shaped trenches.

3. The layout architecture of the discrete gate trench MOSFET according to claim 2, wherein: A source metal is included on and through an etched trench in the oxide capping layer.

4. The layout architecture of the discrete gate trench MOSFET according to claim 3, wherein: The source metal is disposed in the active region and the terminal region; or, the source metal is disposed above the active gate trench and the terminal trench, and does not cover the plurality of trench protection rings so that the plurality of trench protection rings form a floating ring structure.

5. The layout architecture of the discrete gate trench MOSFET according to claim 4, wherein: The source metal is electrically connected to the polysilicon layer of the floating ring structure.

6. The layout architecture of the discrete gate trench MOSFET according to claim 1, wherein: The trench bottoms of the plurality of trench protection rings are all implanted with a trench bottom implant having a second polarity.

7. The layout architecture of the discrete gate trench MOSFET according to claim 6, wherein: The highly doped substrate and the epitaxial layer are N-type doped; the source region is N-type doped; the trench bottom implant is P-type doped; the gate polysilicon and the shielding polysilicon are respectively formed by heavily arsenic-doped polysilicon and / or heavily phosphorus-doped polysilicon.

8. The layout architecture of the discrete gate trench MOSFET according to claim 1, wherein: The channel-interrupting trench is arranged at the periphery of the terminal region, and the plurality of trench protection rings are located between the active region and the channel-interrupting trench.

9. The layout architecture of the discrete gate trench MOSFET according to claim 8, wherein: The polysilicon in the terminal trench is electrically connected to the gate polysilicon of the plurality of active gate trenches connected to the terminal trench.

10. The layout architecture of discrete gate trench MOSFET according to claim 1, wherein: The end of the active gate trench extends to the terminal region to connect to the trench of the terminal trench, and the end of part of the active gate trench is connected to the terminal trench to uniformly distribute the charge in the terminal region and eliminate the charge imbalance in the terminal region.

11. The layout architecture of the discrete gate trench MOSFET according to claim 1, wherein: The discrete gate trench MOSFET is fully charge balanced, and the trench guard ring provides leakage reduction of the saturation drain current (Idss) for the discrete shielded gate unit. During the breakdown of the drain-to-source breakdown voltage (BVdss) of the discrete shielded gate unit under reverse bias, there is still a partial voltage drop at the bottom of the trench of the trench guard ring.

12. The layout architecture of discrete gate trench MOSFET according to claim 1, wherein: The transistor structure formed by the discrete shielded gate unit is a fully charge-balanced discrete gate trench metal oxide semiconductor field effect transistor with a drain-source breakdown voltage range of 60V to 300V.

Images