Semiconductor device

Abstract

The semiconductor device of the embodiment includes a circuit block and a clock circuit that provides a clock signal to the circuit block at a specific time. The clock circuit includes: an output circuit that outputs a clock signal to the circuit block; and a control circuit that controls the timing of the clock signal output by the output circuit. The threshold voltage of the transistor in the output circuit that at least uses the clock signal as an input / output signal is a first threshold voltage, and the threshold voltage of the transistor constituting the control circuit is a second threshold voltage that is higher than the first threshold voltage.

Description

[0001] Citation of relevant applications

[0002] This application claims priority based on the priority of the prior Japanese Patent Application No. 2020-117201, filed on July 7, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0004] With the increasing integration and speed of semiconductor devices, the threshold voltage of transistors mounted in semiconductor devices is constantly being reduced in order to cope with the need for lower signal latency. In addition, as a low-power technology, a gated clock unit is used to stop the circuit operation of unused functional blocks. Summary of the Invention

[0005] The problem to be solved by the implementation method is to provide a semiconductor device that can maintain low latency characteristics and reduce power consumption.

[0006] The semiconductor device of the embodiment includes a circuit block and a clock circuit that provides a clock signal to the circuit block at a specific time. The clock circuit includes: an output circuit that outputs a clock signal to the circuit block; and a control circuit that controls the timing of the clock signal output by the output circuit. The threshold voltage of the transistor in the output circuit that at least uses the clock signal as an input / output signal is a first threshold voltage, and the threshold voltage of the transistor constituting the control circuit is a second threshold voltage that is higher than the first threshold voltage.

[0007] According to the above configuration, a semiconductor device capable of maintaining low latency characteristics and reducing power consumption can be provided. Attached Figure Description

[0008] Figure 1 This is a schematic overall block diagram of the semiconductor device according to the implementation method.

[0009] Figure 2 This is a schematic overall outline block diagram of the semiconductor device according to the implementation method.

[0010] Figure 3A This is a logic circuit diagram of the gated clock unit of the semiconductor device in the implementation method.

[0011] Figure 3B yes Figure 3A The circuit diagram shown is of the latch circuit within the gated clock unit.

[0012] Figure 4 This is an example of the operating waveform of the gated clock unit.

[0013] Figure 5 This is a table showing the simulation results of the rise / fall times of the gated clock unit.

[0014] Figure 6A This is a logic circuit diagram of a gated clock unit of a semiconductor device, which is a variation of the implementation method.

[0015] Figure 6B yes Figure 6A The circuit diagram shown is of the latch circuit within the gated clock unit.

[0016] Figure 7A It is a logic circuit diagram of a gated clock unit that can be applied to a semiconductor device in another implementation.

[0017] Figure 7B yes Figure 7A The circuit diagram shown is of the AND circuit in the gated clock unit.

[0018] Figure 8 yes Figure 7B The diagram shows the transistor configuration within the AND circuit.

[0019] Figure 9 This is an example of the operating waveform of the gated clock unit of a semiconductor device according to another embodiment.

[0020] Figure 10 This is a table showing the simulation results of the rise / fall time of the gated clock unit of a semiconductor device according to another embodiment.

[0021] Figure 11A It is an action waveform diagram that shows the limitations of the setup time and hold time of the clock signal when the threshold voltage of the transistor formed in the latch circuit of the gated clock unit is relatively high.

[0022] Figure 11B It is an action waveform diagram that shows the limitations of the setup and hold time of the clock signal when the threshold voltage of the transistor formed in the latch circuit of the gated clock unit is relatively low.

[0023] Figure 11C It is a waveform diagram showing whether the gated clock unit with a long effective time of enable signal en1 and a short effective time of enable signal en2 can be replaced when the transistor of the latch circuit in the gated clock unit is relatively high and relatively low.

[0024] Figure 12 This is a cross-sectional view of the device structure within a gated clock unit that can be applied in several embodiments of a semiconductor device to which this technology is applied.

[0025] Figure 13This is a cross-sectional view of another device structure within a gated clock unit that can be applied in several embodiments of a semiconductor device that utilize this technology.

[0026] Figure 14 This is a cross-sectional view of another device structure within a gated clock unit that can be applied in several embodiments of a semiconductor device that utilize this technology.

[0027] Figure 15 This is a cross-sectional view of another device structure within a gated clock unit that can be applied in several embodiments of a semiconductor device that utilize this technology. Detailed Implementation

[0028] Next, the embodiments will be described with reference to the accompanying drawings. In the drawings described below, the same or similar parts are labeled with the same or similar symbols. However, the drawings are schematic, and it should be noted that the thickness and planar dimensions of each component differ from reality. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it is natural that the drawings also include parts with different dimensional relationships or proportions.

[0029] Furthermore, the embodiments shown below illustrate apparatus and methods for embodying the technical concept, without specifying the material, shape, structure, or arrangement of the constituent parts. Various modifications can be made to these embodiments within the scope of the claims.

[0030] In the following description, for the sake of simplicity, the clock gating cell, system clock signal clk, and threshold voltage are sometimes referred to as CG cell, clock signal clk, and Vth.

[0031] [Implementation Method] Figure 1 This is a schematic overall configuration block diagram of the semiconductor device 1 according to the embodiment. Figure 1 As shown, CG units 11-14 may include a clock signal clk connected to CG units 11-14 and buffer circuits 411, 412, and 413. CG unit 11 takes the clock signal clk and the enable signal enA as input signals and may include timing circuits (e.g., flip-flop circuits 311 and 312) connected to the clock signal gclk output by CG unit 11.

[0032] The CG unit 12 takes the clock signal clk and the enable signal enB as input signals, and may include timing circuits (e.g., flip-flop circuits 313 and 314) connected to the clock signal gclk output by the CG unit 12.

[0033] The CG unit 13 takes the clock signal clk and the enable signal enC as input signals, and may include a timing circuit (e.g., flip-flop circuits 315 and 316) connected to the clock signal gclk output by the CG unit 13. In addition, the timing circuit (e.g., flip-flop circuits 315 and 316) is connected to the output line of the combinational circuit (e.g., combinational circuits 215 and 216) and outputs the signal.

[0034] The CG unit 14 takes the clock signal clk and the enable signal enD as input signals, and may include a timing circuit (e.g., flip-flop circuits 317 and 318) connected to the clock signal gclk output by the CG unit 14. In addition, the timing circuit (e.g., flip-flop circuits 317 and 318) is connected to the output line of the combinational circuit (e.g., combinational circuits 217 and 218) and outputs the signal.

[0035] Furthermore, in the following description, the sequential circuits (e.g., flip-flop circuits 311-318) connected to the clock signal gclk output from CG units 11-14, and the combinational circuits (e.g., combinational circuits 211-218) connected to the sequential circuits that take the output signals of CG units 11-14 as input signals, are also collectively referred to as circuit blocks. Additionally, the outputs of circuit blocks A-D are the same as the outputs of combinational circuits 215-218.

[0036] Figure 2 This is a schematic overall schematic block diagram of the semiconductor device 1 according to the embodiment. Figure 2 As shown, CG units 11-14 include CG units 11-14, which take the clock signal clk and enable signals enA-D as input signals and control the supply of the clock signal gclk to circuit blocks A-D. Additionally, as... Figure 2 As shown, CG units 11-14 are connected to circuit blocks A-D.

[0037] In the following description, CG units 11 to 14 will be collectively referred to as CG unit 10 or the clock circuit. Additionally, enable signals enA to D will be collectively referred to as enable signals en. CG unit 10 outputs a clock signal gclk in response to the input of enable signal en. CG unit 10 functions as a gated clock unit, which controls the operation or cessation of each circuit block by inputting the enable signal en (e.g., 0 or 1), thus providing a clock to each circuit block whether it is active or inactive.

[0038] In addition, the “H”, “L”, “P” and “N” appended to the symbols of latch circuit 100, AND circuit 101 and OR circuit 102 are explained.

[0039] "H" indicates a circuit in which the transistors that make up the circuit have a relatively high threshold value, while "L" indicates a circuit in which the transistors that make up the circuit have a relatively low threshold value.

[0040] In addition, "P" indicates rising edge triggered type, and "N" indicates falling edge triggered type.

[0041] (CG Unit 10a) The CG unit 10a that can be applied to the semiconductor device 1 in the embodiment will be described. Figure 3A This is a logic circuit diagram of the CG unit 10a of the semiconductor device 1 that can be applied to the implementation method. Figure 3A This is an example of CG Unit 10a.

[0042] Figure 3A The CG unit 10a consists of a latch circuit 100HP (e.g., a D-type latch) as an example of the control circuit within the CG unit 10a, and an AND circuit 101LP as an example of the output circuit within the CG unit 10a. The CG unit 10a, consisting of the latch circuit 100HP and the AND circuit 101LP, is a rising edge triggered positive clock circuit.

[0043] like Figure 3A As shown, the input terminals of CG unit 10a are connected to the input lines of the externally input enable signal en and clock signal clk. The input terminals of latch circuit 100HP are connected to the input lines of the enable signal en and clock signal clk. The input terminals of AND circuit 101LP are connected to the output line of the enable signal enl and the input line of the clock signal clk output by latch circuit 100HP. The output terminals of CG unit 10a are connected to the output line of the clock signal gclk output by AND circuit 101LP.

[0044] Figure 3B yes Figure 3A The circuit diagram of the latch circuit 100HP in the CG unit 10a shown. Figure 3B yes Figure 3A An example of the latch circuit 100HP within the CG unit 10a shown.

[0045] Specifically, such as Figure 3B As shown, the latch circuit 100HP includes four NOT circuits (e.g., NOT circuits 111 to 114) and two transfer gates (e.g., transfer gates 141 and 142).

[0046] The transmission gate 141 is connected to the input line of the clock signal clk at the gate input. Additionally, the transmission gate 141 is connected to the input line of the clock signal clk via NOT circuit 112 at the gate input.

[0047] Furthermore, the transmission gate 141 connects the enable signal en to the input line via the NOT circuit 111, and the output is connected to the input line of the NOT circuit 113 and the transmission gate 142.

[0048] The transmission gate 142 connects the input line of the clock signal clk to the gate input. Additionally, the transmission gate 142 connects the input line of the clock signal clk to the gate input via the NOT circuit 112. Furthermore, the output of the transmission gate 142 is connected to the NOT circuit 114.

[0049] NOT circuit 113 and NOT circuit 114 are connected to the output line of the enable signal enl output by latch circuit 100HP.

[0050] The threshold voltage of all transistors (e.g., field-effect transistors) constructed in the latch circuit 100HP is set higher than that of transistors (e.g., field-effect transistors) constructed in the AND circuit 101LP.

[0051] In other words, by making the threshold voltage of the transistor constructed in the latch circuit 100HP of the CG unit 10a higher than the threshold voltage of the transistor constructed in the AND circuit 101LP of the CG unit 10a, it is possible to suppress the increase in power consumption caused by the leakage current of the transistor.

[0052] When the clock signal clk is high, the latch circuit 100HP outputs the enable signal en as the enable signal enl. On the other hand, when the clock signal clk is low, the data flow is blocked, and the latch circuit 100HP retains the previous data output.

[0053] In other words, the CG unit 10a controls the output of the clock signal gclk in the following way: the enable signal en is sampled at the rising time of the clock signal clk in the latch circuit 100HP, and the value is used to determine whether to allow the newly sampled clock pulse to pass or to block the newly sampled clock pulse through the AND circuit 101LP.

[0054] In other words, the AND circuit 101LP within the CG unit 10a outputs a clock signal gclk based on the enable signal enl and the clock signal clk output from the latch circuit 100HP. Therefore, the clock signal gclk requires low delay characteristics, so all transistors (e.g., field-effect transistors) constructed within the AND circuit 101LP are low threshold voltage transistors.

[0055] (First Comparative Example of CG Unit 10a) Although increasing the threshold voltage of the transistor can suppress the leakage current of the transistor, it will reduce the switching speed of the transistor, which is also considered to affect the transmission of the clock signal.

[0056] Therefore, in comparison with a latch circuit composed entirely of transistors with low threshold voltages, the following situation is illustrated: the transmission of the clock signal is not affected by making the threshold voltage of the transistors constructed in the latch circuit 100HP higher than the threshold voltage of the transistors constructed in the AND circuit 101LP of the CG unit 10a.

[0057] As a comparative example of CG unit 10a, a first comparative example of CG unit 10a will be described. In the following description, the first comparative example of CG unit 10a will also be referred to as the first comparative example.

[0058] The difference between the structure of CG unit 10a and the logic circuit of the first comparative example is that... Figure 3A The latch circuit within the CG unit 10a shown is latch circuit 100LP.

[0059] The threshold voltage of the transistor constructed within the latch circuit 100LP is lower than that of the transistor constructed within the latch circuit 100HP, but the same as that of the transistor constructed within the AND circuit 101LP. In other words, although the transistor structure of the first comparative example has a higher leakage current, it takes into account low delay characteristics.

[0060] Next, a comparison of the operation waveforms of the CG unit 10a of the semiconductor device 1 applicable to the implementation method and the first comparative example will be described. Figure 4 This is an example of the motion waveform of CG unit 10a and the first comparative example.

[0061] Figure 4 The diagram shows the enable signal en and clock signal clk input to CG unit 10a and the first comparison example, as well as the clock signal gclk output by CG unit 10a and the first comparison example. The time from the rising edge of the clock signal clk to the rising edge of the clock signal gclk output by each CG unit is represented by the delay time Tpd. Figure 4 As shown, the delay time Tpd of CG unit 10a is no different from that of the first comparative example.

[0062] In other words, even if the threshold voltage of all transistors in the latch circuit 100HP is set higher than that of the transistors in the AND circuit 101LP, it will not affect the delay time of the clock signal gclk output from the CG unit 10a.

[0063] Figure 5 This is a table showing the simulation results of the rise / fall times for CG unit 10a and the first comparative example. (Example) Figure 5 As shown, the rising edge delay time of both CG unit 10a and the first comparative example is 22.7 ps.

[0064] As explained above, the semiconductor device 1 according to the embodiment can provide a semiconductor device 1 that can maintain the low latency characteristics of the clock signal for the CG unit 10 of the clock line and reduce power consumption.

[0065] [Variations on the Implementation] A variation of the semiconductor device 1, the CG unit 10b, which can be applied to the implementation, will be described. Figure 6A This is a logic circuit diagram of the CG unit 10b of the semiconductor device 1, which can be applied to variations of the implementation method. Figure 6A This is an example of CG unit 10b.

[0066] Figure 6A The CG unit 10b consists of a latch circuit 100HN (e.g., a D-type latch) as an example of the control circuit within the CG unit 10b, and an OR circuit 102LN as an example of the output circuit within the CG unit 10b.

[0067] The difference in the structure of the logic circuits of CG unit 10b and CG unit 10a lies in the following: Figure 6A The latch circuit within the CG unit 10b shown is latch circuit 100HN. Furthermore, CG unit 10b is an OR circuit 102LN, not an AND circuit 101LP.

[0068] The threshold voltage of all transistors (e.g., field-effect transistors) formed in the latch circuit 100HN is set to be higher than that of the transistors (e.g., field-effect transistors) formed in the OR circuit 102LN.

[0069] All transistors (e.g., field-effect transistors) constructed within the OR circuit 102LN are low-threshold voltage transistors. The CG unit 10b, composed of the latch circuit 100HN and the OR circuit 102LN, is a falling-edge triggered negative clock circuit.

[0070] like Figure 6A As shown, the input terminals of CG unit 10b are connected to the input lines of the externally input enable signal en and clock signal clk. The input terminals of latch circuit 100HN are connected to the input lines of the enable signal en and clock signal clk. The input terminals of OR circuit 101LN are connected to the output line of the enable signal enl and the input line of the clock signal clk output by latch circuit 100HN. The output terminals of CG unit 10b are connected to the output line of the clock signal gclk output by OR circuit 102LN.

[0071] Figure 6B yes Figure 6A The circuit diagram of the latch circuit 100HN in the CG unit 10b shown. Figure 6B yes Figure 6A An example of the latch circuit 100HN within the CG unit 10b shown.

[0072] Specifically, such as Figure 6B As shown, the latch circuit 100HN includes five NOT circuits (e.g., NOT circuits 115-119) and two transmission gates (e.g., transmission gates 143 and 144).

[0073] The transmission gate 143 is connected to the input line of the clock signal clk at the gate input. Additionally, the transmission gate 143 is connected to the input line of the clock signal clk at the gate input via the NOT circuit 116.

[0074] Furthermore, the transmission gate 143 connects the enable signal en to the input line via the NOT circuit 115, and the output is connected to the input line of the NOT circuit 117 and the transmission gate 144.

[0075] The transmission gate 144 connects the input line of the clock signal clk to the gate input. Additionally, the transmission gate 144 connects the input line of the clock signal clk to the gate input via the NOT circuit 116. Furthermore, the output of the transmission gate 144 is connected to the NOT circuit 118.

[0076] NOT circuit 117 and NOT circuit 118 are connected to the output line of the enable signal enl output by latch circuit 100HN via NOT circuit 119.

[0077] The operation of CG unit 10b is to control the output of clock signal gclk in the following way: relative to the rising edge of clock signal clk of CG unit 10a, the enable signal en is sampled at the falling edge of clock signal clk. Based on this value, it is determined whether to allow the newly sampled clock pulse to pass or to block the newly sampled clock pulse through OR circuit 102LN.

[0078] The motion waveform and effect of CG unit 10b shown in Figure 6 are obtained by changing the rising edge of the clock signal clk of CG unit 10a to the falling edge of the clock signal clk. The basic motion and effect are the same as those of CG unit 10a, so the attached figures and descriptions are omitted.

[0079] [Another Embodiment] The CG unit 10c of the semiconductor device 1 that can be applied to another embodiment will be described. Figure 7A This is a logic circuit diagram of the CG unit 10c of the semiconductor device 1 that can be applied to another embodiment. Figure 7A This is an example of CG unit 10c.

[0080] Figure 7AThe CG unit 10c consists of a latch circuit 100HP (e.g., a D-type latch) as an example of the control circuit within the CG unit 10c, and an AND circuit 101HP as an example of the output circuit within the CG unit 10c.

[0081] like Figure 7B As shown, the threshold voltage of the transistors (e.g., n-chTr.121, p-chTr.122) that take the clock signal clk as the input signal in the AND circuit 101HP is set to be lower than that of the transistors (e.g., n-chTr.123, p-chTr.124) that take the enable signal en as the input signal.

[0082] In other words, in the CG unit 10c, the threshold voltage of all transistors in the latch circuit 100HP and the transistors in the AND circuit 101HP that do not use the clock signal clk as an input signal are higher than the threshold voltage of the transistors in the AND circuit 101HP that use the clock signal clk as an input signal.

[0083] The CG unit 10c, which includes latch circuit 100HN and AND circuit 101HP, is a rising edge triggered positive clock circuit.

[0084] The difference in the logic circuit structure between CG unit 10c and CG unit 10a lies in the following: Figure 6A The AND circuit within the CG unit 10c shown is an AND circuit 101HP. Other structures within the CG unit 10c are the same as in the implementation method.

[0085] Figure 7B yes Figure 7A The circuit diagram of the AND circuit 101HP within the CG element 10c shown. Figure 7B yes Figure 7A An example of the AND circuit 101HP within the CG element 10c shown.

[0086] Specifically, such as Figure 7B As shown, the AND circuit 101HP consists of two n-channel transistors (e.g., n-channel field-effect transistors n-FETs 121 and 123), two p-channel transistors (e.g., p-channel field-effect transistors p-FETs 122 and 124), and a NOT circuit 120.

[0087] In the following description, n-channel field-effect transistors (n-FETs) and p-channel field-effect transistors (p-FETs) will also be referred to as n-chTr. and p-chTr., respectively.

[0088] n-chTr.121 and p-chTr.122 are connected to the input line of the clock signal clk at the gate input. In addition, the drains of p-chTr.122 and n-chTr.121 are connected to the drain of p-chTr.124 and NOT circuit 120.

[0089] n-chTr.123 and p-chTr.124 are connected to the input line of the enable signal en at the gate input. The sources of p-chTr.122 and p-chTr.124 are connected to the power supply. The source of n-chTr.121 is connected to the drain of n-chTr.123. The source of n-chTr.123 is connected to ground (GND).

[0090] The output lines of the clock signal gclk output by the NOT circuit 120 and the AND circuit 101HP are connected.

[0091] (Second Comparative Example of CG Unit 10c) Considering that the impact on the transmission of clock signal clk differs in the following two cases, namely, only the transistors configured in the AND circuit 101HP that do not use clock signal clk as an input signal are made to have a high threshold voltage; and all transistors are made to have a high threshold voltage, including the transistors configured in the AND circuit 101HP that use clock signal clk as an input signal.

[0092] Therefore, the following explanation states that, compared to the case where all transistors are made to have a high threshold voltage, the case where only the transistors that are not made to have a high threshold voltage within the AND circuit 101HP, which are included in the case where all transistors are made to have a high threshold voltage, will not affect the transmission of the clock signal clk, even if only the transistors that are not made to have a high threshold voltage within the AND circuit 101HP are made to have a high threshold voltage.

[0093] As a comparative example of CG unit 10c, a second comparative example of CG unit 10c will be described. In the following description, the second comparative example of CG unit 10c will also be referred to as the second comparative example.

[0094] The difference between the logic circuit structure of CG unit 10c and the second comparative example lies in the different threshold voltages of the transistors constructed within the AND circuit 101HP. The second comparative example sets all the transistors constructed within the AND circuit 101HP to a higher threshold voltage than the transistors in the AND circuit 101HP of CG unit 10c that use the clock signal as an input signal.

[0095] The transistor within the CG unit 10c, configured as an AND circuit 101HP, is... Figure 8The threshold voltage of the transistor in the AND circuit 101HPA shown is configured.

[0096] The transistor in the second comparative example, configured as an AND circuit 101HP, is... Figure 8 The threshold voltage of the transistor in the AND circuit 101HPB shown is configured. Figure 8 It is CG unit 10c and the second comparative example. Figure 7B The table shows the configuration of the threshold voltages of the transistors within the AND circuit 101HP.

[0097] Next, a comparison of the operation waveforms of the CG unit 10c of the semiconductor device 1 applicable to the implementation method and the second comparative example will be described. Figure 9 This is an example of the motion waveform of CG unit 10c and the second comparative example.

[0098] Figure 9 The enable signal en and clock signal clk input to CG unit 10a, the first comparison example, CG unit 10c and the second comparison example are shown, as well as the clock signal gclk output by CG unit 10a, the first comparison example, CG unit 10c and the second comparison example.

[0099] In addition, the time from the rising edge of the clock signal clk to the rising edge of the clock signal gclk output by each CG unit is represented by the delay time Tpd.

[0100] like Figure 9 As shown, although the delay time Tpd of CG unit 10c is slightly larger than that of CG unit 10a and the first comparative example, the impact of the delay time Tpd is small. Figure 9 As shown, compared with CG unit 10a, the first comparative example and CG unit 10c, the second comparative example has a larger delay time Tpd and a greater impact of the delay time Tpd.

[0101] Figure 10 This table shows the simulation results for the rise / fall times of CG unit 10c and CG unit 10a. The rise delay times of CG unit 10c and CG unit 10a are as follows: Figure 10 As shown, CG unit 10c has a resolution of 24.7 ps, and CG unit 10a has a resolution of 22.7 ps.

[0102] In other words, even if the threshold voltage of all transistors except the transistors that take the clock signal as the input signal in the AND circuit 101HP is set higher than that of the transistors that take the clock signal as the input signal in the AND circuit 101HP, it will not have a significant impact on the delay time of the clock signal gclk output from the CG unit 10c.

[0103] (Timing Limitations) Next, the timing limitations and substitutions of CG unit 10 will be explained. So far, the delay time of the clock signal gclk output by CG unit 10 has been explained. However, the setup time and hold time required for the latch circuit to operate are specified within the latch circuit of CG unit 10. Therefore, the latch circuit within CG unit 10 needs to meet the operating range of the setup time and hold time required for the latch circuit to operate.

[0104] In other words, in the latch circuit within the CG unit 10, there are time point limitations on the setup time and holding time required for the latch circuit to operate.

[0105] In the following description, when the transistor configured in the latch circuit within the CG unit 10 has a relatively high threshold voltage, the time for preparing the enable signal en relative to the clock edge of the clock signal clk of the latch circuit within the CG unit 10 is also referred to as the setup time 130HP. Furthermore, the time for holding the enable signal en relative to the clock edge of the clock signal clk of the latch circuit within the CG unit 10 is also referred to as the hold time 131HP.

[0106] When the transistor formed in the latch circuit within the CG unit 10 has a relatively low threshold voltage, the time for preparing the enable signal en relative to the clock edge of the clock signal clk of the latch circuit within the CG unit 10 is also called the setup time 130LP. Furthermore, the time for holding the enable signal en relative to the clock edge of the clock signal clk of the latch circuit within the CG unit 10 is also called the hold time 131LP.

[0107] Figure 11A This is an action waveform diagram that represents the limitations of the setup time 130HP and the hold time 131HP of the clock signal clk when the transistor formed in the latch circuit within the CG unit 10 has a relatively high threshold voltage.

[0108] Figure 11B This is an action waveform diagram that represents the limitations of the setup time 130LP and the hold time 131LP of the clock signal when the transistors formed in the latch circuit within the CG unit 10 are at a relatively low threshold voltage.

[0109] about Figure 11A The setup time of 130HP and the hold time of 131HP shown are due to the relatively high threshold voltage of the transistor formed in the latch circuit within CG unit 10. Figure 11B The setup time is 130 LP and the hold time is 131 LP, as shown.

[0110] Figure 11CThis is a waveform diagram showing the operation of replacing CG unit A (with a longer effective time for enable signal en1) and CG unit B (with a shorter effective time for enable signal en2) when the transistor in the latch circuit within CG unit 10 is relatively high and relatively low.

[0111] Specifically, such as Figure 11C As shown, the CG unit A with a long effective time of the enable signal en1 satisfies the limitations of setup time 130HP and hold time 131HP, and therefore can be replaced by CG unit 10 with a relatively high threshold voltage transistor constructed in the latch circuit. However, as Figure 11C As shown, the CG unit B with a short effective time of enable signal en2 does not meet the limitations of setup time 130HP and hold time 131HP, and therefore cannot be replaced by CG unit 10 with a relatively high threshold voltage transistor in the latch circuit.

[0112] (Device Structure) Next, for the transistors configured in the CG unit 10 of the semiconductor device 1 that can be applied to several embodiments of the present invention, different threshold voltages can be achieved by changing the device structure of the transistors.

[0113] The following is for reference Figures 12-15 The internal structure of the n-channel MOSFET (metal oxide semiconductor field-effect transistor) shown illustrates the differences in device structures for transistors that achieve different threshold voltages.

[0114] Figure 12 This is a cross-sectional view of the device structure within the CG unit 10, which can be applied in several embodiments of semiconductor devices employing this technology. Additionally, Figure 12 This is an example of the device structure within CG unit 10.

[0115] A transistor with a gate length Lg2 and a high threshold voltage can increase the threshold voltage of an n-channel MOSFET by making its gate length longer than that of a transistor with a gate length Lg1 and a low threshold voltage.

[0116] Figure 13 This is a cross-sectional view of another device structure within the CG unit 10 of the semiconductor device applicable to the implementation method. Additionally, Figure 13 This is an example of the device structure within CG unit 10.

[0117] A transistor with a gate oxide thickness of Tox2 and a high threshold voltage can increase the threshold voltage of an n-channel MOSFET by making its gate oxide thickness greater than that of a transistor with a gate oxide thickness of Tox1 and a low threshold voltage.

[0118] Figure 14This is a cross-sectional view of another device structure within the CG unit 10 of the semiconductor device applicable to the implementation method. Additionally, Figure 14 This is an example of the device structure within CG unit 10.

[0119] A transistor with a high threshold voltage and an impurity concentration of NA2 in the semiconductor region directly beneath the gate oxide can increase the threshold voltage of an n-channel MOSFET by making its impurity concentration higher than that of a transistor with a low threshold voltage and an impurity concentration of NA1 in the semiconductor region directly beneath the gate oxide.

[0120] Figure 15 This is a cross-sectional view of another device structure within the CG unit 10 of the semiconductor device applicable to the implementation method. Additionally, Figure 15 This is an example of the device structure within CG unit 10.

[0121] A transistor with a substrate voltage Vsub2 and a high threshold voltage can increase the threshold voltage of an n-channel MOSFET by applying a negative substrate bias value based on the source voltage, compared to a transistor with a substrate voltage Vsub1 and a low threshold voltage.

[0122] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0123] For example, regarding the transistors of the CG unit 10 of the semiconductor device 1 configured to be applicable to several embodiments of the present invention, an n-channel MOSFET (metal oxide semiconductor field-effect transistor) is described as a representative example, but it may also be a p-channel MOSFET.

Claims

1. A semiconductor device comprising a circuit block and a clock circuit that supplies a clock signal to the circuit block at a clock edge, and the clock circuit has: an output circuit that outputs the clock signal to the circuit block; and a control circuit that controls a timing at which the output circuit outputs the clock signal; a threshold voltage of a transistor of the output circuit that outputs at least the clock signal as an output signal is a first threshold voltage, a threshold voltage of a transistor that constitutes a NOT circuit included in the control circuit is a second threshold voltage that is higher than the first threshold voltage, the control circuit includes a plurality of the transistors, each of which constitutes the NOT circuit, each transistor that constitutes the NOT circuit has the second threshold voltage.

2. The semiconductor device according to claim 1, wherein the control circuit is a latch circuit that: takes the clock signal and an enable signal as input signals, samples the enable signal at a rising or falling time point of the clock signal, and outputs the sampled enable signal to the output circuit.

3. The semiconductor device according to claim 2, wherein the output circuit is an AND circuit that: takes the enable signal output from the control circuit and the clock signal as input signals.

4. The semiconductor device according to claim 2, wherein the output circuit is an OR circuit that: takes the enable signal output from the control circuit and the clock signal as input signals.

5. The semiconductor device according to any one of claims 1 to 4, wherein a gate length of the transistor of the first threshold voltage and the transistor of the second threshold voltage is different.

6. The semiconductor device according to any one of claims 1 to 4, wherein a film thickness of a gate oxide film of the transistor of the first threshold voltage and the transistor of the second threshold voltage is different.

7. The semiconductor device according to any one of claims 1 to 4, wherein an impurity concentration of a semiconductor region under a gate oxide film of the transistor of the first threshold voltage and the transistor of the second threshold voltage is different.

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