Signal processing method for a processing circuit and a sampling circuit

Abstract

The present disclosure provides a signal processing method for sensing voltages of a processing circuit adapted to read an X-ray sensor and a sampling circuit. The processing circuit includes an amplifier and a sampling circuit. The amplifier includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the amplifier is coupled to the X-ray sensor. The sampling circuit is coupled to the output terminal of the amplifier. The sampling circuit obtains a first voltage, a second voltage, and a sampling voltage of the X-ray sensor during different periods. The sampling voltage is between the first voltage and the second voltage. The sampling circuit subtracts the second voltage from the sampling voltage to obtain a third voltage during a readout period, subtracts the first voltage from the second voltage to obtain a fourth voltage, and divides the third voltage by the fourth voltage to read out the sensing voltage of the X-ray sensor.

Description

Technical Field

[0001] The present disclosure relates to a circuit, and more particularly to a signal processing method for a processing circuit and a sampling circuit adapted to read an X-ray sensor. Background Art

[0002] For the readout circuit of a general light sensor, since the thin-film transistors (TFTs) in the light sensor may have unstable transistor characteristics due to manufacturing process errors, the sensed signals read by the readout circuit are prone to errors and cannot fully utilize the decoding range of the analog-to-digital converter (ADC) in the readout circuit. In view of this, several solution embodiments will be proposed below. Summary of the Invention

[0003] The present disclosure is directed to a signal processing method for a processing circuit and a sampling circuit adapted to read an X-ray sensor, which can effectively read the sensed voltage of the X-ray sensor.

[0004] According to an embodiment of the present disclosure, the processing circuit of the present disclosure is adapted to read the sensed voltage of an X-ray sensor. The processing circuit includes an amplifier and a sampling circuit. The amplifier includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the amplifier is coupled to the X-ray sensor. The sampling circuit is coupled to the output terminal of the amplifier. The sampling circuit obtains a first voltage, a second voltage, and a sampling voltage of the X-ray sensor during different sampling periods. The sampling voltage is between the first voltage and the second voltage. The sampling circuit subtracts the second voltage from the sampling voltage to obtain a third voltage, subtracts the first voltage from the second voltage to obtain a fourth voltage, and divides the third voltage by the fourth voltage during the readout period to read the sensed voltage of the X-ray sensor.

[0005] According to an embodiment of the present disclosure, the signal processing method of the sampling circuit of the present disclosure includes the following steps: obtaining a sampling voltage; obtaining a first voltage; obtaining a second voltage; subtracting the second voltage from the sampling voltage to obtain a third voltage; subtracting the first voltage from the second voltage to obtain a fourth voltage; and dividing the third voltage by the fourth voltage.

[0006] Based on the above, the signal processing method of the processing circuit and the sampling circuit of the present disclosure can read the sensed voltage of the X-ray sensor by means of correlated triple sampling (CTS).

[0007] To make the above features and advantages of the present disclosure more obvious and understandable, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a circuit schematic diagram of a photosensor and a processing circuit according to an embodiment of the present disclosure;

[0009] Figure 2 is a schematic diagram of the architecture of a sampling circuit according to an embodiment of the present disclosure;

[0010] Figure 3 is a circuit schematic diagram of a subtractor circuit according to an embodiment of the present disclosure;

[0011] Figure 4 is a signal timing diagram of a processing circuit according to an embodiment of the present disclosure;

[0012] Figure 5 is a voltage relationship diagram of a first voltage, a second voltage, and a sampling voltage according to an embodiment of the present disclosure;

[0013] Figure 6 is a circuit schematic diagram of a divider circuit according to an embodiment of the present disclosure;

[0014] Figure 7 is a schematic diagram of the architecture of a sampling circuit according to another embodiment of the present disclosure;

[0015] Figure 8 is a flowchart of a signal processing method of a sampling circuit according to an embodiment of the present disclosure.

[0016] DESCRIPTION OF REFERENCE NUMERALS

[0017] 100: Processing circuit;

[0018] 110, 310, 700: Sampling circuit;

[0019] 120: Amplifier;

[0020] 121, 311_4 to 311_6, 441 to 445: Capacitor;

[0021] 1201: Inverting input terminal;

[0022] 1202: Non-inverting input terminal;

[0023] 1203: Output terminal;

[0024] 200: Photosensor;

[0025] 201: Signal line;

[0026] 211 to 213, 421 to 433, 631 to 633: transistor switches;

[0027] 214: photodiode;

[0028] 215: storage capacitor;

[0029] 311: switching circuit;

[0030] 311_1 to 311_3: switches;

[0031] 312, 313: subtraction operation units;

[0032] 314: division operation unit;

[0033] 315, 740: analog-to-digital converters;

[0034] 400, 710_1 to 710_N: subtractor circuits;

[0035] 411 to 413, 611 to 614: amplifiers;

[0036] 600, 730: divider circuits;

[0037] 621 to 627: resistor units;

[0038] 720: buffer circuit;

[0039] V1: first voltage;

[0040] V2: second voltage;

[0041] V3: third voltage;

[0042] V4: fourth voltage;

[0043] Vout: sensed voltage;

[0044] VD: digital signal;

[0045] VDD: power supply voltage;

[0046] VA: reference voltage;

[0047] VGND: ground voltage;

[0048] Vset: set voltage;

[0049] Vscan: scan voltage;

[0050] Vselect: selection voltage;

[0051] Vgs: voltage;

[0052] Vin: input voltage;

[0053] P1: Active region;

[0054] P2: Peripheral region;

[0055] t0 to t8: Time;

[0056] Ta, Tb, Tc: Sampling periods;

[0057] ψ1 to ψ4: Switching signals;

[0058] ψreset: Reset signal;

[0059] S810 to S860: Steps. Detailed implementation manners

[0060] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. As long as possible, the same component symbols are used in the drawings and the description to represent the same or similar parts. It should be noted that, for the convenience of the reader's understanding and the simplicity of the drawings, only a part of the electronic device or display device is drawn in the multiple drawings of the present disclosure, and the specific components in the drawings are not drawn in actual proportion. In addition, the number and size of each component in the drawings are only for illustration and are not used to limit the scope of the present disclosure. For example, for clarity, the relative sizes, thicknesses and positions of each film layer, region or structure may be reduced or enlarged.

[0061] Certain terms will be used throughout this specification and the appended claims to refer to particular components. Those skilled in the art should understand that electronic device manufacturers may refer to the same component by different names. This document does not intend to distinguish components that have the same function but different names. In the following specification and claims, words such as "having" and "including" are open-ended terms and should therefore be construed as meaning "including but not limited to...".

[0062] The directional terms mentioned herein, such as: "upper", "lower", "front", "rear", "left", "right", etc., are only references to the directions in the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. It should be understood that when a component or film layer is said to be disposed "on" another component or film layer or "connected" to another component or film layer, the component or film layer may be directly on the other component or film layer or directly connected to the other component or film layer, or there may be an intervening component or film layer (non-direct situation) between the two. On the contrary, when a component or film layer is said to be "directly" on another component or film layer or "directly connected" to another component or film layer, there is no intervening component or film layer between the two.

[0063] As used herein, the terms "about", "equal to", "equivalent to", "the same as", "substantially", or "approximately" generally mean within 10% of a given value or range, or within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. In addition, the phrase "a given range is from a first value to a second value", "a given range falls within the range from a first value to a second value" means that the given range includes the first value, the second value, and other values therebetween.

[0064] In some embodiments of the present disclosure, terms related to joining and connection, such as "connect", "interconnect", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, with other structures provided therebetween. Terms related to joining and connection may also include cases where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected", "coupled" include any direct and indirect electrical connection means.

[0065] In the following embodiments, the same or similar components will be denoted by the same or similar reference numerals, and their detailed descriptions will be omitted. In addition, features in different embodiments can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with each other. Simple equivalent changes and modifications made according to this specification or the claims are still within the scope covered by the present disclosure. Additionally, the terms "first", "second", etc. mentioned in this specification or the claims are only used to name different components or distinguish different embodiments or ranges, and do not limit the upper or lower limits of the number of components, nor are they used to define the manufacturing order or setting order of the components.

[0066] It should be noted that, without departing from the spirit of the present disclosure, the technical features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments. Features between embodiments can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with each other.

[0067] Figure 1 is a circuit schematic diagram of a photosensor 200 and a processing circuit 100 according to an embodiment of the present disclosure. Refer to Figure 1, the processing circuit 100 may be disposed, for example, in the peripheral area P2 of the panel, and the optical sensor 200 may be disposed, for example, in the active area P1 of the panel. The active area P1 of the panel may include, for example, a pixel array (not shown in the figure), and each pixel of the pixel array may include, for example, the optical sensor 200. In this embodiment, the optical sensor 200 may be an active sensor (Active Pixel Sensor, APS), but the present disclosure is not limited thereto. In an embodiment, the optical sensor 200 may also be a passive sensor (Passtive Pixel Sensor, PPS). In this embodiment, the optical sensor 200 may be used to sense X-rays, but the present disclosure is not limited thereto. In an embodiment, the optical sensor 200 may also be an optical sensor for sensing optical signals in other wavelength bands. The optical sensor 200 is coupled to the processing circuit 100 via a signal line 201. In this embodiment, the processing circuit 100 includes a sampling circuit 110 and an amplifier 120. The amplifier 120 includes an inverting input terminal 1201, a non-inverting input terminal 1202, and an output terminal 1203. The inverting input terminal 1201 of the amplifier 120 is coupled to the optical sensor 200 via the signal line 201, and the inverting input terminal 1201 of the amplifier 120 may be coupled to the output terminal 1203 of the amplifier 120 via a capacitor 121. The non-inverting input terminal 1202 of the amplifier 120 is coupled to a ground voltage VGND. The output terminal 1203 of the amplifier 120 is coupled to the sampling circuit 110.

[0068] In this embodiment, the optical sensor 200 includes at least one transistor switch, such as transistor switches 211 to 213, a photodiode 214, and a storage capacitor 215. The transistor switches 211 to 213 can be thin-film transistors (TFTs) having semiconductor materials, and the semiconductor materials can include, for example, top-gate, bottom-gate, or double-gate thin-film transistors of amorphous silicon, low-temperature poly-silicon (LTPS), or metal oxide, or a combination of the above materials, and the present disclosure is not limited thereto. In some embodiments, different thin-film transistors can have different semiconductor materials as described above. The first end of the transistor switch 211 is coupled to a set voltage Vset, and the control end of the transistor switch 211 is coupled to a scan voltage Vscan. The first end of the photodiode 214 is coupled to a reference voltage VA, and the second end of the photodiode 214 is coupled to the second end of the transistor switch 211, the first end of the storage capacitor 215, and the control end of the transistor switch 212. The photodiode 214 can be used to sense optical signals. The second end of the storage capacitor 215 is coupled to a ground voltage VGND. The first end of the transistor switch 212 is coupled to a power supply voltage VDD, and the second end of the transistor switch 212 is coupled to the first end of the transistor switch 213. The control end of the transistor switch 213 is coupled to a selection voltage Vselect, and the second end of the transistor switch 213 is coupled to a signal line 201. In this embodiment, the sampling circuit 110 can perform correlated triple sampling (CTS) to obtain the first voltage, the second voltage, and the sampling voltage of the optical sensor 200 during different periods via the amplifier 120, and perform operations on the first voltage, the second voltage, and the sampling voltage to obtain the sensed voltage of the optical sensor 200.

[0069] Figure 2 It is a schematic diagram of the architecture of the sampling circuit 310 of an embodiment of the present disclosure. In an embodiment of the present disclosure, Figure 1 The sampling circuit 110 can be implemented, for example, as Figure 2 The schematic diagram of the architecture of the sampling circuit 310. Refer to Figure 2 , the sampling circuit 310 includes a switch circuit 311, subtraction operation units 312, 313, a division operation unit 314, and an analog-to-digital converter (ADC) 315. In this embodiment, the switch circuit 311 includes switches 311_1 to 311_3 and capacitors 311_4 to 311_6. The switch circuit 311 is coupled to an input voltage Vin, where the input voltage Vin can be from Figure 1At the output terminal 1203 of the amplifier 120. In this embodiment, the first terminal of the switch 311_1 receives the input voltage Vin, and the second terminal of the switch 311_1 is coupled to the first terminal of the capacitor 311_4 and the subtraction operation unit 312. The second terminal of the capacitor 311_4 is coupled to the ground voltage VGND. The first terminal of the switch 311_2 receives the input voltage Vin, and the second terminal of the switch 311_2 is coupled to the first terminal of the capacitor 311_5 and the subtraction operation units 312 and 313. The second terminal of the capacitor 311_5 is coupled to the ground voltage VGND. The first terminal of the switch 311_3 receives the input voltage Vin, and the second terminal of the switch 311_3 is coupled to the first terminal of the capacitor 311_6 and the subtraction operation unit 313. The second terminal of the capacitor 311_6 is coupled to the ground voltage VGND. The subtraction operation units 312 and 313 are further coupled to the division operation unit 314, and the division operation unit 314 is further coupled to the analog-to-digital converter 315.

[0070] In this embodiment, the sampling circuit 310 can sample Figure 1 the sampling voltage VS generated by the optical sensor 200, such as after sensing an X-ray signal, through the amplifier 120. Specifically, the switches 311_1 to 311_3 of the switch circuit 311 respectively receive the switching signals ψ1 to ψ3 to receive the sampling voltage VS, the first voltage V1, and the second voltage V2 during different sampling periods and store them in the capacitors 311_4 to 311_6. The capacitor 311_4 can store the sampling voltage VS and provide it to the subtraction operation unit 312. The capacitor 311_5 can store the second voltage V2 and provide it to the subtraction operation units 312 and 313. The capacitor 311_6 can store the first voltage V1 and provide it to the subtraction operation unit 313. The subtraction operation unit 312 can perform the operation as shown in the following formula (1), where the subtraction operation unit 312 can subtract the sampling voltage VS from the second voltage V2 to obtain the third voltage V3. The subtraction operation unit 313 can perform the operation as shown in the following formula (2), where the subtraction operation unit 313 can subtract the first voltage V1 from the second voltage V2 to obtain the fourth voltage V4. Then, the subtraction operation units 312 and 313 can respectively provide the third voltage V3 and the fourth voltage V4 to the division operation unit 314, and the division operation unit 314 can perform the operation as shown in the following formula (3), where the division operation unit 314 can divide the third voltage by the fourth voltage to obtain the sensed voltage Vout. In this embodiment, the analog-to-digital converter 315 can convert the sensed voltage Vout into a digital signal VD.

[0071] V3 = VS - V2 ………… Formula (1)

[0072] V4 = V1 - V2 ………… Formula (2)

[0073]

[0074] Figure 3 is a circuit schematic diagram of a subtractor circuit 400 according to an embodiment of the present disclosure. In an embodiment of the present disclosure, Figure 2 the switching circuit 311 and the subtraction operation units 312, 313 can be implemented, for example, as Figure 3 the circuit schematic diagram of the subtractor circuit 400. Referring to Figure 3 , the subtractor circuit 400 includes amplifiers 411, 412, 413, transistor switches 421 to 433, and capacitors 441 to 445. Specifically, the non-inverting input terminal of amplifier 411 receives an input voltage Vin, and the inverting input terminal of amplifier 411 is coupled to a ground voltage VGND. The non-inverting input terminal of amplifier 411 is also coupled to the first terminal of capacitor 441 and the first terminal of transistor switch 421. The second terminal of capacitor 441 and the second terminal of transistor switch 421 are coupled to the output terminal of amplifier 411. The control terminal of transistor switch 421 receives a reset signal ψreset. In this embodiment, the first terminal of transistor switch 422 is coupled to the output terminal of amplifier 411, and the control terminal of transistor switch 422 receives a switching signal ψ2. The second terminal of transistor switch 422 is coupled to the first terminal (positive electrode) of capacitor 442 and the first terminal of transistor switch 423. The control terminal of transistor switch 423 receives a switching signal ψ4, and the second terminal of transistor switch 423 is coupled to the non-inverting input terminal of amplifier 412. The inverting input terminal and the output terminal of amplifier 412 are coupled to form a voltage follower. The second terminal (negative electrode) of capacitor 442 is coupled to the first terminal of transistor switch 425 and the first terminal of transistor switch 424. The control terminal of transistor switch 425 receives a switching signal ψ2, and the second terminal of transistor switch 425 is coupled to the ground voltage VGND.

[0075] In this embodiment, the first terminal of transistor switch 427 is coupled to the output terminal of amplifier 411, and the control terminal of transistor switch 427 receives switching signal ψ3. The second terminal of transistor switch 427 is coupled to the first terminal (negative electrode) of capacitor 443, the first terminal (negative electrode) of capacitor 444, and the first terminal of transistor switch 428. The control terminal of transistor switch 428 receives switching signal ψ4, and the second terminal of transistor switch 428 is coupled to ground voltage VGND. The second terminal (positive electrode) of capacitor 443 is coupled to the second terminal of transistor switch 424 and the first terminal of transistor switch 426. The control terminal of transistor switch 424 receives switching signal ψ4. The control terminal of transistor switch 426 receives switching signal ψ3, and the second terminal of transistor switch 426 is coupled to ground voltage VGND. The second terminal (positive electrode) of capacitor 444 is coupled to the first terminal of transistor switch 430 and the first terminal of transistor switch 429. The control terminal of transistor switch 430 receives switching signal ψ4. The control terminal of transistor switch 429 receives switching signal ψ3, and the second terminal of transistor switch 429 is coupled to ground voltage VGND.

[0076] In this embodiment, the first terminal of transistor switch 431 is coupled to the output terminal of amplifier 411, and the control terminal of transistor switch 431 receives switching signal ψ1. The second terminal of transistor switch 431 is coupled to the first terminal (positive electrode) of capacitor 445 and the first terminal of transistor switch 433. The control terminal of transistor switch 433 receives switching signal ψ4, and the second terminal of transistor switch 433 is coupled to the non-inverting input terminal of amplifier 413. The inverting input terminal and the output terminal of amplifier 413 are coupled to form a voltage follower. The second terminal (negative electrode) of capacitor 445 is coupled to the second terminal of transistor switch 430 and the first terminal of transistor switch 432. The control terminal of transistor switch 432 receives switching signal ψ1, and the second terminal of transistor switch 432 is coupled to ground voltage VGND. In this embodiment, Figure 2 the switch 311_1 of Figure 3 may correspond to, for example, Figure 2 the transistor switch 431 of Figure 4 and the capacitor 311_4 of Figure 2 may correspond to, for example, Figure 3 the transistor switch 427 of Figure 2 and the capacitor 311_5 of Figure 3 may correspond to, for example, the capacitors 444, 443 of Figure 2 the switch 311_3 of Figure 3 may correspond to, for example, Figure 2 the transistor switch 422 of Figure 3 and the capacitor 311_6 of

[0077] In this embodiment, the transistor switches 421, 422, 425, 426, 427, 429, 431, 432 may be P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), and the transistor switches 423, 424, 428, 430, 433 may be N-type metal-oxide-semiconductor field-effect transistors, but the present disclosure is not limited thereto. In this embodiment, when the transistor switches 421 to 433 are switched by the reset signal ψreset and the switching signals ψ1 to ψ3, the capacitor 442 may store the first voltage V1 (+V1). The capacitors 443, 444 may store the second voltage V2 (-V2). The capacitor 445 may store the sampling voltage VS (+VS). And when the transistor switches 421 to 433 are switched by the switching signal ψ4, the output terminal of the amplifier 412 may output the fourth voltage V4 (= the first voltage V1 - the second voltage V2), and the output terminal of the amplifier 413 may output the third voltage V3 (= the sampling voltage VS - the second voltage V2).

[0078] Figure 4 is a signal timing diagram of the processing circuit 100 according to an embodiment of the present disclosure. Figure 4 The signal timing of is an implementation manner corresponding to Figures 1 to 3 each switching signal and voltage signal change in an embodiment of the present disclosure. First, refer to Figure 1 and Figure 4 , during the integration period Ta (time t0 to time t1), the transistor switches 211 to 213 of the optical sensor 200 are in the non-conducting state, and the photodiode 214 causes the voltage Vgs at the control terminal of the transistor 212 to rise due to light sensing. During the sampling period Tb (time t1 to time t7), the selection voltage Vselect is switched to a high potential between time t1 and time t7, so that the transistor switch 213 is conducting between time t1 and time t7. The scan voltage Vscan is switched to a high potential between time t3 and time t7, so that the transistor switch 211 is conducting between time t3 and time t7. The set voltage Vset is switched from a low potential (the second voltage V2) to a high potential (the first voltage V1) at time t3, and remains at the high potential between time t3 and time t5, so that the control terminal of the transistor switch 212 receives a high potential (the first voltage V1) between time t3 and time t5.

[0079] Next, refer to Figure 3 and Figure 4, during the sampling period Tb (from time t1 to time t7), the switching signal ψ1 switches from a high potential to a low potential between time t1 and time t2 (i.e., the first sampling period), and the reset signal ψreset maintains a high potential between time t1 and time t2, so as to turn on the transistor switches 431 and 432, and make the capacitor 445 store the sampling voltage VS (+VS). The reset signal ψreset switches from a high potential to a low potential between time t2 and time t3 to reset the capacitor 441 for the next sampling. Then, the switching signal ψ2 switches from a high potential to a low potential between time t3 and time t4 (i.e., the second sampling period), and the reset signal ψreset maintains a high potential between time t3 and time t4, so as to turn on the transistor switches 422 and 425, and make the capacitor 442 store the first voltage V1 (+V1). The reset signal ψreset switches from a high potential to a low potential between time t4 and time t5 to reset the capacitor 441 for the next sampling. Then, the switching signal ψ3 switches from a high potential to a low potential between time t5 and time t6 (i.e., the third sampling period), and the reset signal ψreset maintains a high potential between time t5 and time t6, so as to turn on the transistor switches 426, 427, and 429, and make the capacitors 443 and 444 store the second voltage V2 (-V2) respectively. The reset signal ψreset switches from a high potential to a low potential between time t6 and time t7 to reset the capacitor 441. Finally, during the readout period Tc, the switching signal ψ4 switches from a high potential to a low potential (or from a low potential to a high potential, depending on the type of transistor switch used) between time t7 and time t8, so as to turn on the transistor switches 423, 424, 428, 430, and 433. Therefore, the output terminal of the amplifier 412 can output the fourth voltage V4 (= the first voltage V1 - the second voltage V2), and the output terminal of the amplifier 413 can output the third voltage V3 (= the sampling voltage VS - the second voltage V2). And, as Figure 2 The division operation unit 314 as shown can perform the operation as shown in formula (3) to generate the sensed voltage Vout.

[0080] Refer back to Figure 1 and Figure 4, according to the timing relationship of the switching signals ψ1 to ψ3, the sampling circuit 110 can sequentially obtain the sampling voltage VS, the first voltage V1, and the second voltage V2 during the first sampling period (time t1 to time t2), the second sampling period (time t3 to time t4), and the third sampling period (time t5 to time t6), respectively. It should be noted that the first reset period (time t2 to time t3) is included between the first sampling period and the second sampling period, and the sampling circuit 110 obtains the sampling voltage VS via the storage capacitor 215 of the optical sensor 200 before the first reset period. The second reset period (time t4 to time t5) is included between the second sampling period and the third sampling period, and the sampling circuit 110 obtains the first voltage V1 via the set voltage Vset at a high potential before the second reset period. The third reset period (time t6 to time t7) is included between the third sampling period and the read period Tc, and the sampling circuit 110 obtains the second voltage V2 via the set voltage Vset at a low potential before the third reset period. In this regard, the voltage magnitude relationship of the sampling voltage VS, the first voltage V1, and the second voltage V2 in this embodiment can be as Figure 5 shown. Figure 5 is a voltage relationship diagram of the first voltage V1, the second voltage V2, and the sampling voltage VS of an embodiment of the present disclosure. As Figure 5 shown, the sampling voltage VS is between the first voltage V1 and the second voltage V2.

[0081] Incidentally, in a measurement embodiment, the measurer can, for example, measure the electrical signal between at least one optical sensor and the readout circuit among the measurement objects (for example: the sensing array), so as to judge whether the measurement object implements the architecture and timing design of the optical sensor and the processing circuit as in the present disclosure according to whether the measured voltage magnitude and signal timing relationship are the same as the results of Figure 4 for each switching signal and voltage signal.

[0082] That is to say, referring to Figure 2 and Figure 4 , the sampling circuit 310 can obtain the sampling voltage VS, the first voltage V1, and the second voltage V2 in a related triple-sampling manner during the sampling period Tb, and perform the operations of the above formulas (1) and (2) through the subtraction operation units 312 and 313 to obtain the third voltage V3 and the fourth voltage V4. And the division operation unit 314 can perform the operation of the above formula (3) to obtain the sensed voltage Vout and provide it to the analog-to-digital converter 315. The analog-to-digital converter 315 can convert the sensed voltage Vout into a digital signal VD. It should be noted that according to Figures 1 to 5Regarding the read timing and voltage magnitude relationship of the sampling voltage VS, the first voltage V1, and the second voltage V2, the processing circuit 100 can effectively compensate for the influence of process variations of each transistor in the optical sensor 200 on the sensing signal, such as the threshold voltage (VTH) and the mobility, or can achieve the effect of reducing or eliminating background noise, so as to improve the read quality of the sensing signal of the optical sensor 200 with high dynamic range or high resolution.

[0083] Figure 6 It is a circuit schematic diagram of the divider circuit 600 according to an embodiment of the present disclosure. In an embodiment of the present disclosure, Figure 2 The division operation unit 314 can be implemented, for example, as Figure 6 The circuit schematic diagram of the divider circuit 600. Refer to Figure 6 , the divider circuit 600 includes amplifiers 611 to 614, resistor units 621 to 628, and transistor switches 631 to 633. In one embodiment, the transistor switches 631 to 633 can be bipolar junction transistors (BJTs) respectively. For example, the transistor switches 631 to 633 can be N-type bipolar junction transistors or P-type bipolar junction transistors respectively, and the present disclosure is not limited thereto. The resistor units 621 to 628 can be composed of one or more resistors respectively. In another embodiment, the resistor units 621 to 628 can be one or more equivalent resistors. It should be noted that the resistor units 621 to 628 do not necessarily all have to be equivalent resistors or resistors, and some can be equivalent resistors and some can be resistors. For example, the resistor units 621 to 624 are equivalent resistors, and the resistor units 625 to 628 are resistors. In this embodiment, the first end of the resistor unit 621 can receive the third voltage V3 (= sampling voltage VS - second voltage V2) output by the subtractor circuit 400 as Figure 3 , and the second end of the resistor unit 621 is coupled to the inverting input terminal of the amplifier 611. The inverting input terminal of the amplifier 611 is coupled to the collector (C) of the transistor switch 631, and the emitter (E) of the transistor switch 631 is coupled to the output terminal of the amplifier 611. The base (B) of the transistor switch 631 is coupled to the ground voltage VGND. The non-inverting input terminal of the amplifier 611 is coupled to the ground voltage VGND. The output terminal of the amplifier 611 is coupled to the first end of the resistor unit 623. In this embodiment, the first end of the resistor unit 622 can receive as Figure 3The fourth voltage V4 (=the first voltage V1 - the second voltage V2) output by the subtractor circuit 400, and the second end of the resistor unit 622 is coupled to the inverting input terminal of the amplifier 612. The inverting input terminal of the amplifier 612 is coupled to the collector of the transistor switch 633, and the emitter of the transistor switch 633 is coupled to the output terminal of the amplifier 612. The base of the transistor switch 633 is coupled to the ground voltage VGND. The non-inverting input terminal of the amplifier 612 is coupled to the ground voltage VGND. The output terminal of the amplifier 612 is coupled to the first end of the resistor unit 624.

[0084] In this embodiment, the second end of the resistor unit 623 is coupled to the inverting input terminal of the amplifier 613 and the first end of the resistor unit 625. The second end of the resistor unit 625 is coupled to the output terminal of the amplifier 613. The second end of the resistor unit 624 is coupled to the non-inverting input terminal of the amplifier 613 and the first end of the resistor unit 626. The second end of the resistor unit 626 is coupled to the ground voltage VGND and the first end of the resistor unit 628. The output terminal of the amplifier 613 is coupled to the collector of the transistor switch 632, and the collector of the transistor switch 632 is coupled to the base of the transistor switch 632. The emitter of the transistor switch 632 is coupled to the inverting input terminal of the amplifier 614. In this embodiment, the inverting input terminal of the amplifier 614 is further coupled to the first end of the resistor unit 627, and the second end of the resistor unit 627 is coupled to the output terminal of the amplifier 614. The non-inverting input terminal of the amplifier 614 is coupled to the second end of the resistor unit 628. The output terminal of the amplifier 614 can output the sensed voltage Vout.

[0085] In this embodiment, the amplifier 611 can perform the operation of taking the logarithm of the third voltage V3, and the amplifier 612 can perform the operation of taking the logarithm of the fourth voltage V4. The amplifier 613 can perform the subtraction of the logarithmically taken third voltage V3 and the logarithmically taken fourth voltage V4 according to the following formula (4), and the amplifier 614 can perform the operation of taking the antilogarithm of the output result of the amplifier 613 to obtain the output sensed voltage Vout. It should be noted that the values of the coefficients α1, α2, α3 are determined by the resistance values of the resistor units 621 to 628. In one embodiment, if the resistance values of the resistor units 621 to 624, 627, 628 are the same, then α3 is 1.

[0086]

[0087] Figure 7 is a schematic diagram of the architecture of the sampling circuit 700 according to another embodiment of the present disclosure. Refer to Figure 7, the sampling circuit 700 of this embodiment includes a plurality of subtractor circuits 710_1 to 710_N, a buffer circuit 720, a divider circuit 730, and an analog-to-digital converter 740, where N is a positive integer. The plurality of subtractor circuits 710_1 to 710_N are coupled to the buffer circuit 720. The buffer circuit 720 is coupled to the divider circuit 730. The divider circuit 730 is coupled to the analog-to-digital converter 740. First, refer to Figure 1 , since Figure 1 's sampling circuit 110 receives one or a row of photosensors 200 through the signal line 201, so Figure 1 's sampling circuit 110 may include one Figure 3 's subtractor circuit 400 and one Figure 6 's divider circuit 600. However, compared with Figure 1 , the subtractor circuits 710_1 to 710_N of the sampling circuit 700 of this embodiment can be coupled to multiple or multiple rows of photosensors through multiple signal lines, so that the subtractor circuits 710_1 to 710_N obtain the first voltage, the second voltage, and the sampling voltage of their respective corresponding photosensors. And, the first voltage, the second voltage, and the sampling voltage respectively provided by the subtractor circuits 710_1 to 710_N are temporarily stored via the buffer circuit 720 and output to the divider circuit 730 for operation in a time-sharing manner. The divider circuit 730 can output the sensed voltages of multiple photosensors to the analog-to-digital converter 740 in a time-sharing manner. In other words, since the sampling circuit 700 is disposed in the peripheral area P2 of the panel as shown in Figure 1 , the design of the sampling circuit 700 of this embodiment can effectively reduce the area of the processing circuit in the peripheral area P2, so as to achieve the effects of cost savings, narrow borders, or enable the peripheral area P2 of the panel as shown in Figure 1 to obtain additional space to configure other functional circuits.

[0088] Figure 8 is a flowchart of a signal processing method of a sampling circuit according to an embodiment of the present disclosure. Refer to Figure 2 and Figure 8 , the signal processing method of this embodiment is applicable to the sampling circuit 310 of Figure 2 embodiment. The sampling circuit 310 can pass through Figure 1The amplifier 120 samples the optical sensor 200. In step S810, the sampling circuit 310 can obtain a sampling voltage VS, and the switching circuit 311 stores the sampling voltage VS in the capacitor 311_4 according to the switching results of the switching signals ψ1 to ψ3. In step S820, the sampling circuit 310 can obtain a first voltage V1, and the switching circuit 311 stores the first voltage V1 in the capacitor 311_6 according to the switching results of the switching signals ψ1 to ψ3. In step S830, the sampling circuit 310 can obtain a second voltage V2, and the switching circuit 311 stores the second voltage V2 in the capacitor 311_5 according to the switching results of the switching signals ψ1 to ψ3. The sampling voltage VS is between the first voltage V1 and the second voltage V2. In step S840, the subtraction unit 312 of the sampling circuit 310 subtracts the second voltage V2 from the sampling voltage VS to obtain a third voltage V3. In step S850, the subtraction unit 313 of the sampling circuit 310 subtracts the first voltage V1 from the second voltage V2 to obtain a fourth voltage V4. In step S860, the division unit 314 of the sampling circuit 310 divides the third voltage V3 by the fourth voltage V4 to obtain a sensed voltage Vout. Therefore, the signal processing method of this embodiment can enable the sampling circuit 310 to effectively obtain the sensed voltage Vout.

[0089] In addition, for the relevant implementation content and circuit characteristics of the sampling circuit 310 in this embodiment, sufficient teachings, suggestions, and implementation descriptions can be obtained by referring to the description of the above Figures 1 to 7 embodiment, so no further elaboration will be provided.

[0090] In summary, the processing circuit of the present disclosure can read the sensed voltage of the optical sensor through a relevant triple-sampling method to effectively compensate for the problem of sensed signal drift or the influence of background noise caused by process variations of transistors in the optical sensor, for example, the influence of the threshold voltage or drift rate can be eliminated. Therefore, the processing circuit of the present disclosure can improve the readout quality of the sensed signal for optical sensors with high dynamic range or high resolution.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, and are not intended to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A processing circuit adapted to read a sensing voltage of an X-ray sensor, characterized in that: include: an amplifier comprising an inverting input terminal, a non-inverting input terminal, and an output terminal, wherein the inverting input terminal of the amplifier is coupled to the X-ray sensor; as well as a sampling circuit coupled to the output terminal of the amplifier, The sampling circuit obtains a first voltage, a second voltage, and a sampling voltage of the X-ray sensor at different times, and the sampling voltage is between the first voltage and the second voltage. During a readout period, the sampling circuit subtracts the second voltage from the sampling voltage to obtain a third voltage, subtracts the first voltage from the second voltage to obtain a fourth voltage, and divides the third voltage by the fourth voltage to read the sensing voltage of the X-ray sensor.

2. The processing circuit according to claim 1, wherein: The sampling circuit sequentially obtains the sampled voltage, the first voltage, and the second voltage in a first sampling period, a second sampling period, and a third sampling period respectively.

3. The processing circuit according to claim 2, wherein: A reset period is included between the first sampling period and the second sampling period, wherein the sampling circuit obtains the sample voltage via the storage capacitor of the X-ray sensor before the reset period.

4. The processing circuit according to claim 1, wherein: The sampling circuit includes a subtractor circuit and a divider circuit.

5. The processing circuit according to claim 4, characterized in that: The divider circuit is composed of a plurality of bipolar junction transistors and a plurality of amplifiers.

6. The processing circuit according to claim 4, characterized in that The subtractor circuit is configured to subtract the second voltage from the sampling voltage to output the third voltage, and to subtract the first voltage from the second voltage to output the fourth voltage.

7. The processing circuit according to claim 4, characterized in that: The sampling circuit further includes a plurality of subtractor circuits and a buffer circuit, and the plurality of subtractor circuits are coupled to the divider circuit via the buffer circuit.

8. The processing circuit according to claim 1, wherein: The sampling circuit further includes: The analog-to-digital converter is coupled to the sampling circuit and is used for converting the sensing voltage into a digital signal.

9. A signal processing method for a sampling circuit, characterized in that: The sampling circuit is coupled to the output terminal of the amplifier, and the X-ray sensor is coupled to the inverting input terminal of the amplifier. The signal processing method includes: Obtaining a sampling voltage of the X-ray sensor through the sampling circuit; Obtaining a first voltage of the X-ray sensor through the sampling circuit; Obtaining a second voltage of the X-ray sensor through the sampling circuit; During a readout period, the sampling circuit subtracts the second voltage from the sampling voltage to obtain a third voltage, subtracts the first voltage from the second voltage to obtain a fourth voltage, and divides the third voltage by the fourth voltage to read a sensing voltage of the X-ray sensor.

10. The signal processing method according to claim 9, characterized in that: The sampling voltage is between the first voltage and the second voltage.

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