Circuit board and display device including the same

Abstract

A circuit board and a display device including the same are provided. The circuit board includes a signal line for transmitting a signal, a first metal layer overlapping the signal line, a first conductive layer spaced apart from the first metal layer, a base layer insulating the signal line from the first metal layer and the first conductive layer, and a first capacitor including a first terminal electrically coupled to the first metal layer and a second terminal electrically coupled to the first conductive layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0092391, filed on July 24, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present invention generally relate to display devices, and more specifically, to display devices comprising circuit boards provided with signal lines. Background Technology

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation system units, and game consoles are equipped with display devices for displaying images. The display device includes a display panel and a driver integrated circuit (IC) connected to one side of the display panel to drive it. The driver IC generates drive signals and provides these signals to the display panel.

[0005] The driver integrated circuit can be mounted on a circuit board, such as a printed circuit board (PCB) or a flexible printed circuit board (FPCB). One side of the circuit board can be connected to one side of the display panel, and the other side of the circuit board can be connected to the main processor. The driver integrated circuit can receive drive voltages and control signals from the main processor through the circuit board.

[0006] The circuit board may include signal lines to transmit control signals received from the main processor to the driver integrated circuit. The signal transmission characteristics of the signal lines on the circuit board may affect the display quality of the display device.

[0007] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0008] The applicant recognizes that signal transmission characteristics deteriorate as the length of signal lines on the circuit board of the display device increases.

[0009] The circuit board and display device comprising the circuit board, constructed according to the principles and illustrative implementation of the present invention, can improve signal transmission characteristics by, for example, adjusting the capacitance between the signal lines disposed in the circuit board and the conductive layer of the circuit board. Accordingly, even when the length of the signal lines is increased, the circuit board can reduce or prevent the degradation of signal transmission characteristics. Therefore, the degradation of the display quality of the display device can be reduced or prevented.

[0010] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or can be learned by practice of the inventive concept.

[0011] According to an aspect of the present application, a circuit board for a display device includes a signal line for transmitting a signal, a first metal layer overlapping the signal line, a first conductive layer spaced apart from the first metal layer, a base layer insulating the signal line from the first metal layer and the first conductive layer, and a first capacitor including a first terminal electrically coupled to the first metal layer and a second terminal electrically coupled to the first conductive layer.

[0012] The first metal layer can include a first floating layer having a substantially polygonal shape completely overlapping the signal line.

[0013] The first conductive layer can be configured to receive a ground voltage.

[0014] The first terminal of the first capacitor can directly contact the first metal layer, and the second terminal of the first capacitor can directly contact the first conductive layer.

[0015] The first metal layer and the first conductive layer can be formed of the same material and disposed on a first surface of the base layer.

[0016] The circuit board can further include a second metal layer overlapping the signal line, a second conductive layer spaced apart from the second metal layer, and a second capacitor including a first terminal electrically coupled to the second metal layer and a second terminal electrically coupled to the second conductive layer.

[0017] The second metal layer and the second conductive layer can be formed of the same material and disposed on a second surface of the base layer, and the base layer can insulate the signal line from the second metal layer and the second conductive layer.

[0018] A capacitance between the signal line and the first conductive layer can be determined by a parasitic capacitance between the signal line and the first metal layer and a first capacitance of the first capacitor, and the first capacitance of the first capacitor can be determined with respect to the parasitic capacitance between the signal line and the first metal layer.

[0019] According to another aspect of the present application, a display device includes a display panel for displaying an image and including a first pad, and a circuit board including a second pad to be connected to the first pad of the display panel. The circuit board can include a signal line for transmitting a signal, a first metal layer overlapping the signal line, a first conductive layer spaced apart from the first metal layer, a base layer insulating the signal line from the first metal layer and the first conductive layer, and a first capacitor including a first terminal electrically coupled to the first metal layer and a second terminal electrically coupled to the first conductive layer.

[0020] The circuit board can further include a driving circuit to be electrically connected to the second pad.

[0021] The circuit board can further include a connector, and the signal line can be electrically coupled to the driving circuit and the connector.

[0022] The first metal layer can include a first floating layer having a substantially polygonal shape that completely overlaps the signal line.

[0023] The first conductive layer can be configured to receive a ground voltage.

[0024] The first terminal of the first capacitor can directly contact the first metal layer, and the second terminal of the first capacitor can directly contact the first conductive layer.

[0025] The first metal layer and the first conductive layer can be formed of the same material and can be disposed on the first surface of the base layer.

[0026] The circuit board can further include a second metal layer overlapping the signal line, a second conductive layer spaced apart from the second metal layer, and a second capacitor including a first terminal electrically coupled to the second metal layer and a second terminal electrically coupled to the second conductive layer.

[0027] The second metal layer and the second conductive layer can be formed of the same material and disposed on the second surface of the base layer, and the base layer can insulate the signal line from the second metal layer and the second conductive layer.

[0028] The first capacitance of the first capacitor can be determined with respect to a parasitic capacitance between the signal line and the first metal layer.

[0029] The circuit board can include a flexible circuit board.

[0030] The base layer can include an insulating layer having flexibility.

[0031] It is to be understood that both the foregoing general description and the following detailed description are illustrative and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application.

[0033] Figure 1 is a perspective view of an embodiment of a display device constructed in accordance with the principles of the present application.

[0034] Figure 2A and Figure 2B is Figure 1 an exploded perspective view of the display device of

[0035] Figure 3 isFigure 2A plan view of the display panel and the circuit board shown in

[0036] Figure 4 is a cross-sectional view illustratively showing the connection between the display panel and the circuit board of Figure 2A

[0037] Figure 5 is a cross-sectional view of a comparative embodiment of the circuit board taken along line I-I' of Figure 3

[0038] Figure 6 is a cross-sectional view of another embodiment of the circuit board taken along line I-I' of Figure 3

[0039] Figure 7A is a schematic diagram showing the capacitance between the first signal line and the upper conductive layer of Figure 6

[0040] Figure 7B is a schematic diagram showing the capacitance between the second signal line and the upper conductive layer of Figure 6

[0041] Figure 8 is a cross-sectional view of yet another embodiment of the circuit board taken along line I-I' of Figure 3

[0042] Figure 9 is a schematic diagram showing the capacitance between the first signal line and the lower conductive layer of Figure 8

[0043] Figure 10 is a plan view illustratively showing the upper floating layer and the upper conductive layer of the circuit board shown in Figure 3

[0044] Figure 11 and Figure 12 is a graph illustratively showing the insertion loss as a function of the frequency of the signal transmitted through the signal line. DETAILED DESCRIPTION

[0045] ​​​​​​​​In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of an apparatus or method that employs one or more inventive concepts disclosed herein. It will be apparent, however, that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments. Furthermore, various embodiments can be different, but not necessarily excluding, one another. For example, specific shapes, configurations, and characteristics of an embodiment can be used or implemented in another embodiment without departing from the inventive concepts.

[0046] Unless otherwise indicated, the illustrated embodiments will be understood as providing illustrative features that can vary in practice. Thus, unless otherwise indicated, features, components, modules, layers, films, panels, regions, and / or aspects of various embodiments (hereinafter sometimes collectively referred to as "elements") can be combined, separated, interchanged, and / or rearranged without departing from the inventive concepts.

[0047] The use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries, of the elements shown. As such, no inference should be drawn that the specific materials, shapes, configurations, relative sizes, proportions, etc. shown in the drawings are intended to convey any preference or requirement for a particular material, shape, configuration, relative size, proportion, etc. In addition, elements shown in the drawings are not necessarily drawn to scale. The particular implementations shown in the drawings are illustrative only and other implementations can be used without departing from the inventive concepts.

[0048] When an element or layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, or “directly coupled to” another element or layer, then there are no intervening elements or layers present. For the purposes of this disclosure, the term “connected” can include physical, electrical, and / or fluidic connections, with or without intervening elements. In addition, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to the three axes of a rectangular coordinate system, such as the x-axis, the y-axis, and the z-axis, and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one of the group consisting of X, Y, and Z” can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0049] Although the terms “first”, “second”, etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0050] Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper”, “on” or “over”, “side” (as in “sidewall”), and the like, can be used herein for descriptive purposes, and can refer to the relative positions of elements in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the drawings. For example, if a device is turned over in the drawing, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the terms “below” and “beneath” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or located in another orientation) and the spatially relative descriptors used herein interpreted accordingly.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms "comprise", "comprising", "include", "including", "contain", "containing" and / or "comprising" when used in this specification are taken to specify the presence of stated features, integers, steps, operations, elements, components and / or groups thereof but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0053] Figure 1 A perspective view of an embodiment of a display device constructed in accordance with the principles of the present invention.

[0054] Referring to Figure 1 , the display device DD can be a liquid crystal display device, a field emission display device, a plasma display device, or an organic light emitting display device. However, this is merely exemplary. The display device DD is not limited to the types of display devices listed above.

[0055] In Figure 1 , a flat panel display device is shown as an example of the display device DD. However, embodiments of the present invention are not limited thereto. The display device DD can be a foldable display device or a rollable display device, and is not particularly limited. The display device DD can be used in large electronic devices such as televisions and monitors, and in small and medium-sized electronic devices such as mobile phones, tablet computers, car navigation system units, game consoles, and smart watches, etc.

[0056] The display device DD can display an image toward a third direction DR3 on a display surface IS parallel to each of the first direction DR1 and the second direction DR2. The display surface IS of the display device DD can include one or more regions. The display surface IS on which the image is displayed can correspond to a front surface of the display device DD. The display device DD includes a display region DA on which the image IM is displayed and a non-display region NDA adjacent to the display region DA. The non-display region NDA is a region on which no image is displayed. The non-display region NDA can be referred to as a bezel region.

[0057] As an example, the display region DA can have a substantially quadrangular shape. The non-display region NDA can surround the display region DA. However, embodiments of the present disclosure are not limited thereto. The shape of the display region DA and the shape of the non-display region NDA can be designed in correlation.

[0058] Figure 2A and Figure 2B is Figure 1 an exploded perspective view of a display device. Specifically, Figure 2A shows a display device DD including a display panel DP in an unfolded (i.e., flat) state, and Figure 2B shows a display device DD including a display panel DP in a folded state.

[0059] Referring to Figure 2A with Figure 2B , the display device DD includes a window member WM, an anti-reflection unit ARU, a display panel DP, a circuit board FCB, a support member SPP, and a lower case or bracket BC.

[0060] The window member WM provides a front surface of the display device DD. The window member WM can include a glass substrate, a sapphire substrate, a plastic substrate, or the like. Also, the window member WM can include functional coating layers such as a fingerprint-proof layer, an anti-reflection layer, and a hard coating layer. In embodiments, Figure 2A and Figure 2B shows the window member WM having a substantially flat shape in the display region DA. However, the shape of the window member WM can be changed. An edge of the window member WM facing the first direction DR1 can provide a curved surface.

[0061] The front surface (or upper surface, or first surface) and the back surface (or lower surface, or second surface) of each member are defined based on the direction of the display image. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be converted to different directions.

[0062] The display panel DP is provided on the rear surface of the window member WM and generates an image. Also, the display panel DP can detect a touch input of a user. The display panel DP providing a substantially flat display surface is illustratively shown. However, the shape of the display panel DP can be changed. An edge of the display panel DP facing the first direction DR1 can be bent from the center portion to provide a curved surface.

[0063] The display panel DP is a panel displaying an image, and can be any one of a liquid crystal display (LCD) panel, an electrophoretic display panel, an organic light emitting diode (OLED) panel, a light emitting diode (LED) panel, an inorganic electroluminescence (EL) display panel, a field emission display (FED) panel, a surface-conduction electron emitter display (SED) panel, a plasma display panel (PDP), a cathode ray tube (CRT), an ultra-small light emitting device display panel, a micro LED display panel, a quantum dot panel, and other known display panels. Hereinafter, an organic light emitting display device will be illustratively described, and the display panel DP will also be described as an organic light emitting panel. However, the display device DD and the display panel DP are not limited thereto. Various types of display devices and display panels can be used.

[0064] The display panel DP can include a first non-bendable portion NBA1, a second non-bendable portion NBA2, and a bendable portion BA. The first non-bendable portion NBA1 can correspond to a portion of a display area DA (see Figure 4 ) and a portion of a non-display area NDA (see Figure 4 ) of the display panel DP. The second non-bendable portion NBA2 and the bendable portion BA can correspond to the non-display area NDA (see Figure 4 ) of the display panel DP.

[0065] The bendable portion BA of the display panel DP can be disposed between the first non-bendable portion NBA1 and the second non-bendable portion NBA2. The first non-bendable portion NBA1, the bendable portion BA, and the second non-bendable portion NBA2 can be sequentially disposed in the second direction DR2. The maximum width of the bendable portion BA and the second non-bendable portion NBA2 in the first direction DR1 can be smaller than the maximum width of the first non-bendable portion NBA1.

[0066] Figure 2A The unfolded state of the display panel DP is illustratively shown, and Figure 2BA state in which the bendable portion BA of the display panel DP is bent is illustratively shown. The bendable portion BA of the display panel DP can be bent in a state in which the first non-bendable portion NBA1 of the display panel DP is coupled with the support member SPP. In a state in which the display panel DP is bent, the second non-bendable portion NBA2 of the display panel DP can overlap the first non-bendable portion NBA1 of the display panel DP. The bendable portion BA can be bent along a bending axis BX substantially parallel to the first direction DR1. The display panel DP can be accommodated within the lower case BC when bent.

[0067] The anti-reflection unit ARU is disposed between the window member WM and the display panel DP. The anti-reflection unit ARU can include a polarizing film and / or a phase retardation film. Depending on the working principle of the anti-reflection unit ARU, the number of phase retardation films and the phase retardation length of the phase retardation films can be determined. The anti-reflection unit ARU can include a color filter.

[0068] The circuit board FCB can be a printed circuit board (PCB) or a flexible printed circuit board (FPCB). One end of the circuit board FCB can be bonded on a pad provided in one area of the display panel DP to be electrically connected to the display panel DP.

[0069] The circuit board FCB can include a driving circuit DIC. The driving circuit DIC can be implemented as an integrated circuit (IC) and mounted on the circuit board FCB in a chip on film (COF) manner. One or more passive elements and active elements can also be mounted on the circuit board FCB. The other end of the circuit board FCB can include a connector CNT, which can be electrically connected to a main circuit board equipped with a main processor.

[0070] The circuit board FCB transmits a signal received from the main circuit board to the integrated circuit through a signal line, and can provide a signal output from the integrated circuit to the display panel DP.

[0071] The support member SPP is disposed on the rear surface of the display panel DP and supports the display panel DP. The support member SPP can be a metal plate having greater rigidity than a reference material. For example, the support member SPP can be a stainless steel plate. The color of the support member SPP can be black so as to block external light from being incident on the display panel DP. In another embodiment, the support member SPP can be omitted. In an embodiment, the support member SPP can be a protective film.

[0072] The window member WM and the lower case BC can be coupled to each other to accommodate the anti-reflection unit ARU, the display panel DP, the support member SPP, and the circuit board FCB.

[0073] Figure 3 is Figure 2A a plan view of the display panel and the circuit board shown in FIG. Figure 4is illustratively shown Figure 2A a cross-sectional view of a connection between the display panel and the circuit board.

[0074] Referring to Figure 3 and Figure 4 , the display device DD can include a display panel DP and a circuit board FCB. Figure 3 and Figure 4 illustrate the circuit board FCB in a deployed state. However, the circuit board FCB can be folded in the direction of the rear surface of the display panel DP.

[0075] The display panel DP includes a substrate SUB, a circuit element layer CRL, a light emitting element layer ED, and a thin film encapsulation layer TFE. The display panel DP can further include a functional layer, such as a refractive index control layer.

[0076] The substrate SUB can include at least one plastic film. The substrate SUB can include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate. The substrate SUB can be formed of a flexible material (e.g., polyimide).

[0077] The circuit element layer CRL can include one or more insulating layers, one or more conductive layers, and a semiconductor layer. The one or more conductive layers of the circuit element layer CRL can constitute a signal line or a control circuit of a pixel.

[0078] The light emitting element layer ED includes at least an organic light emitting diode. The light emitting element layer ED can further include an organic film, such as a pixel defining film.

[0079] The thin film encapsulation layer TFE encapsulates the light emitting element layer ED. The thin film encapsulation layer TFE can include at least one inorganic film (hereinafter, an encapsulation inorganic film) or at least one organic film (hereinafter, an encapsulation organic film). The encapsulation inorganic film protects the light emitting element layer ED from moisture / oxygen, and the encapsulation organic film protects the light emitting element layer ED from foreign substances such as dust particles. The encapsulation inorganic film can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The encapsulation organic film can include an acrylic organic layer, but is not limited thereto. In addition, the principles of the present application are not limited thereto, and the display panel DP can not include the thin film encapsulation layer TFE, but include an encapsulation substrate that encapsulates the light emitting element layer ED. The encapsulation substrate can be composed of glass, sapphire, plastic, etc. The thin film encapsulation layer TFE can be disposed in the non-display area NDA as well as in the display area DA.

[0080] The display panel DP includes a display area DA and a non-display area NDA in a plane. The display area DA and the non-display area NDA of the display panel DP correspond to the display area DA (see Figure 1 ) and the non-display area NDA (see Figure 1), and thus, are denoted by the same reference numerals. The display area DA and the non-display area NDA of the display panel DP can not necessarily be the same as the display area DA (see Figure 1 ) and the non-display area NDA (see Figure 1 ) of the display device DD, and can be changed depending on the structure and / or design of the display panel DP. Figure 4 The light emitting element layer ED shown in FIG. 1A can be provided in the display area DA.

[0081] The display panel DP includes one or more pixels PX. An area in which the one or more pixels PX are provided is defined as the display area DA. In the illustrated embodiment, the non-display area NDA can be defined along the edges of the display area DA.

[0082] The display panel DP can include scan lines GL, data lines DL, light emitting lines EL, scan control lines SCL, initialization voltage lines VINTL, and voltage lines VL.

[0083] On one side of the non-display area NDA, a scan driving circuit SDC to which the scan lines GL and the light emitting lines EL are connected can be provided.

[0084] The scan lines GL extend from the scan driving circuit SDC in the first direction DR1 and are connected to corresponding ones of the one or more pixels PX, respectively. Each of the light emitting lines EL extends from the scan driving circuit SDC in the first direction DR1 and can be arranged in parallel to corresponding ones of the scan lines GL. The data lines DL extend in the second direction DR2 and are connected to corresponding ones of the one or more pixels PX, respectively. The scan control lines SCL can provide a control signal to the scan driving circuit SDC. The initialization voltage lines VINTL can provide an initialization voltage to the one or more pixels PX. The voltage lines VL are connected to the one or more pixels PX and can provide a first voltage to the one or more pixels PX. The voltage lines VL can include one or more lines extending in the first direction DR1 and one or more lines extending in the second direction DR2.

[0085] Some of the scan lines GL, the data lines DL, the light emitting lines EL, the scan control lines SCL, the initialization voltage lines VINTL, and the voltage lines VL can be provided on the same layer, and some of them can be provided on different layers.

[0086] In the non-display area NDA, panel pads BP are arranged on the circuit element layer CRL of the display panel DP. The panel pads BP can be arranged side by side in the first direction DR1. The panel pads BP are shown and described as being arranged in one line in the first direction DR1, but the embodiments are not limited thereto. For example, the panel pads BP can be arranged in two or more lines, or can be arranged in a zigzag shape.

[0087] The data lines DL, the scan control lines SCL, the initialization voltage line VINTL, and the voltage line VL are connected to the panel pads BP.

[0088] The panel pads BP of the display panel DP can be connected to the substrate pads AP of the circuit board FCB. The circuit board FCB can include a drive circuit DIC. The drive circuit DIC can be composed of an integrated circuit. The circuit board FCB can be a flexible printed circuit board, and the drive circuit DIC as an integrated circuit can be mounted on the flexible printed circuit board. In Figure 3 On the circuit board FCB, one drive circuit DIC is mounted. However, many integrated circuits can be mounted on the circuit board FCB. For example, the drive circuit DIC can include a data driver (or a source driver) to drive the data lines DL of the display panel DP.

[0089] Figure 3 and Figure 4 The drive circuit DIC is shown as being disposed on the upper surface of the circuit board FCB, but the embodiments are not limited thereto. The drive circuit DIC can be disposed on the rear surface of the circuit board FCB.

[0090] Figure 3 and Figure 4 The display panel DP and the circuit board FCB are shown as being electrically connected to each other through the panel pads BP and the substrate pads AP. However, the display panel DP and the circuit board FCB can be electrically connected to each other by directly contacting each other without separate pads.

[0091] Many signal lines electrically connecting the substrate pads AP and the drive circuit DIC can be arranged on the circuit board FCB.

[0092] Figure 3 The panel pads BP of the display panel DP shown in FIG. 1 are arranged on the upper surface of the display panel DP, and the substrate pads AP are arranged on the rear surface of the circuit board FCB. Thus, when the panel pads BP and the substrate pads AP are connected, some regions of the circuit board FCB overlap with a portion of the upper side of the display panel DP.

[0093] When the panel pads BP and the substrate pads AP are connected, the panel pads BP and the substrate pads AP are not visible from the upper surface of the circuit board FCB. Thus, in Figure 3 In FIG. 1, the panel pads BP and the substrate pads AP are marked with dotted lines. In another embodiment, the panel pads BP can be arranged on the rear surface of the display panel DP, and the substrate pads AP can be arranged on the upper surface of the circuit board FCB. In this case, when the panel pads BP and the substrate pads AP are connected, some regions of the display panel DP can overlap with a portion of the upper side of the circuit board FCB.

[0094] One end of the circuit board FCB includes a connector CNT. The connector CNT can be electrically connected to a main circuit board equipped with a main processor. The connector CNT can include a land.

[0095] In the illustrated embodiment, the substrate land AP, the panel land BP, and the connector CNT are terms defined for convenience of description, and embodiments of the present application are not limited thereto.

[0096] To facilitate understanding of connection of the lands, in Figure 3 the substrate land AP and the panel land BP are shown as not being fully connected. However, it is preferable that the substrate land AP and the panel land BP be sufficiently and fully connected. When the substrate land AP and the panel land BP are sufficiently and fully connected, the control signal and the image signal from the driving circuit DIC can be transmitted to the display panel DP substantially without distortion.

[0097] The circuit board FCB can include a signal line SL electrically connected to the connector CNT. The signal line SL can include signal lines SL1 and SL2 electrically connecting the driving circuit DIC and the connector CNT. The signal line SL can further include a signal line connecting the substrate land AP or an electronic element not shown in the drawing to the connector CNT.

[0098] When the length L1 of the signal line SL between the driving circuit DIC and the connector CNT increases due to various reasons, line resistance or parasitic capacitance can increase. In this case, a signal transmitted through the signal line SL can be distorted.

[0099] The driving circuit DIC can transmit and receive a signal to and from a main processor connected with the connector CNT by any one of various interface methods. The interface method can be any one of a universal serial interface (USI), a CPU interface, an RGB interface, a mobile industry processor interface (MIPI), a mobile display digital interface (MDDI), a compact display port (CDP), a mobile pixel link (MPL), a current mode advanced differential signal (CMADS), a serial peripheral interface (SPI), an inter-integrated circuit (I2C) interface, a display port (DP) and embedded display port (eDP) interface, a camera control interface (CCI), a camera serial interface (CSI), a micro controller unit (MCU) interface, a high-definition multimedia interface (HDMI), and an in-panel interface (IPI). In addition, the interface method can be one of various high-speed serial interface methods.

[0100] As an example, a MIPI interface, which is one of high-speed interfaces, requires an insertion loss of -5 dB or more at a frequency of 1.5 GHz. However, when the length LI of the signal line SL between the drive circuit DIC and the connector CNT increases, the insertion loss is reduced to -5 dB or less, so that it can be impossible to satisfy the specifications of the MIPI interface.

[0101] Figure 5 is a cross-sectional view of an embodiment (e.g., a comparative embodiment) of a circuit board taken along a line I-I’ of Figure 3

[0102] Referring to Figure 5 , the circuit board FCB includes an upper conductive layer UML (or a first conductive layer), a base layer BL, a lower conductive layer BML (or a second conductive layer), and a signal line SL. On an upper portion of the upper conductive layer UML, a protective layer (or a coating layer) can be provided. Also, on a lower portion of the lower conductive layer BML, a protective layer can be provided. In the following description, the terms “upper portion” and “lower portion” are named only according to positions with respect to the signal line SL in the third direction DR3, and embodiments of the present application are not limited thereto.

[0103] The base layer BL can include a polyimide-based material, a polytetrafluoroethylene-based material, a material obtained by synthesizing a polyimide-based material and a polytetrafluoroethylene-based material, or an insulating layer having flexibility. Also, the base layer BL can include a first adhesive layer for coupling the insulating layer and the upper conductive layer UML, and a second adhesive layer for coupling the insulating layer and the lower conductive layer BML.

[0104] The upper conductive layer UML and the lower conductive layer BML can be formed of a conductive material such as copper. The upper conductive layer UML and the lower conductive layer BML can be electrically connected to a ground voltage in order to protect the signal line SL from electromagnetic interference (EMI) or noise. The upper conductive layer UML and the lower conductive layer BML can be electrically connected through a via hole passing through the base layer BL. Either one of the upper conductive layer UML and the lower conductive layer BML can be electrically connected to the connector CNT to receive the ground voltage.

[0105] The signal line SL can include a first signal line SL1 and a second signal line SL2. The first signal line SL1 and the second signal line SL2 can be formed of a conductive material having a predetermined width and a predetermined thickness. Figure 5 It is shown that the first signal line SL1 and the second signal line SL2 are formed on the same layer. However, the first signal line SL1 and the second signal line SL2 can be formed on different layers and overlap each other in the third direction DR3. In this case, the first signal line SL1 and the second signal line SL2 can be insulated from each other by an insulating layer.

[0106] The first signal line SL1 and the second signal line SL2 can be provided to overlap the upper conductive layer UML, as​Figure 5 As shown, the first signal line SL1 and the second signal line SL2 are spaced apart from the upper conductive layer UML by a predetermined distance d1. Additionally, the first signal line SL1 and the second signal line SL2 are spaced apart from the lower conductive layer BML by a predetermined distance.

[0107] A first parasitic capacitance Cca (or parasitic capacitance) can be formed between the first signal line SL1 and the upper conductive layer UML. A second parasitic capacitance Ccb can be formed between the second signal line SL2 and the upper conductive layer UML.

[0108] like Figure 3 As shown, when the length L1 of the signal lines SL1 and SL2 between the drive circuit DIC and the connector CNT increases, the first parasitic capacitance Cca and the second parasitic capacitance Ccb may increase. When the first parasitic capacitance Cca and the second parasitic capacitance Ccb increase, the signal transmitted through the first signal line SL1 and the second signal line SL2 may leak into the upper conductive layer UML and become distorted.

[0109] Similarly, parasitic capacitance is also formed between each of the first signal line SL1 and the second signal line SL2 and the lower conductive layer BML, which may cause the signal transmitted through the first signal line SL1 and the second signal line SL2 to be distorted.

[0110] Figure 6 It is along Figure 3 A cross-sectional view of another embodiment of the circuit board taken by line I-I'.

[0111] Reference Figure 6 The circuit board FCB includes an upper conductive layer UML (or a first conductive layer), a base layer BL, a lower conductive layer BML (or a second conductive layer), an upper floating layer UFML (or a first floating layer), and signal lines SL. A protective layer (or coating) may be provided on the upper conductive layer UML and the upper floating layer UFML. Additionally, a protective layer may be provided on the lower part of the lower conductive layer BML.

[0112] The base layer (BL) can be composed of polyimide materials, polytetrafluoroethylene materials, materials obtained by synthesizing polyimide and polytetrafluoroethylene materials, or flexible insulating materials.

[0113] The upper conductive layer UML, lower conductive layer BML, and upper floating layer UFML can be formed from a conductive material such as copper. The upper conductive layer UML and the upper floating layer UFML can be formed from the same material using the same process.

[0114] The upper conductive layer UML and the lower conductive layer BML can be electrically connected to the ground voltage to protect the signal line SL from electromagnetic interference (EMI) or noise.

[0115] The upper conductive layer UML and the upper floating layer UFML can be spaced apart in the first direction DR1 and / or the second direction DR2 (see Figure 3 As a result, the upper floating layer UFML can be maintained in an electrically floating state to which no signal is applied.

[0116] The circuit board FCB further includes a first capacitor C1. A first terminal T1 of the first capacitor C1 is connected to the upper floating layer UFML, and a second terminal T2 of the first capacitor C1 is connected to the upper conductive layer UML. The first terminal T1 of the first capacitor C1 can be directly connected to the upper floating layer UFML, and the second terminal T2 of the first capacitor C1 can be directly connected to the upper conductive layer UML. For example, even when a protective layer (or a coating layer) is provided on the upper portion of the upper floating layer UFML and on the upper portion of the upper conductive layer UML, the first terminal T1 of the first capacitor C1 can be directly electrically connected to the upper floating layer UFML, and the second terminal T2 of the first capacitor C1 can be directly electrically connected to the upper conductive layer UML.

[0117] The signal line SL can include a first signal line SL1 and a second signal line SL2. The first signal line SL1 and the second signal line SL2 can be formed of a conductive material having a predetermined width and a predetermined thickness.

[0118] The first signal line SL1 can be spaced apart from the upper floating layer UFML by a predetermined distance d1, and the second signal line SL2 can be spaced apart from the upper floating layer UFML by the predetermined distance d1. Although the spacing distance between the first signal line SL1 and the upper floating layer UFML and the spacing distance between the second signal line SL2 and the upper floating layer UFML are shown to be the same as d1, embodiments are not limited thereto. For example, the spacing distance between the first signal line SL1 and the upper floating layer UFML and the spacing distance between the second signal line SL2 and the upper floating layer UFML can be different from each other. In addition, the first signal line SL1 and the second signal line SL2 can be spaced apart from the lower conductive layer BML by a predetermined distance.

[0119] Between the first signal line SL1 and the upper floating layer UFML, a first parasitic capacitance Cc1 can be formed. Between the second signal line SL2 and the upper floating layer UFML, a second parasitic capacitance Cc2 can be formed.

[0120] Figure 7A is a conceptual schematic diagram describing a capacitance between the first signal line SL1 and the upper conductive layer UML. Figure 6

[0121] Referring to Figure 6 and Figure 7A ​The first parasitic capacitance Ccl formed between the first signal line Sll and the upper floating layer UFML is connected in series to the first capacitor Cl. When the first parasitic capacitance Ccl and the first capacitor Cl are connected in series between the first signal line Sll and the upper conductive layer UML, the total capacitance C between the first signal line Sll and the upper conductive layer UML becomes smaller than the first parasitic capacitance Ccl (C < Ccl). The capacitance C between the first signal line Sll and the upper conductive layer UML can be represented by Equation 1 below.

[0122] [Equation 1]

[0123]

[0124] As shown in Equation 1, the total capacitance C between the first signal line Sll and the upper conductive layer UML can be determined according to the capacitances of the first parasitic capacitance Ccl and the first capacitor Cl. For example, when the capacitance of the first capacitor Cl is set to correspond to the first parasitic capacitance Ccl (Cl = Ccl), the total capacitance C can be about 1 / 2 of the first parasitic capacitance Ccl. That is, when the capacitance of the first capacitor Cl is determined based on the first parasitic capacitance Ccl, the total capacitance C between the first signal line Sll and the upper conductive layer UML can be reduced. As the total capacitance C between the first signal line Sll and the upper conductive layer UML is reduced, distortion of a signal transmitted through the first signal line Sll is also reduced.

[0125] Figure 7B is a schematic view illustrating a capacitance between the second signal line SL2 and the upper conductive layer UML of Figure 6

[0126] Referring to Figure 6 and Figure 7B , the second parasitic capacitance Cc2 formed between the second signal line SL2 and the upper floating layer UFML is connected in series to the first capacitor Cl. When the second parasitic capacitance Cc2 and the first capacitor Cl are connected in series between the second signal line SL2 and the upper conductive layer UML, the total capacitance C between the second signal line SL2 and the upper conductive layer UML becomes smaller than the second parasitic capacitance Cc2 (C < Cc2). For example, when the capacitance of the first capacitor Cl is set to correspond to the second parasitic capacitance Cc2, the total capacitance C can be about 1 / 2 of the second parasitic capacitance Cc2. As the total capacitance C between the second signal line SL2 and the upper conductive layer UML is reduced, distortion of a signal transmitted through the second signal line SL2 is also reduced.

[0127] Figure 8 is a cross-sectional view of still another embodiment of a circuit board taken along line I-I' of Figure 3

[0128] Referring to Figure 8 ​​The circuit board FCB includes an upper conductive layer UML (or a first conductive layer), a base layer BL, a lower conductive layer BML (or a second conductive layer), an upper floating layer UFML (or a first floating layer), a lower floating layer BFML (or a second floating layer), and a signal line SL. On an upper portion of the upper conductive layer UML and an upper portion of the upper floating layer UFML, a protective layer (or a coating layer) can be provided. In addition, on a lower portion of the lower conductive layer BML and a lower portion of the lower floating layer BFML, a protective layer can be provided.

[0129] The base layer BL can be composed of a polyimide-based material, a polytetrafluoroethylene-based material, a material obtained by synthesizing a polyimide-based material and a polytetrafluoroethylene-based material, or an insulating material having flexibility.

[0130] The upper conductive layer UML, the lower conductive layer BML, the upper floating layer UFML, and the lower floating layer BFML can be composed of a conductive material such as copper. The upper conductive layer UML and the upper floating layer UFML can be formed of the same material in the same process. Also, the lower conductive layer BML and the lower floating layer BFML can be formed of the same material in the same process.

[0131] The upper conductive layer UML and the lower conductive layer BML can each be electrically connected to a ground voltage so as to protect the signal line SL from electromagnetic interference (EMI) or noise.

[0132] The upper conductive layer UML and the upper floating layer UFML can be spaced apart in the first direction DR1 and / or the second direction DR2 (see Figure 3 ) from each other to be electrically isolated from each other. As a result, the upper floating layer UFML can be maintained in a floating state. The lower conductive layer BML and the lower floating layer BFML can be spaced apart in the first direction DR1 and / or the second direction DR2 (see Figure 3 ) from each other to be electrically isolated from each other. As a result, the lower floating layer BFML can be maintained in an electrically floating state.

[0133] The circuit board FCB further includes a first capacitor C1 and a second capacitor C2. A first terminal T1 of the first capacitor C1 is connected to the upper floating layer UFML, and a second terminal T2 of the first capacitor C1 is connected to the upper conductive layer UML. The first terminal T1 of the first capacitor C1 can be directly connected to the upper floating layer UFML, and the second terminal T2 of the first capacitor C1 can be directly connected to the upper conductive layer UML. For example, even when a protective layer (or a coating layer) is provided on the upper portion of the upper floating layer UFML and on the upper portion of the upper conductive layer UML, the first terminal T1 of the first capacitor C1 can be directly electrically connected to the upper floating layer UFML, and the second terminal T2 of the first capacitor C1 can be directly electrically connected to the upper conductive layer UML.

[0134] The first terminal T3 of the second capacitor C2 is connected to the lower floating layer BFML, and the second terminal T4 of the second capacitor C2 is connected to the lower conductive layer BML. The first terminal T3 of the second capacitor C2 can be directly connected to the lower floating layer BFML, and the second terminal T4 of the second capacitor C2 can be directly connected to the lower conductive layer BML. For example, even when a protective layer (or a coating layer) is disposed on the lower portion of the lower floating layer BFML and on the lower portion of the lower conductive layer BML, the first terminal T3 of the second capacitor C2 can be directly connected to the lower floating layer BFML, and the second terminal T4 of the second capacitor C2 can be directly connected to the lower conductive layer BML.

[0135] The signal line SL can include a first signal line SL1 and a second signal line SL2. The first signal line SL1 and the second signal line SL2 can be formed of a conductive material having a predetermined width and a predetermined thickness.

[0136] Each of the first signal line SL1 and the second signal line SL2 can be spaced apart from the upper floating layer UFML by a predetermined distance d1. Between the first signal line SL1 and the upper floating layer UFML, a first parasitic capacitance Cc1 can be formed. Between the second signal line SL2 and the upper floating layer UFML, a second parasitic capacitance Cc2 can be formed.

[0137] As described above with reference to Figure 6 to Figure 7B , due to the series connection of the first parasitic capacitance Cc1 and the first capacitor C1, the capacitance between the first signal line SL1 and the upper conductive layer UML can be reduced. Also, due to the series connection of the second parasitic capacitance Cc2 and the first capacitor C1, the capacitance between the second signal line SL2 and the upper conductive layer UML can be reduced.

[0138] Figure 9 is a schematic view illustrating a capacitance between the first signal line SL1 and the lower conductive layer BML of Figure 8 .

[0139] With reference to Figure 8 and Figure 9 , the first signal line SL1 is spaced apart from the lower floating layer BFML by a predetermined distance d2. A third parasitic capacitance Cc3 formed between the first signal line SL1 and the lower floating layer BFML is connected in series to the second capacitor C2. When the third parasitic capacitance Cc3 and the second capacitor C2 are connected in series between the first signal line SL1 and the lower conductive layer BML, the total capacitance C between the first signal line SL1 and the lower conductive layer BML becomes smaller than the third parasitic capacitance Cc3 (C < Cc3). For example, when the capacitance of the second capacitor C2 is set to correspond to the third parasitic capacitance Cc3 (C2 = Cc3), the total capacitance C between the first signal line SL1 and the lower conductive layer BML can be about 1 / 2 of the third parasitic capacitance Cc3.

[0140] When the capacitance between the first signal line SL1 and the upper conductive layer UML is reduced by the first capacitor C1 and the capacitance between the first signal line SL1 and the lower conductive layer BML is reduced by the second capacitor C2, distortion of a signal transmitted through the first signal line SL1 can be reduced.

[0141] Figure 10 is a plan view illustratively showing the upper floating layer UFML and the upper conductive layer UML of the circuit board FCB shown in Figure 3

[0142] Referring to Figure 10 , the circuit board FCB includes the upper floating layer UFML and the upper conductive layer UML. The upper floating layer UFML and the upper conductive layer UML can be formed of the same material in the same process. The upper floating layer UFML and the upper conductive layer UML can be spaced apart in the first direction DR1 and the second direction DR2 so as to be electrically isolated.

[0143] The upper floating layer UFML can have an inverted "L" shape so as to overlap the signal lines SL1 and SL2, as shown in Figure 10 . The upper floating layer UFML can have a generally polygonal shape so as to overlap all of the signal lines SL1 and SL2. The upper floating layer UFML can have a generally rectangular shape so as to overlap some of the signal lines SL in plan.

[0144] The upper conductive layer UML can be electrically connected to the connector CNT through the power supply line VGL. Through the connector CNT and the power supply line VGL, the upper conductive layer UML can be supplied with a ground voltage.

[0145] One or more capacitors can be connected in series between the upper floating layer UFML and the upper conductive layer UML. In the example shown in Figure 10 , three capacitors C1-1, C1-2, and C1-3 are provided in series between the upper floating layer UFML and the upper conductive layer UML, but embodiments are not limited thereto.

[0146] Figure 8 The lower floating layer BFML and the lower conductive layer BML shown in Figure 10 may respectively have substantially the same shape as the shape of the upper floating layer UFML and the upper conductive layer UML shown in

[0147] Figure 11 and Figure 12 is a graph illustratively showing insertion loss according to a frequency of a signal transmitted through a signal line. In particular, Figure 11 is a graph corresponding to the embodiment of Figure 5 , and Figure 12 is a graph corresponding to the embodiment of Figure 6 . ​

[0148] First, refer to Figure 11 ,like Figure 5 As shown, the upper conductive layer UML may overlap with the first signal line SL1 and the second signal line SL2. A first parasitic capacitance Cca may be formed between the first signal line SL1 and the upper conductive layer UML, and a second parasitic capacitance Ccb may be formed between the second signal line SL2 and the upper conductive layer UML.

[0149] When the signal lines SL1 and SL2 between the drive circuit DIC and the connector CNT Figure 3 As the length L1 shown in the diagram increases, the first parasitic capacitance Cca and the second parasitic capacitance Ccb may increase.

[0150] As a high-speed interface, the MIPI interface requires an insertion loss of -5dB or greater at a frequency of 1.5GHz. However, when the length L1 of the signal lines SL1 and SL2 between the driver circuit DIC and the connector CNT is increased, the insertion loss can be reduced to -5dB or less, such as... Figure 11 As shown in the image.

[0151] Next, refer to Figure 12 In such Figure 6 A floating layer UFML may be disposed on the upper part of the first signal line SL1 and the second signal line SL2 shown. The floating layer UFML is not electrically connected to the upper conductive layer UML. The circuit board FCB also includes a first capacitor C1. The first terminal T1 of the first capacitor C1 is connected to the floating layer UFML, and the second terminal T2 of the first capacitor C1 is connected to the upper conductive layer UML.

[0152] The first parasitic capacitance Cc1 formed between the first signal line SL1 and the upper floating layer UFML is connected in series with the first capacitor C1. When the first parasitic capacitance Cc1 and the first capacitor C1 are connected in series between the first signal line SL1 and the upper conductive layer UML (see... Figure 7A The total capacitance C between the first signal line SL1 and the upper conductive layer UML can become smaller than the first parasitic capacitance Cc1. As a result, as Figure 12 As shown, the insertion loss is -5dB or greater when the frequency of the signal transmitted through the first signal line SL1 is 1.5GHz.

[0153] The circuit board constructed according to the principles and embodiments described above according to the present invention can prevent the degradation of signal transmission characteristics even when the length of the signal lines increases. Therefore, the degradation of the display quality of the display device can be reduced or prevented.

[0154] While certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments but is intended to cover what is described herein, including any future equivalents or modifications, as well as any related methods or art within scope of the claims.

Claims

1. A circuit board for a display device, the circuit board comprising: a signal line for transmitting a signal; a first metal layer overlapping the signal line; a first conductive layer spaced apart from the first metal layer and electrically isolated from the signal line; a base layer insulating the signal line from the first metal layer and the first conductive layer; and a first capacitor including a first terminal electrically coupled to the first metal layer and a second terminal electrically coupled to the first conductive layer, wherein the first metal layer includes a first floating layer maintained in an electrically floating state without a signal applied thereto. The first floating layer has a polygonal shape fully overlapping the signal line.

2. The circuit board of claim 1, wherein, The first conductive layer is configured to receive a ground voltage.

3. The circuit board of claim 1, wherein, The first terminal of the first capacitor directly contacts the first metal layer, and the second terminal of the first capacitor directly contacts the first conductive layer.

4. The circuit board of claim 1, wherein, The first metal layer and the first conductive layer are formed of a same material and disposed on a first surface of the base layer.

5. The circuit board of claim 1, wherein, 6.The circuit board of claim 1, further comprising: a second metal layer overlapping the signal line; a second conductive layer spaced apart from the second metal layer; and a second capacitor including a first terminal electrically coupled to the second metal layer and a second terminal electrically coupled to the second conductive layer. 7.The circuit board of claim 6, wherein: the second metal layer and the second conductive layer are formed of a same material and disposed on a second surface of the base layer; and the base layer insulates the signal line from the second metal layer and the second conductive layer. 8.The circuit board of claim 1, wherein: a capacitance between the signal line and the first conductive layer is determined by a parasitic capacitance between the signal line and the first metal layer and a first capacitance of the first capacitor; and the first capacitance of the first capacitor is determined with respect to the parasitic capacitance between the signal line and the first metal layer. 9.A display device comprising: a display panel for displaying an image and including a first pad; and a circuit board including a second pad to be connected to the first pad of the display panel, wherein the circuit board comprises: a signal line for transmitting a signal; a first metal layer overlapping the signal line; a first conductive layer spaced apart from the first metal layer and electrically isolated from the signal line; a base layer insulating the signal line from the first metal layer and the first conductive layer; and a first capacitor including a first terminal electrically coupled to the first metal layer and a second terminal electrically coupled to the first conductive layer, wherein the first metal layer includes a first floating layer maintained in an electrically floating state without a signal applied thereto. The circuit board further includes a driving circuit to be electrically connected to the second pad. ​ ​ 10. The display device of claim 9, wherein, ​

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