Pipeline optimization method, system and application of adaptive dynamic allocation buffer

Abstract

The present invention discloses a pipeline optimization method, system and application for adaptive dynamic allocation of buffers, and relates to the technical field of integrated circuit design. The method comprises the following steps: obtaining the output data flow structure of each submodule at each level in the pipeline structure, determining the minimum buffer unit that can be dynamically allocated; stacking a buffer structure with a buffer depth of 2n according to the aforementioned minimum buffer unit; allocating an initial buffer to the pipeline based on the principle of buffer depth equivalence, so that the buffer depth of each data path in the pipeline structure is consistent; monitoring the occurrence ratio of the cache full state between each previous and next submodule within each adaptive cycle T, calculating the cache full state duty cycle to determine the corresponding response level, and allocating the buffer depth between adjacent submodules within the next adaptive cycle T according to the response level. The present invention can significantly improve the utilization rate of buffer resources, reduce the number of idle bubbles in the pipeline, and optimize pipeline performance.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a pipeline optimization method, system and application of adaptive dynamic allocation buffering. Background Art

[0002] In the field of chip design, pipeline design is one of the most important means to improve hardware performance. By splitting a complete target operation process into several front and back operation modules and performing pipeline parallel processing, the overall performance of the system can be greatly improved.

[0003] On the one hand, a ping-pong operation is usually used between the front and back submodules of the pipeline. For example, see Figure 1 As shown in the figure, SUBn and SUBn+1 are the front and back submodules on the pipeline respectively. Ping-pong buffer is used in the middle, and the buffer depth is set to 2. The operation process is as follows:

[0004] 1) At time Tn, SUBn completes the calculation of Unitn and stores the result in buffer0.

[0005] 2) At time Tn+1, SUBn continues to calculate Unitn+1 and stores the result in buffer1. At the same time, SUBn+1 finds that the data in buffer0 is valid (corresponding to Unitn) and completes the calculation of Unitn at this time.

[0006] 3) At time Tn+2, SUBn calculates the next Unit and writes the result to buffer0, while SUBn+1 takes the valid data from buffer1 and completes the corresponding calculation.

[0007] By alternating the ping-pong buffer (with a fixed buffer depth of 2) according to the above rules, the pipeline can execute in parallel. However, in actual applications, it has been found that using a ping-pong buffer with a fixed buffer depth to achieve parallel execution of previous and subsequent sub-modules in the pipeline can lead to significant differences in the operation time of each sub-module in various scenarios, such as complex and diverse computing units and DRAM data latency. This reduces the actual efficiency of the ping-pong operation in the pipeline and affects the design's performance stability in complex and changing scenarios. In some scenarios that require continuous and stable performance, such as fixed frame rate video encoding and decoding and real-time video image transmission, this fixed buffer depth design is difficult to meet application requirements.

[0008] On the other hand, in the design of synchronous pipeline chips, it is usually necessary to go through several design iterations to balance the transmission rates of the previous and next sub-modules in the pipeline system, so that each pipeline module can continuously and uninterruptedly process the input data stream, thereby achieving the optimal performance of the entire pipeline system. As an example, the typical pipeline structure in the synchronous pipeline system chip design can be seen in Figure 2As shown in the figure, assume that the initial design is divided into four front-end and back-end submodules on the pipeline, namely SUB1, SUB2, SUB3 and SUB4. Among them, SUB1 submodule is in the first stage, SUB2 submodule is in the second stage, SUB3 submodule is in the third stage, and so on. The system pipeline operation process is as follows:

[0009] 1. T1 cycle: The SUB1 submodule completes the calculation of pipeline unit Unit1 and sends its result to the subsequent SUB2 submodule.

[0010] 2. T2 cycle: SUB1 accesses the calculation of the new Unit2 and sends the result to the subsequent SUB2 submodule, while SUB2 calculates Unit1 in this cycle and sends the result to the subsequent SUB3 submodule.

[0011] 3. T3 cycle: SUB1 accesses the calculation of the new Unit3 and sends the result to the subsequent SUB2 submodule, while SUB2 calculates Unit2 in this cycle and sends the result to the subsequent SUB3 submodule, and SUB3 calculates Unit1 in this cycle and sends the result to the subsequent SUB4 submodule.

[0012] 4. T4 cycle: SUB1 accesses the calculation of the new Unit4 and sends the result to the subsequent SUB2 sub-module, while SUB2 calculates Unit3 in this cycle and sends the result to the subsequent SUB3 sub-module, while SUB3 calculates Unit2 in this cycle and sends the result to the subsequent SUB4 sub-module, and SUB4 calculates Unit1 in this cycle and uses the result as the final output.

[0013] At this point, during cycle T4, the pipeline begins running at full capacity. Each of the SUB1, SUB2, SUB3, and SUB4 submodules begins fully parallel computation until all units are completed. If each submodule, SUB1, SUB2, SUB3, and SUB4, performs each unit of the pipeline at the same time, the system will be optimal. In this state, each of the SUB1 / 2 / 3 / 4 submodules in the pipeline executes in full parallel, with no idle bubbles (also known as pipeline bubbles or idle wait states) occurring.

[0014] However, of course, the above description is only an ideal situation. In actual design, the processing time of each SUB submodule in different computing scenarios and different computing units is often not fixed. Under the influence of internal and external factors such as the complexity and diversity of computing units and DRAM data latency, the computing time of each submodule on the pipeline may often be inconsistent, resulting in a large number of idle bubbles in the front and back submodules of the pipeline, thus affecting the overall performance of the pipeline system. For example, see Figure 3As shown, it is assumed that the initial design is divided into four front-end and back-end sub-modules on the pipeline, namely SUB1, SUB2, SUB3 and SUB4, among which SUB1 sub-module is at the first level, SUB2 sub-module is at the second level, SUB3 sub-module is at the third level, and so on.

[0015] In cycle T2: SUB1 submodule processes pipeline unit Unitb faster while SUB2 submodule processes pipeline unit Unite slower in the same cycle. When the buffer between SUB1 and SUB2 is full, SUB1 submodule needs to wait for SUB2 submodule to complete Unite calculation before it can move Unitb into SUB2 pipeline stage. At this time, SUB1 has bubble A waiting for the next stage. Figure 3 The square marked A in .

[0016] In cycle T3: SUB1 submodule processes Unitc slowly while SUB2 submodule processes Unitf quickly. When the buffer between SUB1 and SUB2 is empty (bufferempty), SUB2 submodule needs to wait until SUB1 submodule completes Unitc calculation and moves into SUB2 pipeline stage before it can start calculation. At this time, SUB2 has bubble B in the previous stage. Figure 3 The block marked with B.

[0017] Idle bubbles appear in the pipeline. Figure 3 Emptying the pipeline (blank squares in the middle) reduces the parallelism of each submodule, impacting overall system performance. Reducing the number of idle bubbles in the pipeline to optimize pipeline performance is a pressing technical challenge. Summary of the Invention

[0018] The present invention aims to overcome the shortcomings of the prior art by providing a pipeline optimization method, system, and application for adaptive dynamic buffer allocation. The present invention dynamically allocates buffer units between pipeline submodules based on the idle wait status of each submodule, configuring different buffer depths for different application scenarios. This significantly improves buffer resource utilization, reduces the number of idle bubbles in the pipeline, and optimizes pipeline performance.

[0019] To achieve the above objectives, the present invention provides the following technical solutions:

[0020] A pipeline optimization method for adaptive dynamic allocation buffering includes the following steps:

[0021] Obtaining the output data flow structure of each submodule in the pipeline structure, determining the smallest buffer unit that can be dynamically allocated; stacking a buffer structure with a buffer depth of 2n based on the aforementioned smallest buffer unit, where n is an integer greater than or equal to 1;

[0022] Based on the principle of buffer depth parity, the initial buffer is allocated to the pipeline. At this time, when there are multiple data paths from the first-level submodule to the last-level submodule in the pipeline structure, the buffer depth of each data path is consistent;

[0023] Based on the set adaptive period T, the occurrence ratio of the cache full state between each front-end and back-end sub-module is monitored in each adaptive period T, and the duty cycle of the cache full state in the corresponding period T is calculated; according to the preset mapping relationship between the cache full state duty cycle and the response level, after determining the response level corresponding to the aforementioned calculated duty cycle, the buffer depth between adjacent sub-modules is allocated according to the response level in the next adaptive period T.

[0024] Furthermore, the method for determining the smallest buffer unit that can be dynamically allocated is:

[0025] Analyze the output data flow structures of all submodules, where the output data flow structures include RAM depth information and RAM width information, and determine the greatest common divisor M×N of the output data flow structures of all submodules, where M represents the greatest common divisor of the RAM depths of the output data flow structures of the submodules, and N represents the greatest common divisor of the RAM widths of the output data flow structures of the submodules;

[0026] The RAM depth and RAM width of the minimum buffer unit are configured according to the aforementioned greatest common divisor M×N, wherein the RAM depth of the minimum buffer unit is equal to M, and the RAM width of the minimum buffer unit is equal to N.

[0027] Furthermore, the value of the cache full state duty cycle is less than 1, the response levels are at least 2, different cache full state duty cycle ranges are configured corresponding to different response levels, and different response levels are configured with buffer structures of different buffer depths.

[0028] Furthermore, there are 4 response levels, and the mapping relationship between the cache full state duty cycle and the response level is as follows:

[0029] When the cache full state duty cycle is greater than or equal to 0 and less than 25%, it corresponds to level 4 response level; when the cache full state duty cycle is greater than or equal to 25% and less than 50%, it corresponds to level 3 response level; when the cache full state duty cycle is greater than or equal to 50% and less than 75%, it corresponds to level 2 response level; when the cache full state duty cycle is greater than or equal to 75% and less than 100%, it corresponds to level 1 response level.

[0030] Furthermore, the mapping relationship between the response level and the buffer depth is as follows:

[0031] Level 1 response level corresponds to an 8-level buffer depth, where n=4; level 2 response level corresponds to a 6-level buffer depth, where n=3; level 3 response level corresponds to a 4-level buffer depth, where n=2; level 4 response level corresponds to a 2-level buffer depth, where n=1.

[0032] Furthermore, the adaptive period T is set by the user, or the adaptive period T is set by the system.

[0033] Furthermore, when a buffer structure with a buffer depth of 2n is stacked according to the aforementioned minimum buffer unit, an input / output interface multiplexer / demultiplexer mux / demux is configured for each buffer, and the multiplexer / demultiplexer is selected by the selection signal distribution of the multiplexer switch.

[0034] The present invention also provides a pipeline optimization method in a synchronous pipeline chip, comprising the following steps:

[0035] Obtaining idle waiting state information between the front and rear submodules in the pipeline structure, wherein the idle waiting state information includes two types: an idle bubble type equal to the front stage and an idle bubble type equal to the rear stage;

[0036] Determine whether the idle waiting state between the front and rear submodules is the idle bubble of the rear stage;

[0037] When the judgment is yes, the aforementioned pipeline structure is optimized by the aforementioned method.

[0038] The present invention also provides a pipeline optimization system with adaptive dynamic allocation buffer, the system includes a pipeline structure analysis device and a dynamic adjustment buffer device;

[0039] The pipeline structure analysis device is used to obtain the output data flow structure of each sub-module in the pipeline structure, determine the minimum buffer unit that can be dynamically allocated, and stack a buffer structure with a buffer depth of 2n based on the minimum buffer unit, where n is an integer greater than or equal to 1;

[0040] The dynamic buffer adjustment device includes a pipeline initial design module, a cache full count module and a cache scheduling module;

[0041] The pipeline initial design module is used to allocate initial buffers for the pipeline based on the principle of buffer depth parity. At this time, when there are multiple data paths from the first-stage submodule to the last-stage submodule in the pipeline structure, the buffer depth of each data path is consistent;

[0042] The cache full counting module is used to obtain the set adaptive period T, monitor the occurrence ratio of the cache full state between each previous and next sub-module in each adaptive period T, and calculate the duty cycle of each cache full state in the corresponding period T;

[0043] The cache scheduling module is used to determine the response level corresponding to the above-calculated empty ratio according to the preset mapping relationship between the cache full state duty cycle and the response level, and allocate the buffer depth between adjacent sub-modules within the next adaptive period T according to the response level.

[0044] Furthermore, when a buffer structure with a buffer depth of 2n is stacked according to the aforementioned minimum buffer unit, an input / output interface multiplexer / demultiplexer mux / demux is configured for each buffer, and a selection signal of the multiplexer switch is generated by the aforementioned cache scheduling module.

[0045] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the existing technology, as an example: the present invention can dynamically allocate buffer units between the sub-modules of each pipeline stage according to the idle waiting status of each sub-module of the pipeline stage, and configure different buffer depths in different application scenarios, thereby significantly improving the utilization rate of existing buffer resources, reducing the number of idle bubbles in the pipeline, and optimizing the pipeline performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a ping-pong buffer structure between the front-end and back-end modules of the pipeline in the prior art.

[0047] Figure 2 The figure is a schematic diagram of a typical pipeline structure in the synchronous pipeline system chip design in the prior art.

[0048] Figure 3 The figure is a schematic diagram of the pipeline structure when idle bubbles appear on the pipeline in the prior art.

[0049] Figure 4 The embodiment of the present invention provides a pipeline structure including multiple data paths.

[0050] Figure 5 A mapping relationship table of the cache full state duty cycle, response level, and buffer depth of the buffer structure provided in an embodiment of the present invention.

[0051] Figure 6 A schematic diagram of the module structure of a dynamic scheduling buffer device provided by an embodiment of the present invention.

[0052] Figure 7 A schematic diagram of a 2n deep buffer structure configured through mux / demux according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following is a further detailed description of the pipeline optimization method, system and application of the adaptive dynamic allocation buffer disclosed in the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered isolated, and they can be combined with each other to achieve better technical effects. In the drawings of the following embodiments, the same reference numerals appearing in each drawing represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0054] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not intended to limit the conditions under which the invention can be implemented. Any structural modification, change in proportional relationship, or adjustment of size should fall within the scope of the technical content disclosed in the invention without affecting the efficacy and purpose of the invention. The scope of the preferred embodiments of the present invention includes alternative implementations, in which the functions can be performed in a non-described or discussed order, including performing the functions in a substantially simultaneous manner or in a reverse order according to the functions involved, which should be understood by those skilled in the art of the art to which the embodiments of the present invention belong.

[0055] Technologies, methods, and apparatus known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values. Example

[0056] The idle waiting states between the front-end and back-end submodules in a pipeline structure can be divided into two types: waiting for the front-end idle bubble type and waiting for the back-end idle bubble type. Waiting for the front-end idle bubble is usually caused by the front-end submodule operating slower than the back-end submodule. This can usually be reduced or eliminated by optimizing the front-end submodule. The present invention mainly optimizes the waiting for the back-end idle bubble in the pipeline structure, reducing the probability of the occurrence of waiting for the back-end idle bubble through an adaptive dynamic allocation buffer strategy.

[0057] This embodiment provides a pipeline optimization method for adaptive dynamic buffer allocation, comprising the following steps:

[0058] S100, obtaining the output data flow structure of each sub-module in the pipeline structure, and determining the smallest buffer unit that can be dynamically allocated; then, stacking a buffer structure with a buffer depth of 2n according to the aforementioned smallest buffer unit, where n is an integer greater than or equal to 1.

[0059] When determining the smallest buffer unit that can be dynamically allocated, it is necessary to determine the parameter values ​​of the RAM depth and RAM width of the smallest buffer unit. In this embodiment, the specific method for determining the above parameter values ​​of the smallest buffer unit that can be dynamically allocated is as follows:

[0060] S110 , analyzing the output data stream structure of all submodules, where the output data stream structure includes RAM depth information and RAM width information.

[0061] S120 , determining the greatest common divisor M×N of the output data flow structures of all submodules, where M represents the greatest common divisor of the RAM depths of the output data flow structures of each submodule, and N represents the greatest common divisor of the RAM widths of the output data flow structures of each submodule.

[0062] S130 , configuring the RAM depth and RAM width of the minimum buffer unit according to the aforementioned greatest common divisor M×N, wherein the RAM depth of the minimum buffer unit is equal to M, and the RAM width of the minimum buffer unit is equal to N.

[0063] After the minimum buffer unit is determined, a buffer structure with a buffer depth of 2n can be stacked based on the minimum buffer unit, where n is an integer greater than or equal to 1.

[0064] When n=1, the buffer depth is 2, that is, a two-level buffer structure is formed. The buffer structure with a buffer depth of 2 is the ping-pong buffer (or ping-pong cache) structure in the prior art.

[0065] When n=2, the buffer depth is 4, forming a 4-level buffer structure.

[0066] When n=3, the buffer depth is 6, forming a 6-level buffer structure.

[0067] When n=4, the buffer depth is 8, forming an 8-level buffer structure.

[0068] And so on.

[0069] S200 , allocating an initial buffer for the pipeline based on the principle of buffer depth parity. At this time, when the pipeline structure has multiple data paths from the first-stage submodule to the last-stage submodule, the buffer depth of each data path is consistent.

[0070] As an example and not a limitation, for example, there are two data paths from the first-level sub-module to the last-level sub-module in the pipeline structure. By using the principle of buffer depth equivalence, the initial buffer is allocated between the front-end and rear-end sub-modules so that the buffer depths of the two data paths are consistent, for example, the buffer depths of the two data paths are both 8 levels, or other depth levels.

[0071] S300, based on the set adaptive cycle T, monitors the occurrence ratio of the cache full state between each front-end and back-end sub-module in each adaptive cycle T, and calculates the duty cycle of the cache full state in the corresponding cycle T; according to the preset mapping relationship between the cache full state duty cycle and the response level, after determining the response level corresponding to the aforementioned calculated duty cycle, allocates the buffer depth between adjacent sub-modules in the next adaptive cycle T according to the response level.

[0072] In specific settings, the adaptive period T can be set by the user, for example, the user can personalize the adaptive period T according to the scale of the pipeline structure; the adaptive period T can also be set by the system, for example, using the adaptive period T set by default in the system. Preferably, the adaptive period T is set by the user, for example, the user can set the calculation interval of every N pipeline units as an adaptive period T, where N is an integer greater than or equal to 2.

[0073] After determining the adaptive period T, we can monitor the occurrence ratio of the buffer full state between each upstream and downstream sub-module within each adaptive period T, and calculate the duty cycle of the buffer full state in the corresponding period T to obtain the buffer full duty cycle.

[0074] The cache full state duty cycle is the ratio of the time occupied by the cache full state in an adaptive period T to the period T. The value of the cache full state duty cycle is greater than or equal to 0 and less than 1. In this embodiment, there are at least two response levels, and different cache full state duty cycle ranges are configured for different response levels, and different response levels are configured with buffer structures of different buffer depths.

[0075] The following combination Figure 4 The pipeline structure shown describes in detail the pipeline optimization method provided by this embodiment.

[0076] Figure 4 The pipeline structure shown in the figure has two data paths from the first-level sub-module to the last-level sub-module. The first data path is sub1->sub2->sub6, and the second data path is sub1->sub3->sub4->sub5->sub6. In different application scenarios, the activity frequencies of the two paths are different.

[0077] First, determine the smallest dynamically allocable buffer unit: Based on the output data stream structures of all submodules sub1, sub2, sub3, sub4, sub5, and sub6, find the greatest common divisor MxN, where M is the RAM depth of the smallest buffer unit, and N is the RAM width of the smallest buffer unit. Based on these minimum buffer unit RAM depths and RAM widths, stack buffer structures with buffer depths of 2, 4, 6, 8, and so on. The buffer structure with a buffer depth of 2 is the ping-pong buffer described above.

[0078] Secondly, according to the principle of buffer depth parity, initial buffers are allocated to each submodule of the pipeline, so that the total buffer depth of the two data paths of the aforementioned pipeline structure is consistent. In specific implementation, the buffer depth of each data path can be made consistent by configuring the buffer depth between each submodule of the pipeline (one submodule is regarded as a node). For example, Figure 4 In the example, the total buffer depth of the data path sub1->sub2->sub6 is 12 levels, and the total buffer depth of the data path sub1->sub3->sub4->sub5->sub6 is also 12 levels. Among them, the buffer depths of sub1->sub2 and sub1->sub3 are both 4 levels, and the buffer depths of sub2->sub6 and sub3->sub4->sub5->sub6 are both 8 levels. Specifically, the buffer depth of sub3->sub4 is 2 levels, the buffer depth of sub4->sub5 is 4 levels, and the buffer depth of sub5->sub6 is both 2 levels.

[0079] Then, the adaptive cycle T is determined according to the N value set by the user. The calculation interval of each N pipeline unit is an adaptive cycle T. In each adaptive cycle T, the occurrence ratio of each cache full state is calculated. According to the duty cycle of the cache full state in the T cycle, the adaptive cycle is calculated. Figure 5 The preset mapping table shown in FIG. 1 is used to determine the response level corresponding to the calculated duty cycle. As an example of a typical method, Figure 5 There are four response levels in the cache write state. The mapping relationship between the cache write state duty cycle and the response level is as follows: when the cache write state duty cycle is greater than or equal to 0 and less than 25%, it corresponds to level 4 response level; when the cache write state duty cycle is greater than or equal to 25% and less than 50%, it corresponds to level 3 response level; when the cache write state duty cycle is greater than or equal to 50% and less than 75%, it corresponds to level 2 response level; when the cache write state duty cycle is greater than or equal to 75% and less than 100%, it corresponds to level 1 response level.

[0080] Finally, after the response level is determined, the pipeline buffer can be allocated according to the buffer depth corresponding to the response level in the next adaptive cycle T. Figure 5The mapping relationship between the response level and the buffer depth is as follows: the response level 1 corresponds to the 8-level buffer depth, at this time n=4; the response level 2 corresponds to the 6-level buffer depth, at this time n=3; the response level 3 corresponds to the 4-level buffer depth, at this time n=2; the response level 4 corresponds to the 2-level buffer depth, at this time n=1.

[0081] In this embodiment, when a buffer structure with a buffer depth of 2n is stacked according to the aforementioned minimum buffer unit, each buffer can be configured with an input and output interface multiplexer / demultiplexer mux / demux, see Figure 6 As shown, the multiplexer / demultiplexer is selected by allocating a select signal of a multiplexer (mux) switch, and the select signal of the mux switch can be generated by a cache scheduling module set in the system.

[0082] Another embodiment of the present invention further provides a pipeline optimization method in a synchronous pipeline chip. The method comprises the following steps:

[0083] S10, obtaining idle waiting state information between the previous and next stage submodules in the pipeline structure, wherein the idle waiting state information includes two types, namely, an idle bubble type equal to the previous stage and an idle bubble type equal to the next stage.

[0084] S20, determining whether the idle waiting state between the front and rear submodules is the idle bubble of the rear stage.

[0085] S30: When the determination is yes, the pipeline structure is optimized by using a pipeline optimization method of adaptive dynamic allocation buffer.

[0086] The pipeline optimization method of adaptive dynamic allocation buffer includes the following steps:

[0087] S31, obtain the output data flow structure of each sub-module in the pipeline structure, determine the minimum buffer unit that can be dynamically allocated; then, stack a buffer structure with a buffer depth of 2n based on the aforementioned minimum buffer unit, where n is an integer greater than or equal to 1.

[0088] When determining the smallest buffer unit that can be dynamically allocated, it is necessary to determine the parameter values ​​of the RAM depth and RAM width of the smallest buffer unit. In this embodiment, the specific method for determining the above parameter values ​​of the smallest buffer unit that can be dynamically allocated is as follows: analyzing the output data stream structure of all sub-modules, wherein the output data stream structure includes RAM depth information and RAM width information; determining the greatest common divisor M×N of the output data stream structures of all sub-modules, wherein M represents the greatest common divisor of the RAM depth of the output data stream structures of each sub-module, and N represents the greatest common divisor of the RAM width of the output data stream structures of each sub-module; configuring the RAM depth and RAM width of the smallest buffer unit according to the aforementioned greatest common divisor M×N, wherein the RAM depth of the smallest buffer unit is equal to M, and the RAM width of the smallest buffer unit is equal to N.

[0089] After the minimum buffer unit is determined, a buffer structure with a buffer depth of 2n can be stacked based on the minimum buffer unit, where n is an integer greater than or equal to 1.

[0090] S32, allocating an initial buffer for the pipeline based on the principle of buffer depth equality. At this time, when the pipeline structure has multiple data paths from the first-stage submodule to the last-stage submodule, the buffer depth of each data path is consistent.

[0091] S33, based on the set adaptive cycle T, monitor the occurrence ratio of the cache full state between each front-end and back-end sub-module in each adaptive cycle T, and calculate the duty cycle of the cache full state in the corresponding cycle T; according to the preset mapping relationship between the cache full state duty cycle and the response level, after determining the response level corresponding to the aforementioned calculated duty cycle, allocate the buffer depth between adjacent sub-modules in the next adaptive cycle T according to the response level.

[0092] In specific settings, the adaptive period T can be set by the user, for example, the user can personalize the adaptive period T according to the scale of the pipeline structure; the adaptive period T can also be set by the system, for example, using the adaptive period T set by default in the system. Preferably, the adaptive period T is set by the user, for example, the user can set the calculation interval of every N pipeline units as an adaptive period T, where N is an integer greater than or equal to 2.

[0093] After determining the adaptive period T, we can monitor the occurrence ratio of the buffer full state between each upstream and downstream sub-module within each adaptive period T, and calculate the duty cycle of the buffer full state in the corresponding period T to obtain the buffer full duty cycle.

[0094] The cache full state duty cycle is the ratio of the time occupied by the cache full state in an adaptive period T to the period T. The value of the cache full state duty cycle is greater than or equal to 0 and less than 1. In this embodiment, there are at least two response levels, and different cache full state duty cycle ranges are configured for different response levels, and different response levels are configured with buffer structures of different buffer depths.

[0095] For other technical features, please refer to the previous embodiments and will not be repeated here.

[0096] Another embodiment of the present invention provides a pipeline optimization system for adaptively and dynamically allocating buffers.

[0097] The system includes a pipeline structure analysis device and a dynamic adjustment buffer device.

[0098] The pipeline structure analysis device is used to obtain the output data flow structure of each sub-module in the pipeline structure, determine the minimum buffer unit that can be dynamically allocated, and stack a buffer structure with a buffer depth of 2n based on the aforementioned minimum buffer unit, where n is an integer greater than or equal to 1.

[0099] The dynamic buffer adjustment device includes a pipeline initial design module, a cache full count module and a cache scheduling module. Figure 7 shown.

[0100] The pipeline initial design module is used to allocate initial buffers for the pipeline based on the principle of buffer depth equivalence. At this time, when there are multiple data paths from the first-level submodule to the last-level submodule in the pipeline structure, the buffer depths of the various data paths are consistent.

[0101] The cache full counting module is used to obtain the set adaptive period T, and monitor the occurrence ratio of the cache full state between each previous and next sub-module in each adaptive period T, and calculate the duty cycle of each cache full state in the corresponding period T.

[0102] The cache scheduling module is used to determine the response level corresponding to the above-calculated empty ratio according to the preset mapping relationship between the cache full state duty cycle and the response level, and allocate the buffer depth between adjacent sub-modules within the next adaptive period T according to the response level.

[0103] In this embodiment, when a buffer structure with a buffer depth of 2n is stacked based on the aforementioned minimum buffer units, an input / output interface multiplexer / demultiplexer mux / demux is configured for each buffer, and a selection signal of the multiplexer switch is generated by the aforementioned cache scheduling module.

[0104] Other technical features are described in the previous embodiments and will not be repeated here.

[0105] In the above description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, within the scope of the intended protection of the present disclosure, the components can be selectively and operationally combined in any number. In addition, terms such as "including", "encompassing" and "having" should be interpreted as inclusive or open by default, rather than exclusive or closed, unless they are explicitly defined to the contrary. All technical, scientific or other terms have the meaning understood by those skilled in the art unless they are defined to the contrary. Common terms found in dictionaries should not be interpreted too idealistically or too impractically in the context of relevant technical documents, unless the present disclosure explicitly defines them as such. Any changes and modifications made by a person of ordinary skill in the field of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A pipeline optimization method for adaptive dynamic allocation buffering, characterized in that The steps include: Obtaining the output data flow structure of each submodule in the pipeline structure, determining the smallest buffer unit that can be dynamically allocated; stacking a buffer structure with a buffer depth of 2n based on the aforementioned smallest buffer unit, where n is an integer greater than or equal to 1; Based on the principle of buffer depth parity, the initial buffer is allocated to the pipeline. At this time, when there are multiple data paths from the first-level submodule to the last-level submodule in the pipeline structure, the buffer depth of each data path is consistent; Based on a set adaptive period T, the occurrence ratio of the cache full state between each previous and next sub-module is monitored within each adaptive period T, and the duty cycle of the cache full state in the corresponding period T is calculated. After determining the response level corresponding to the calculated duty cycle based on a preset mapping relationship between the cache full state duty cycle and the response level, the buffer depth between adjacent sub-modules is allocated according to the response level within the next adaptive period T. Among them, the value of the cache full state duty cycle is less than 1, the response levels are at least 2, different cache full state duty cycle ranges are configured corresponding to different response levels, and different response levels are configured with buffer structures with different buffer depths.

2. The pipeline optimization method for adaptive dynamic allocation buffering according to claim 1, characterized in that: The method for determining the smallest buffer unit that can be dynamically allocated is, Analyze the output data flow structures of all submodules, where the output data flow structures include RAM depth information and RAM width information, and determine the greatest common divisor M×N of the output data flow structures of all submodules, where M represents the greatest common divisor of the RAM depths of the output data flow structures of the submodules, and N represents the greatest common divisor of the RAM widths of the output data flow structures of the submodules; The RAM depth and RAM width of the minimum buffer unit are configured according to the aforementioned greatest common divisor M×N, wherein the RAM depth of the minimum buffer unit is equal to M, and the RAM width of the minimum buffer unit is equal to N.

3. The pipeline optimization method for adaptive dynamic allocation buffering according to claim 1, characterized in that: There are 4 response levels, and the mapping relationship between the cache full state duty cycle and the response level is as follows: When the cache full state duty cycle is greater than or equal to 0 and less than 25%, it corresponds to level 4 response level; when the cache full state duty cycle is greater than or equal to 25% and less than 50%, it corresponds to level 3 response level; when the cache full state duty cycle is greater than or equal to 50% and less than 75%, it corresponds to level 2 response level; when the cache full state duty cycle is greater than or equal to 75% and less than 100%, it corresponds to level 1 response level.

4. The pipeline optimization method for adaptive dynamic allocation buffering according to claim 3, characterized in that: The mapping relationship between the response level and the buffer depth is as follows: Level 1 response level corresponds to an 8-level buffer depth, and n=4 at this time; level 2 response level corresponds to a 6-level buffer depth, and n=3 at this time; level 3 response level corresponds to a 4-level buffer depth, and n=2 at this time; level 4 response level corresponds to a 2-level buffer depth, and n=1 at this time.

5. The pipeline optimization method for adaptive dynamic allocation buffering according to claim 1, characterized in that: The adaptive period T is set by a user, or the adaptive period T is set by a system.

6. The pipeline optimization method for adaptive dynamic allocation buffering according to claim 1, characterized in that: When a buffer structure with a buffer depth of 2n is stacked according to the aforementioned minimum buffer unit, each buffer is configured with an input and output interface multiplexer / demultiplexer mux / demux, and the multiplexer / demultiplexer is selected by the selection signal distribution of the multiplexer switch.

7. A pipeline optimization method in a synchronous pipeline chip, characterized in that Including steps: Obtaining idle waiting state information between the front and rear submodules in the pipeline structure, wherein the idle waiting state information includes two types: an idle bubble type equal to the front stage and an idle bubble type equal to the rear stage; Determine whether the idle waiting state between the front and rear submodules is the idle bubble of the rear stage; When the determination is yes, the pipeline structure is optimized by the method according to any one of claims 1 to 6.

8. A pipeline optimization system with adaptive dynamic buffer allocation, characterized by: It includes an assembly line structure analysis device and a dynamic adjustment buffer device; The pipeline structure analysis device is used to obtain the output data flow structure of each sub-module in the pipeline structure, determine the minimum buffer unit that can be dynamically allocated, and stack a buffer structure with a buffer depth of 2n based on the minimum buffer unit, where n is an integer greater than or equal to 1; The dynamic buffer adjustment device includes a pipeline initial design module, a cache full count module and a cache scheduling module; The pipeline initial design module is used to allocate initial buffers for the pipeline based on the principle of buffer depth parity. At this time, when there are multiple data paths from the first-stage submodule to the last-stage submodule in the pipeline structure, the buffer depth of each data path is consistent; The cache full counting module is used to obtain a set adaptive period T, monitor the occurrence ratio of the cache full state between each previous and next sub-module in each adaptive period T, and calculate the duty cycle of each cache full state in the corresponding period T; The cache scheduling module is used to determine the response level corresponding to the calculated duty cycle according to a preset mapping relationship between the cache full state duty cycle and the response level, and allocate the buffer depth between adjacent submodules in the next adaptive period T according to the response level; Among them, the value of the cache full state duty cycle is less than 1, the response levels are at least 2, different cache full state duty cycle ranges are configured corresponding to different response levels, and different response levels are configured with buffer structures with different buffer depths.

9. The system according to claim 8, characterized in that: When a buffer structure with a buffer depth of 2n is stacked according to the aforementioned minimum buffer unit, each buffer is configured with an input and output interface multiplexer / demultiplexer mux / demux, and the selection signal of the multiplexer switch is generated by the aforementioned cache scheduling module.

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