Data backup and reading system and method thereof

Abstract

The present invention provides a data backup and reading method and a data backup and reading method for a memory storage device. The memory storage device includes a memory controller, a first memory module and a second memory module. The method includes: the memory controller receives a write instruction from a host system; the memory controller writes the write data included in the write instruction to the first memory module, and writes the write data to the second memory module; and when it is determined that the first memory module is damaged, the host system reads the write data stored in the second memory module. The first memory module and the second memory module are rewritable non-volatile memory modules.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and in particular to a data backup and reading system and a data backup and reading method. Background Art

[0002] With the rapid development of science and technology, the development of the information industry is also advancing by leaps and bounds. In order to meet the increasing needs of users, the functions of computers and other processing devices themselves and their executable applications are gradually increasing. With the increase in functions, the amount of data and files generated is also increasing. Because rewritable non-volatile memory modules (for example, flash memory) have the characteristics of data non-volatility, power saving, small size, no mechanical structure, and fast reading and writing speed, they are most suitable for portable electronic products, such as notebook computers. A solid-state drive is a memory storage device that uses flash memory as a storage medium. Therefore, in recent years, the flash memory industry has become a very popular part of the electronics industry.

[0003] In the past, memory storage devices such as USB flash drives and solid-state hard drives did not have a backup function, which often caused the memory storage device to be unable to read precious files due to external forces or other force majeure factors in daily life. In addition, the cost of sending the memory storage device for repair is also high. Therefore, how to provide a data backup function to reduce the chance of losing important data is a goal that technicians in this field should strive for. Summary of the invention

[0004] The embodiments of the present invention provide a data backup and reading system and a data backup and reading method, which can reduce the risk of storage data loss and thus improve the reliability and security of data storage.

[0005] An embodiment of the present invention provides a data backup and reading method for a memory storage device, wherein the memory storage device includes a memory controller, a first memory module, and a second memory module. The data backup and reading method includes: the memory controller receives a write instruction from a host system; the memory controller writes the write data included in the write instruction to the first memory module, and writes the write data to the second memory module; and when it is determined that the first memory module is damaged, the host system reads the write data stored in the second memory module. The first memory module and the second memory module are rewritable non-volatile memory modules.

[0006] An embodiment of the present invention further provides a data backup and reading system. The data backup and reading system includes a host system and a memory storage device. The memory storage device is electrically connected to the host system, and the memory storage device includes a memory controller, a first memory module and a second memory module. The memory controller receives a write instruction from the host system. The memory controller writes the write data included in the write instruction to the first memory module, and writes the write data to the second memory module. Furthermore, when it is determined that the first memory module is damaged, the host system reads the write data stored in the second memory module. The first memory module and the second memory module are rewritable non-volatile memory modules.

[0007] Based on the above, according to the data backup and reading system and the data backup and reading method of the embodiment of the present invention, it is possible to store the written data from the host system, and at the same time, perform data backup on the written data and store it in other memory modules. In addition, when the components in the memory storage device are damaged, based on the difference of the damaged components, the host system can read data from the undamaged memory module through the various interfaces of the memory storage device. In this way, the risk of loss of stored data due to damage to the components in the memory storage device can be reduced, thereby improving the reliability and security of data storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0009] Figure 1 is a schematic diagram of a data backup and reading system according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of an external debugging board according to an embodiment of the present invention;

[0013] Figure 5 is a flow chart of a data backup and reading method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0015] Figure 1 is a schematic diagram of a data backup and reading system according to an embodiment of the present invention.

[0016] Please refer to Figure 1 The data backup and reading system 10 includes but is not limited to a host system 11 , a memory storage device 12 and an external debug board 13 .

[0017] The host system 11 may be any type of computer system. For example, the host system 11 may be a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, etc. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 may include a solid state drive, a USB flash drive, or other types of non-volatile storage devices. The host system 11 may be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express), a Universal Serial Bus (USB), or other types of connection interfaces. Therefore, the host system 11 may store data in the memory storage device 12 and / or read data from the memory storage device 12.

[0018] The memory storage device 12 includes, but is not limited to, a connection interface 121 , a memory controller 122 , memory modules 123_1 and 123_2 , a debug port 124 , and a debug pin 125 .

[0019] The connection interface 121 is used to connect the memory storage device 12 to the host system 11 . For example, the connection interface 121 may support connection interface standards such as SATA, PCI Express or USB. The memory storage device 12 may communicate with the host system 11 via the connection interface 121 .

[0020] The memory controller 122 is connected to the connection interface 121 and the memory modules 123_1 and 123_2. The memory controller 122 has one or more debug pins 125, which allow the user to use a tool program to access the memory controller 122 through, for example, a serial peripheral interface bus (SPI) transmission protocol, and to debug the memory controller 122 from an external host. The debug pin 125 is mainly formed by connecting the transmission pin of the serial peripheral interface bus through a signal line, and then using the tool program provided in accordance with the transmission protocol to read part of the memory in the memory controller 122. In an embodiment of the present invention, the circuit of the memory controller 122 is designed to transmit data read from the memory module to an external host through the debug pin 125.

[0021] The memory controller 122 may be used to control the memory storage device 12. For example, the memory controller 122 may control the connection interface 121 and the memory modules 123_1 and 123_2 to perform data access and data management. For example, the memory controller 122 may include a central processing unit (CPU), a graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application specific integrated circuits (ASIC), programmable logic devices (PLD), or other similar devices or combinations of these devices.

[0022] The memory modules 123_1 and 123_2 are used to store data. The memory modules 123_1 and 123_2 may include rewritable non-volatile memory modules. The memory module 123 includes a memory cell array. The memory cells in the memory modules 123_1 and 123_2 store data in the form of voltage. For example, the memory modules 123_1 and 123_2 may include a single level cell (SLC) NAND flash memory module, a multi level cell (MLC) NAND flash memory module, a triple level cell (TLC) NAND flash memory module, a quad level cell (QLC) NAND flash memory module, a three-dimensional NAND flash memory module (3D NAND flash memory module) (which may have multiple three-level or four-level memory cells) or other memory modules with similar characteristics. The memory cells in the memory modules 123_1 and 123_2 are arranged in an array. It is worth mentioning that in Figure 1 The embodiment shown has two memory modules, but the present invention does not limit the number of memory modules.

[0023] In one embodiment, the memory controller 122 is also called a flash memory controller. In one embodiment, the memory modules 123_1 and 123_2 are also called flash memory modules. The memory modules 123_1 and 123_2 can receive a command sequence from the memory controller 122 and access data stored in the storage unit according to the command sequence.

[0024] The debug port 124 is used to electrically connect the memory storage device 12 to the external debug board 13, and the debug board controller 143 debugs the memory storage device 12 through the debug port 124. For example, the debug port 124 may support connection interface standards such as I2C, SATA, PCI Express or USB.

[0025] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention.

[0026] Please refer to Figure 1 and Figure 2 The memory controller 122 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory modules 123_1 and 123_2 to communicate with the memory modules 123_1 and 123_2.

[0027] The memory control circuit 23 is electrically connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory modules 123_1 and 123_2 via the memory interface 22. The memory control circuit 23 can also be regarded as the control core of the memory controller 122. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 122. In addition, the memory control circuit 23 may include one or more buffer memories for temporarily storing data.

[0028] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention.

[0029] Please refer to Figure 1 and Figure 3 , the memory module includes a plurality of physical units 301(0) to 301(C). Each physical unit includes a plurality of storage units and is used to store data in a non-volatile manner. A plurality of physical units may form a physical block. A plurality of physical units (or storage units) in a physical block may be erased simultaneously. In addition, the memory control circuit 23 may configure a plurality of logical units 311(0) to 311(D) to map at least a portion of the physical units. For example, a logical unit may be composed of one or more logical addresses. The mapping relationship between the logical unit and the physical unit may be recorded in a logical to physical mapping table.

[0030] In one embodiment, the memory module is logically divided into a data area 310, an idle area 320, and a system area 330. The physical units 301(1)-301(A) logically belonging to the data area 310 store data (also called user data) from the host system 11. After the physical units in the data area 310 are erased, they will be associated with the idle area 320. In other words, the physical units 301(A+1)-301(B) in the idle area 320 have all been erased and do not store valid data. Among them, multiple physical units in the idle area 320 can form an idle physical block.

[0031] The physical units 301(B+1)-301(C) logically belonging to the system area 330 are used to record system data. For example, the system data includes the manufacturer and model of the memory module, the number of physical blocks of the memory module, the number of physical units of each physical block, etc. In particular, the number of physical units in the data area 310, the idle area 320 and the system area 330 will vary according to different memory specifications.

[0032] Figure 4 is a schematic diagram of an external debugging board according to an embodiment of the present invention. Figure 4The external debugging board 13 includes but is not limited to a debugging interface 141 , a connection interface 142 and a debugging board controller 143 .

[0033] The debugging interface 141 is used to electrically connect the external debugging board 13 to the memory storage device 12. For example, the debugging interface 141 can be a port such as an M.2 connector that supports connection interface standards such as SATA, PCI Express, or USB, but the present invention is not limited thereto. The external debugging board 13 can communicate with the memory storage device 12 via the debugging interface 141.

[0034] The connection interface 142 is used to electrically connect the external debugging board 13 to the host system 11, and the external debugging board 13 can communicate with the host system 11 via the connection interface 142. For example, the connection interface 142 can support connection interface standards such as SATA, PCI Express or USB. In one embodiment, the connection interface 142 includes a Universal Asynchronous Receiver / Transmitter (UART) port, but the present invention is not limited thereto.

[0035] The debug board controller 143 is electrically connected to the debug interface 141 and the connection interface 142. The debug board controller 143 may transmit the logic of the debug mode request to the debug port 124 of the memory storage device 12 via the debug interface 141. And the debug board controller 143 may be connected to the host system 11 via the connection interface 142, and receive commands from the host system 11 via the connection interface 142, and may convert the debug signal of the host system 11 into the signal required by the debug port 124 via the connection interface 142. The debug board controller 143 may also be regarded as the control core of the external debug board 13. Alternatively, the external debug board 13 may be incorporated into the host system 11 as already shown.

[0036] In an exemplary embodiment, the memory controller 122 receives a write instruction from the host system 11. Then, the memory controller 122 writes the write data included in the write instruction to multiple memory modules. For example, after receiving the write instruction, the memory controller 122 can transmit the write data to the multiple memory modules by branching the output signal including the write data into signals corresponding to the interfaces of the multiple memory modules, and inputting the branched output signals into the corresponding memory modules. In other words, the memory controller 122 can back up the write data in multiple memory modules.

[0037] In this exemplary embodiment, one of the multiple memory modules used for backing up data can be used as a main memory module. When the memory controller 122 receives a data read instruction from the host system 11, it will give priority to reading the data stored in the main memory module. On the other hand, other memory modules other than the main memory module can be used as backup memory modules to back up the written data when the memory storage device 12 operates normally.

[0038] Please refer to Figure 1 For the convenience of explanation, it is assumed that there are two memory modules, but the present invention does not limit the number of memory modules. The memory controller 122 receives a write instruction from the host system 11. Then, the memory controller 122 writes the write data included in the write instruction to the memory module 123_1 (also referred to as the first memory module), and writes the write data to the memory module 123_2 (also referred to as the second memory module). In an exemplary embodiment, the memory controller 122 may set the first memory module as the main memory module, and may set the second memory module as the backup memory module.

[0039] In different scenarios, various components included in the memory storage device 12 may be damaged and fail to operate normally. For example, when it is determined that a memory module (such as a main memory module) is damaged, the host system 11 can store the written data from other memory modules. Figure 1 When it is determined that the memory module 123_1 is damaged, the host system 11 can read the write data stored in the memory module 123_2.

[0040] In an exemplary embodiment, when it is determined that the memory module 123_1 is damaged, the host system 11 transmits a data read instruction to the memory controller 122 to read the write data stored in the memory module 123_2 through the memory controller 122. In this exemplary embodiment, the data read instruction transmitted by the host system 11 indicates to read the write data stored in the memory module 123_2. Here, the memory controller 122 reads the stored write data from the memory module 123_2 in response to receiving the data read instruction, and transmits the read data to the host system 11 via the connection interface 121.

[0041] In an exemplary embodiment, the memory module 123_2 can be electrically connected to the host system 11 through the external debug board 13. For example, the debug interface 141 of the external debug board 13 can be connected to the debug port 124 of the memory storage device 12 in a pin-type connection structure. When it is determined that the memory module 123_1 is damaged, the host system 11 will transmit a data read instruction to the external debug board 13. Here, the debug board controller 143 of the external debug board 13, in response to receiving the data read instruction from the host system 11, can convert the data read instruction of the host system 11 into a signal required by the debug port 124 through the connection interface 142, so that the debug board controller 143 can read the write data stored in the memory module 123_2 through the debug port 124 of the memory storage device 12.

[0042] In this exemplary embodiment, the host system 11 transmits a data read instruction to the connection interface 142 of the external debugging board 13, and the data read instruction indicates to read the write data stored in the memory module 123_2. Here, the debugging board controller 143 responds to receiving the data read instruction.

[0043] The write data stored in the memory module 123_2 is read through the debug port 124 of the memory storage device 12, and the read data is transmitted to the host system 11 through the connection interface 142. In this way, the host system 11 can read data from the debug port 124 of the memory storage device 12 using the external debug board 13.

[0044] In an exemplary embodiment, the host system 11 may further determine whether the memory controller is damaged. In this exemplary embodiment, the memory module 123_2 may be electrically connected to the host system 11 via the external debugging board 13. When it is determined that the memory module 123_1 and the memory controller 122 are damaged, the debug board controller 143 of the external debugging board 13 responds to receiving a data read instruction from the host system 11 and reads the write data stored in the memory module 123_2 via the debug port 124 of the memory storage device 12. The specific content of reading data via the external debugging board 13 can be referred to above, and will not be repeated here. In this way, the host system 11 can use the external debugging board 13 to read data from the debug port 124 of the memory storage device 12, so that the data in the memory module can be read without passing through the damaged memory controller 122.

[0045] In an exemplary embodiment, the host system 11 may be electrically connected to the memory controller 12 via the debug pin 125 of the memory controller 12, and the host system 11 may read the written data via the debug pin 125. For example, when it is determined that the memory module 123_1 is damaged, the host system 11 may read the written data stored in the memory module 123_2 via the debug pin 125 of the memory controller 12. In this exemplary embodiment, the host system 11 transmits a data read instruction to the debug pin 125, and the data read instruction indicates to read the written data stored in the memory module 123_2. Here, the memory controller 12 reads the written data stored in the memory module 123_2 in response to receiving the data read instruction, and transmits the read data to the host system 11 via the debug pin 125.

[0046] Figure 5 is a flow chart of a data backup and reading method according to an embodiment of the present invention.

[0047] Please refer to Figure 5 In step S502, the memory controller receives a write instruction from the host system. In step S504, the memory controller writes the write data included in the write instruction to the first memory module, and writes the write data to the second memory module. In step S506, when it is determined that the first memory module is damaged, the host system reads the write data stored in the second memory module.

[0048] However, Figure 5 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 5 Each step in the above process can be implemented as multiple codes or circuits, which is not limited by the present invention. Figure 5 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0049] In summary, the data backup and reading system and the data backup and reading method provided in this embodiment can store the written data from the host system, and at the same time perform data backup on the written data and store it in other memory modules. Thereby, the risk of loss of stored data can be reduced. In addition, when the components in the memory storage device are damaged, based on the difference of the damaged components, the host system can read data from the undamaged memory module through the various interfaces of the memory storage device. Thereby, the risk of loss of stored data due to damage of the components in the memory storage device can be reduced, thereby improving the reliability and security of data storage.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data backup and reading method for a memory storage device, wherein the memory storage device comprises a connection interface, a memory controller, a first memory module and a second memory module, characterized in that: The memory storage device further includes a debugging port, wherein the debugging port is connected to the second memory module, and the data backup and reading method includes: The memory controller receives a write instruction from a host system; The memory controller writes the write data included in the write instruction into the first memory module, and writes the write data into the second memory module; When it is determined that the first memory module is damaged, the host system reads the write data stored in the second memory module, wherein the first memory module and the second memory module are rewritable non-volatile memory modules, and the second memory module is electrically connected to the host system through the debug port and an external debug board; and When it is determined that the first memory and the memory controller are damaged, the host system transmits a data read instruction to the external debug board, and the debug board controller of the external debug board reads the write data stored in the second memory module via the debug port in response to receiving the data read instruction from the host system.

2. The data backup and reading method according to claim 1, characterized in that: When it is determined that the first memory module is damaged, the host system transmits a data read instruction to the memory controller so as to read the write data stored in the second memory module through the memory controller.

3. The data backup and reading method according to claim 1, characterized in that: The memory controller has a debug pin, and the host system is electrically connected to the memory controller via the debug pin, wherein: The host system reads the written data via the debug pin.

4. The data backup and reading method according to claim 3, characterized in that: When it is determined that the first memory module is damaged, the host system reads the write data stored in the second memory module via the debug pin.

5. A data backup and reading system, comprising: Host system; External debugging board; as well as A memory storage device is electrically connected to the host system, the memory storage device includes a connection interface, a debug port, a memory controller, a first memory module and a second memory module, the debug port is connected to the second memory module, and the second memory module is electrically connected to the host system through the debug port and the external debug board, wherein: The memory controller receives a write instruction from the host system, The memory controller writes the write data included in the write instruction to the first memory module, and writes the write data to the second memory module, When it is determined that the first memory module is damaged, the host system reads the write data stored in the second memory module, wherein the first memory module and the second memory module are rewritable non-volatile memory modules, and When it is determined that the first memory and the memory controller are damaged, the host system transmits a data read instruction to the external debug board, and the debug board controller of the external debug board reads the write data stored in the second memory module via the debug port in response to receiving the data read instruction from the host system.

6. The data backup and reading system according to claim 5, characterized in that: When it is determined that the first memory module is damaged, the host system transmits a data read instruction to the memory controller so as to read the write data stored in the second memory module through the memory controller.

7. The data backup and reading system according to claim 5, characterized in that: The memory controller has a debug pin, and the host system is electrically connected to the memory controller via the debug pin, wherein: The host system reads the written data via the debug pin.

8. The data backup and reading system according to claim 7, characterized in that: When it is determined that the first memory module is damaged, the host system reads the write data stored in the second memory module via the debug pin.

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