System for locating pipeline bottlenecks in chip pipeline partitioning and applications

Abstract

The application discloses a system for locating a pipeline bottleneck in chip pipeline division and application, and relates to the technical field of integrated circuit design. The system comprises a verification counting device and a bottleneck locating device. The verification counting device is used for simulating and verifying the pipeline stage design of a user, and calculating clock cycle number information of each sub-module of the pipeline stage for processing a pipeline unit during the simulation and verification process. The clock cycle number information comprises a first clock cycle number and a second clock cycle number, which are respectively the pipeline unit cycle number calculated when the sub-module itself processes the pipeline unit and the actual pipeline unit cycle number calculated when the sub-module processes the pipeline unit on the pipeline system. The bottleneck locating device is used for locating a bottleneck module in the pipeline design according to the first clock cycle number and the second clock cycle number. The application can quickly locate the pipeline bottleneck by comparing the performance of each module of the pipeline stage itself and on the system, and can significantly accelerate the design iteration and performance optimization process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a system for locating a pipeline bottleneck in chip pipeline division and application thereof. BACKGROUND

[0002] In the field of chip design, pipeline design is a primary means to improve hardware performance. Pipeline technology is a technology that has both spatial parallelism and temporal parallelism in computer technology. It divides a sequential processing process into several sub-processing processes, each of which can work concurrently on independent modules. In the design of system chips, the overall performance of the system can be greatly improved by dividing a complete target operation process into several operation modules and processing them in parallel. In the design of synchronous pipeline system chips, the primary consideration is how to divide the pipeline stages.

[0003] A target operation algorithm is usually described by a C program. According to the modular programming method of the C language, a complete algorithm is usually divided into multiple functions for step-by-step calculation. However, the original intention is to facilitate software development and maintenance, and the module (function) division does not consider the specific implementation on hardware. For example, Chinese patent Zl201310016195.4 provides a scheme for completing module pipeline division based on C-to-RTL synthesis: it synthesizes each function of the C program by hardware, and finally determines the pipeline hardware module division by means of certain performance optimization objectives and constraints. The above scheme determines the pipeline division by means of the C-to-RTL synthesis method, and the essence is still to divide the hardware modules based on the internal function division of the C program.

[0004] However, due to the immaturity of C-oriented synthesis tools in the current chip design field, commercial use is less, making it difficult to use the module pipeline division scheme based on the C program in actual hardware design. In actual hardware design, the hardware module pipeline division is basically completed by designers relying on their own experience. First, the chip designers analyze the performance of each pipeline module to complete the initial pipeline design by experience, and then balance the transmission rates of each module in the front and back stages of the pipeline system through several design iterations to make each pipeline module continuously and uninterruptedly process the input data stream, so as to optimize the overall system performance. After the initial pipeline design is completed, how to quickly locate the bottleneck module in the initial pipeline design to guide further optimization of the pipeline and accelerate the design iteration is a technical problem that needs to be solved in the design of pipeline system chips. SUMMARY

[0005] The system for locating a pipeline bottleneck in chip pipeline division and the application have the advantages that the system can locate the pipeline bottleneck quickly by comparing the performance of each module of the pipeline stage and on the system through the two sets of clock cycle data of each module of the pipeline stage and the processing of each pipeline unit on the system, and can further output an optimization strategy, which can significantly accelerate the design iteration and performance optimization process.

[0006] To achieve the above object, the present application provides the following technical scheme.

[0007] The system for locating a pipeline bottleneck in chip pipeline division comprises:

[0008] The verification counting device comprises a verification platform, a counter and an information transmission unit.

[0009] The verification platform is used for receiving the pipeline stage design information of a user and performing simulation verification on the pipeline stage design.

[0010] The counter is used for calculating the clock cycle number information of the processing of the pipeline unit by each sub-module of the pipeline stage during the simulation verification process, wherein the clock cycle information comprises a first clock cycle number and a second clock cycle number, the first clock cycle number is the pipeline unit cycle number calculated when the sub-module processes the pipeline unit by itself, and the second clock cycle number is the actual pipeline unit cycle number calculated when the sub-module processes the pipeline unit on the pipeline system.

[0011] The information transmission unit is used for sending the clock cycle number information obtained by the counter to the bottleneck locating device.

[0012] The bottleneck locating device is used for locating the bottleneck module in the pipeline stage design according to the first clock cycle number of each sub-module of the pipeline stage and the number of the pipeline unit, obtaining the time consumption information of each sub-module with the pipeline unit as an index, and locating the bottleneck module in the pipeline stage design according to the second clock cycle number of each sub-module of the pipeline stage and the number of the pipeline unit, and obtaining the connection information between adjacent sub-modules with the pipeline unit as an index.

[0013] Further, for each sub-module, a pipeline unit calculation start signal unit_start and a pipeline unit calculation end signal unit_done are arranged in the sub-module, and the counter is configured to:

[0014] When the first clock cycle number is calculated, the clock cycle count between the adjacent unit_start and unit_done signals is obtained as the first clock cycle number sub_self_cycles, and

[0015] In the calculation of the second clock cycle number, the clock cycle number between the adjacent unit_done and unit_done signals is obtained as the second clock cycle number sub_sys_cycles.

[0016] Further, according to the first clock cycle number sub_self_cycles and the second clock cycle number sub_sys_cycles, the first clock cycle array intsub_self_cycls[sub_num][unit_num] and the second clock cycle array intsub_sys_cycls[sub_num][unit_num] are generated in combination with the sub-module sequence and the pipeline unit sequence.

[0017] The information transmission unit is configured to send the first clock cycle array and the second clock cycle array information obtained by the calculator to the bottleneck positioning device.

[0018] Further, the bottleneck positioning device comprises a visualization unit configured to draw the self-pipeline unit cycle number over time histogram of each sub-module according to the first clock cycle number of each sub-module and the pipeline unit number, and draw the system pipeline unit actual cycle number over time histogram of each sub-module according to the second clock cycle number of each sub-module and the pipeline unit number, and output the self-pipeline unit cycle number over time histogram and the system pipeline unit actual cycle number over time histogram to a display structure.

[0019] Further, the bottleneck positioning device draws the self-pipeline unit cycle number over time histogram and the system pipeline unit actual cycle number over time histogram by calling the gnuplot tool under UNIX.

[0020] The horizontal coordinate of the self-pipeline unit cycle number over time histogram is the pipeline unit index, and the vertical coordinate is the pipeline unit cycle number calculated by each sub-module itself; the horizontal coordinate of the system pipeline unit actual cycle number over time histogram is the pipeline unit index, and the vertical coordinate is the pipeline unit actual cycle number calculated by each sub-module on the pipeline system.

[0021] Further, the pipeline optimization device is further configured to obtain optimization target information of a user, and perform speed optimization on the bottleneck module with the longest time consumption according to the optimization target information.

[0022] Further, whether there is an idle bubble between adjacent sub-modules is determined according to the connection information between the adjacent sub-modules, and the cache size between the adjacent sub-modules is optimized when the idle bubble is determined to exist.

[0023] Further, when it is determined that idle bubbles of the same level or later level appear on a certain sub-module, the buffer between the sub-module and its downstream sub-module is increased to balance the calculation variance of the downstream sub-module.

[0024] The application also provides a method for locating a pipeline bottleneck in chip pipeline division, comprising the following steps:

[0025] Receiving the pipeline stage design information of a user, and performing simulation verification on the pipeline stage design through a verification platform;

[0026] Monitoring the simulation verification process, and calculating the clock cycle number information of each sub-module of the pipeline stage in processing the pipeline unit through a counter, wherein the clock cycle information comprises a first clock cycle number and a second clock cycle number, the first clock cycle number is the pipeline unit cycle number calculated when the sub-module itself processes the pipeline unit, and the second clock cycle number is the actual pipeline unit cycle number calculated when the sub-module processes the pipeline unit on the pipeline system;

[0027] According to the first clock cycle number and the pipeline unit number of each sub-module of the pipeline stage, the time consumption information of each sub-module is acquired as an index of the pipeline unit to locate the bottleneck module in the pipeline stage design; and according to the second clock cycle number and the pipeline unit number of each sub-module of the pipeline stage, the connection information between adjacent sub-modules is acquired as an index of the pipeline unit to locate the bottleneck module in the pipeline stage design.

[0028] Further, for each sub-module, a pipeline unit calculation start signal unit_start and a pipeline unit calculation end signal unit_done are arranged inside the sub-module; and the counter is configured to:

[0029] When the first clock cycle number is calculated, the clock cycle count between the adjacent unit_start and unit_done signals is acquired as the first clock cycle number sub_self_cycles; and,

[0030] When the second clock cycle number is calculated, the clock cycle count between the adjacent unit_done and unit_done signals is acquired as the second clock cycle number sub_sys_cycles.

[0031] Compared with the prior art, the application has the following advantages and positive effects as an example: by statistically counting and recording two groups of clock cycle data of each module of the pipeline stage itself and in processing each pipeline unit on the system during simulation, the performance of each module of the pipeline stage itself and on the system is compared to realize rapid positioning of the pipeline bottleneck, and further, an optimization strategy can be given to significantly accelerate the design iteration and performance optimization process.

[0032] Further, in locating the pipeline bottleneck, the statistical data is automatically generated into a histogram in combination with the visualization tool, and the user can obtain the performance data of each module of the pipeline and on the system by visually observing the operation processing time of each module. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A structure schematic diagram of a typical synchronous design pipeline.

[0034] Figure 2 An information transmission schematic diagram of the system for locating the pipeline bottleneck provided by the embodiment of the present application.

[0035] Figure 3 A principle schematic diagram of calculating the first clock cycle number sub_self_cycles and the second clock cycle number sub_sys_cycles by the unit_start and unit_done signals provided by the embodiment of the present application.

[0036] Figure 4 A self-pipeline unit cycle number time accumulation histogram provided by the embodiment of the present application.

[0037] Figure 5 An optimized self-pipeline unit cycle number time accumulation histogram provided by the embodiment of the present application.

[0038] Figure 6 A system-pipeline unit actual cycle number time accumulation histogram provided by the embodiment of the present application.

[0039] Figure 7 A method flowchart for locating the pipeline bottleneck provided by the embodiment of the present application. DETAILED DESCRIPTION

[0040] The system for locating the pipeline bottleneck in the chip pipeline division and the application disclosed by the present application will be further described in detail in combination with the accompanying drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered in isolation, and they can be combined with each other to achieve better technical effects. In the drawings of the following embodiments, the same reference numerals appearing in each drawing represent the same features or components and can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0041] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to the present specification are merely used to cooperate with the content disclosed in the present specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions for implementing the invention. Any modification of the structure, change of the proportional relationship or adjustment of the size, which does not affect the effect and purpose that can be achieved by the invention, shall fall within the scope of the technical content disclosed by the invention. The scope of the preferred embodiments of the present invention includes additional implementations, in which the functions can be performed in a substantially simultaneous manner or in reverse order according to the functions involved, without being performed in the order as described or discussed, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0042] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail herein. However, where appropriate, such techniques, methods, and devices can be regarded as part of the specification to the extent that such techniques, methods, and devices are applicable and adaptable to the technical content disclosed in the present specification. In all examples shown and discussed herein, any specific value should be interpreted as merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiments can have different values. Embodiments

[0043] For a typical pipeline structure in a synchronous pipeline system chip design, please refer to Figure 1 As an example, Figure 1SUB1, SUB2, SUB3 and SUB4, wherein SUB1 is at the first stage, SUB2 is at the second stage, SUB3 is at the third stage, and so on. The pipeline running process of the system (i.e. the system where the pipeline is located) is as follows: T1 period: SUB1 submodule completes the calculation of the flow water unit Unit1 and sends its result to the next stage SUB2 submodule. T2 period: SUB1 accesses the calculation of the new flow water unit Unit2 and sends the result to the next stage SUB2 submodule, while SUB2 calculates the flow water unit Unit1 in this period and sends the result to the next stage SUB3 submodule. T3 period: SUB1 accesses the calculation of the new flow water unit Unit3 and sends the result to the next stage SUB2 submodule, while SUB2 calculates the flow water unit Unit2 in this period and sends the result to the next stage SUB3 submodule, while SUB3 calculates the flow water unit Unit1 in this period and sends the result to the next stage SUB4 submodule. T4 period: SUB1 accesses the calculation of the new flow water unit Unit4 and sends the result to the next stage SUB2 submodule, while SUB2 calculates the flow water unit Unit3 in this period and sends the result to the next stage SUB3 submodule, while SUB3 calculates the flow water unit Unit2 in this period and sends the result to the next stage SUB4 submodule, and SUB4 calculates the flow water unit Unit1 in this period and sends the result as the final output. By T4 period, the pipeline starts full load operation, and each submodule SUB1, SUB2, SUB3 and SUB4 starts full flow water parallel calculation until the completion of all flow water unit Unit calculation.

[0044] If each submodule SUB1, SUB2, SUB3 and SUB4 in Figure 1 the initial design is consistent in the operation time of each flow water unit Unit, the system will reach the most ideal state. In this state, each module SUB1 / 2 / 3 / 4 of the pipeline is completely parallel, the flow water is full load execution, and there is no idle bubble (or pipeline bubble or idle waiting state). However, in actual design, due to the difficulty in accurately estimating the processing speed of each submodule in the initial design of the module division, the processing time of different submodules (SUB) for the same flow water unit (Unit) is also difficult to completely consistent, so that there are more idle bubbles (bubble) between the front and rear stage submodules on the pipeline, which reduces the parallelism of each submodule and affects the system performance.

[0045] The application starts from the simulation verification stage after the initial design of the pipeline, acquires two sets of clock period number information of each sub-module (SUB) of the pipeline stage and processing each pipeline unit (Unit) on the system during the simulation verification, realizes the rapid positioning of the system bottleneck by comparing and observing the performance of each sub-module itself and on the system, and further can give the corresponding optimization strategy for guidance to accelerate the design iteration or performance optimization process.

[0046] Specifically, referring to Figure 2 The system for positioning the pipeline bottleneck in the chip pipeline division provided by the application is shown in the figure.

[0047] The system can include a verification counting device and a bottleneck positioning device.

[0048] The verification counting device can specifically include a verification platform, a counter and an information transmission unit.

[0049] The verification platform is used to receive the pipeline stage design information of the user and perform simulation verification on the pipeline stage design.

[0050] The counter is used to calculate the clock period number information of the pipeline unit (Unit) processed by each sub-module (SUB) of the pipeline stage during the simulation verification process, and the clock period information includes a first clock period number and a second clock period number, the first clock period number is the pipeline unit period number calculated when the sub-module processes the pipeline unit, and the second clock period number is the actual pipeline unit period number calculated when the sub-module processes the pipeline unit on the pipeline system.

[0051] The information transmission unit is used to send the clock period number information obtained by the counter to the bottleneck positioning device.

[0052] After receiving the information sent by the verification counting device, the bottleneck positioning device can realize the rapid positioning of the system pipeline bottleneck by comparing the performance of each sub-module of the pipeline stage itself and on the system according to the two sets of clock period data. Specifically, the bottleneck positioning device can acquire the time consumption information of each sub-module with the pipeline unit as the index according to the first clock period number and the number of pipeline units of each sub-module of the pipeline stage to locate the bottleneck module in the pipeline stage design, and acquire the connection information between adjacent sub-modules with the pipeline unit as the index according to the second clock period number and the number of pipeline units of each sub-module of the pipeline stage to locate the bottleneck module in the pipeline stage design.

[0053] In other words, for each submodule in the pipelined design, the counter calculates two sets of data: the number of pipeline unit cycles calculated by the submodule itself (i.e., the number of pipeline unit cycles calculated when the submodule processes the pipeline unit, which is the first clock cycle count) and the actual number of pipeline unit cycles calculated by the submodule on the pipeline system (i.e., the actual number of pipeline unit cycles calculated by the submodule when processing the pipeline unit on the pipeline system, which is the second clock cycle count). In this embodiment, it is preferable to calculate the above two sets of data for each submodule by constructing pipeline unit calculation start and end signals inside each submodule.

[0054] In practical implementation, for each submodule, a pipeline unit calculation start signal `unit_start` and a pipeline unit calculation end signal `unit_done` are set within the submodule. At this time, the first clock cycle count is set to `sub_self_cycles` (i.e., the number of pipeline unit calculation cycles performed by the submodule itself), and the second clock cycle count is set to `sub_sys_cycles` (i.e., the actual number of pipeline unit calculation cycles performed by the submodule on the pipeline system). Combined with... Figure 3 As shown, the cycle count between the start signal unit_start and the end signal unit_done is the required number of first clock cycles, sub_self_cycles.

[0055] For the second clock cycle number sub_sys_cycles, since Figure 3 The presence of a buffer bubble in the pipeline causes the submodule not to immediately configure the start signal unit_start (to start the computation of the next pipeline unit) after configuring the end signal unit_done. Therefore, the actual computation cycle of the submodule on the system needs to include the number of clock cycles corresponding to this buffer bubble. In other words, the second clock cycle number sub_sys_cycles is the cycle count between the two end signals unit_done.

[0056] Accordingly, the calculator is configured to: when calculating the first clock cycle count, obtain the clock cycle count between two adjacent unit_start and unit_done signals as the first clock cycle count sub_self_cycles; and when calculating the second clock cycle count, obtain the clock cycle count between two adjacent unit_done and unit_done signals as the second clock cycle count sub_sys_cycles.

[0057] Preferably, according to the first clock cycle number sub_self_cycles and the second clock cycle number sub_sys_cycles, in combination with the sub-module sequence and the pipeline unit sequence, the first clock cycle array intsub_self_cycls[sub_num][unit_num] and the second clock cycle array intsub_sys_cycls[sub_num][unit_num] can be generated. The information transmission unit is configured to send the first clock cycle array and the second clock cycle array information obtained by the calculator to the bottleneck positioning device.

[0058] In the embodiment, the bottleneck positioning device can further comprise a visualization unit. The visualization unit is configured to draw the self-pipeline unit cycle number of the sub-module over time accumulated histogram according to the first clock cycle number of each sub-module of the pipeline stage and the pipeline unit number, draw the system pipeline unit actual cycle number of the sub-module over time accumulated histogram according to the second clock cycle number of each sub-module of the pipeline stage and the pipeline unit number, and send the self-pipeline unit cycle number over time accumulated histogram and the system pipeline unit actual cycle number over time accumulated histogram to the display structure for output.

[0059] In the preferred embodiment, the bottleneck positioning device draws the self-pipeline unit cycle number over time accumulated histogram and the system pipeline unit actual cycle number over time accumulated histogram by calling the gnuplot tool under UNIX.

[0060] In the specific implementation, after receiving the first clock cycle array and the second clock cycle array, the bottleneck positioning device can call the gnuplot visualization tool under UNIX to automatically generate the corresponding histogram with the obtained data, so that the user can intuitively compare and observe the performance of each sub-module itself and on the system, and quickly obtain the module bottleneck information of the pipeline design through the histogram.

[0061] The horizontal coordinate of the self-pipeline unit cycle number over time accumulated histogram is the pipeline unit index, and the vertical coordinate is the pipeline unit cycle number calculated when each sub-module processes the pipeline unit.

[0062] The horizontal coordinate of the system pipeline unit actual cycle number over time accumulated histogram is the pipeline unit index, and the vertical coordinate is the pipeline unit actual cycle number calculated when each sub-module processes the pipeline unit on the pipeline system.

[0063] In the embodiment, further, the system can further give the corresponding optimization strategy according to the bottleneck information to accelerate the design iteration or performance optimization process.

[0064] At this time, the system can further comprise a pipeline optimization device. Considering that the processing speed of the pipeline is the main index for evaluating the pipeline design, the pipeline optimization device is configured to obtain optimization target information of a user, and perform speed optimization on a bottleneck module with the longest time consumption according to the optimization target information.

[0065] Preferably, the pipeline optimization device can further determine whether there is an idle bubble between adjacent sub-modules according to the connection information between the adjacent sub-modules, and optimize the cache size between the adjacent sub-modules when the idle bubble is determined to exist. Further, when an idle bubble of a later stage is determined to exist on a certain sub-module, the cache between the sub-module and a downstream sub-module thereof is increased to balance the calculation variance of the downstream sub-module.

[0066] That is, when locating the bottleneck of the pipeline and guiding the optimization strategy, the embodiment can locate from two dimensions. The details are described below. Figure 4 to Figure 6 Detailed description.

[0067] 1) Obtain time consumption information of each sub-module through the first number of clock cycles sub_self_cycles to locate a bottleneck module in the pipeline stage design, and perform speed optimization on the sub-module with the longest time consumption.

[0068] As an example of a typical way, still taking four front and rear stage sub-modules SUB1, SUB2, SUB3 and SUB4 as an example, a sub_self_cycls histogram drawn by a visualization tool is shown in FIG. 2. The horizontal coordinate of the sub_self_cycls histogram is a flow unit unit index, the vertical coordinate is the number of cycles of calculation of each sub-module SUB on the corresponding flow unit unit, and the histogram adopts a row stacked manner. Figure 4

[0069] From the bottleneck analysis of the above histogram, it can be known that the sub-module SUB1 has the longest time consumption, and the sub-module SUB1 with the longest time consumption is located as a bottleneck module. When subsequent pipeline optimization is performed, the speed of the SUB1 sub-module can be optimized first.

[0070] Specifically, an optimized sub_self_cycls histogram is shown in FIG. 3. It can be directly seen that the number of self-computation cycles of the SUB1 sub-module reaches the optimization target (the time consumption is shortened, and the number of cycles is reduced from about 300 to about 200). Figure 5

[0071] 2) After the optimization of the SUB1 sub-module in 1), the connection information between adjacent sub-modules is obtained by analyzing a system flow unit actual cycle number accumulation histogram with time to locate a bottleneck module in the pipeline stage design.

[0072] ​​For example, see the histogram of sub_sys_cycls drawn using a visualization tool. Figure 6 As shown. When the SUB2, SUB3, and SUB4 submodules are running in the pipeline system, Figure 6 There is a noticeable bulge at the circle in the image, and the starting point is due to the slowdown in processing of the SUB2 submodule.

[0073] There are usually two possibilities for SUB2 to slow down: either the preceding submodule SUB1 slows down, or the following submodule SUB3 slows down. (Comparison) Figure 6 histogram of sub_sys_cycls and Figure 5 The histogram of sub_self_cycls shows that SUB1 remains unchanged, while SUB3 has a large variance in the number of cycles processed by different flow units (the calculation of SUB3 slows down in the area where the circle is located), which causes idle bubbles to appear on SUB2 that are equivalent to those of the subsequent stages. Therefore, SUB2 and SUB3 are identified as bottleneck modules.

[0074] When the pipeline optimization device performs optimization, if it determines that the aforementioned idle bubble is an idle bubble of the subsequent stage, it selects to increase the buffer between the bottleneck modules SUB2 and SUB3 to balance the calculation variance of the bottleneck module SUB3, thereby optimizing the pipeline performance.

[0075] See Figure 7 As shown, another embodiment of the present invention provides a method for locating pipeline bottlenecks in chip pipeline partitioning. The method includes the following steps:

[0076] S100 receives the user's pipeline design information and performs simulation verification of the pipeline design through the verification platform.

[0077] S200, monitor the simulation verification process, and calculate the clock cycle information of each submodule in the pipeline stage processing pipeline units through a counter. The clock cycle information includes a first clock cycle number and a second clock cycle number. The first clock cycle number is the number of pipeline unit cycles calculated by the submodule itself when processing pipeline units, and the second clock cycle number is the actual number of pipeline unit cycles calculated by the submodule when processing pipeline units on the pipeline system.

[0078] S300: Based on the first and second clock cycle counts of each submodule in the pipeline stage, the bottleneck module in the pipeline stage design is located. Specifically, based on the first clock cycle count and the number of pipeline units of each submodule in the pipeline stage, the timing information of each submodule is obtained using the pipeline unit as an index to locate the bottleneck module in the pipeline stage design; and based on the second clock cycle count and the number of pipeline units of each submodule in the pipeline stage, the connection information between adjacent submodules is obtained using the pipeline unit as an index to locate the bottleneck module in the pipeline stage design.

[0079] That is, for each sub-module in the pipeline design, the counter calculates two sets of data: the number of pipeline unit cycles calculated by the sub-module itself (i.e. the number of pipeline unit cycles calculated by the sub-module itself when processing the pipeline unit, which is the first number of clock cycles) and the number of actual pipeline unit cycles calculated by the sub-module on the pipeline system (i.e. the number of actual pipeline unit cycles calculated by the sub-module on the pipeline system when processing the pipeline unit, which is the second number of clock cycles). In this embodiment, the two sets of data of each sub-module are preferably calculated by constructing a pipeline unit calculation start signal and a pipeline unit calculation end signal inside each sub-module.

[0080] In implementation, for each sub-module, a pipeline unit calculation start signal unit_start and a pipeline unit calculation end signal unit_done are provided inside the sub-module. At this time, let the first number of clock cycles be sub_self_cycles (i.e. the number of pipeline unit cycles calculated by the sub-module itself), and let the second number of clock cycles be sub_sys_cycles (i.e. the number of actual pipeline unit cycles calculated by the sub-module on the pipeline system). As shown in FIG. 2, the period count between the start signal unit_start and the end signal unit_done is the first number of clock cycles sub_self_cycles. Figure 3

[0081] As shown in FIG. 2, the period count between the start signal unit_start and the end signal unit_done is the first number of clock cycles sub_self_cycles. Figure 3 As shown in FIG. 2, the period count between the start signal unit_start and the end signal unit_done is the first number of clock cycles sub_self_cycles.

[0082] Accordingly, the counter is configured to: when calculating the first number of clock cycles, obtain the clock period count between the two adjacent signals unit_start and unit_done as the first number of clock cycles sub_self_cycles; and when calculating the second number of clock cycles, obtain the clock period count between the two adjacent signals unit_done and unit_done as the second number of clock cycles sub_sys_cycles.

[0083] ​Preferably, according to the first clock cycle number sub_self_cycles and the second clock cycle number sub_sys_cycles, in combination with the sub-module sequence and the pipeline unit sequence, the first clock cycle array intsub_self_cycls[sub_num][unit_num] and the second clock cycle array intsub_sys_cycls[sub_num][unit_num] can be generated. The information transmission unit is configured to send the first clock cycle array and the second clock cycle array information obtained by the calculator to the bottleneck positioning device.

[0084] In the embodiment, the bottleneck positioning device can further comprise a visualization unit. The visualization unit is configured to draw the self-pipeline unit cycle number of the sub-module over time accumulated histogram according to the first clock cycle number of each sub-module of the pipeline stage and the pipeline unit number, draw the system-pipeline unit actual cycle number of the sub-module over time accumulated histogram according to the second clock cycle number of each sub-module of the pipeline stage and the pipeline unit number, and send the self-pipeline unit cycle number over time accumulated histogram and the system-pipeline unit actual cycle number over time accumulated histogram to the display structure for output.

[0085] In the preferred embodiment, the bottleneck positioning device draws the self-pipeline unit cycle number over time accumulated histogram and the system-pipeline unit actual cycle number over time accumulated histogram by calling the gnuplot tool under UNIX.

[0086] Other technical features are described in the foregoing embodiments, which will not be repeated here.

[0087] In the foregoing description, the disclosure of the present application is not intended to limit itself to these aspects. Rather, the components can be selectively and operatively combined in any number of ways within the scope of the target protection of the disclosure. In addition, the terms such as "include", "comprise" and "have" should be interpreted as inclusive or open, rather than exclusive or closed, unless they are explicitly defined as the opposite. All technical, scientific or other terms are consistent with the meaning understood by those skilled in the art, unless they are defined as the opposite. The common terms found in the dictionary should not be interpreted too idealistically or too unrealistically in the context of the relevant technical documents, unless the disclosure explicitly limits them as such. Any modification or modification made by those skilled in the art according to the above disclosure is within the scope of protection of the claims.

Claims

1. A system for locating pipeline bottlenecks in chip pipeline partitioning, characterized in that... include: The verification counting device includes a verification platform, a counter, and an information transmission unit; The verification platform is used to receive the user's pipeline design information and perform simulation verification on the pipeline design. The counter is used to calculate the number of clock cycles for each submodule of the pipeline to process the pipeline unit during the simulation verification process. The clock cycle information includes a first clock cycle number and a second clock cycle number. That is, for each submodule, the counter calculates two sets of data. The first clock cycle number is the number of pipeline unit cycles calculated when the submodule processes the pipeline unit itself, and the second clock cycle number is the actual number of pipeline unit cycles calculated when the submodule processes the pipeline unit on the pipeline system. The information transmission unit is used to send the clock cycle number information obtained by the calculator to the bottleneck positioning device; The bottleneck location device is used to locate the bottleneck module in the pipeline stage design by obtaining the time consumption information of each sub-module based on the first clock cycle number and the number of pipeline units of each sub-module, using the pipeline unit as an index. Furthermore, based on the second clock cycle number and pipeline unit number of each submodule in the pipeline stage, the connection information between adjacent submodules is obtained using the pipeline unit as an index to locate the bottleneck module in the pipeline stage design.

2. The system according to claim 1, characterized in that: For each submodule, a pipeline unit calculation start signal `unit_start` and a pipeline unit calculation end signal `unit_done` are set within the submodule; the calculator is configured as follows: When calculating the first clock cycle count, the clock cycle count between the two adjacent unit_start and unit_done signals is obtained as the first clock cycle count sub_self_cycles; and, When calculating the second clock cycle count, the clock cycle count between two adjacent unit_done and unit_done signals is obtained as the second clock cycle count sub_sys_cycles.

3. The system according to claim 2, characterized in that: The calculator is also configured to generate a first clock cycle array intsub_self_cycls [sub_num][unit_num] and a second clock cycle array intsub_sys_cycls [sub_num][unit_num] based on the aforementioned first clock cycle number sub_self_cycles and second clock cycle number sub_sys_cycles, combined with the submodule order and pipeline unit order; The information transmission unit is used to send the first clock cycle array and the second clock cycle array information obtained by the calculator to the bottleneck positioning device.

4. The system according to claim 1, characterized in that: The bottleneck location device includes a visualization unit, which is used to draw a histogram of the number of its own pipeline unit cycles over time based on the first clock cycle number and the number of pipeline units of each sub-module in the pipeline stage, and to draw a histogram of the actual number of system pipeline unit cycles of the sub-module on the pipeline system over time based on the second clock cycle number and the number of pipeline units of each sub-module in the pipeline stage, and to send the aforementioned histogram of its own pipeline unit cycles over time and the histogram of the actual number of system pipeline unit cycles over time to the display structure for output.

5. The system according to claim 4, characterized in that: The bottleneck location device draws a histogram of its own pipeline unit cycle count over time and a histogram of the actual cycle count of the system pipeline unit over time by calling the gnuplot tool under UNIX. The horizontal axis of the histogram of the number of self-flowing unit cycles over time is the flowing unit index, and the vertical axis is the number of flowing unit cycles calculated by each submodule when processing the flowing unit. The horizontal axis of the histogram of the actual number of system flowing unit cycles over time is the flowing unit index, and the vertical axis is the actual number of flowing unit cycles calculated by each submodule when processing the flowing unit on the pipeline system.

6. The system according to claim 1, characterized in that: It also includes a pipeline optimization device, which is used to acquire the user's optimization target information and optimize the speed of the bottleneck module with the longest time consumption based on the aforementioned optimization target information.

7. The system according to claim 6, characterized in that: The pipeline optimization device is further configured to: determine whether there are idle bubbles between adjacent sub-modules based on the connection information between adjacent sub-modules, and optimize the buffer size between the adjacent sub-modules when an idle bubble is determined to exist.

8. The system according to claim 7, characterized in that: When an idle bubble of equal level appears in a certain submodule, the cache between that submodule and its downstream submodules is increased to balance the calculation variance of its downstream submodules.

9. A method for locating pipeline bottlenecks in chip pipeline partitioning, characterized in that... Includes the following steps: Receive pipeline design information from users and perform simulation verification of the pipeline design through the verification platform; The monitoring simulation verification process uses a counter to calculate the number of clock cycles for each submodule in the pipeline stage to process the pipeline unit. The clock cycle information includes a first clock cycle number and a second clock cycle number. That is, for each submodule, the counter calculates two sets of data. The first clock cycle number is the number of pipeline unit cycles calculated by the submodule itself when processing the pipeline unit, and the second clock cycle number is the actual number of pipeline unit cycles calculated by the submodule when processing the pipeline unit on the pipeline system. Based on the first clock cycle count and pipeline unit count of each submodule in the pipeline stage, the time consumption information of each submodule is obtained by using the pipeline unit as an index to locate the bottleneck module in the pipeline stage design. Furthermore, based on the second clock cycle number and pipeline unit number of each submodule in the pipeline stage, the connection information between adjacent submodules is obtained using the pipeline unit as an index to locate the bottleneck module in the pipeline stage design.

10. The method according to claim 9, characterized in that: For each submodule, a pipeline unit calculation start signal `unit_start` and a pipeline unit calculation end signal `unit_done` are set within the submodule; the calculator is configured as follows: When calculating the first clock cycle count, the clock cycle count between the two adjacent unit_start and unit_done signals is obtained as the first clock cycle count sub_self_cycles; and, When calculating the second clock cycle count, the clock cycle count between two adjacent unit_done and unit_done signals is obtained as the second clock cycle count sub_sys_cycles.

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