Timing optimization method, system, device and storage medium

Abstract

The present application discloses a timing optimization method, including: obtaining wiring results, performing timing analysis based on the wiring results, and obtaining a timing solution path; determining whether there is room for optimization for the timing solution path; if there is room for optimization, optimizing the solution path with optimization space according to a preset optimization strategy until there is no room for optimization for the timing solution path; if there is no room for optimization, ending the optimization. By removing the existing wiring results of the critical path to be optimized, and utilizing the resources released after the idle wiring resources have been removed, a new solution path is searched for the connection relationship with poor timing. By utilizing the remaining wiring resources after the wiring is completed, the congestion factor is reconsidered to search for a solution path with better timing for the currently optimized path. The establishment time timing of the critical path is improved, and the stability of the wiring is enhanced. The embodiments of the present application provide a timing optimization system, device, and storage medium.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a timing optimization method, system, device and storage medium. Background Art

[0002] Existing FPGA routing algorithms search for valid solution paths by identifying and resolving conflicts. This search requires considering both congestion and timing factors. In the later stages of iteration, the ratio of congestion to timing factors often becomes unbalanced, leaving room for optimization in the timing of the found paths. Currently, there's no effective solution for this problem during the search process, and after generating routing results, timing optimization for critical paths is limited to manual routing. Summary of the Invention

[0003] Based on this, the present invention provides a timing optimization method, system, device and storage medium, which solve the problems of low wiring efficiency and poor path timing in the prior art.

[0004] An embodiment of the present invention provides a timing optimization method, including:

[0005] Obtaining wiring results, performing timing analysis based on the wiring results, and obtaining a timing path;

[0006] Determine whether there is room for optimization of the timing path;

[0007] If there is room for optimization, the timing path with room for optimization is optimized according to a preset optimization strategy until there is no room for optimization left for the timing path;

[0008] If there is no room for optimization, the optimization is terminated.

[0009] Furthermore, determining whether there is room for optimization of the timing path includes:

[0010] Set target timing margin;

[0011] comparing the timing margin of the current timing path with the target timing margin;

[0012] If the timing margin of the current timing path is smaller than the target timing margin, then there is room for optimization of the current timing path;

[0013] Otherwise, there is no room for optimization.

[0014] Optimizing the timing path with room for optimization according to a preset optimization strategy includes:

[0015] Select a target node, obtain the connection relationship between the last level nodes of the timing path, and select an erasure node of the timing path of the target node;

[0016] The current sequential path of the node preceding the erased node is stored; the erased node and all subsequent nodes on the solution path are deleted;

[0017] Search for a new solution path and perform timing analysis on the new solution path based on the timing analysis interface;

[0018] Comparing the timing analysis result of the new solution path with the timing analysis result of the original solution path;

[0019] If the timing margin of the new solution path is greater than the timing margin of the original solution path, the new solution path is selected;

[0020] Otherwise, the new solution path is searched to the previous node of the erased node for erasure, and then the stored current timing path of the previous node of the erased node is filled;

[0021] The connection relationships between all nodes on the timing path are traversed in sequence to optimize the timing path.

[0022] Furthermore, the step of selecting an erasing node of a target node timing path includes:

[0023] Starting from the target node, traverse all nodes on the solution path forward. When the number of next-level solution path nodes of a node is not 1, the node is erased.

[0024] An embodiment of the present invention further provides a timing optimization system, including:

[0025] An acquisition module is used to obtain a wiring result, perform timing analysis based on the wiring result, and obtain a timing path;

[0026] A judgment module, used to judge whether there is room for optimization of the timing path;

[0027] The optimization module is configured to optimize the timing path with optimization space according to a preset optimization strategy until there is no optimization space left for the timing path.

[0028] Furthermore, the judgment module includes:

[0029] The optimization space judgment module is used to set a target timing margin and compare the timing margin of the current timing path with the target timing margin. If the timing margin of the current timing path is less than the target timing margin, then there is optimization space for the current timing path; otherwise, there is no optimization space.

[0030] Furthermore, the optimization module includes:

[0031] An erasing module, configured to select a target node, obtain a connection relationship between nodes at the last level of a timing path, and select an erasing node of the timing path of the target node;

[0032] The current sequential path of the node preceding the erased node is stored; the erased node and all subsequent nodes on the solution path are deleted;

[0033] Path optimization module, used to search for new solution paths and perform timing analysis on the new solution paths based on the timing analysis interface;

[0034] Comparing the timing analysis result of the new solution path with the timing analysis result of the original solution path;

[0035] If the timing margin of the new solution path is greater than the timing margin of the original solution path, the new solution path is selected;

[0036] Otherwise, the new solution path is searched to the previous node of the erased node for erasure, and then the stored current timing path of the previous node of the erased node is filled;

[0037] The loop module is used to sequentially traverse the connection relationships between all nodes on the timing path to optimize the timing path.

[0038] Furthermore, the erasing module includes:

[0039] The erasing node selection module is used to traverse all nodes on the solution path starting from the target node. When the number of next-level solution path nodes of a node is not 1, the node is an erasing node.

[0040] An embodiment of the present invention further provides a timing optimization device, including:

[0041] Memory for storing computer programs;

[0042] A processor is configured to implement the steps of any of the above-mentioned timing optimization methods when executing the computer program.

[0043] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned timing optimization methods are implemented.

[0044] The embodiment of the present application provides a timing optimization method, which searches for a new solution path for a connection relationship with poor timing by removing the existing wiring results of the critical path to be optimized and using the resources released after the idle wiring resources have been removed. By using the remaining wiring resources after the wiring is completed, the congestion factor is reconsidered to search for a solution path with better timing for the currently optimized path. The critical path setup timing is improved and the stability of the wiring is enhanced. The embodiment of the present application provides a timing optimization system, device and storage medium, which have the above-mentioned beneficial effects and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A flowchart of a timing optimization method provided in an embodiment of the present application;

[0047] Figure 2 A flowchart of optimizing the path with optimization space according to a preset optimization strategy provided in an embodiment of the present application;

[0048] Figure 3 A structural diagram of a timing optimization system provided in an embodiment of the present application;

[0049] Figure 4 A structural diagram of another timing optimization system provided in an embodiment of the present application;

[0050] Figure 5 A structural diagram of another timing optimization system provided in an embodiment of the present application;

[0051] Figure 6 A structural diagram of a timing optimization device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0053] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0054] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0055] Please refer to Figure 1 , Figure 1 A flowchart of a timing optimization method provided in an embodiment of the present application;

[0056] It specifically includes the following steps:

[0057] Step S101: Obtain wiring results, perform timing analysis based on the wiring results, and obtain a timing path;

[0058] Timing analysis verifies that a user design can run at its rated speed. Its goal is to examine all timing paths and check for violations, i.e., timing margins less than zero. Setup time refers to the minimum time data must remain stable before a clock edge reaches a trigger. When checking for setup timing violations, the timing margin is calculated by subtracting the data signal arrival time from the required arrival time of the signal at the current checkpoint. A timing margin greater than zero indicates no violation; otherwise, a setup timing violation is detected. The specific timing analysis method can be specified by the user or manufacturer.

[0059] Step S102: Determine whether there is room for optimization of the timing path;

[0060] Optionally, determining whether there is room for optimization of the timing path includes:

[0061] A target timing margin is set, and the timing margin of the current timing path is compared with the target timing margin. If the timing margin of the current timing path is smaller than the target timing margin, there is room for optimization of the current timing path, and the process proceeds to step S103; otherwise, there is no room for optimization, and the process proceeds to step S104.

[0062] Before the optimization process begins, the user can import or manually input the target timing margin, or the system can connect to a specified location and download it. This application does not specifically limit the method for obtaining the target timing margin;

[0063] Step S103: If there is room for optimization, optimizing the timing path with room for optimization according to a preset optimization strategy until there is no room for optimization for the timing path;

[0064] Please refer to Figure 2 , Figure 2 A flowchart of optimizing the path with optimization space according to a preset optimization strategy provided in an embodiment of the present application;

[0065] It specifically includes the following steps:

[0066] Step S201: Select a target node, obtain the connection relationship between the last-level nodes in the timing path, select an erasure node in the timing path of the target node; store the current timing path of the node preceding the erasure node; delete the erasure node and all subsequent nodes on the solution path;

[0067] Copy the current solution path. If the subsequent searched new solution path does not have a better timing than the original solution path, restore the original solution path. When copying the original solution path, start from the node before the erased node. When restoring the solution path, search for the node before the erased node on the solution path to be restored and directly fill the existing solution path with the copied original solution path.

[0068] Optionally, selecting an erasing node of a target node timing path includes:

[0069] Starting from the target node, traverse all nodes on the solution path forward. When the number of next-level solution path nodes of a node is not 1, the node is erased.

[0070] To ensure optimization speed and effectiveness, the node to be erased is selected at the bifurcation point closest to the current target node, leaving the remaining solution paths connected to the last-level nodes of the target node's timing solution path unchanged. This erasure method changes the fewest paths, ensuring that the original path results of most timing paths are not affected. Furthermore, this erasure method requires the fewest paths to be searched, reducing the time required for path search.

[0071] Step S202: Search for a new solution path, perform timing analysis on the new solution path according to the timing analysis interface, compare the timing analysis result of the new solution path with the timing analysis result of the original solution path, and if the timing margin of the new solution path is greater than the timing margin of the original solution path, select the new solution path; otherwise, search the new solution path to the node before the erased node, erase it, and then fill in the stored current timing path of the node before the erased node.

[0072] The new solution path search method can reuse existing record-based search algorithms, such as A* and path finder, which are not specifically limited in this application. These algorithms mask the impact of congestion on node costs, so that the resulting solution path is primarily related to the time sequence of establishment. Because congestion is masked, the path searched by the current algorithm may conflict with points on existing solution paths. Therefore, when searching for a solution path, all points on all existing solution paths with any connections must be masked.

[0073] Recalculate the timing, and this process uses the existing timing analysis interface. Due to the influence of factors such as path reuse in the routing algorithm and inaccurate timing estimation results, the establishment time timing of the searched solution path may still be worse than the original solution path, so after obtaining a legal solution path, it is necessary to perform timing analysis again and compare it with the original timing analysis results. If the timing margin of the current result is larger, it means that the timing of the new solution path is better, otherwise it is worse. If the timing of the current result is worse, it is necessary to restore to the original solution path. When restoring, first search for the erase node of the current path according to the method of searching for the erase node in step S201, delete the erase node and all points on the solution path after the node, and then use the previously copied solution path to fill the existing solution path to complete the restoration.

[0074] Step S203: traverse the connection relationships between all nodes on the timing path in sequence to optimize the timing path.

[0075] Determine whether there is still room for optimization on the current timing solution path. If so, find the connection relationship between the nodes preceding the current connection relationship on the current timing solution path based on the results of the last timing analysis. If there is no room for optimization, exit the optimization process. If all the connections between nodes on the entire timing solution path have been optimized, and the timing margin of the solution path is still not greater than or equal to the target timing margin, exit the optimization of the current path.

[0076] Step S104: If there is no room for optimization, then the optimization is terminated.

[0077] This embodiment of the application removes the existing routing results for the critical path to be optimized and uses the resources released after the idle routing resources have been removed to search for a new solution path for the connection relationship with poor timing. By using the remaining routing resources after the routing is completed and reconsidering congestion factors, a solution path with better timing is searched for the currently optimized path. This improves the setup timing of the critical path and enhances the stability of the routing.

[0078] See also Figure 3 , Figure 3 This is a structural diagram of a timing optimization system provided in an embodiment of the present application, the system comprising:

[0079] An acquisition module 301 is configured to acquire a wiring result, perform timing analysis based on the wiring result, and acquire a timing path;

[0080] A judgment module 302 is used to judge whether there is room for optimization of the timing path;

[0081] The optimization module 303 is configured to optimize the timing path with room for optimization according to a preset optimization strategy until there is no room for optimization left for the timing path.

[0082] See also Figure 4 , Figure 4 This is a structural diagram of another timing optimization system provided in an embodiment of the present application. The judgment module 302 includes:

[0083] The optimization space judgment module is used to set a target timing margin and compare the timing margin of the current timing path with the target timing margin. If the timing margin of the current timing path is less than the target timing margin, then there is optimization space for the current timing path; otherwise, there is no optimization space.

[0084] See also Figure 5 , Figure 5 This is a structural diagram of another timing optimization system provided in an embodiment of the present application. The optimization module 303 includes:

[0085] An erasing module is used to select a target node, obtain the connection relationship between the last-level nodes in the timing path, select an erasing node in the timing path of the target node, store the current timing path of the node preceding the erasing node, and delete all nodes on the solution path following the erasing node.

[0086] A path optimization module is used to search for a new solution path, perform timing analysis on the new solution path according to the timing analysis interface, compare the timing analysis result of the new solution path with the timing analysis result of the original solution path, and select the new solution path if the timing margin of the new solution path is greater than the timing margin of the original solution path; otherwise, the new solution path is searched to the node before the erased node, erased, and then filled with the stored current timing path of the node before the erased node;

[0087] The loop module is used to sequentially traverse the connection relationships between all nodes on the timing path to optimize the timing path.

[0088] Optionally, the erasure module includes:

[0089] The erasing node selection module is used to traverse all nodes on the solution path starting from the target node. When the number of next-level solution path nodes of a node is not 1, the node is an erasing node.

[0090] Since the embodiments of the system part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the system part, and will not be repeated here.

[0091] See also Figure 6 , Figure 6 A structural diagram of a timing optimization device provided in an embodiment of the present application.

[0092] The timing optimization device 400 may vary significantly depending on its configuration or performance. It may include one or more processors (central processing units, CPUs) 401 (e.g., one or more processors), memory 402, and one or more storage media 405 (e.g., one or more mass storage devices) storing application programs 403 or data 404. The memory 402 and storage media 405 may be either transient or persistent storage. The program stored in the storage medium 405 may include one or more modules (not shown), each of which may include a series of instruction operations within the device. Furthermore, the processor 401 may be configured to communicate with the storage medium 405 to execute the series of instruction operations stored in the storage medium 405 on the timing optimization device 400.

[0093] The timing optimization device 400 may also include one or more power supplies 406, one or more wired or wireless network interfaces 407, one or more input and output interfaces 408, and / or one or more operating systems 409, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0094] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0095] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0096] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A timing optimization method, characterized in that: include: Obtaining wiring results, performing timing analysis based on the wiring results, and obtaining a timing path; Determine whether there is room for optimization of the timing path; If there is room for optimization, the timing path with room for optimization is optimized according to a preset optimization strategy until there is no room for optimization left for the timing path; If there is no room for optimization, the optimization is terminated. Optimizing the timing path with room for optimization according to a preset optimization strategy includes: Select a target node, obtain the connection relationship between the last level nodes of the timing path, and select an erasure node of the timing path of the target node; Storing the current timing path of the node preceding the erased node; Delete the erased node and all subsequent nodes on the solution path; Search for a new solution path and perform timing analysis on the new solution path based on the timing analysis interface; Comparing the timing analysis result of the new solution path with the timing analysis result of the original solution path; If the timing margin of the new solution path is greater than the timing margin of the original solution path, the new solution path is selected; Otherwise, the new solution path is searched to the previous node of the erased node for erasure, and then the stored current timing path of the previous node of the erased node is filled; The connection relationships between all nodes on the timing path are traversed in sequence to optimize the timing path.

2. A timing optimization method according to claim 1, characterized in that: The determining whether there is room for optimization of the timing path includes: Set target timing margin; comparing the timing margin of the current timing path with the target timing margin; If the timing margin of the current timing path is smaller than the target timing margin, then there is room for optimization of the current timing path; Otherwise, there is no room for optimization.

3. The timing optimization method according to claim 1, wherein: The step of selecting an erasing node of a target node timing path includes: Starting from the target node, traverse all nodes on the solution path forward. When the number of next-level solution path nodes of a node is not 1, the node is erased.

4. A timing optimization system, characterized in that: include: An acquisition module is used to obtain a wiring result, perform timing analysis based on the wiring result, and obtain a timing path; A judgment module, used to judge whether there is room for optimization of the timing path; An optimization module, configured to optimize the timing path with optimization space according to a preset optimization strategy until there is no optimization space left for the timing path; The optimization module includes: An erasing module, configured to select a target node, obtain a connection relationship between nodes at the last level of a timing path, and select an erasing node of the timing path of the target node; The current sequential path of the node preceding the erased node is stored; the erased node and all subsequent nodes on the solution path are deleted; Path optimization module, used to search for new solution paths and perform timing analysis on the new solution paths based on the timing analysis interface; Comparing the timing analysis result of the new solution path with the timing analysis result of the original solution path; If the timing margin of the new solution path is greater than the timing margin of the original solution path, the new solution path is selected; Otherwise, the new solution path is searched to the previous node of the erased node for erasure, and then the stored current timing path of the previous node of the erased node is filled; The loop module is used to sequentially traverse the connection relationships between all nodes on the timing path to optimize the timing path.

5. A timing optimization system according to claim 4, characterized in that: The judgment module includes: Optimize the space judgment module to set the target timing margin; comparing the timing margin of the current timing path with the target timing margin; If the timing margin of the current timing path is smaller than the target timing margin, then there is room for optimization of the current timing path; Otherwise, there is no room for optimization.

6. A timing optimization system according to claim 4, characterized in that: The erasing module includes: The erasing node selection module is used to traverse all nodes on the solution path starting from the target node. When the number of next-level solution path nodes of a node is not 1, the node is an erasing node.

7. A timing optimization device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the timing optimization method according to any one of claims 1 to 3 when executing the computer program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the timing optimization method according to any one of claims 1 to 3.

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