Display device

Abstract

A display device is provided. The display device of the present invention includes a plurality of pixels each connected to at least one of a plurality of scan lines and at least one of a plurality of emission lines, a scan driver that supplies a plurality of scan signals to the plurality of scan lines, and an emission driver including a plurality of stages connected to the plurality of emission lines, each of the plurality of stages supplying an emission signal to a corresponding emission line. A first stage among the plurality of stages includes a first transistor including a first electrode connected to a first power supply line, a second electrode connected to a first emission line, and a gate electrode connected to a first scan line, and a second transistor including a first electrode connected to a first node and a second electrode connected to the first emission line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from and all benefits derived from Korean Patent Application No. 10-2020-0084732, filed on Jul. 9, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present invention relate to a display device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has been attracting attention. In response to this, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices is increasing.

[0005] A display device displays an image by combining light emitted from a plurality of pixels. In order to write data into pixels and control the emission time of pixels, a scan driver and an emission driver are required. Summary of the Invention

[0006] When the scan driver and the emission driver are mounted on a display substrate, a dead area where an image cannot be displayed increases.

[0007] A technical problem to be solved is to provide a display device capable of reducing dead zones by simplifying the configuration of an emission driver.

[0008] In addition, a technical problem to be solved is to provide a display device capable of preventing a flicker phenomenon during power-on.

[0009] A display device in an embodiment of the present invention may include a plurality of pixels, a scan driver, and an emission driver, wherein each of the plurality of pixels is connected to at least one of a plurality of scan lines and at least one of a plurality of emission lines. The scan driver provides a plurality of scan signals to the plurality of scan lines. The emission driver includes a plurality of stages connected to the plurality of emission lines, each of the plurality of stages providing an emission signal to a corresponding emission line among the plurality of emission lines. A first stage among the plurality of stages may include a first transistor and a second transistor, the first transistor including a first electrode connected to a first power line, a second electrode connected to a first emission line among the plurality of emission lines, and a gate electrode connected to the first scan line among the plurality of scan lines. The second transistor includes a first electrode connected to a first node and a second electrode connected to the first emission line.

[0010] In an embodiment, the gate electrode of the second transistor may be connected to the first electrode of the second transistor.

[0011] In an embodiment, the display device may further include a common resistor including a first electrode connected to the first node and a second electrode connected to the second power line.

[0012] In an embodiment, the display device may further include a display substrate on which a plurality of pixels and an emission driver are arranged, and a circuit board on which a common resistor is arranged.

[0013] In an embodiment, the display device may further include a flexible circuit board electrically connecting the display substrate and the circuit board.

[0014] In an embodiment, a second stage among the multiple stages may include a third transistor and a fourth transistor, the third transistor including a first electrode connected to the first power line, a second electrode connected to a second emission line among the multiple emission lines, and a gate electrode connected to the second scan line among the multiple scan lines, the fourth transistor including a first electrode connected to the first node and a second electrode connected to the second emission line, and the gate electrode of the fourth transistor may be connected to the first electrode of the fourth transistor.

[0015] In an embodiment, the first stage may further include a fifth transistor including a first electrode connected to the first power line and a second electrode connected to the first emission line.

[0016] In an embodiment, the second stage may further include a sixth transistor including a first electrode connected to the first power line, a second electrode connected to the second emission line, and a gate electrode connected to the first scan line.

[0017] In an embodiment, the scan driver may sequentially apply a scan signal of an on level to the first scan line and the second scan line in each of a first frame period and a second frame period subsequent to the first frame period.

[0018] In an embodiment, the emission driver may maintain an off-level emission signal in the first and second emission lines during a first frame period and sequentially provide the off-level emission signal to the first and second emission lines during a second frame period.

[0019] In an embodiment, the second power line may be maintained at a voltage of an off level during the first frame period, and maintained at a voltage of an on level during the second frame period.

[0020] In an embodiment, the first frame period may be a frame period immediately after the display device is powered on.

[0021] In an embodiment, the scan driver may sequentially supply a first scan signal and a second scan signal of an on-level to the first scan line and the second scan line during one frame period, and the period of the on-level of the first scan signal and the period of the on-level of the second scan signal may not overlap with each other during one frame period.

[0022] In an embodiment, during one frame period, the second stage may apply a first off-level emission signal to the second emission line in synchronization with a first on-level scan signal, and apply a second off-level emission signal to the second emission line in synchronization with a second on-level scan signal.

[0023] In an embodiment, the first to fourth transistors may be P-type transistors, and the plurality of pixels may include P-type transistors.

[0024] In an embodiment, during a display period of the plurality of pixels, a voltage of the first power line may be greater than a voltage of the second power line.

[0025] In an embodiment, the first to fourth transistors may be N-type transistors, and the plurality of pixels may include N-type transistors.

[0026] In an embodiment, during a display period of the plurality of pixels, a voltage of the first power line may be lower than a voltage of the second power line.

[0027] In an embodiment, the first scan line, the second scan line, and the second emission line may be connected to the same pixel among the plurality of pixels.

[0028] In an embodiment, the pixels connected to the second scan line and the second emission line among the plurality of pixels may not be connected to the first scan line. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

[0030] Figure 1 is a block diagram for explaining an embodiment of a display device according to the present invention.

[0031] Figure 2 is a circuit diagram for explaining an embodiment of a pixel according to the present invention.

[0032] Figure 3 is a circuit diagram for explaining an embodiment of a transmission driver according to the present invention.

[0033] Figure 4 is a timing chart for explaining an embodiment of an emission driver and a driving method of a pixel according to the present invention.

[0034] Figure 5 are diagrams for explaining embodiments of a display substrate, a flexible circuit board, and a circuit board according to the present invention.

[0035] Figure 6 is a timing chart for explaining an embodiment of a method of driving a display device according to the present invention.

[0036] Figure 7 is a circuit diagram for explaining another embodiment of a pixel according to the present invention.

[0037] Figure 8 is a circuit diagram for explaining another embodiment of a transmission driver according to the present invention.

[0038] Figure 9 is a circuit diagram for explaining another embodiment of a pixel according to the present invention.

[0039] Figure 10 is a circuit diagram for explaining another embodiment of a transmission driver according to the present invention. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. Embodiments of the present invention can be implemented in various forms and are not limited to the embodiments described herein.

[0041] In order to clearly describe the present invention, parts not related to the description are omitted, and the same or similar parts are represented by the same reference numerals throughout the specification. Therefore, the above reference numerals can be used in other drawings.

[0042] In addition, for the sake of convenience of description, the size and thickness of each component shown in the drawings are arbitrarily shown, and therefore, the present invention is not necessarily limited to those shown in the drawings. In the drawings, the thickness may be exaggerated to clearly show layers and regions.

[0043] It should be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0044] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0045] The wording used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. Unless the content clearly indicates otherwise, the singular forms "a," "an," and "the," as used herein, are also intended to include the plural forms, including "at least one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It will also be understood that when the terms "comprise" and / or "comprising" or "include" and / or "including" are used in this specification, they indicate the presence of stated features, regions, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, parts, and / or groups thereof.

[0046] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It should be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figures. In an embodiment, when the device in one of the figures is turned over, the element described as being on the "lower" side of the other elements will subsequently be oriented to be on the "upper" side of the other elements. Thus, the exemplary term "lower" can cover both the "lower" and "upper" orientations depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, the element described as being "below" or "beneath" the other elements will subsequently be oriented to be "above" the other elements. Thus, the exemplary terms "lower" or "under" can cover both the above and below orientations.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0048] Embodiments are described herein with reference to schematic cross-sectional illustrations that are idealized embodiments. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. In embodiments, regions shown or described as flat may typically have rough and / or nonlinear features. In addition, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0049] Figure 1 is a block diagram for explaining an embodiment of a display device according to the present invention.

[0050] Reference Figure 1 The display device 10 in the embodiment of the present invention may include a timing controller 11 , a data driver 12 , a scan driver 13 , an emission driver 14 and a pixel unit 15 .

[0051] The timing controller 11 receives the grayscale and control signals of each image frame from an external processor and provides control signals suitable for each specification to the data driver 12, scan driver 13, emission driver 14, etc. to display an image corresponding to the image frame.

[0052] The timing controller 11 may render grayscales to correspond to the specifications of the pixel unit 15. In an embodiment, for example, an external processor may provide red grayscale, green grayscale, and blue grayscale for each unit point. However, for example, when the pixel unit 15 has a pentile structure, since adjacent unit points share pixels, pixels may not correspond one-to-one to each grayscale. In this case, grayscale rendering may be desirable. When pixels correspond one-to-one to each grayscale, grayscale rendering may be unnecessary.

[0053] The data driver 12 may use the rendered or unrendered grayscale and control signals to generate data voltages to be supplied to the data lines DL1, DL2, DL3, ..., DLj, ..., and DLn. In an embodiment, the data driver 12 may sample the grayscale using a clock signal and apply data voltages corresponding to the grayscale to the data lines DL1 to DLn in units of pixel rows (e.g., pixels connected to the same scan line). Here, j and n may be integers greater than 0, and j may be equal to or less than n.

[0054] The scan driver 13 can receive clock signals, scan start signals, etc. from the timing controller 11 to generate scan signals to be provided to the scan lines SL0, SL1, SL2, ..., SL(i-1), SLi, ... and SLm, where i and m can be integers greater than 0, and i can be equal to or less than m.

[0055] The scan driver 13 may provide scan signals to the scan lines SL0 to SLm. In an embodiment, for example, the scan driver 13 may sequentially provide scan signals having on-level pulses. The scan driver 13 may include a scan stage configured in the form of a shift register. The scan driver 13 may generate scan signals by sequentially transmitting a scan start signal in the form of an on-level pulse to the next scan stage under the control of a clock signal.

[0056] The emission driver 14 may include stages connected to the emission lines EL1, EL2, EL3, ..., ELi, ..., and ELo, where o may be an integer greater than 0. Each stage may provide an emission signal to the corresponding emission line. In an embodiment, for example, the emission driver 14 may sequentially provide an emission signal having an off-level pulse to the emission lines EL1 to ELo.

[0057] The pixel unit 15 may include a plurality of pixels. Each pixel may be connected to at least one of the scan lines SL0 to SLm and at least one of the emission lines EL1 to ELo. Furthermore, each pixel may be connected to at least one data line. In an embodiment, for example, in a pixel PXij, a scan input terminal may be connected to the i-th scan line SLi, and a data input terminal may be connected to the j-th data line DLj.

[0058] Figure 2 is a circuit diagram for explaining an embodiment of a pixel according to the present invention.

[0059] Reference Figure 2 , the pixel PXij may include transistors T1 , T2 , T3 , T4 , T5 , T6 and T7 , a storage capacitor Cst and a light emitting diode LD.

[0060] Hereinafter, a circuit including a P-type transistor will be described as an example. However, those skilled in the art will be able to design a circuit including an N-type transistor by changing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art will be able to design a circuit including a combination of a P-type transistor and an N-type transistor. A P-type transistor may be a transistor that increases the amount of current by being turned on when the voltage difference between the gate electrode and the source electrode increases in the negative direction. An N-type transistor may be a transistor that increases the amount of current by being turned on when the voltage difference between the gate electrode and the source electrode increases in the positive direction. In an embodiment, for example, the transistor can be configured in various forms such as a thin film transistor ("TFT"), a field effect transistor ("FET"), and a bipolar junction transistor ("BJT").

[0061] The transistor T1 may include a gate electrode connected to the node N1, a first electrode connected to the node N2, and a second electrode connected to the node N3. The transistor T1 may also be referred to as a driving transistor.

[0062] Transistor T2 may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the j-th data line DLj, and a second electrode connected to node N2. Transistor T2 may also be referred to as a scan transistor. The first electrode of transistor T2 may be a data input terminal DIT of pixel PXij. Furthermore, the gate electrode of transistor T2 may be a scan input terminal SIT of pixel PXij.

[0063] The transistor T3 may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the node N1, and a second electrode connected to the node N3. The transistor T3 may also be referred to as a diode-connected transistor.

[0064] The transistor T4 may include a gate electrode connected to the (i-1)th scan line SL(i-1), a first electrode connected to the node N1, and a second electrode connected to the initialization line INTL. In another embodiment, the gate electrode of the transistor T4 may be connected to another scan line. The transistor T4 may also be referred to as a gate initialization transistor.

[0065] The transistor T5 may include a gate electrode connected to the i-th emission line ELi, a first electrode connected to the first display power line ELVDDL, and a second electrode connected to the node N2. The transistor T5 may also be referred to as an emission transistor. In another embodiment, the gate electrode of the transistor T5 may be connected to another emission line.

[0066] The transistor T6 may include a gate electrode connected to the i-th emission line ELi, a first electrode connected to the node N3, and a second electrode connected to the anode of the light emitting diode LD. The transistor T6 may also be referred to as an emission transistor. In another embodiment, the gate electrode of the transistor T6 may be connected to another emission line.

[0067] The transistor T7 may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the initialization line INTL, and a second electrode connected to the anode of the light emitting diode LD. The transistor T7 may also be referred to as an anode initialization transistor. In another embodiment, the gate electrode of the transistor T7 may be connected to another scan line. In an embodiment, for example, the gate electrode of the transistor T7 may be connected to the (i+1)-th scan line.

[0068] A first electrode of the storage capacitor Cst may be connected to the first display power line ELVDDL, and a second electrode of the storage capacitor Cst may be connected to the node N1.

[0069] The light emitting diode LD may include an anode connected to the second electrode of the transistor T6 and a cathode connected to the second display power line ELVSSL. The light emitting diode LD may include an organic light emitting diode, an inorganic light emitting diode, a quantum dot / well light emitting diode, etc. In addition, the light emitting diode LD may include a plurality of light emitting diodes connected in series, in parallel, or in series and parallel.

[0070] A first display power supply voltage may be applied to the first display power supply line ELVDDL, a second display power supply voltage may be applied to the second display power supply line ELVSSL, and an initialization voltage may be applied to the initialization line INTL. In an embodiment, for example, during a display period of the display device 10, the first display power supply voltage may be greater than the second display power supply voltage. In an embodiment, for example, the initialization voltage may be equal to or greater than the second display power supply voltage. In an embodiment, for example, the initialization voltage may correspond to a data voltage having the smallest magnitude among available data voltages. In an embodiment, for example, the magnitude of the initialization voltage may be smaller than the magnitude of the available data voltages.

[0071] Figure 3 is a circuit diagram for explaining an embodiment of a transmission driver according to the present invention.

[0072] Reference Figure 3 , the emission driver 14 in the embodiment of the present invention may include a plurality of stages ST1 , ST2 , . . . , and STi , . . .

[0073] In an embodiment, for example, the first stage ST1 may include a first transistor M1 , a second transistor M2 , and a fifth transistor M5 .

[0074] The first transistor M1 may include a first electrode connected to the first power line VGHL, a second electrode connected to the first emission line EL1, and a gate electrode connected to the first scan line SL1.

[0075] The second transistor M2 may include a first electrode connected to the first node NM1 and a second electrode connected to the first emission line EL1. The gate electrode of the second transistor M2 may be connected to the first electrode of the second transistor M2. That is, the second transistor M2 may be connected in the form of a diode. In an embodiment, the second transistor M2 may be replaced by a diode.

[0076] The fifth transistor M5 may include a first electrode connected to the first power line VGHL and a second electrode connected to the first emission line EL1. A gate electrode of the fifth transistor M5 may be connected to the scan line SL0.

[0077] In an embodiment, for example, the second stage ST2 may include a third transistor M3 , a fourth transistor M4 , and a sixth transistor M6 .

[0078] The third transistor M3 may include a first electrode connected to the first power line VGHL, a second electrode connected to the second emission line EL2, and a gate electrode connected to the second scan line SL2.

[0079] The fourth transistor M4 may include a first electrode connected to the first node NM1 and a second electrode connected to the second emission line EL2. The gate electrode of the fourth transistor M4 may be connected to the first electrode of the fourth transistor M4. That is, the fourth transistor M4 may be connected in the form of a diode. In an embodiment, the fourth transistor M4 may be replaced by a diode.

[0080] The sixth transistor M6 may include a first electrode connected to the first power line VGHL, a second electrode connected to the second emission line EL2, and a gate electrode connected to the first scan line SL1.

[0081] In an implementation, for example, the i-th stage STi may include a seventh transistor M7 , an eighth transistor M8 , and a ninth transistor M9 .

[0082] The seventh transistor M7 may include a first electrode connected to the first power line VGHL, a second electrode connected to the i-th emission line ELi, and a gate electrode connected to the i-th scan line SLi.

[0083] The eighth transistor M8 may include a first electrode connected to the first node NM1 and a second electrode connected to the i-th emission line ELi. The gate electrode of the eighth transistor M8 may be connected to the first electrode of the eighth transistor M8. That is, the eighth transistor M8 may be connected in the form of a diode. In an embodiment, the eighth transistor M8 may be replaced by a diode.

[0084] The ninth transistor M9 may include a first electrode connected to the first power line VGHL, a second electrode connected to the i-th emission line ELi, and a gate electrode connected to the (i-1)-th scan line SL(i-1).

[0085] The display device 10 may include a common resistor CREG having a first electrode connected to a first node NM1 and a second electrode connected to a second power supply line VGLL. The stages ST1, ST2, ..., and STi, ... may be commonly connected to the common resistor CREG via the first node NM1. The common resistor CREG may have a high resistance value and require a large area for placement (e.g., mounting). Therefore, the common resistor CREG may be preferably placed outside the emission driver 14.

[0086] In the illustrated embodiment, since each of the stages ST1, ST2, ..., and STi, ... includes three transistors and does not require a separate clock signal, its configuration can be simplified. Therefore, the dead zone can be reduced.

[0087] Figure 4 is a timing chart for explaining an embodiment of an emission driver and a driving method of a pixel according to the present invention.

[0088] The scan driver 13 may sequentially supply an (i-1)th scan signal and an i-th scan signal of an on-level to the (i-1)th scan line SL(i-1) and the i-th scan line SLi during one frame period. During one frame period, periods ta1 to ta2 of the on-level of the (i-1)th scan signal and periods ta3 to ta4 of the on-level of the i-th scan signal may not overlap with each other.

[0089] During one frame period, the i-th stage STi of the emission driver 14 may apply a first off-level emission signal to the i-th emission line ELi (ta1 to ta2) in synchronization with the (i-1)-th scan signal of the on-level, and apply a second off-level emission signal to the i-th emission line ELi (ta3 to ta4) in synchronization with the i-th scan signal of the on-level.

[0090] Specifically, at time point ta1, the data voltage DATA(i-1)j for the (i-1)th pixel may be applied to the jth data line DLj, and a scan signal of a turn-on level (logic low level) may be applied to the (i-1)th scan line SL(i-1).

[0091] At this time, since the scan signal of the off level (logic high level) is applied to the i-th scan line SLi, the transistor T2 may be in an off state and may prevent the data voltage DATA(i-1)j for the (i-1)-th pixel from being written to the pixel PXij. Since the transistor T4 is in an on state, the node N1 may be connected to the initialization line INTL and the voltage of the node N1 may be initialized.

[0092] At this time, since the ninth transistor M9 of the i-th stage STi is turned on, the first power supply voltage VGH of the first power supply line VGHL can be applied to the i-th emission line ELi. During the display period of the display device 10, the first power supply voltage VGH can be in an off-level (logic high level). Accordingly, since the emission signal of the off-level is applied to the i-th emission line ELi, the transistors T5 and T6 can be in an off-state, and unnecessary light emission of the light emitting diode LD due to the process of applying the initialization voltage can be prevented.

[0093] At this time, the first node NM1 may be charged with the first power voltage VGH through the ninth transistor M9 and the eighth transistor M8. However, the other emission lines EL1 and EL2 may be maintained at a turn-on level (logic low level) due to the diode-connected transistors M2 and M4.

[0094] At time point ta2, a scan signal of an off level may be applied to the (i-1)th scan line SL(i-1), and the ninth transistor M9 of the i-th stage STi may be turned off. Accordingly, the i-th emission line ELi and the first node NM1 in a floating state may be connected to the second power supply line VGLL and charged with the second power supply voltage VGL. During the display period of the display device 10, the second power supply voltage VGL may be at an on level (logic low level).

[0095] At time point ta3, the data voltage DATAij for the i-th pixel PXij may be applied to the j-th data line DLj, and a scan signal of an on-level may be applied to the i-th scan line SLi. Accordingly, transistors T2, T1, and T3 may be in an on state, and the j-th data line DLj and node N1 may be electrically connected. Accordingly, a compensation voltage obtained by subtracting the threshold voltage of transistor T1 from the data voltage DATAij may be applied to the second electrode of the storage capacitor Cst (i.e., node N1), and the storage capacitor Cst may maintain a voltage corresponding to the difference between the first display power supply voltage and the compensation voltage. This period may also be referred to as a threshold voltage compensation period.

[0096] At this time, since the transistor T7 is in the on state, the anode of the light emitting diode LD and the initialization line INTL may be connected, and the light emitting diode LD may be initialized with an amount of charge corresponding to the voltage difference between the initialization voltage and the second display power voltage.

[0097] At this time, since the seventh transistor M7 of the i-th stage STi is turned on, the first power supply voltage VGH of the first power supply line VGHL can be applied to the i-th emission line ELi. Accordingly, since the emission signal of the off level is applied to the i-th emission line ELi, the transistors T5 and T6 can be in a turned-off state, and unnecessary light emission of the light emitting diode LD due to the process of compensating the threshold voltage can be prevented.

[0098] At this time, the first node NM1 may be charged with the first power voltage VGH through the seventh transistor M7 and the eighth transistor M8. However, the other emission lines EL1 and EL2 may be maintained at an on level due to the diode-connected transistors M2 and M4.

[0099] At time point ta4, the off-level scan signal may be applied to the i-th scan line SLi, and the seventh transistor M7 of the i-th stage STi may be turned off. Accordingly, the i-th emission line ELi and the first node NM1 in the floating state may be connected to the second power line VGLL and charged with the second power voltage VGL.

[0100] When the emission signal of the on level is applied to the i-th emission line ELi, transistors T5 and T6 may be in a turned-on state. Accordingly, a driving current path may be provided through the first display power line ELVDDL, transistor T5, transistor T1, transistor T6, light emitting diode LD, and second display power line ELVSSL.

[0101] The amount of driving current flowing through the first and second electrodes of the transistor T1 may be controlled according to the voltage held in the storage capacitor Cst. The light emitting diode LD may emit light having brightness corresponding to the amount of driving current.

[0102] Figure 5 are diagrams for explaining embodiments of a display substrate, a flexible circuit board, and a circuit board according to the present invention.

[0103] Reference Figure 5 , the display device 10 in the embodiment of the present invention may include a display substrate DSUB, at least one flexible circuit board FPCB and a circuit board PCB.

[0104] The pixels of the pixel unit 15 and the emission driver 14 may be arranged on the display substrate DSUB. Figure 5 An example is shown in which the emission driver 14 is arranged on a first side (e.g., right side) of the pixel unit 15. In another embodiment, the emission driver 14 may be arranged on a second side (e.g., left side) opposite to the first side of the pixel unit 15, or may be arranged on both sides of the pixel unit 15. The display substrate DSUB may be rigid or flexible.

[0105] The common resistor CREG can be arranged on a circuit board PCB. As described above, the common resistor CREG can be a resistor having a high resistance value and occupying a large area. When the common resistor CREG is arranged (e.g., mounted) on the display substrate DSUB, the dead zone is greatly increased. Therefore, it is preferable to arrange (e.g., mount) the common resistor CREG on the circuit board PCB. The circuit board PCB can be rigid or flexible.

[0106] The flexible circuit board (FPCB) can electrically connect the display substrate (DSUB) and the circuit board (PCB). In an embodiment, for example, the pads of the display substrate (DSUB) can contact the pads of the flexible circuit board (FPCB). In an embodiment, the pads of the circuit board (PCB) can contact other pads of the flexible circuit board (FPCB). In an embodiment, for example, the flexible circuit board (FPCB) can be configured in the form of a chip-on-film (COF) substrate.

[0107] Although not in Figure 5 , the scan driver 13 may be disposed on the display substrate DSUB, and the data driver 12 and the timing controller 11 may be disposed on the flexible circuit board FPCB or the circuit board PCB. A power supply unit (not shown) that supplies power to the first power line VGHL and the second power line VGLL may be disposed on the flexible circuit board FPCB or the circuit board PCB.

[0108] Since the flexible circuit board FPCB can be folded, the circuit board PCB can be arranged on the rear surface of the display substrate DSUB (ie, the surface opposite to the front surface where the pixel units 15 are arranged). Accordingly, the area occupied by the common resistor CREG may not be included in the dead zone.

[0109] Figure 6 is a timing chart for explaining an embodiment of a method of driving a display device according to the present invention.

[0110] Reference Figure 6 , a plurality of frame periods FP1, FP2, and FP3 are shown as examples. In each of the frame periods FP1, FP2, and FP3, data corresponding to one image frame may be written into the pixel unit 15.

[0111] In the illustrated embodiment, it is assumed that the first frame period FP1 is a frame period immediately after power is turned on to the display device 10. The second frame period FP2 may be a frame period after the first frame period FP1.

[0112] The scan driver 13 may sequentially apply a scan signal of an on level to the scan lines SL0 , SL1 , SL2 , . . . , and SLi , . . . in each frame period.

[0113] The emission driver 14 may maintain an OFF-level emission signal on the emission lines EL1, EL2, ..., and ELi, ... during the first frame period FP1. In this case, the second power line VGLL may be maintained at an OFF-level voltage during the first frame period FP1. In an embodiment, for example, the OFF-level voltage may be the same as or similar to the first power supply voltage VGH of the first power line VGHL. During the first frame period FP1, since both the first power line VGHL and the second power line VGLL are maintained at an OFF-level voltage, the stages ST1, ST2, ..., and STi, ... of the emission driver 14 may maintain an OFF-level emission signal regardless of the operation of the transistors.

[0114] Immediately after the display device 10 is powered on, the amount of charge in each node of the display device 10 may be in an uncertain state. Accordingly, by preventing light emission from the pixel unit 15 during at least the first frame period FP1 immediately after the display device 10 is powered on, flickering can be prevented. In the illustrated embodiment, light emission from the pixel unit 15 is prevented only during the first frame period FP1. However, in another embodiment, light emission from the pixel unit 15 may be prevented during two or more frame periods.

[0115] When the second frame period FP2 starts, the voltage of the second power line VGLL may be changed to the second power voltage VGL, and the emission signals of the emission lines EL1, EL2, ..., and ELi, ... may be initialized to the second power voltage VGL. The second power line VGLL may be maintained at a voltage at a turn-on level (e.g., the second power voltage VGL) during the second frame period FP2.

[0116] The emission driver 14 may sequentially supply an emission signal of an off level to the emission lines EL1, EL2, . . . , and ELi, . . . during the second frame period FP2 (refer to Figure 3 and Figure 4 description).

[0117] Since the operation of the emission driver 14 in the third frame period FP3 is the same as that in the second frame period FP2 , repeated description will be omitted.

[0118] exist Figures 1 to 6 In an embodiment, the transistors of the emission driver 14 may be P-type transistors, and each of the pixels of the pixel unit 15 may include a P-type transistor. Accordingly, during the display periods FP2 and FP3 of the pixels, the first power supply voltage VGH of the first power supply line VGHL may be greater than the second power supply voltage VGL of the second power supply line VGLL.

[0119] Figure 7 is a circuit diagram for explaining another embodiment of a pixel according to the present invention.

[0120] Reference Figure 7 , in another embodiment of the present invention, the pixel PXija may include transistors T1a, T2a and T3a, a storage capacitor Csta and a light emitting diode LDa.

[0121] The transistor T1a may include a gate electrode connected to the second electrode of the storage capacitor Csta, a first electrode connected to the second electrode of the transistor T3a, and a second electrode connected to the anode of the light emitting diode LDa. The transistor T1a may also be referred to as a driving transistor.

[0122] The transistor T2a may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the j-th data line DLj, and a second electrode connected to the second electrode of the storage capacitor Csta. The transistor T2a may also be referred to as a scan transistor. The first electrode of the transistor T2a may be the data input terminal DIT of the pixel PXija. Furthermore, the gate electrode of the transistor T2a may be the scan input terminal SIT of the pixel PXija.

[0123] The transistor T3a may include a gate electrode connected to the i-th emission line ELi, a first electrode connected to the first display power line ELVDDL, and a second electrode connected to the first electrode of the transistor T1a. The transistor T3a may also be referred to as an emission transistor.

[0124] A first electrode of the storage capacitor Csta may be connected to the first display power line ELVDDL, and a second electrode of the storage capacitor Csta may be connected to the gate electrode of the transistor T1 a .

[0125] The light emitting diode LDa may include an anode connected to the second electrode of the transistor T1a and a cathode connected to the second display power line ELVSSL. During the emission period of the light emitting diode LDa, the first display power voltage applied to the first display power line ELVDDL may be greater than the second display power voltage applied to the second display power line ELVSSL.

[0126] exist Figure 2 In FIG, the (i-1)th scanning line SL(i-1), the i-th scanning line SLi and the i-th emission line ELi are connected to the same pixel PXij. In contrast, in Figure 7 , the pixel PXija connected to the i-th scan line SLi and the i-th emission line ELi is not connected to the (i-1)-th scan line SL(i-1).

[0127] Figure 8 is a circuit diagram for explaining another embodiment of a transmission driver according to the present invention.

[0128] Reference Figure 8, the emission driver 14a may include a plurality of stages ST1a, ST2a, . . . , and STia, . . .

[0129] In an embodiment, for example, the first stage ST1 a may include a first transistor A1 and a second transistor A2 .

[0130] The first transistor A1 may include a first electrode connected to the first power line VGHL, a second electrode connected to the first emission line EL1, and a gate electrode connected to the first scan line SL1.

[0131] The second transistor A2 may include a first electrode connected to the first node NM1 and a second electrode connected to the first emission line EL1. The gate electrode of the second transistor A2 may be connected to the first electrode of the second transistor A2. That is, the second transistor A2 may be connected in the form of a diode. In an embodiment, the second transistor A2 may be replaced by a diode.

[0132] In an embodiment, for example, the second stage ST2 a may include a third transistor A3 and a fourth transistor A4 .

[0133] The third transistor A3 may include a first electrode connected to the first power line VGHL, a second electrode connected to the second emission line EL2, and a gate electrode connected to the second scan line SL2.

[0134] The fourth transistor A4 may include a first electrode connected to the first node NM1 and a second electrode connected to the second emission line EL2. The gate electrode of the fourth transistor A4 may be connected to the first electrode of the fourth transistor A4. That is, the fourth transistor A4 may be connected in the form of a diode. In an embodiment, the fourth transistor A4 may be replaced by a diode.

[0135] In an embodiment, for example, the i-th stage STia may include a seventh transistor A7 and an eighth transistor A8.

[0136] The seventh transistor A7 may include a first electrode connected to the first power line VGHL, a second electrode connected to the i-th emission line ELi, and a gate electrode connected to the i-th scan line SLi.

[0137] The eighth transistor A8 may include a first electrode connected to the first node NM1 and a second electrode connected to the i-th emission line ELi. The gate electrode of the eighth transistor A8 may be connected to the first electrode of the eighth transistor A8. That is, the eighth transistor A8 may be connected in the form of a diode. In an embodiment, the eighth transistor A8 may be replaced by a diode.

[0138] The display device 10 may include a common resistor CREG having a first electrode connected to the first node NM1 and a second electrode connected to the second power line VGLL. The stages ST1a, ST2a, ..., and STia, ... may be commonly connected to the common resistor CREG through the first node NM1.

[0139] In the illustrated embodiment, since each of the stages ST1a, ST2a, ..., and STia, ... includes two transistors and does not require a separate clock signal, its configuration can be simplified. Therefore, the dead zone can be reduced.

[0140] In addition to not receiving the previous scanning signal (for example, the (i-1)th scanning signal), Figure 7 Pixel PXija and Figure 8 The transmit driver 14a can be connected with Figure 4 In the embodiment, Figure 4 The driving method in the period ta3 to ta4 can be applied to Figure 7 Pixel PXija and Figure 8 Therefore, for example, repeated description is omitted.

[0141] Figure 9 is a circuit diagram for explaining another embodiment of a pixel according to the present invention.

[0142] Reference Figure 9 , the pixel PXijb may include transistors T1b, T2b, and T3b, a storage capacitor Cstb, and a light emitting diode LDb.

[0143] The transistor T1b may include a gate electrode connected to a first electrode of the storage capacitor Cstb, a first electrode connected to a second electrode of the transistor T3b, and a second electrode connected to the second electrode of the storage capacitor Cstb. The transistor T1b may also be referred to as a driving transistor.

[0144] Transistor T2b may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the j-th data line DLj, and a second electrode connected to the gate electrode of transistor T1b. Transistor T2b may also be referred to as a scan transistor. The first electrode of transistor T2b may be the data input terminal DIT of pixel PXijb. Furthermore, the gate electrode of transistor T2b may be the scan input terminal SIT of pixel PXijb.

[0145] The transistor T3b may include a gate electrode connected to the i-th emission line ELi, a first electrode connected to the first display power line ELVDDL, and a second electrode connected to the first electrode of the transistor T1b. The transistor T3b may also be referred to as an emission transistor.

[0146] A first electrode of the storage capacitor Cstb may be connected to the gate electrode of the transistor T1b, and a second electrode of the storage capacitor Cstb may be connected to the second electrode of the transistor T1b.

[0147] The light emitting diode LDb may include an anode connected to the second electrode of the transistor T1b and a cathode connected to the second display power line ELVSSL. During the emission period of the light emitting diode LDb, the first display power voltage applied to the first display power line ELVDDL may be greater than the second display power voltage applied to the second display power line ELVSSL.

[0148] Figure 10 is a circuit diagram for explaining another embodiment of a transmission driver according to the present invention.

[0149] Reference Figure 10 , the emission driver 14b may include a plurality of stages ST1b, ST2b, . . . , and STib, . . .

[0150] In an embodiment, for example, the first stage ST1b may include a first transistor B1 and a second transistor B2.

[0151] The first transistor B1 may include a first electrode connected to the first power line VGLL, a second electrode connected to the first emission line EL1, and a gate electrode connected to the first scan line SL1.

[0152] The second transistor B2 may include a first electrode connected to the first node NM1' and a second electrode connected to the first emission line EL1. The gate electrode of the second transistor B2 may be connected to the first electrode of the second transistor B2. That is, the second transistor B2 may be connected in the form of a diode. In an embodiment, the second transistor B2 may be replaced by a diode.

[0153] In an embodiment, for example, the second stage ST2 b may include a third transistor B3 and a fourth transistor B4 .

[0154] The third transistor B3 may include a first electrode connected to the first power line VGLL, a second electrode connected to the second emission line EL2, and a gate electrode connected to the second scan line SL2.

[0155] The fourth transistor B4 may include a first electrode connected to the first node NM1' and a second electrode connected to the second emission line EL2. The gate electrode of the fourth transistor B4 may be connected to the first electrode of the fourth transistor B4. That is, the fourth transistor B4 may be connected in the form of a diode. In an embodiment, the fourth transistor B4 may be replaced by a diode.

[0156] In an embodiment, for example, the i-th stage STib may include a seventh transistor B7 and an eighth transistor B8.

[0157] The seventh transistor B7 may include a first electrode connected to the first power line VGLL, a second electrode connected to the i-th emission line ELi, and a gate electrode connected to the i-th scan line SLi.

[0158] The eighth transistor B8 may include a first electrode connected to the first node NM1' and a second electrode connected to the i-th emission line ELi. The gate electrode of the eighth transistor B8 may be connected to the first electrode of the eighth transistor B8. That is, the eighth transistor B8 may be connected in the form of a diode. In an embodiment, the eighth transistor B8 may be replaced by a diode.

[0159] The display device 10 may include a common resistor CREG' having a first electrode connected to the first node NM1' and a second electrode connected to the second power line VGHL. The stages ST1b, ST2b, ..., and STib, ... may be commonly connected to the common resistor CREG' through the first node NM1'.

[0160] In the illustrated embodiment, since each of the stages ST1b, ST2b, ..., and STib, ... includes two transistors and does not require a separate clock signal, its configuration can be simplified. Therefore, the dead zone can be reduced.

[0161] In addition to the pixel PXijb and the emission driver 14b including N-type transistors, Figure 9 The pixel PXijb and Figure 10 The transmit driver 14b is connected to Figure 7 Pixel PXija and Figure 8 The emission driver 14a is substantially the same as that of the pixel PXijb. Accordingly, the pixel PXijb and the emission driver 14b can be driven in the same manner as the pixel PXija and the emission driver 14a, except that the on-level and the off-level are opposite to each other. Therefore, a detailed description of the driving method is omitted.

[0162] exist Figure 9 and Figure 10 In an embodiment, the transistors of the emission driver 14b are N-type transistors, and each pixel of the pixel unit 15 includes an N-type transistor. Accordingly, during a display period of the pixel, the first power supply voltage VGL of the first power supply line VGLL may be lower than the second power supply voltage VGH of the second power supply line VGHL.

[0163] The display device according to the present invention can reduce the dead zone by simplifying the configuration of the emission driver.

[0164] In addition, the display device according to the present invention can prevent the flicker phenomenon during power-on.

[0165] The accompanying drawings and the detailed description of the present invention referred to above are merely illustrative of the present invention. It should be understood that the present invention is disclosed for illustrative purposes only and is not intended to limit the meaning or scope of the present invention. Therefore, it will be understood by those skilled in the art that various modifications and equivalent embodiments are possible.

Claims

1. A display device comprising: a plurality of pixels, each of the plurality of pixels being connected to at least one of the plurality of scan lines and at least one of the plurality of emission lines; a scan driver that provides a plurality of scan signals to the plurality of scan lines; as well as a transmit driver comprising a plurality of stages connected to the plurality of transmit lines, each of the plurality of stages providing a transmit signal to a corresponding transmit line among the plurality of transmit lines, a first stage among the plurality of stages comprising: A first transistor, the first transistor comprising: a first electrode connected to a first power line; a second electrode connected to a first emission line among the plurality of emission lines; and a gate electrode connected to a first scan line among the plurality of scan lines; and A second transistor, the second transistor comprising: a first electrode connected to a first node, wherein the first node is connected to a second power line; and a second electrode connected to the first emission line, The gate electrode of the second transistor is connected to the first electrode of the second transistor.

2. The display device according to claim 1, further comprising: A common resistor includes a first electrode connected to the first node and a second electrode connected to the second power line.

3. The display device according to claim 2, further comprising: a display substrate on which the plurality of pixels and the emission driver are arranged; as well as A circuit board is provided on which the common resistor is arranged.

4. The display device according to claim 2, wherein: The second level among the plurality of levels comprises: a third transistor including a first electrode connected to the first power line, a second electrode connected to a second emission line among the plurality of emission lines, and a gate electrode connected to a second scan line among the plurality of scan lines; and a fourth transistor including a first electrode connected to the first node and a second electrode connected to the second emission line, and The gate electrode of the fourth transistor is connected to the first electrode of the fourth transistor.

5. The display device according to claim 4, wherein The first stage further includes a fifth transistor including a first electrode connected to the first power line and a second electrode connected to the first emission line.

6. The display device according to claim 5, wherein: The second stage further includes a sixth transistor including a first electrode connected to the first power line, a second electrode connected to the second emission line, and a gate electrode connected to the first scan line.

7. The display device according to claim 4, wherein: The first transistor to the fourth transistor are P-type transistors, wherein the plurality of pixels include the P-type transistors, and During a display period of the plurality of pixels, a voltage of the first power line is greater than a voltage of the second power line.

8. The display device according to claim 4, wherein: The first transistor to the fourth transistor are N-type transistors, wherein the plurality of pixels include the N-type transistors, and During a display period of the plurality of pixels, a voltage of the first power line is lower than a voltage of the second power line.

9. The display device according to claim 6, wherein: The first scan line, the second scan line, and the second emission line are connected to the same pixel among the plurality of pixels.

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