Semiconductor package structure and method of forming the same

Abstract

The present application relates to a semiconductor package structure and a method of forming the same. The semiconductor package structure includes a first die and a second die disposed opposite the first die, and the first die and the second die are connected by signal I / O pads. The second die further includes external I / O pads for external connection, and a dummy pad is disposed between the signal I / O pads and the external I / O pads.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and more particularly, to a semiconductor package structure and a forming method thereof. BACKGROUND

[0002] In the current package using hybrid bonding interconnection (HBI), there are small I / O (input / output) with small size for signal transmission, and there are also large I / O with large size for external connection (such as connecting power supply and ground). As shown in FIG. 1, the small I / O 12 between two dies 10, 20 is located in the region of the HBI bonding interface, and the large I / O 22 is located outside the region of the HBI bonding interface 30. When bonding two dies 10, 20, the large I / O 22 and the small I / O 12 will be subjected to a chemical mechanical polishing (CMP) process. Based on the different sizes of the large I / O 22 and the small I / O 12, after the CMP process, the small I / O pitch in the region of the small I / O 12 will cause a relatively serious erosion problem, so that the top surface height of the small I / O 12 is low, and a problem of uneven topography of the large I / O 22 and the small I / O 12 is caused. Therefore, when performing the bonding process, the uneven topography of the lower die 20 can cause poor bonding. Figure 1 SUMMARY

[0003] In view of the poor bonding problem caused by the uneven topography in the related art, the present application provides a semiconductor package structure and a forming method thereof.

[0004] According to an aspect of an embodiment of the present application, a semiconductor package structure is provided, comprising: a first die; a second die, which is arranged opposite to the first die, and the first die and the second die are connected through signal I / O pads; wherein the second die further comprises external I / O pads for external connection, and a dummy pad is arranged between the signal I / O pads and the external I / O pads.

[0005] In some embodiments, the dummy pad is located outside the projection area of the first die on the second die.

[0006] In some embodiments, the pitch between the dummy pads is the same as the pitch between the signal I / O pads.

[0007] In some embodiments, the top surface of the dummy pad is lower than the top surface of the external I / O pad.

[0008] ​In some embodiments, the dummy pads are located within a projection area of the first die on the second die.

[0009] In some embodiments, a dielectric layer covering the signal I / O pads is provided at the first die, wherein a gap is present between the top surface of the dummy pads and the dielectric layer.

[0010] In some embodiments, a pitch between the dummy pads is smaller than a pitch between the signal I / O pads.

[0011] In some embodiments, in a cross-section perpendicular to a stacking direction of the first die and the second die, an area of the dummy pads is smaller than an area of the signal I / O pads.

[0012] In some embodiments, a distance between the signal I / O pads is larger than a distance between the signal I / O pads and the dummy pads.

[0013] In some embodiments, a top surface of the dummy pads is lower than a top surface of the signal I / O pads.

[0014] In some embodiments, the dummy pads are ring-shaped structures surrounding the signal I / O pads.

[0015] In some embodiments, an inner portion of the ring-shaped structure dummy pads is located within a projection area of the first die on the second die.

[0016] In some embodiments, both the first die and the second die are in contact with the ring-shaped structure dummy pads.

[0017] In some embodiments, the dummy pads comprise a metal body and a barrier layer outside the metal body, wherein the barrier layer is exposed at an edge of the first die.

[0018] According to another aspect of the embodiments of the present application, a method for forming a semiconductor package structure is provided, comprising: providing a first die having first signal I / O pads and a second die having second signal I / O pads, wherein the second die further comprises external I / O pads for external connection, and a dummy pad is provided between the second signal I / O pads and the external I / O pads; directly bonding the first signal I / O pads to the second signal I / O pads to bond the first die and the second die.

[0019] In some embodiments, before directly bonding the first signal I / O pads to the second signal I / O pads, further comprising: performing a grinding process on the second signal I / O pads, the external I / O pads and the dummy pad at the second die.

[0020] In some embodiments, after the grinding process, a top surface of the dummy pad is lower than a top surface of the external I / O pads.

[0021] In some embodiments, the top surface of the dummy pad is lower than the top surface of the second signal I / O pad.

[0022] In some embodiments, directly bonding the first signal I / O pad to the second signal I / O pad includes forming a protective layer through a chemical plating process.

[0023] In some embodiments, directly bonding the first signal I / O pad to the second signal I / O pad includes forming a protective layer through a photopolymerization process. Attached Figure Description

[0024] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0025] Figure 1 This is a schematic diagram of poor die bonding in existing semiconductor packaging structures.

[0026] Figure 2A This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.

[0027] Figure 2B It includes Figure 2A A magnified view of a portion of the pseudo pad area.

[0028] Figure 3 A top view schematic diagram of a semiconductor package structure according to another embodiment of the present invention is shown.

[0029] Figure 4A This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.

[0030] Figure 4B yes Figure 4A A magnified view of a portion of region A41 in the diagram.

[0031] Figure 4C yes Figure 4A A magnified view of region A42 in the diagram.

[0032] Figure 5A and Figure 5B These are top views of semiconductor packaging structures according to other embodiments of the present invention.

[0033] Figure 6A This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.

[0034] Figure 6B yes Figure 6A A magnified view of a portion of region A61 in the diagram.

[0035] Figure 6C is Figure 6A a top view schematic diagram of a semiconductor package structure.

[0036] Figure 7A is a schematic diagram of a semiconductor package structure according to an embodiment of the present application.

[0037] Figure 7B is Figure 7A a partial enlarged schematic diagram of the area A71 in

[0038] Figures 8A to 8D schematic diagrams showing various stages of a method of forming a semiconductor package structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component can not be in direct contact. Further, the present application can make repeated reference to a number and / or letter in various examples. Such repetition is for the sake of simplicity and clarity and does not itself imply a relationship between the various embodiments and / or configurations discussed.

[0040] Figure 2A is a schematic diagram of a semiconductor package structure according to an embodiment of the present application. Figure 2B is a schematic diagram of a semiconductor package structure according to an embodiment of the present application. Figure 2A is a partial enlarged schematic diagram of the area including the dummy pads in Figure 2A and Figure 2B As shown in FIG. 1 1 and FIG. 12, the first die 1 10 and the second die 210 are oppositely arranged. The first die 1 10 is above the second die 210. The first die 1 10 and the second die 210 are connected by signal I / O pads 130 for signal transmission. The signal I / O pads 130 include first signal I / O pads 131 from the first die 1 10 and second signal I / O pads 132 from the second die 210. The sidewalls of the first signal I / O pads 131 and the second signal I / O pads 132 are oppositely aligned, and can be collectively referred to as the signal I / O pads 130. The first signal I / O pads 131 penetrate the first dielectric layer 120, and the second signal I / O pads 132 penetrate the second dielectric layer 220. The first signal I / O pads 131 and the second signal I / O pads 132 are directly bonded, and a bonding interface 155 is formed at the position where the first signal I / O pads 131 and the second signal I / O pads 132 are bonded to each other.

[0041] The second die 210 further includes external I / O pads 240 for external connection. The external I / O pads 240 penetrate the second dielectric layer 220. The size of the external I / O pads 240 for external connection is larger than the size of the first signal I / O pads 131 and the second signal I / O pads 132 for signal transmission. That is, the width of the external I / O pads 240 in the lateral direction is larger than the width of the first signal I / O pads 131 and the second signal I / O pads 132. A dummy pad 250 is disposed between the second signal I / O pads 132 and the external I / O pads 240. In some embodiments, the size of the dummy pad 250 can be the same as the size of the second signal I / O pads 132. The pitch P21 between two adjacent dummy pads 250 can be the same as the pitch between two adjacent second signal I / O pads 132. The distance D21 between two adjacent dummy pads 250 can be the same as the distance D22 between the dummy pad 250 and the second signal I / O pads 132. Due to the dummy pad 250, after the CMP process, the top surface of the second signal I / O pads 132 is flush with the top surface of the dummy pad 250, and the top surface of the external I / O pads 240 is higher than the top surface of the dummy pad 250, i.e., higher than the extended joint interface 155 of the second signal I / O pads 132 and the first signal I / O pads 131. The area corresponding to the dummy pad 250 acts as an extended area of the joint interface 155, equivalent to an extension of the joint interface 155 of the second signal I / O pads 132 and the first signal I / O pads 131. The flat joint interface 155 is enlarged so that the joint interface 155 opposite the sidewall of the first die 110 is flat. The uneven surface between the external I / O pads 240 and the dummy pad 250 is not opposite the sidewall of the first die 110. Thus, the problem of poor bonding between the first die 110 and the second die 210 can be avoided.

[0042] The size of the first die 110 is smaller than the size of the second die 210. The first die 110 has a projection area SP on the second die 210. The projection area SP of the first die 110 is outside the area of the second die 210 corresponding to the joint interface 155. Figure 2A In the illustrated embodiment, the dummy pads 250 are located outside the projection area SP of the first die 110 on the second die 210. That is, the dummy pads 250 are located in the area outside the sidewall of the first die 110. Two groups of dummy pads 250 are disposed in the lateral direction outside the projection area SP of the first die 110. In other embodiments, the number of dummy pads 250 can be configured in other appropriate manners.

[0043] Figure 3 A top view of a semiconductor package structure according to another embodiment of the present application is shown. As shown in FIG. 6, the semiconductor package structure includes a first die 110 and a second die 210. The first die 110 and the second die 210 are bonded together. The first die 110 includes a first dielectric layer 120 and a first signal I / O pad 131. The second die 210 includes a second dielectric layer 220 and a second signal I / O pad 132. The first signal I / O pad 131 and the second signal I / O pad 132 are bonded together to form a joint interface 155. The joint interface 155 is flat. Figure 3As shown, two sets of dummy pads 250 are provided. Part of the two sets of dummy pads 250 can be located within the projection area SP of the first die 110, and at least the outermost set of dummy pads 250 is located outside the projection area SP of the first die 110 to form an extended bonding interface. Other suitable configurations of the number of dummy pads 250 can be provided. In some other embodiments, at least one set of dummy pads 250 is located outside the projection area SP of the first die 110. The size of the dummy pads 250 can be the same as the size of the second signal I / O pads 132, i.e. in a top view, the diameter of the circular dummy pads 250 is the same as the diameter of the circular second signal I / O pads 132. The pitch P31 between the dummy pads 250 and the second signal I / O pads 132 can be the same as the pitch P32 between two adjacent signal I / O pads 130.

[0044] Figure 4A is a schematic view of a semiconductor package structure according to an embodiment of the present application. Figure 4B is Figure 4A is a partial enlarged view of the area A41 in Figure 4A and Figure 4B As shown, dummy pads 250 are provided between the outer I / O pads 240 and the second signal I / O pads 132. Part of the dummy pads 250 is located within the projection area SP of the first die 110 on the second die 210. The width of the dummy pads 250 can be the same as the width of the outer I / O pads 240. The distance D41 between the outermost signal I / O pads 130 and the sidewall of the first die 110 is greater than the distance D42 between the outermost signal I / O pads 130 and the dummy pads 250. In some embodiments, the distance D41 between the outermost signal I / O pads 130 and the sidewall of the first die 110 can be equal to the distance D43 between the signal I / O pads 130. With such a configuration, it is equivalent to reducing the area of the second dielectric layer 220 under the signal I / O pads 130 of the first die 110, and the density of the second signal I / O pads 132 in the second dielectric layer 220 under the first die 110 is increased. Therefore, after the CMP process, the top surface of the second signal I / O pads 132 will be higher, and higher than the top surface of the dummy pads 250 and the outer I / O pads 240. That is, the bonding interface 155 between the first signal I / O pads 131 and the second signal I / O pads 132 is higher than the top surface of the outer I / O pads 240. Thus, it can be ensured that the first signal I / O pads 131 and the second signal I / O pads 132 can be well bonded.

[0045] Figure 4C is Figure 4A is a partial enlarged view of the area A42 in Figure 4A and Figure 4CAs shown, dummy pads 250 are provided between the external I / O pads 240 and the second signal I / O pads 132. In this embodiment, the dummy pads 250 can include first dummy pads 251 in the first dielectric layer 120 and second dummy pads 252 in the second dielectric layer 220. In this embodiment, the distance D44 (or pitch) between the signal I / O pads 130 is greater than the distance D45 (or pitch) between the signal I / O pads 130 and the first dummy pads 251, and the distance D44 (or pitch) between the signal I / O pads 130 is greater than the distance D46 (or pitch) between the signal I / O pads 130 and the second dummy pads 252. In some embodiments, the distance D45 or pitch between the signal I / O pads 130 and the first dummy pads 251 can be equal to the distance D46 or pitch between the signal I / O pads 130 and the second dummy pads 252. In other embodiments, the distance D45 or pitch between the signal I / O pads 130 and the first dummy pads 251 can not be equal to the distance D46 or pitch between the signal I / O pads 130 and the second dummy pads 252. By providing the first dummy pads 251 and the second dummy pads 252 with a pitch smaller than the pitch of the signal I / O pads 130, the area of the second dielectric layer 220 where the signal I / O pads 130 are located is effectively reduced, which can result in a higher bonding interface 155 between the signal I / O pads 130 after the CMP process, and higher than the top surface of the second dummy pads 252 and the external I / O pads 240. The first dummy pads 251 and the second dummy pads 252 are spaced apart and do not contact each other. In such embodiments, the first signal I / O pads 131 and the second signal I / O pads 132 can be bonded well due to the higher bonding interface 155 between the signal I / O pads 130.

[0046] Figure 5A and Figure 5B are top views of semiconductor package structures according to other embodiments of the present application. In Figure 5A In the embodiment shown, a set of dummy pads 250 are provided between the signal I / O pads 130 and the external I / O pads 240. The pitch P51 between the dummy pads 250 and the signal I / O pads 130 is smaller than the pitch P52 between the signal I / O pads 130. In Figure 5B In the embodiment shown, a set of dummy pads 250 are provided between the signal I / O pads 130 and the external I / O pads 240. The pitch P51 between the dummy pads 250 and the signal I / O pads 130 is smaller than the pitch P52 between the signal I / O pads 130. In Figure 4B and Figure 4C similar to the description with reference toFigure 5A and Figure 5B The configuration of the embodiment of

[0047] Figure 6A is a schematic view of a semiconductor package structure according to an embodiment of the present application. Figure 6B is Figure 6A is a partial enlarged view of region A61 in Figure 6C is Figure 6A is a top view of the semiconductor package structure shown in Figure 6A and Figure 6B As shown in Figure 6C and Figure 6C As shown in

[0048] Figure 7A is a schematic view of a semiconductor package structure according to an embodiment of the present application. Figure 7B is Figure 7A is a partial enlarged view of region A71 in Figure 7BAs shown, both the first dummy pad 251 and the second dummy pad 252 include a metal body 258 and a barrier layer 259 padding outside the metal body 258. The barrier layer 259 of the first dummy pad 251 is exposed at the sidewall of the first die 110. In this embodiment, after the CMP process, the surfaces of the first dummy pad 251 and the second dummy pad 252 are recessed, with the sidewall of the first die 110 facing the top surface of the recessed second dummy pad 252, thereby avoiding the problem of poor bonding between the first die 110 and the second die 210.

[0049] Embodiments of the present invention also provide a method for forming a semiconductor package structure. Figures 8A to 8D A schematic diagram of multiple stages of a method for forming a semiconductor package structure according to an embodiment of the present invention is shown.

[0050] like Figure 8A As shown, a first die 110 with a first signal I / O pad 131 and a second die 210 with a second signal I / O pad 132 are provided. The second die 210 further includes an external I / O pad 240 for external connections. A dummy pad 250 is provided between the second signal I / O pad 132 and the external I / O pad 240, for example, as shown in the reference above. Figures 2A to 7B The described pseudo pad is 250.

[0051] Then, a polishing process, such as a CMP process, can be performed on the second signal I / O pad 132, external I / O pad 240, and dummy pad 250 at the second die 210. After the polishing process, the top surface of the dummy pad 250 is lower than the top surface of the external I / O pad 240 (e.g., ...). Figure 2B ), or the top surface of the dummy pad 250 is lower than the top surface of the second signal I / O pad 132 (e.g. Figure 4B , Figure 4C ), or the top surface of the dummy pad 250 is opposite to the side wall of the first die 110 and the top surface of the dummy pad is recessed (e.g. Figure 6B , Figure 7B ).

[0052] like Figure 8B As shown, the first signal I / O pad 131 is directly bonded to the second signal I / O pad 132 to bond the first die 110 and the second die 210. By setting the dummy pad 250, a good bond between the first die 110 and the second die 210 can be ensured.

[0053] In some embodiments, the protective layer can be formed by a chemical plating process or by a photopolymer plating process. The protective layer can be formed on the exposed dummy pads 250 or the external I / O pads 240.

[0054] like Figure 8CAs shown, the bonded first die 110 and second die 210 are mounted to the substrate 810. Then, as shown in FIG. 8C, bond wires 815 are formed to electrically connect the external I / O pads 240 of the second die 210 with the substrate. Figure 8D As shown, bond wires 815 are formed to electrically connect the external I / O pads 240 of the second die 210 with the substrate.

[0055] The foregoing is a summary and / or embodiment(ies) of the present disclosure. Embodiments of the present disclosure can be better understood and / or implemented by reference to the accompanying drawings. The foregoing summary and / or embodiment(ies) of the present disclosure are not intended to be exhaustive or to limit the scope of the present disclosure to the embodiments described. Many modifications and variations to the present disclosure are possible in light of this disclosure. It is intended that the scope of the present disclosure be defined by the claims attached hereto.

Claims

1. A semiconductor packaging structure, characterized in that, include: First die; The second die is disposed opposite to the first die, and the first die and the second die are connected by signal I / O pads; The second die further includes external I / O pads for external connections, and a dummy pad is provided between the signal I / O pads and the external I / O pads. The size of the external I / O pads is larger than the size of the signal I / O pads. Wherein, at least a portion of the dummy pads are located outside the projection area of ​​the first die on the second die, the top surface of the dummy pads is lower than the top surface of the external I / O pads, and the top surface of the dummy pads is flush with the top surface of the signal I / O pads, wherein the size of the dummy pads is the same as the size of the signal I / O pads, the pitch between the dummy pads is the same as the pitch between the signal I / O pads, and the distance between the dummy pads is the same as the distance between the dummy pads and the signal I / O pads.

2. The semiconductor packaging structure according to claim 1, characterized in that, In the top view, the dummy pads and the signal I / O pads are circular.

3. A semiconductor packaging structure, characterized in that, include: First die; The second die is disposed opposite to the first die, and the first die and the second die are connected by signal I / O pads; The second die further includes external I / O pads for external connections, and a dummy pad is provided between the signal I / O pads and the external I / O pads. The size of the external I / O pads is larger than the size of the signal I / O pads. Wherein, at least a portion of the dummy pad is located outside the projection area of ​​the first die on the second die, and the top surface of the dummy pad is lower than the top surface of the signal I / O pad, wherein the distance between the signal I / O pads is greater than the distance between the signal I / O pad and the dummy pad.

4. The semiconductor packaging structure according to claim 3, characterized in that, Another portion of the dummy pad is located within the projection area of ​​the first die on the second die.

5. The semiconductor packaging structure according to claim 4, characterized in that, The first die has a dielectric layer covering the signal I / O pads, wherein there is a gap between the top surface of the dummy pads and the dielectric layer.

6. The semiconductor packaging structure according to claim 3, characterized in that, The pitch between the dummy pads is smaller than the pitch between the signal I / O pads.

7. The semiconductor packaging structure according to claim 3, characterized in that, The top surface of the dummy pad is recessed.

8. The semiconductor packaging structure according to claim 3, characterized in that, The dummy pad is a ring structure surrounding the signal I / O pad.

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