A method for inhibiting electrostatic damage to an integrated circuit

Abstract

The embodiment of the present application discloses a method for inhibiting integrated circuit from static damage, comprising: providing a first chip, and arranging an integrated circuit on the first chip; providing a second chip, and arranging an electrostatic protection circuit on the second chip, the electrostatic protection circuit comprising: a first output port, a second output port and a first resistor; wherein, when an electrostatic pulse flows through the first resistor, the resistance of the first resistor increases; connecting the first output port with an output port of the integrated circuit, so that the electrostatic protection circuit can inhibit the integrated circuit from static damage. Moreover, the electrostatic protection circuit is arranged on the second chip, and the integrated circuit is arranged on the first chip, so that the integrated circuit and the electrostatic protection circuit are arranged on different chips, avoiding the problem that the integrated circuit cannot be designed for electrostatic protection due to the limitation of the base material of the chip on which the integrated circuit is arranged, and realizing the electrostatic protection of the integrated circuit of new material.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for suppressing electrostatic damage to integrated circuits. Background Technology

[0002] With the development of integrated circuit technology, new material integrated circuits have become a research focus for researchers. The substrate materials of these new material integrated circuits are different from those of silicon-based integrated circuits, which makes them have superior performance compared to silicon-based integrated circuits, making them a rising star in improving computer speed and reducing the power consumption of electronic devices.

[0003] However, these novel material integrated circuits are typically highly sensitive to electrostatic pulses and prone to electrostatic damage. Furthermore, limitations in the properties of their substrate materials prevent the implementation of existing electrostatic protection designs for integrated circuits, hindering effective electrostatic protection and making these circuits susceptible to malfunction due to electrostatic damage in practical applications. Therefore, providing an electrostatic protection method that can suppress electrostatic damage to these novel material integrated circuits has become a key research focus for those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a method for suppressing electrostatic damage to integrated circuits. This electrostatic protection method can suppress electrostatic damage to electrostatic-sensitive novel material integrated circuits, thus contributing to the development of novel material integrated circuits.

[0005] To address the above problems, the embodiments of this application provide the following technical solutions:

[0006] A method for suppressing electrostatic damage to integrated circuits, comprising:

[0007] A first chip is provided, and an integrated circuit is disposed on the first chip, wherein the integrated circuit includes an output port;

[0008] A second chip is provided, on which an electrostatic discharge (ESD) protection circuit is disposed. The ESD protection circuit includes an output port and a first resistor. The output port includes a first output port and a second output port. The second output port is connected to the first output port through the first resistor. The first end of the first resistor is connected to the first output port, and the second end is connected to the second output port. When an ESD pulse flows in from the second output port and passes through the first resistor, the resistance of the first resistor increases.

[0009] Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit provides electrostatic protection for the integrated circuit.

[0010] Optionally, the first chip is a carbon-based chip, and the second chip is a silicon-based chip.

[0011] Optionally, the electrostatic discharge protection circuit further includes: a first diode, a capacitor, a first N-type field-effect transistor, and a ground terminal, wherein the cathode of the first diode is connected to a first terminal of the capacitor through the drain of the first N-type field-effect transistor, the gate of the first N-type field-effect transistor is connected to a second terminal of the capacitor, the source of the first N-type field-effect transistor is connected to the ground terminal, and the ground terminal is grounded; the method further includes:

[0012] Connect the positive terminal of the first diode to the second terminal of the first resistor and the second output port respectively, so that the second output port is connected to the second terminal of the first resistor through the positive terminal of the first diode;

[0013] The electrostatic discharge protection circuit further includes a second diode, and the method further includes:

[0014] Connect the negative terminal of the second diode to the positive terminal of the first diode, and connect the positive terminal to the ground terminal.

[0015] Optionally, the integrated circuit further includes an input port, and the electrostatic discharge protection circuit further includes: an input output port, a third diode, and a fourth diode, wherein the input output port includes a first input output port and a second input output port, the second input output port is connected to the first input output port through the positive terminal of the third diode, the negative terminal of the third diode is connected to the first terminal of the capacitor, the negative terminal of the fourth diode is connected to the positive terminal of the third diode, and the positive terminal is connected to the ground output port;

[0016] The electrostatic discharge protection circuit further includes: a second resistor and a second N-type field-effect transistor, wherein the first end of the second resistor is connected to the first input output port, the second end is connected to the positive terminal of the third diode, the drain of the second N-type field-effect transistor is connected to the first end of the second resistor, and the source is connected to the gate of the second N-type field-effect transistor and the ground output port respectively.

[0017] The first input output port is connected to the input port of the integrated circuit so that the electrostatic discharge protection circuit provides electrostatic protection for the integrated circuit.

[0018] Optionally, the integrated circuit further includes a power supply port, and the electrostatic discharge protection circuit further includes: a power output port and a fifth diode, wherein the power output port includes a first power output port and a second power output port, the first power output port is connected to the drain of the first N-type field-effect transistor, the second power output port is connected to the cathode of the third diode, the cathode of the fifth diode is connected to the first power output port, and the anode is connected to the ground output port; the method further includes:

[0019] The first power output port is connected to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0020] Optionally, the first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode.

[0021] Optionally, the electrostatic discharge protection circuit further includes: a third resistor; the method further includes:

[0022] The first end of the third resistor is connected to the gate of the first N-type field-effect transistor, and the second end is connected to the ground terminal.

[0023] Optionally, the integrated circuit further includes a ground port, the ground output port including a first ground output port and a second ground output port; the method further includes:

[0024] Connect the first ground output port to the ground port of the integrated circuit, connect the second ground output port to the first ground output port, and ground the second ground output port.

[0025] Compared with existing technologies, the above technical solution has the following advantages:

[0026] The technical solution provided in this application embodiment is used to protect an integrated circuit from electrostatic discharge (ESD) through an ESD protection circuit, thereby suppressing ESD damage to the integrated circuit. The method includes: providing a first chip and placing an integrated circuit on the first chip, the integrated circuit including an output port; providing a second chip and placing an ESD protection circuit on the second chip, the ESD protection circuit including an output port and a first resistor, the output port including a first output port and a second output port, and when an ESD pulse flows in from the second output port and passes through the first resistor, the resistance value of the first resistor increases; connecting the first output port to the output port of the integrated circuit, thereby connecting the ESD protection circuit to the integrated circuit. When an ESD pulse flows in from the second output port and passes through the first resistor, the resistance value of the first resistor increases, which can suppress the ESD pulse from flowing into the integrated circuit, thus enabling the ESD protection method to protect the integrated circuit from ESD, helping to suppress ESD damage to the integrated circuit and ensuring the reliability of the integrated circuit. Furthermore, the electrostatic discharge (ESD) protection circuit is disposed on the second chip, while the integrated circuit is disposed on the first chip. This means that the integrated circuit and the ESD protection circuit are disposed on different chips, eliminating the need for ESD protection design on the first chip. In other words, ESD protection design is not required on the chip containing the integrated circuit, thus avoiding the problem of being unable to perform ESD protection design on the integrated circuit due to limitations in the substrate material of the chip containing the integrated circuit. This enables ESD protection for ESD-sensitive novel integrated circuits, thereby contributing to the reliability of novel material integrated circuits and promoting their development. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A flowchart illustrating a method for suppressing electrostatic damage to integrated circuits, provided in an embodiment of this application;

[0029] Figure 2 This is a schematic diagram of the circuit structure in a method for suppressing electrostatic damage to integrated circuits provided in an embodiment of this application;

[0030] Figure 3 A schematic diagram of the positive electrostatic pulse IV curve at the input output port and the leakage current curve between the second input output port and the ground port of an electrostatic protection circuit provided in this application embodiment;

[0031] Figure 4 A schematic diagram of the negative electrostatic pulse IV curve of the input / output / power output port of an electrostatic protection circuit provided in this application embodiment, and the leakage current curve between the input / output / power output port and the ground output port.

[0032] Figure 5 A schematic diagram of the positive electrostatic pulse IV curve at the output port and the leakage current curve between the second output port and the ground port of an electrostatic protection circuit provided in this application embodiment.

[0033] Figure 6 This is a schematic diagram of the positive electrostatic pulse (IV) curve at the power supply output port and the leakage current curve between the second power supply output port and the ground output port, provided in an embodiment of this application for an electrostatic protection circuit. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0036] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0037] To overcome the physical limitations of traditional silicon-based integrated circuits, researchers have focused on placing integrated circuits on chips made of novel materials. These novel integrated circuits use different substrate materials than traditional silicon-based integrated circuits. Carbon-based integrated circuits, formed by placing them on carbon-based chips, exhibit superior performance, making them one of the most widely studied new materials for integrated circuits. The core component of carbon-based integrated circuits is the carbon-based transistor, which operates five times faster than a silicon-based transistor of the same size while consuming less than one-fifth the energy. This combination of higher speed and lower energy consumption makes carbon-based integrated circuits a promising candidate for widespread research.

[0038] According to the inventors' research, most of these novel material integrated circuits are typically highly sensitive to electrostatic pulses and are referred to as electrostatic-sensitive novel material integrated circuits. They are prone to electrostatic damage. Furthermore, due to limitations in the characteristics of the substrate material of the chip on which these electrostatic-sensitive novel material integrated circuits are located, it is impossible to directly implement electrostatic protection design on the integrated circuit chip itself. In other words, it is impossible to achieve on-chip electrostatic protection design for integrated circuits. This makes it impossible for existing integrated circuit electrostatic protection designs to protect against electrostatic damage, thus failing to suppress electrostatic damage in such integrated circuits. As a result, in practical applications, these integrated circuits are prone to functional failure due to electrostatic damage, affecting the application and development of novel material integrated circuits.

[0039] For example, carbon-based integrated circuits suffer from problems such as thin carbon film, low conductivity, and poor heat dissipation. As a result, it is impossible to directly complete the electrostatic discharge (ESD) protection design for the carbon-based integrated circuit on the chip itself. In other words, it is impossible to achieve on-chip ESD protection for the integrated circuit, and thus it is impossible to effectively suppress ESD damage to the carbon-based integrated circuit, affecting its application.

[0040] Therefore, in order to support the development of integrated circuits and achieve electrostatic protection for electrostatic-sensitive novel material integrated circuits, providing a method to suppress electrostatic damage to such electrostatic-sensitive novel material integrated circuits has become a research focus for those skilled in the art.

[0041] Based on this, embodiments of this application provide a method for suppressing electrostatic damage to integrated circuits. This method utilizes an electrostatic protection circuit to suppress electrostatic damage to the integrated circuit, such as... Figure 1 As shown, the method includes:

[0042] S1: As Figure 2 As shown, a first chip 100 is provided, and an integrated circuit is disposed on the first chip 100 to form an integrated circuit with a specific function. The integrated circuit includes an output port 02. The integrated circuit is a novel material integrated circuit, but this application does not limit it and it depends on the specific situation.

[0043] S2: Continue as follows Figure 2 As shown, an electrostatic discharge (ESD) protection circuit is laid out on the second chip 200 to complete the fabrication of an ESD protection circuit with protective capabilities. The ESD protection circuit includes an output port and a first resistor 11. The output port includes a first output port 111 and a second output port 112. The second output port 112 is connected to the first output port 112 through the first resistor 11. The first end of the first resistor 11 is connected to the first output port 111, and the second end is connected to the second output port 112. When an ESD pulse flows into the second output port 112 and passes through the first resistor 11, the resistance of the first resistor 11 increases.

[0044] S3: Connect the first output port to the output port of the integrated circuit to suppress the flow of electrostatic pulses into the integrated circuit, so that the electrostatic protection circuit can protect the integrated circuit from electrostatic damage.

[0045] It should be noted that the first output port is connected to the integrated circuit output port by a wire bonding method, and the first output port is connected to the first end of the first resistor by a metal wire connection. Therefore, even if the first output port is connected to the integrated circuit output port and the first output port is also connected to the first end of the first resistor, the integrated circuit output port will not be directly connected to the first end of the first resistor.

[0046] It should also be noted that, in the embodiments of this application, the output port includes two output ports: a first output port and a second output port, and the integrated circuit includes one output port. However, this application does not limit this. In other embodiments of this application, the electrostatic protection circuit may also include one output port or at least three output ports, and the integrated circuit may include at least two output ports, depending on the specific circumstances.

[0047] Specifically, in this embodiment, the integrated circuit is disposed on the first chip, the electrostatic discharge (ESD) protection circuit is disposed on the second chip, and the output port of the integrated circuit is connected to the first output port of the ESD protection circuit. This allows the ESD protection circuit to be connected to the integrated circuit. When an ESD pulse flows in from the second output port and passes through the first resistor, the resistance of the first resistor increases, which can suppress the ESD pulse from flowing into the integrated circuit. This enables the ESD protection method to suppress ESD damage to the integrated circuit and ensure the reliability of the integrated circuit.

[0048] Furthermore, due to the limitations of the substrate material, on-chip electrostatic protection (ESP) designs for known ESD-sensitive novel material integrated circuits are impossible. This prevents existing ESP designs from effectively protecting these circuits from ESD damage, hindering their practical application. However, the ESP protection method provided in this application places the ESP protection circuit on a second chip and the integrated circuit on a first chip. This separates the integrated circuit and the ESP protection circuit from the ESP protection circuit, eliminating the need for ESP design on the first chip. This avoids the problem of ESP protection limitations caused by the substrate material of the integrated circuit chip, enabling ESP protection for ESD-sensitive novel integrated circuits. This, in turn, improves the reliability of novel material integrated circuits and promotes their development.

[0049] Furthermore, the electrostatic discharge (ESD) protection method provided in this application embodiment places the ESD protection circuit on the second chip and the integrated circuit on the first chip, so that the integrated circuit and the ESD protection circuit are placed on different chips. This allows the ESD protection circuit to achieve off-chip ESD protection for the integrated circuit, thereby enabling the ESD protection circuit to also be applied to integrated circuits with high on-chip ESD protection design costs. Providing ESD protection for integrated circuits with high on-chip ESD protection design costs helps to save ESD protection costs for integrated circuits and promotes the development of integrated circuits.

[0050] Meanwhile, in the electrostatic discharge (ESD) protection method provided in this application embodiment, the resistance of the first resistor increases when an ESD pulse flows through it. Compared to ESD protection circuits using ordinary resistors, this avoids the problem of a significant decrease in resistance when a large ESD pulse flows in, thus helping to suppress the flow of ESD pulses into the integrated circuit. Therefore, the ESD protection method provided in this application embodiment helps to suppress ESD damage to the integrated circuit, thereby helping to ensure the reliability of the integrated circuit. Furthermore, in this application embodiment, when an ESD pulse flows in from the second output port, the resistance of the first resistor increases; when no ESD pulse flows in, the resistance of the first resistor remains unchanged and is relatively small. This allows the ESD protection method to achieve safe and effective ESD protection using a smaller resistance value, helping to suppress the flow of ESD pulses into the integrated circuit, and further helping to ensure the reliability of the integrated circuit.

[0051] Based on the above embodiments, in this embodiment, when an electrostatic pulse flows in from the second output port, the second output port is connected to the first output port through the first resistor. Thus, after the electrostatic pulse flows in from the second output port, it will flow through the first resistor. Since the resistance of the first resistor increases when the electrostatic pulse flows through it, the potential difference across the first resistor increases, which can suppress the electrostatic pulse from flowing into the integrated circuit, thereby helping to suppress electrostatic damage to the integrated circuit.

[0052] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the electrostatic discharge protection circuit further includes a first diode 12, a capacitor 14, a first N-type field-effect transistor 15, and a ground terminal output port 20. The cathode of the first diode 12 is connected to the first terminal of the capacitor 14 through the drain of the first N-type field-effect transistor 15. The gate of the first N-type field-effect transistor 15 is connected to the second terminal of the capacitor, and its source is connected to the ground terminal output port, which is grounded. The method further includes:

[0053] S4: Connect the positive terminal of the first diode to the second terminal of the first resistor and the second output terminal respectively, so that the second output terminal is connected to the second terminal of the first resistor through the positive terminal of the first diode, thereby enabling the electrostatic protection circuit to protect the integrated circuit and the electrostatic protection method to suppress electrostatic damage to the integrated circuit.

[0054] The electrostatic discharge protection circuit further includes a second diode 13, and the method further includes:

[0055] S5: Connect the negative terminal of the second diode to the positive terminal of the first diode, and connect the negative terminal to the ground terminal. Since the positive terminal of the first diode is connected to the second and second output terminals of the first resistor respectively, the negative terminal of the second diode is connected to the second and second output terminals of the first resistor respectively, so that the electrostatic protection circuit can protect the integrated circuit, thereby enabling the electrostatic protection method to suppress electrostatic damage to the integrated circuit.

[0056] Specifically, in this embodiment, when an electrostatic pulse flows in from the second output port, according to the forward conduction characteristic of the diode, the positive electrostatic pulse will not flow through the second diode, but will flow through the path formed by the first diode and the first N-type field-effect transistor, and will flow out from the ground port. The second output port is connected to the first output port through the first resistor, so the positive electrostatic pulse, after flowing in from the second output port, will also flow through the path formed by the first resistor and the integrated circuit, and flow into the integrated circuit. The process of the positive electrostatic pulse flowing through the path formed by the first diode and the first N-type field-effect transistor is as follows: the positive electrostatic pulse flows through the first diode, and after flowing through the first diode, it couples with the capacitor, releasing charge to the gate of the first N-type field-effect transistor, raising the gate potential of the first N-type field-effect transistor, causing the first N-type field-effect transistor to conduct, allowing the positive electrostatic pulse to flow through the first N-type field-effect transistor, and then flow out from the ground port, thereby allowing the positive electrostatic pulse to flow through the path formed by the first diode and the first N-type field-effect transistor. The principle of the positive static current passing through the path formed by the first diode and the first N-type field-effect transistor is as follows: after the positive static pulse flows in from the second output port, it flows through the first diode and couples with the capacitor, causing the capacitor to release charge to the gate of the first N-type field-effect transistor, raising the gate potential of the first N-type field-effect transistor, thereby turning on the first N-type field-effect transistor, so that the positive static current passes through the path formed by the first diode and the first N-type field-effect transistor.

[0057] It should be noted that integrated circuits typically include multiple electronic devices such as resistors, capacitors, and field-effect transistors. In this embodiment, the resistance of the integrated circuit is made relatively large, greater than the resistance of the path formed by the first N-type field-effect transistor and the first diode. Since the current intensity flowing into each parallel branch is related to the resistance of each branch, the current intensity flowing into a branch with a large resistance is low, and the current intensity flowing into a branch with a small resistance is high. Therefore, after the positive electrostatic pulse flows in from the second output port, the electrostatic pulse intensity flowing through the path formed by the first N-type field-effect transistor and the first diode is greater than the electrostatic pulse intensity flowing through the path formed by the first resistor and the integrated circuit. This ensures that the intensity of the positive electrostatic pulse flowing through the electrostatic protection circuit after flowing in from the second output port is greater than the intensity flowing into the integrated circuit. This allows most of the intensity of the positive electrostatic pulse to flow out through the electrostatic protection circuit, effectively reducing the intensity of the electrostatic pulse flowing into the integrated circuit. Consequently, the electrostatic protection method can, to a certain extent, suppress electrostatic damage to the integrated circuit, thus helping to ensure the reliability of the integrated circuit.

[0058] When a negative electrostatic discharge (ESD) pulse flows in from the second output port, according to the forward conduction characteristic of the diode, the ESD pulse will not flow through the first diode, but will flow through the second diode and exit from the ground port. The second output port is connected to the first output port through the first resistor. Therefore, after the negative ESD pulse flows in from the second output port, it will also flow through the path formed by the first resistor and the integrated circuit, and then into the integrated circuit. It is known that the resistance of the integrated circuit is relatively large, while the resistance of the diode is relatively small. This makes the resistance of the path formed by the integrated circuit and the first resistor greater than the resistance of the second diode. Consequently, after the negative ESD pulse flows in from the second output port, the ESD pulse intensity flowing through the second diode is greater than the resistance flowing through the path formed by the integrated circuit and the first resistor. In other words, after the negative ESD pulse flows in from the second output port, the ESD pulse intensity flowing through the ESD protection circuit is greater than the intensity flowing into the integrated circuit. This effectively reduces the intensity of the ESD pulse flowing into the integrated circuit, thereby enabling the ESD protection method to suppress ESD damage to the integrated circuit to a certain extent. ESD protection of the integrated circuit helps ensure its reliability.

[0059] In addition, it should be noted that the above embodiments describe the case where electrostatic pulses flow into the integrated circuit from the outside through the second output port. Another scenario is where electrostatic pulses exist inside the integrated circuit. The electrostatic protection circuit can also suppress electrostatic damage to the integrated circuit when electrostatic pulses exist inside the integrated circuit. Specifically, when an electrostatic pulse exists inside the integrated circuit and acts on the output port, if the electrostatic pulse is positive, and the first output port is known to be connected to the integrated circuit's output port, part of the positive electrostatic pulse remains inside the integrated circuit, and part flows into the electrostatic protection circuit through the first output port. Since the integrated circuit's output port is connected to the first output port, the first output port is connected to the first terminal of the first resistor, and the anode of the first diode is connected to the second terminal of the first resistor, the first output port is connected to the anode of the first diode through the first resistor. Furthermore, since the cathode of the second diode is connected to the anode of the first diode, the first output port is connected to the cathode of the second diode through the first resistor. Based on the forward conduction characteristics of the diode, a portion of the positive electrostatic pulse flows into the electrostatic discharge protection circuit through the first output port, then through the first resistor, and finally through the path formed by the first diode and the first N-type field-effect transistor, exiting from the ground port. Given that the integrated circuit has a relatively high resistance, the intensity of the positive electrostatic pulse flowing into the electrostatic discharge protection circuit is greater than the intensity remaining inside the integrated circuit. This results in most of the positive electrostatic pulse flowing into the electrostatic discharge protection circuit through the first output port and exiting from the ground port. This allows the electrostatic discharge protection method to reduce the intensity of the electrostatic pulse within the integrated circuit, suppressing electrostatic damage to a certain extent and thus helping to ensure the reliability of the integrated circuit. The principle of the positive electrostatic pulse flowing through the path formed by the first diode and the first N-type field-effect transistor is the same as the principle of the positive electrostatic pulse flowing through the path formed by the first diode and the first N-type field-effect transistor when flowing into the second output port, and will not be repeated here.

[0060] If the electrostatic pulse is negative, similarly, a portion of the pulse remains inside the integrated circuit, while a portion flows into the electrostatic discharge (ESD) protection circuit through the first output port. Given that the first output port is connected to the negative terminal of the second diode via the first resistor, based on the forward conduction characteristic of the diode, after flowing into the ESD protection circuit through the first output port, the negative ESD pulse will flow through the first resistor, then through the second diode, and finally exit from the ground port. Since the integrated circuit has a relatively high resistance, the pulse intensity flowing through the second diode after the negative ESD pulse enters the ESD protection circuit through the first output port is greater than the pulse intensity remaining inside the integrated circuit. In other words, the pulse intensity flowing into the ESD protection circuit is greater than the intensity remaining inside the integrated circuit, causing most of the negative ESD pulse to flow out through the ESD protection circuit. This allows the ESD protection method to reduce the intensity of the ESD pulse inside the integrated circuit, thereby suppressing ESD damage to the integrated circuit to a certain extent and helping to ensure the reliability of the integrated circuit.

[0061] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the integrated circuit also includes an input port 02, and the electrostatic discharge protection circuit also includes: an input output port, a third diode 31, and a fourth diode 32;

[0062] The input / output ports include a first input / output port 311 and a second input / output port 312. The first input / output port 311 is connected to the input port 02 of the integrated circuit. The second input / output port 312 is connected to the first input / output port 311 through the anode of the third diode 31. That is, the anode of the third diode is connected to both the second and first input / output ports. The cathode of the third diode 31 is connected to the first terminal of the capacitor 14. The cathode of the fourth diode 32 is connected to the anode of the third diode 31, and the anode of the fourth diode is connected to the ground terminal 20. Since the anode of the third diode is connected to both the second and first input / output ports, and the cathode of the fourth diode is connected to the anode of the third diode, the cathode of the fourth diode is also connected to both the first and second input / output ports.

[0063] The electrostatic discharge protection circuit further includes: a second resistor 33 and a second N-type field-effect transistor 34; wherein, the first end of the second resistor 33 is connected to the first input output port 311, and the second end is connected to the positive terminal of the third diode 31. It is known that the second input output port is connected to the positive terminal of the third diode, thus the second input output port is connected to the second end of the second resistor; the drain of the second N-type field-effect transistor 34 is connected to the first end of the second resistor 33, and the source is connected to the gate of the second N-type field-effect transistor 34 and the ground output port 20, respectively; the method further includes:

[0064] S6: Connect the first input output port to the input port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0065] It should be noted that the first input output port is connected to the integrated circuit input port by a wire bonding method, and the first input output port is connected to the first end of the second resistor by a metal wire. Therefore, even if the first input output port is connected to the integrated circuit input port and the first input output port is also connected to the first end of the second resistor, the integrated circuit input port will not be directly connected to the first end of the second resistor.

[0066] It should also be noted that, in the embodiments of this application, the input output port includes two input output ports: a first input output port and a second input output port. The integrated circuit includes one input port, but this application does not limit this. In other embodiments of this application, the electrostatic discharge protection circuit may also include one input output port or at least three input output ports, and the integrated circuit may include at least two input ports, depending on the specific circumstances.

[0067] Specifically, in this embodiment, the first input output port of the electrostatic discharge (ESD) protection circuit is connected to the input port of the integrated circuit, thereby connecting the ESD protection circuit to the integrated circuit. This allows the ESD protection circuit to provide ESD protection to the integrated circuit, suppressing ESD pulses from flowing into the integrated circuit through its input port, thus helping to prevent ESD damage to the integrated circuit and contributing to its development.

[0068] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second input output port, since the anode of the third diode is connected to the second input output port and the cathode of the fourth diode is connected to the second input output port, according to the forward conduction characteristics of the diodes, the positive electrostatic pulse will not flow through the fourth diode, but will flow through the path formed by the third diode and the first N-type field-effect transistor, and flow out from the ground output port. Furthermore, since the first input output port is connected to the second input output port, the positive electrostatic pulse, after flowing in from the second input output port, will also flow through the first input output port, and then into the integrated circuit through the integrated circuit input port connected to the first input output port. The process of the positive electrostatic pulse flowing through the path formed by the third diode and the first N-type field-effect transistor is as follows: the positive electrostatic pulse flows through the third diode, and after flowing through the third diode, it couples with the capacitor, releasing charge to the gate of the first N-type field-effect transistor, raising the gate potential of the first N-type field-effect transistor, causing the first N-type field-effect transistor to conduct, allowing the positive electrostatic pulse to flow through the first N-type field-effect transistor, and then flowing out from the ground terminal, thus allowing the positive electrostatic pulse to flow through the path formed by the third diode and the first N-type field-effect transistor. The principle of the positive electrostatic pulse flowing through the path formed by the third diode and the first N-type field-effect transistor is the same as the principle of the positive electrostatic pulse flowing from the second output terminal through the path formed by the first diode and the first N-type field-effect transistor, and will not be repeated here.

[0069] It should be noted that the resistance of the integrated circuit is known to be relatively large, exceeding the resistance of the path formed by the third diode and the first N-type field-effect transistor. Therefore, after the positive electrostatic pulse flows in from the second input port, the pulse intensity flowing through the path formed by the third diode and the first N-type field-effect transistor is greater than the pulse intensity flowing into the integrated circuit. In other words, after the positive electrostatic pulse flows in from the second input port, the pulse intensity flowing through the electrostatic protection circuit is greater than the pulse intensity flowing into the integrated circuit. This causes most of the positive electrostatic pulse to pass through the electrostatic protection circuit and flow out from the ground port, effectively reducing the intensity of the electrostatic pulse flowing into the integrated circuit. This allows the electrostatic protection circuit to suppress electrostatic damage to the integrated circuit to a certain extent, thereby helping to ensure the reliability of the integrated circuit.

[0070] Furthermore, when a positive electrostatic pulse flows into the second input terminal, it is known that the gate and source of the second N-type field-effect transistor (FET) are connected, and the gate is also connected to the ground terminal. This means the gate and source of the second N-type FET are short-circuited and both are grounded (referred to as Gate Ground NMOS, or GGNMOS). This causes the source and gate of the second N-type FET to be at a low potential. Therefore, when the positive electrostatic pulse flows through the drain of the second N-type FET and its intensity is low, the second N-type FET is in a turned-off state. When the intensity of the positive electrostatic pulse is high, the second N-type FET will conduct, and the positive electrostatic pulse will flow through the second N-type FET and exit from the ground terminal. Thus, when a positive electrostatic pulse flows into the second input terminal and its intensity is high enough to turn on the second N-type FET, the positive electrostatic pulse will also flow through the path formed by the second resistor and the second N-type FET, exiting from the ground terminal. This allows the electrostatic protection method to suppress electrostatic damage to the integrated circuit. It should be noted that GGNMOS is a MOS device frequently used in electrostatic discharge protection circuits, and its working principle is well known to those skilled in the art. Therefore, the specific working principle of GGNMOS will not be described in detail here.

[0071] It should also be noted that, in order to ensure the protection of the integrated circuit by the electrostatic discharge (ESD) protection circuit, the conduction voltage of the second N-type field-effect transistor in the ESD protection circuit provided in this application embodiment is lower than the ESD damage voltage of the integrated circuit. This means that the ESD pulse intensity that the second N-type field-effect transistor can conduct is less than the ESD pulse intensity that causes ESD damage to the ESD circuit, thereby ensuring the protection of the integrated circuit by the ESD protection circuit.

[0072] When a negative electrostatic pulse flows in from the second input port, it is known that the negative terminal of the fourth diode is connected to the second input port, and the positive terminal is connected to the ground port. According to the forward conduction characteristic of the diode, the negative electrostatic pulse, after flowing in from the second input port, will flow through the fourth diode and out from the ground port. Furthermore, the integrated circuit input port is connected to the first input port, and the first input port is connected to the second input port through the second resistor. Simultaneously, the drain of the second N-type field-effect transistor is also connected to the first end of the second resistor. Therefore, the positive electrostatic pulse, after flowing in from the second input port, will also flow through the path formed by the second resistor and the first N-type field-effect transistor, as well as the path formed by the second resistor and the integrated circuit.

[0073] It should be noted that when the drain of an N-type field-effect transistor (FET) is connected to a negative voltage, the PN junction of the FET will conduct, making the FET function like a diode. Therefore, when the negative electrostatic pulse flows through the second resistor and the drain of the second N-type FET, the FET functions like a diode. Since the drain of the second N-type FET is connected to the first terminal of the second resistor, and the source is connected to the ground terminal, the second N-type FET functions like a diode with its negative terminal connected to the first terminal of the second resistor and its positive terminal connected to the ground terminal. This causes the electrostatic pulse to flow through the second resistor and the second N-type FET, exiting from the ground terminal. When the negative electrostatic pulse flows through the drain of the second N-type field-effect transistor through the second resistor, the second N-type field-effect transistor acts as a diode, making its resistance similar to that of the fourth diode. Consequently, the resistance of the fourth diode is less than the resistance of the path formed by the second resistor and the second N-type field-effect transistor. Furthermore, since the integrated circuit has a larger resistance than the second N-type field-effect transistor, the resistance of the path formed by the second resistor and the second N-type field-effect transistor is less than the resistance of the path formed by the second resistor and the integrated circuit. Therefore, after the negative electrostatic pulse flows into the second input port, the intensity flowing through the fourth diode is greater than the intensity flowing through the path formed by the second resistor and the second N-type field-effect transistor, and the intensity flowing through the path formed by the second resistor and the second N-type field-effect transistor is greater than the intensity flowing through the path formed by the second resistor and the integrated circuit. That is, after the positive electrostatic pulse flows into the second input port, the intensity flowing through the fourth diode and the path formed by the second resistor and the second N-type field-effect transistor is greater than the intensity flowing through the path formed by the second resistor and the integrated circuit. This causes most of the intensity of the negative electrostatic pulse to flow out through the path formed by the second resistor and the second N-type field-effect transistor and the fourth diode, reducing the intensity of the electrostatic pulse flowing into the integrated circuit. As a result, the electrostatic protection method can, to a certain extent, suppress electrostatic damage to the integrated circuit and ensure the reliability of the integrated circuit.

[0074] Furthermore, when an electrostatic pulse (ESP) exists inside the integrated circuit and acts on its input port, if the ESP is positive, since the integrated circuit input port is connected to the first input / output port, part of the positive ESP remains inside the integrated circuit, while part flows through the first input / output port connected to the integrated circuit input port and into the ESD protection circuit. If the positive ESP is weak and cannot turn on the second N-type field-effect transistor (FET), part of the positive ESP flows into the ESD protection circuit and then through the path formed by the second resistor, the third diode, and the first N-type FET. Since the resistance of the path formed by the third diode and the first N-type FET is less than the resistance of the integrated circuit, the intensity of the positive ESP flowing through the path is greater than the intensity remaining inside the integrated circuit. This allows the ESD protection circuit to reduce the intensity of the ESP inside the integrated circuit, thus suppressing ESD damage to the integrated circuit to a certain extent.

[0075] Furthermore, if the electrostatic pulse is a positive electrostatic pulse and has a relatively high intensity, enough to turn on the second N-type field-effect transistor (FET), then after flowing through the first input / output port, the positive electrostatic pulse will flow not only through the path formed by the second resistor, the third diode, and the first N-type FET, but also through the second N-type FET, and exit from the ground port. This can further reduce the intensity of the electrostatic pulse inside the integrated circuit, thereby allowing the electrostatic protection circuit to suppress electrostatic damage to the integrated circuit to a certain extent. It should be noted that the intensity of the positive electrostatic pulse flowing through the path formed by the second resistor, the third diode, and the first N-type FET, and the intensity flowing through the second N-type FET, are related to the resistance of the path formed by the second resistor, the third diode, and the first N-type FET, and the resistance of the second N-type FET. A path with relatively higher resistance will have a smaller electrostatic pulse intensity, and vice versa.

[0076] If the electrostatic pulse is negative, similarly, a portion of the negative electrostatic pulse remains inside the integrated circuit, while a portion flows into the electrostatic discharge (ESD) protection circuit through the first input port. After flowing into the ESD protection circuit, it passes through the first N-type field-effect transistor (FET) and exits from the ground port, and also passes through the first diode and exits from the ground port. Since the resistance of the first N-type FET is less than the resistance of the integrated circuit, and the resistance of the first diode is also less than the resistance of the integrated circuit, the intensity of the negative ESD pulse flowing into the ESD protection circuit is greater than the intensity remaining inside the integrated circuit. This allows the ESD protection method to reduce the intensity remaining inside the integrated circuit and suppress ESD damage to the integrated circuit.

[0077] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the integrated circuit also includes a power port 03, and the electrostatic discharge protection circuit also includes a power output port and a fifth diode 41;

[0078] The power output ports include a first power output port 411 and a second power output port 412. The first power output port 411 is also connected to the drain of the first N-type field-effect transistor 15, and the second power output port 412 is connected to the negative terminal of the third diode. Since the negative terminal of the third diode is connected to the drain of the first N-type field-effect transistor 15 through the first terminal of the capacitor 14, the second power output port 412 is connected to the drain of the first N-type field-effect transistor 15 through the first terminal of the capacitor 14. Since the first power output port 411 is connected to the drain of the first N-type field-effect transistor 15, the second power output port 412 is connected to the first power output port through the first terminal of the capacitor 14 and the drain of the first N-type field-effect transistor 15.

[0079] The negative terminal of the fifth diode 41 is connected to the first power output port 411. Since the second power output port 412 is connected to the first power output port 411 through the first terminal of the capacitor 14 and the drain of the first N-type field-effect transistor 15, the negative terminal of the fifth diode 41 is connected to the corresponding second power output port 412 through the first terminal of the capacitor 14, the drain of the first N-type field-effect transistor 15, and the first power output port 411. Furthermore, the positive terminal of the fifth diode 41 is connected to the ground output port 20. The method further includes:

[0080] S7: Connect the first power output port to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0081] It should be noted that the first power output port is connected to the integrated circuit power port by a wire bonding method, and the first power output port is connected to the drain of the first N-type field-effect transistor by a metal wire. The first power output port is also connected to the negative terminal of the fifth diode by a metal wire. Therefore, even if the first power output port is connected to the integrated circuit power port, and the first power output port is also connected to the drain of the first N-type field-effect transistor and the negative terminal of the fifth diode, the integrated circuit power port will not be directly connected to the drain of the first N-type field-effect transistor, nor will it be directly connected to the negative terminal of the fifth diode.

[0082] It should also be noted that, in the embodiments of this application, the power output port includes two power output ports: a first power output port and a second power output port. The integrated circuit includes one power port, but this application does not limit this. In other embodiments of this application, the electrostatic discharge protection circuit may also include one power output port or at least three power output ports, and the integrated circuit may include at least two power ports, depending on the specific circumstances.

[0083] Specifically, in this embodiment, the power output port of the electrostatic discharge protection circuit is connected to the power port of the integrated circuit, thereby enabling the electrostatic discharge protection circuit to protect the integrated circuit from electrostatic discharge and suppress electrostatic pulses from flowing into the integrated circuit through the power port of the integrated circuit. This helps to suppress electrostatic damage to the integrated circuit and ensure the development of the integrated circuit.

[0084] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second power output port, since the negative terminal of the third diode is connected to the second power output port, the positive electrostatic pulse will not flow through the third diode; since the second power output port is connected to the drain of the first N-type field-effect transistor through the first terminal of the capacitor, the positive electrostatic pulse will flow through the first N-type field-effect transistor; since the first power output port is connected to the drain of the first N-type field-effect transistor, the positive electrostatic pulse will flow through the first power output port and flow into the integrated circuit through the power port of the integrated circuit connected to the first power output port; since the negative terminal of the fifth diode is connected to the first power output port, the positive electrostatic pulse will not flow through the fifth diode; since the negative terminal of the first diode is connected to the drain of the first N-type field-effect transistor, the positive electrostatic pulse will not flow through the first diode. In summary, after the positive electrostatic pulse flows in from the second output port, it will flow through the first N-type field-effect transistor, flow out from the ground terminal output port, and also flow into the integrated circuit through the power port of the integrated circuit connected to the first power output port. It is known that the resistance of the integrated circuit is greater than the resistance of the first N-type field-effect transistor (FET). Therefore, when the positive electrostatic pulse flows in from the second output port, the pulse intensity flowing through the first N-type FET is greater than the pulse intensity flowing into the integrated circuit. This causes most of the positive electrostatic pulse to flow out through the first N-type FET, thus reducing the pulse intensity flowing into the integrated circuit and, to a certain extent, suppressing electrostatic damage to the integrated circuit, thereby helping to ensure the reliability of the integrated circuit. Specifically, the process of the positive electrostatic pulse flowing through the first N-type FET is as follows: after flowing in from the second power output port, the positive electrostatic pulse couples with the capacitor, releasing charge to the gate of the first N-type FET, raising the gate potential of the first N-type FET, causing the first N-type FET to conduct, allowing the positive electrostatic pulse to flow through the first N-type FET and out from the ground output port.

[0085] When a negative electrostatic pulse flows in from the second power output port, since the second power output port is connected to the first power output port through the first terminal of the capacitor and the drain of the first N-type field-effect transistor, the negative electrostatic pulse will flow through the first power output port connected to the power port of the integrated circuit and flow into the integrated circuit from the power port of the integrated circuit. At the same time, it will also flow through the drain of the N-type field-effect transistor. It is known that the drain of the field-effect transistor is connected to a negative voltage, which will make the PN junction of the N-type field-effect transistor conduct, making the N-type field-effect transistor equivalent to a diode. Since the drain of the first N-type field-effect transistor is connected to the second power output port and the source is connected to the ground output port, when the negative electrostatic pulse flows through the drain of the first N-type field-effect transistor, the first N-type field-effect transistor is equivalent to a diode with the negative terminal connected to the second power output port and the positive terminal connected to the ground output port. Therefore, the negative electrostatic pulse will also flow through the first N-type field-effect transistor and flow out from the ground output port. Since the negative terminal of the fifth diode is connected to the first power supply output port and the positive terminal is connected to the ground output port, the positive electrostatic pulse will also flow through the fifth diode and exit from the ground output port. It is known that when the negative electrostatic pulse flows in, the first N-type field-effect transistor (FET) acts as a diode. Therefore, when the negative electrostatic pulse flows in, the first N-type FET and the fifth diode have the same conduction capability. Considering the minute resistance on the wires in the circuit, the intensity of the negative electrostatic pulse flowing through the first N-type FET and the fifth diode is related to the length of the wire between the first N-type FET and the fifth diode and the second power supply output port. A shorter wire results in a stronger path, and a longer wire results in a weaker path. Because the integrated circuit has a larger resistance than the diode, the intensity of the negative electrostatic pulse flowing into the integrated circuit is greater when it passes through the fifth diode and the first N-type field-effect transistor than when it flows into the integrated circuit. As a result, most of the negative electrostatic pulse can flow out from the ground terminal through the fifth diode and the first N-type field-effect transistor. This allows the electrostatic protection method to reduce the intensity of the electrostatic pulse flowing into the integrated circuit and suppress electrostatic damage to the integrated circuit.

[0086] In addition, based on the forward conduction characteristics of diodes, after the negative electrostatic pulse flows in, it will also flow through the path formed by the third diode and the fourth diode, the path formed by the third diode and the second N-type field-effect transistor, and the path formed by the first diode and the second diode. Since the first N-type field-effect transistor is equivalent to a diode at this time, and the resistance on the wire is very small, it cannot affect the resistance between the different paths formed by the circuit elements. Therefore, the resistance of the path formed by the second diode and the first diode, the path formed by the third diode and the second N-type field-effect transistor, and the path formed by the third diode and the fourth diode is greater than the resistance of the first N-type field-effect transistor. Furthermore, since the path formed by the second diode and the first diode includes two diodes... The path formed by the third diode and the fourth diode includes two diodes, and the path formed by the third diode and the second N-type field-effect transistor includes one diode and one field-effect transistor. Therefore, the resistance of the paths formed by the second diode and the first diode, the third diode and the second N-type field-effect transistor, and the third diode and the fourth diode is greater than the resistance of the fifth diode. Consequently, the electrostatic pulse intensity flowing through the first N-type field-effect transistor and the fifth diode is greater than the intensity flowing through the paths formed by the second diode and the first diode, the third diode and the second N-type field-effect transistor, and the third diode and the fourth diode. The electrostatic pulse intensity flowing through the paths formed by the second diode and the first diode, the third diode and the second N-type field-effect transistor, and the third diode and the fourth diode is related to the resistance of each path; a higher resistance results in a lower electrostatic pulse intensity, and a lower resistance results in a higher electrostatic pulse intensity. This will not be elaborated further here.

[0087] Furthermore, when an electrostatic pulse (ESP) exists inside the integrated circuit and acts on its power port, if the ESP is positive, since the first power output port is connected to the integrated circuit's power port, part of the ESP will remain inside the integrated circuit, while part will flow through the first power output port and into the ESD protection circuit. According to the forward conduction characteristic of a diode, after flowing into the ESD protection circuit, part of the ESP will flow through the drain of the first N-type field-effect transistor (FET) and couple with the capacitor, releasing charge to the FET and raising its gate potential, thus turning it on. This allows the positive ESP to flow through the first power output port, then through the FET, and finally out through the ground port. Because the integrated circuit's resistance is greater than the FET's resistance, the intensity of the positive ESP flowing through the FET is greater than the intensity remaining inside the integrated circuit. Therefore, this ESP method can reduce the intensity of the ESP inside the integrated circuit, thereby suppressing ESD damage to the integrated circuit to a certain extent.

[0088] If the electrostatic pulse is negative, a portion of it will remain inside the integrated circuit, while another portion will flow through the first power output port connected to the integrated circuit's power supply port and through the drain of the first N-type field-effect transistor (FET). As previously mentioned, the first N-type FET is essentially a diode with its negative terminal connected to the first power output port and its positive terminal connected to the ground output port. Due to the forward conduction characteristic of a diode, the negative electrostatic pulse will flow through the first N-type FET and exit from the ground output port. Since the negative terminal of the fifth diode is connected to the first power output port and its positive terminal is connected to the ground output port, the negative electrostatic pulse will also flow through the fifth diode. In this case, the fifth diode has the same conduction capability as the first N-type FET. Considering the minute resistance in the circuit's wires, the intensity of the negative electrostatic pulse flowing through the first N-type FET and the fifth diode depends on the length of the wire between the first N-type FET and the fifth diode and the second power output port. Shorter wires result in a stronger path, while longer wires result in a weaker path. Because the integrated circuit has a larger resistance than the diode, the intensity of the negative electrostatic pulse flowing through the first N-type field-effect transistor and the fifth resistor is greater than the intensity remaining inside the integrated circuit. This allows the electrostatic protection method to reduce the intensity of the electrostatic pulse inside the integrated circuit and suppress electrostatic damage to the integrated circuit.

[0089] In addition, based on the forward conduction characteristics of diodes, after the negative electrostatic pulse flows into the electrostatic protection circuit, it will also flow through the path formed by the third diode and the fourth diode, the path formed by the third diode and the second N-type field-effect transistor, and the path formed by the first diode and the second diode. Since the first N-type field-effect transistor is equivalent to a diode at this time, and the resistance on the wire is very small, it cannot affect the resistance between the different paths formed by the circuit elements. Therefore, the resistance of the path formed by the second diode and the first diode, the path formed by the third diode and the second N-type field-effect transistor, and the path formed by the third diode and the fourth diode is greater than the resistance of the first N-type field-effect transistor. Furthermore, since the path formed by the second diode and the first diode includes two... The circuit formed by the third and fourth diodes includes two diodes, and the circuit formed by the third diode and the second N-type field-effect transistor includes one diode and one field-effect transistor. Therefore, the resistance of the circuits formed by the second and first diodes, the third and second N-type field-effect transistors, and the third and fourth diodes is greater than the resistance of the fifth diode. Consequently, the electrostatic pulse intensity flowing through the first N-type field-effect transistor and the fifth diode is greater than the intensity flowing through the circuits formed by the second and first diodes, the third and second N-type field-effect transistors, and the third and fourth diodes. The intensity of the electrostatic pulse flowing through the circuits formed by the second and first diodes, the third and second N-type field-effect transistors, and the third and fourth diodes is related to the resistance of each circuit; a higher resistance results in a lower intensity electrostatic pulse, and a lower resistance results in a higher intensity electrostatic pulse. Further details are omitted here.

[0090] It should be noted that when an electrostatic pulse (ESP) exists inside the integrated circuit, after flowing through the first input port, first output port, or first power output port, it may flow through other ports of the ESP protection circuit. However, due to the low resistance and strong shunt capability of the ESP protection circuit, the intensity of the ESP flowing through these other ports will also be low. Therefore, even if the ESP flows through other ports of the ESP protection circuit, it will not affect the operation of those other ports. Similarly, when an ESP flows into the second input port, second output port, or second power output port of the ESP protection circuit, it may also flow through other ports. Likewise, due to the low resistance and strong shunt capability of the ESP protection circuit, the intensity of the ESP flowing through these other ports will also be low. Therefore, even if the ESP flows through other ports of the ESP protection circuit, it will not affect the operation of those other ports.

[0091] It should also be noted that, in this embodiment, to avoid affecting the normal operation of the integrated circuit, the turn-on voltage of the field-effect transistor in the electrostatic discharge (ESD) protection circuit is approximately 20% higher than the turn-on voltage of the integrated circuit. This ensures that when the integrated circuit is turned on, the field-effect transistor in the ESD protection circuit is in a closed state. This prevents the power signal from flowing through the ESD protection circuit's field-effect transistor and then exiting from the ground terminal after passing through the second power output port, thus preventing the integrated circuit from malfunctioning. Furthermore, according to... Figure 1 As can be seen, each diode in the electrostatic discharge protection circuit is in reverse connection with the second power output port. This ensures that after the power signal of the integrated circuit flows through the second power output port, the power signal will not flow through the diodes and out of the ground terminal, thus guaranteeing the normal operation of the integrated circuit.

[0092] Optionally, in one embodiment of this application, the first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode. However, this application does not limit the specific choice of diode, and the choice depends on the circumstances.

[0093] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the electrostatic discharge protection circuit further includes: a third resistor 50; the method further includes:

[0094] S8: Connect the first end of the third resistor 50 to the gate of the first N-type field-effect transistor 15, and the second end to the ground terminal 20. Since the gate of the first N-type field-effect transistor 15 is connected to the second end of the capacitor 14, the first end of the third resistor 50 is connected to the second end of the capacitor 14 through the gate of the first N-type field-effect transistor 15. After the electrostatic pulse couples with the capacitor, the capacitor will discharge to the gate of the first N-type field-effect transistor, accumulating charge at the gate of the first N-type field-effect transistor, triggering the first N-type field-effect transistor to turn on. However, if too much charge accumulates at the gate of the first N-type field-effect transistor, it will cause damage to the first N-type field-effect transistor. The addition of the third resistor can share some of the electrical energy released by the capacitor, which helps to prevent too much charge from accumulating at the gate of the first N-type field-effect transistor and damaging the first N-type field-effect transistor. This helps to ensure the reliability of the electrostatic protection circuit, so that the electrostatic protection circuit can reliably reduce the possibility of electrostatic damage to the integrated circuit and ensure the reliability of the integrated circuit.

[0095] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the ground output port 20 includes a first ground output port 21 and a second ground output port 22; the method further includes:

[0096] S9: Connect the first ground output port 21 to the ground port 04 of the integrated circuit, connect the second ground output port 22 to the first ground output port 21, and ground the second ground output port 22, thereby grounding the ground port 04 of the integrated circuit, enabling the electrostatic discharge circuit to discharge electrostatic pulses from the second ground output port 22. The first ground output port and the ground port of the integrated circuit are connected by a wire bonding, and the first ground output port and the second ground output port are connected by a metal wiring. It should be noted that in this embodiment, the ground output port includes two ground output ports (first ground output port and second ground output port), and the integrated circuit includes one ground port. However, this application is not limited to this. In other embodiments of this application, the electrostatic discharge circuit may also include one ground output port or at least three ground output ports, and the integrated circuit may include at least two ground ports, depending on the specific circumstances.

[0097] It should be noted that, continuing as Figure 2As shown, the second power output port 412 of the electrostatic discharge (ESD) protection circuit is connected to an external power supply 61, the second input output port 312 is connected to an external input port 62, the second output output port 112 is connected to an external output port 63, and the second ground output port 22 is grounded to ground 64. This ensures that the integrated circuit can be connected to the outside world while being protected by the ESD protection circuit, guaranteeing the normal operation of the integrated circuit. Furthermore, the various output ports of the ESD protection circuit are connected to the various ports of the integrated circuit and the various external ports via wire bonding, but this application does not limit this connection; it depends on the specific circumstances.

[0098] To gain a clearer understanding of the electrostatic discharge (ESD) protection capability of the circuit, a TLP (ThinPrep) device was used to test its protection capability. The ESD protection capability of the circuit will be described below based on the test results from the TLP device.

[0099] Specifically, when a positive electrostatic pulse (ESP) is applied to the second input output port, in order to test the ESP protection capability of the ESP protection circuit, a TLP device is used to monitor the positive ESP flowing into the second input output port and the leakage current between the second input output port and the ground output port. The results are as follows: Figure 3 As shown, curve 1 is the IV curve of the electrostatic pulse at the second input output port, and curve 2 is the leakage current curve between the second input output port and the ground port. Figure 3 It can be seen that when the positive electrostatic pulse intensity increases to 8V or slightly higher, the leakage current is small. As the positive electrostatic pulse intensity continues to increase, the leakage current rises rapidly, at which point electrostatic damage occurs to the integrated circuit. This indicates that the electrostatic protection circuit can withstand a positive electrostatic pulse of 8V or slightly higher flowing into the second input output port. When a negative electrostatic pulse acts on the second input output port, the TLP is also used to monitor the negative electrostatic pulse at the second input port and the leakage current between the second input port and the ground port. The results are as follows. Figure 4 As shown, curve 1 is the electrostatic pulse IV curve of the second input output port, and curve 2 is the leakage current curve between the second input output port and the ground port. Figure 4 It can be seen that when the intensity of the negative electrostatic pulse increases to 8V or slightly higher, the leakage current is small. As the electrostatic pulse continues to increase, the leakage current increases rapidly. At this time, electrostatic damage occurs to the integrated circuit, indicating that the electrostatic protection circuit can withstand a negative electrostatic pulse with an intensity of 8V or slightly higher flowing in from the second input output port.

[0100] When a positive electrostatic pulse (ESP) is applied to the second output port, in order to test the ESD protection capability of the ESD protection circuit, a TLP device is used to monitor the positive ESD pulse flowing into the second output port and the leakage current between the second output port and the ground port. The results are as follows: Figure 5 As shown, curve 1 is the positive electrostatic pulse (ESP) IV curve of the second output port, and curve 2 is the leakage current curve between the second output port and the ground port. According to... Figure 5 It can be seen that when the positive electrostatic pulse intensity increases to 8V or slightly higher, the leakage current is small, and the integrated circuit does not suffer electrostatic damage. However, as the positive electrostatic pulse continues to increase, the leakage current increases rapidly, and electrostatic damage occurs in the integrated circuit. This indicates that the electrostatic protection circuit can withstand a positive electrostatic pulse of 8V or slightly higher flowing into the second output port. When a negative electrostatic pulse acts on the second output port, the TLP is also used to monitor the electrostatic pulse at the second output port and the leakage current between the second output port and the ground port. The results are then obtained as follows... Figure 4 As shown, the electrostatic discharge protection circuit can withstand negative electrostatic pulses with an intensity of 8V or slightly higher than 8V flowing in from the second output port.

[0101] When a positive electrostatic pulse is applied to the second power output port, a TLP device is used to monitor the positive electrostatic pulse flowing into the second power output port and the leakage current between the second power output port and the ground output port. The results are as follows: Figure 6 As shown, curve 1 is the positive electrostatic pulse (ESP) IV curve of the second power output port, and curve 2 is the leakage current curve between the second power output port and the ground port. According to... Figure 6 It can be seen that when the positive electrostatic pulse intensity increases to 14V or slightly higher, the leakage current is small, and the integrated circuit is not damaged at this time. As the positive electrostatic pulse continues to increase, the leakage current increases rapidly, and electrostatic damage occurs in the integrated circuit. This indicates that the electrostatic protection circuit can withstand a positive electrostatic pulse of 14V or slightly higher flowing into the second power output port. When a negative electrostatic pulse acts on the second input output port, the TLP is also used to monitor the negative electrostatic pulse at the second power output port and the leakage current between the second power output port and the ground port. The results are then obtained as follows... Figure 4 As shown, the electrostatic discharge protection circuit can withstand negative electrostatic pulses with an intensity of 8V or slightly higher than 8V flowing in from the second power output port.

[0102] In summary, this application provides a method for suppressing electrostatic discharge (ESD) damage to an integrated circuit. The method includes: providing a first chip and distributing an integrated circuit on the first chip, the integrated circuit including an output port; providing a second chip and distributing an ESD protection circuit on the second chip, the ESD protection circuit including an output port and a first resistor, the output port including a first output port and a second output port, wherein when an ESD pulse flows in from the second output port and passes through the first resistor, the resistance value of the first resistor increases; connecting the first output port to the output port of the integrated circuit, thereby connecting the ESD protection circuit to the integrated circuit, when an ESD pulse flows in from the second output port and passes through the first resistor, the resistance value of the first resistor increases, which can suppress the ESD pulse from flowing into the integrated circuit, thus enabling the ESD protection method to protect the integrated circuit from ESD damage and helping to suppress ESD damage to the integrated circuit. Furthermore, the electrostatic discharge (ESD) protection circuit is disposed on the second chip, while the integrated circuit is disposed on the first chip. This means that the integrated circuit and the ESD protection circuit are disposed on different chips, eliminating the need for ESD protection design on the first chip. In other words, ESD protection design is not required on the chip containing the integrated circuit, thus avoiding the problem of being unable to perform ESD protection design on the integrated circuit due to limitations in the substrate material of the chip containing the integrated circuit. This enables ESD protection for ESD-sensitive novel integrated circuits, thereby contributing to the reliability of novel material integrated circuits and promoting their development.

[0103] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0104] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for suppressing electrostatic damage to integrated circuits, characterized in that, include: A first chip is provided, and an integrated circuit is disposed on the first chip, wherein the integrated circuit includes an output port; A second chip is provided, on which an electrostatic discharge (ESD) protection circuit is disposed. The ESD protection circuit includes an output port and a first resistor. The output port includes a first output port and a second output port. The second output port is connected to the first output port through the first resistor. The first end of the first resistor is connected to the first output port, and the second end is connected to the second output port. When an ESD pulse flows in from the second output port and passes through the first resistor, the resistance of the first resistor increases. Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit provides electrostatic discharge protection for the integrated circuit; The first chip is a carbon-based chip, and the second chip is a silicon-based chip.

2. The method according to claim 1, characterized in that, The electrostatic discharge protection circuit further includes: a first diode, a capacitor, a first N-type field-effect transistor (FET), and a ground terminal output port, wherein the cathode of the first diode is connected to a first terminal of the capacitor through the drain of the first N-type FET, the gate of the first N-type FET is connected to a second terminal of the capacitor, and the source of the first N-type FET is connected to the ground terminal output port, which is grounded; the method further includes: Connect the positive terminal of the first diode to the second terminal of the first resistor and the second output port respectively, so that the second output port is connected to the second terminal of the first resistor through the positive terminal of the first diode; The electrostatic discharge protection circuit further includes a second diode, and the method further includes: Connect the negative terminal of the second diode to the positive terminal of the first diode, and connect the positive terminal to the ground terminal.

3. The method according to claim 2, characterized in that, The integrated circuit further includes an input port, and the electrostatic discharge protection circuit further includes an input output port, a third diode, and a fourth diode. The input output port includes a first input output port and a second input output port. The second input output port is connected to the first input output port through the positive terminal of the third diode. The negative terminal of the third diode is connected to the first terminal of the capacitor. The negative terminal of the fourth diode is connected to the positive terminal of the third diode, and the positive terminal is connected to the ground output port. The electrostatic discharge protection circuit further includes: a second resistor and a second N-type field-effect transistor, wherein the first end of the second resistor is connected to the first input output port, the second end is connected to the positive terminal of the third diode, the drain of the second N-type field-effect transistor is connected to the first end of the second resistor, and the source is connected to the gate of the second N-type field-effect transistor and the ground output port respectively. The method also includes: The first input output port is connected to the input port of the integrated circuit so that the electrostatic discharge protection circuit provides electrostatic protection for the integrated circuit.

4. The method according to claim 3, characterized in that, The integrated circuit further includes a power supply port, and the electrostatic discharge protection circuit further includes: a power output port and a fifth diode, wherein the power output port includes a first power output port and a second power output port, the first power output port is connected to the drain of the first N-type field-effect transistor, the second power output port is connected to the cathode of the third diode, the cathode of the fifth diode is connected to the first power output port, and the anode is connected to the ground output port; the method further includes: The first power output port is connected to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

5. The method according to claim 4, characterized in that, The first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode.

6. The method according to claim 2, characterized in that, The electrostatic discharge protection circuit further includes a third resistor; the method further includes: The first end of the third resistor is connected to the gate of the first N-type field-effect transistor, and the second end is connected to the ground terminal.

7. The method according to claim 2, characterized in that, The integrated circuit further includes a ground port, wherein the ground output port includes a first ground output port and a second ground output port; the method further includes: Connect the first ground output port to the ground port of the integrated circuit, connect the second ground output port to the first ground output port, and ground the second ground output port.

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