Three-dimensional memory, its fabrication method, storage system and electronic device

Abstract

This invention relates to a three-dimensional memory and its fabrication method, storage system, and electronic device. The fabrication method of the three-dimensional memory includes: forming a stacked structure on a substrate, the substrate including multiple block regions and gate line slot regions located between adjacent block regions; forming multiple channel holes located on the block regions and gate line slot regions and penetrating the stacked structure; forming gate line slits on the gate line slot regions, the gate line slits being used to separate the stacked structures on adjacent block regions. This avoids the problem of poor channel hole morphology consistency caused by uneven stress distribution in the stacked structures on the block regions during the etching process of forming channel holes on the block regions, which is beneficial for increasing the process window for subsequent processes and improving the uniformity of electrical parameters of the storage cells in the three-dimensional memory.

Description

[Technical Field]

[0001] The present invention relates to the field of memory technology, specifically to a three-dimensional memory and its fabrication method, storage system and electronic device. [Background Technology]

[0002] With the development of technology, the semiconductor industry is constantly seeking new production methods to enable each memory die in a memory device to have a greater number of memory cells. Among them, 3D NAND (three-dimensional NAND gate) memory has become a cutting-edge and highly promising three-dimensional memory technology due to its advantages such as high storage density and low cost.

[0003] Existing 3D NAND flash memory typically comprises multiple memory block regions, separated by gate line gaps, with multiple channel structures distributed within each block region. However, during the etching process to form channel holes within the memory block regions, the stress distribution of the stacked structures in the gate line gaps becomes uneven. Channel holes near the gate line gaps exhibit poor shape retention during etching and are prone to deformation, resulting in inconsistent morphology of the formed deep-hole structures. This, in turn, affects the process window for subsequent fabrication processes. [Summary of the Invention]

[0004] This invention provides a three-dimensional memory and its fabrication method, storage system and electronic device, to improve the morphological consistency of the channel holes in the storage block region, thereby increasing the process window for subsequent processes.

[0005] To at least partially solve the above problems, embodiments of the present invention provide a method for fabricating a three-dimensional memory. The method includes: forming a stacked structure on a substrate, the substrate including a plurality of block regions and gate line slot regions located between adjacent block regions; forming a plurality of channel holes located on the block regions and the gate line slot regions and penetrating the stacked structure; and forming gate line slits on the gate line slot regions to separate the stacked structures on adjacent block regions.

[0006] Before forming the grid line slots in the grid line slot region, the process includes: sequentially forming a storage function layer and a channel layer on the inner wall of the channel hole to form a channel structure; removing the channel layer in the channel hole located in the grid line slot region; and forming an insulating layer to fill the remaining space in the channel hole.

[0007] Specifically, forming a gate line slot in the gate line slot region includes removing the stacked structure, insulating layer, and storage function layer located in the gate line slot region to form the gate line slot.

[0008] Before forming the gate slit in the gate slit region, the method further includes: forming a corresponding channel plug in the block region at the end of the channel hole away from the substrate, wherein the channel plug is connected to the channel layer in the corresponding channel hole.

[0009] The block area includes a core area and a step area that are connected. Before forming grid slits in the grid slit area, it also includes removing part of the stacked structure in the step area to form a step structure.

[0010] Multiple channel holes extend into the substrate in a direction perpendicular to the substrate.

[0011] The process of forming grid line slots in the grid line slot region further includes: forming grid line gap structures in the grid line slots.

[0012] To at least partially solve the above problems, embodiments of the present invention also provide a three-dimensional memory, the three-dimensional memory comprising: a substrate, the substrate including a plurality of block regions and gate line slot regions located between adjacent block regions; a stacked structure located on the substrate; gate line slots located on the gate line slot regions, the gate line slots being used to separate the stacked structures on adjacent block regions; a plurality of channel structures and a plurality of virtual channel structures located on the block regions and penetrating the stacked structures, the virtual channel structures being connected to the gate line slots, and the channel structures not being connected to the gate line slots.

[0013] In this design, the bottom surface of the gate slits partially protrudes into the substrate in a direction facing the substrate, thereby forming multiple openings on the substrate.

[0014] The three-dimensional memory also includes a gate gap structure located in the gate gap.

[0015] The channel structure includes a first dielectric pillar, a channel layer surrounding the first dielectric pillar, and a first storage function layer surrounding the channel layer. The virtual channel structure includes a second dielectric pillar.

[0016] The virtual channel structure also includes a second storage function layer surrounding the second media pillar.

[0017] The three-dimensional memory also includes a channel plug located at the end of the channel structure away from the substrate, the channel plug being connected to the channel layer in the corresponding channel structure.

[0018] To at least partially solve the above problems, embodiments of the present invention also provide a storage system, which includes a controller and a three-dimensional memory as described above, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

[0019] To at least partially solve the above problems, embodiments of the present invention also provide an electronic device that includes the above-described storage system.

[0020] The electronic devices include at least one of the following: mobile phones, desktop computers, tablet computers, laptops, servers, in-vehicle equipment, wearable devices, and power banks.

[0021] The beneficial effects of the embodiments of the present invention are as follows: Unlike related technologies, the three-dimensional memory and its fabrication method, storage system and electronic device provided by the embodiments of the present invention form a stacked structure on a substrate, the substrate including multiple block regions and gate line slot regions located between adjacent block regions, and then form multiple channel holes located on the block regions and gate line slot regions and penetrating the stacked structure. Subsequently, gate line slits are formed on the gate line slot regions to separate the stacked structures on adjacent block regions. In this way, during the etching process of forming channel holes on the block regions, the problem of poor channel hole morphology consistency caused by uneven stress distribution of the stacked structure on the block regions can be avoided, thereby increasing the process window of subsequent processes and improving the uniformity of electrical parameters of storage cells in the three-dimensional memory. [Attached Image Description]

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating the method for fabricating a three-dimensional memory provided in an embodiment of the present invention;

[0024] Figure 2 This is a top view of the structure after step S11 is completed, as provided in the embodiment of the present invention.

[0025] Figure 3 It is along Figure 2 A schematic diagram of the cross-sectional structure intercepted by line O-O' in the diagram;

[0026] Figure 4 This is a top view of the structure after step S12 is completed, as provided in the embodiment of the present invention.

[0027] Figure 5 It is along Figure 4 A schematic diagram of the cross-sectional structure intercepted by line O-O' in the diagram;

[0028] Figure 6 This is a top view schematic diagram of the semiconductor structure obtained after forming a channel hole, provided by related technologies;

[0029] Figure 7 This is another flowchart illustrating the method for fabricating a three-dimensional memory provided in an embodiment of the present invention;

[0030] Figure 8 This is a cross-sectional structural diagram after step S14 is completed according to an embodiment of the present invention;

[0031] Figure 9 This is a cross-sectional structural diagram after step S151 is completed according to an embodiment of the present invention;

[0032] Figure 10 This is a cross-sectional structural diagram after step S153 is completed according to an embodiment of the present invention;

[0033] Figure 11 This is a top view of the structure after step S154 is completed, as provided in the embodiment of the present invention.

[0034] Figure 12 It is along Figure 11 A schematic diagram of the cross-sectional structure intercepted by line O-O' in the diagram;

[0035] Figure 13 This is a cross-sectional structural diagram after step S154 is completed according to an embodiment of the present invention;

[0036] Figure 14 This is a cross-sectional structural diagram after step S16 is completed according to an embodiment of the present invention;

[0037] Figure 15 This is a cross-sectional structural diagram after step S13 is completed according to an embodiment of the present invention;

[0038] Figure 16 This is another cross-sectional structural diagram after step S13 is completed, as provided in the embodiment of the present invention;

[0039] Figure 17 This is a top view of the structure after step S20 is completed, as provided in the embodiment of the present invention.

[0040] Figure 18 It is along Figure 17 A schematic diagram of the cross-sectional structure intercepted by line O-O' in the diagram;

[0041] Figure 19 This is a schematic diagram of the structure of the storage system provided in an embodiment of the present invention;

[0042] Figure 20 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0043] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be particularly noted that the following embodiments are only used to illustrate the embodiments of the present invention and do not limit the scope of the embodiments of the present invention. Similarly, the following embodiments are only some embodiments of the embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of the present invention.

[0044] Furthermore, the directional terms mentioned in the embodiments of this invention, such as [up], [down], [front], [back], [left], [right], [inner], [outer], and [side], are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding the embodiments of this invention, and not for limiting the embodiments of this invention. In the various drawings, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0045] The embodiments of the present invention may be presented in various forms, and some examples will be described below.

[0046] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the present invention. The specific process of the method for fabricating the three-dimensional memory is as follows:

[0047] Step S11: Form a stacked structure on a substrate, the substrate including multiple block regions and gate line gap regions located between adjacent block regions.

[0048] The top view of the structure after step S11 is shown in the figure below. Figure 2 As shown, the cross-sectional structure diagram after step S11 is as follows: Figure 3 As shown, and, Figure 3 Specifically along Figure 2 A schematic diagram of the cross-sectional structure taken by line O-O' in the diagram.

[0049] The substrate 11 can be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The stacked structure 12 may include multiple alternating layers of a gate sacrificial layer 121 and a gate insulating layer 122 stacked perpendicular to the longitudinal direction Z of the substrate 11. In specific implementations, methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and laser-assisted deposition can be used to form the gate sacrificial layer 121 and the gate insulating layer 122 of the stacked structure 12 on the substrate 11.

[0050] In the above-mentioned stacked structure 12, the gate sacrificial layer 121 can be made of silicon nitride, and the gate insulating layer 122 can be made of silicon oxide, thereby forming a silicon nitride / silicon oxide stacked structure. In subsequent steps, the gate sacrificial layer 121 will be replaced by a replacement process and a conductive material (e.g., tungsten) will be filled in the same position to form a gate layer.

[0051] In a three-dimensional memory, the number of layers in the stacked structure 12 determines the number of memory cells it contains in the vertical direction (direction Z perpendicular to the substrate 11). For example, the number of layers in the stacked structure 12 can be 32, 64, 96, 128, etc., and the more layers the stacked structure 12 has, the higher the integration of the corresponding three-dimensional memory.

[0052] Specifically, the substrate 11 may include a first region K1, a gate line gap region GLS, and a second region K2 sequentially connected in a first lateral direction Y parallel to the substrate 11. The gate line gap region GLS can be used to form gate line gaps in subsequent process steps, and the gate line gaps can be used to separate the gate sacrificial layer 121 in the stacked structure 12 on two adjacent regions (e.g., the first region K1 and the second region K2). The aforementioned regions K1 / K2 can be used to form channel structures, virtual channel structures, and word line contacts in subsequent process steps.

[0053] Step S12: Form multiple channel holes located in the block region and the grid line gap region and penetrating the stacked structure.

[0054] The top view of the structure after step S12 is shown in the figure below. Figure 4 As shown, the cross-sectional structure diagram after step S12 is as follows: Figure 5 As shown, and, Figure 5 Specifically along Figure 4 A schematic diagram of the cross-sectional structure taken by line O-O' in the diagram.

[0055] Specifically, anisotropic etching (e.g., dry etching) or isotropic etching (e.g., wet etching) can be used to etch the stacked structure 12 from top to bottom on the block region K1 / K2 and the gate gap region GLS to form a channel hole 13 penetrating the stacked structure 12 from top to bottom. In one specific embodiment, as Figure 5 As shown, the aforementioned channel hole 13 can penetrate the aforementioned stacked structure 12 in the longitudinal direction Z perpendicular to the substrate 11 and extend into the interior of the substrate 11 to form an opening 11A on the substrate 11, thereby achieving sufficient etching to ensure that the substrate 11 can be exposed through the channel hole 13, and also helps to increase the support effect of the channel structure formed in the channel hole 13 on the stacked structure 12 in subsequent processes.

[0056] It is worth noting that the inventors have discovered that, according to the manufacturing method of the three-dimensional memory in the related art, such as Figure 6 As shown, during the etching of the stacked structure 22 to form the channel hole 23 on the block region K1' / K2', because the stacked structure 22 located on the gate gap region GLS' that forms the gate gap in the subsequent process steps will be reserved and will not be etched and patterned, the stress from the stacked structure 22 experienced when etching the channel hole 23 near the gate gap region GLS' (e.g., channel hole 23B) is greater than the stress experienced when etching the channel hole 23 far away from the gate gap region GLS' (e.g., channel hole 23A). Due to the stress of the stacked structure 22, under the same etching conditions, the channel holes 23 near the gate line gap region GLS' will have insufficient etching. Furthermore, the channel holes 23 near the gate line gap region GLS' have poor shape retention during the etching process and are prone to deformation. Consequently, the channel structure formed in the channel holes 23 near the gate line gap region GLS' in subsequent processes is difficult to maintain the same morphology as the channel structure formed in the channel holes 23 far from the gate line gap region GLS', affecting the uniformity of electrical parameters of the memory cells in the three-dimensional memory.

[0057] Understandably, compared to methods that only etch stacked structures to form channel holes on block areas, such as... Figure 4 As shown, the solution in this embodiment not only etches the stacked structure 12 to form the channel hole 13 on the block region K1 / K2, but also simultaneously etches the stacked structure 12 to form the channel hole 13 on the gate line gap region GLS. This can effectively reduce the difference between the stress from the stacked structure 12 experienced when the channel hole 13 is etched near the gate line gap region GLS and the stress experienced when the channel hole 13 is etched away from the gate line gap region GLS. This can at least partially solve the problems of insufficient etching and severe deformation of the channel hole 13 near the gate line gap region GLS, improve the morphological consistency of the channel hole 13 near the gate line gap region GLS and the channel hole 13 away from the gate line gap region GLS, increase the process window for subsequent processes, and help improve the uniformity of electrical parameters of memory cells in three-dimensional memory.

[0058] In this embodiment, the above-mentioned multiple channel holes 13 can be evenly distributed on the block regions K1 / K2 and the gate line gap region GLS of the substrate 11. That is, the channel holes 13 located on the block regions K1 / K2 and the channel holes 13 located on the gate line gap region GLS are the same in other characteristics (such as shape, size and spacing distance between adjacent channel holes) except for the distribution position.

[0059] Thus, by forming channel holes 13 simultaneously in the block regions K1 / K2 and the gate line gap region GLS in the same etching step, and arranging the channel holes 13 in the block regions K1 / K2 and the channel holes 13 in the gate line gap region GLS with the same arrangement pattern, the difference between the stress from the stacked structure 12 experienced when etching the channel holes 13 near the gate line gap region GLS and the stress from the stacked structure 12 experienced when etching the channel holes 13 far from the gate line gap region GLS can be completely eliminated. This completely solves the problems of insufficient etching and severe deformation of the channel holes 13 near the gate line gap region GLS, so that the channel holes 13 near the gate line gap region GLS and the channel holes 13 far from the gate line gap region GLS can be completely consistent in morphology. This further increases the process window for subsequent processes and is beneficial to further improve the consistency of electrical parameters of each memory cell in the three-dimensional memory.

[0060] Specifically, the aforementioned plurality of channel holes 13 can be arranged in multiple rows along a first transverse Y direction parallel to the substrate 11. Furthermore, in some specific embodiments, such as... Figure 4 As shown, adjacent rows of channel holes 13 can be staggered on a second horizontal direction X perpendicular to the first horizontal direction Y and parallel to the substrate 11 to increase the density of memory cells in three-dimensional storage. In some alternative embodiments, adjacent rows of channel holes 13 can also be aligned on the second horizontal direction X, that is, the plurality of channel holes 13 can be arranged in rows and columns with the first horizontal direction Y and the second horizontal direction X being the row direction and the column direction, respectively.

[0061] Step S13: Form grid line slots in the grid line slot area to separate the stacked structures on adjacent block areas.

[0062] Among them, such as Figure 7 As shown, before step S13 above, the following may also be included:

[0063] Step S14: A storage function layer and a channel layer are sequentially formed on the inner wall of the channel hole to form a channel structure.

[0064] The cross-sectional structure diagram after step S14 is shown below. Figure 8 As shown.

[0065] Specifically, physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser-assisted deposition, and other methods can be used to sequentially deposit a storage functional layer 142 and a channel layer 141 on the inner wall of the aforementioned channel hole 13 to obtain a channel structure 14 having a storage functional layer 142 and a channel layer 141.

[0066] The aforementioned storage functional layer 142 may include a charge blocking layer, a charge trapping layer, and a tunneling layer sequentially formed on the inner wall of the channel via 13. Specifically, the materials of the charge blocking layer, charge trapping layer, tunneling layer, and channel layer may be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, corresponding to the aforementioned channel structure as a "SONO" structure. Furthermore, it is understood that although the storage functional layer exemplified here uses an ONO structure composed of a first oxide layer, a nitride layer, and a second oxide layer as an example structure, other possible structures are also possible.

[0067] Step S15: Remove the trench layer from the trench holes located in the grid line gap area.

[0068] Specifically, step S15 above may include:

[0069] Step S151: Form a sacrificial layer on the stacked structure to cover the remaining space in the filling channel hole.

[0070] The cross-sectional structure diagram after step S151 is shown below. Figure 9 As shown.

[0071] Specifically, the sacrificial layer 15 can be formed on the surface (i.e., the upper surface) of the stacked structure 12 away from the substrate 11 using methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and laser-assisted deposition. The material of the sacrificial layer 15 may include amorphous carbon, and the sacrificial layer 15 can conform to the surface of the stacked structure 12 away from the substrate 11. Thus, after the sacrificial layer 15 covers and fills the channel hole 13, the sacrificial layer 15 located directly above the channel hole 13 will be recessed into the channel hole 13 in the direction towards the substrate 11, forming a first groove 15A on the surface of the sacrificial layer 15 away from the substrate 11. Furthermore, it is understood that due to the different deposition rates of the sacrificial layer 15 on the inner walls of the channel hole 13, gaps or voids may exist inside the sacrificial layer 15 located in the channel hole 13 (i.e., the sacrificial layer 15 filling the remaining space in the channel hole 13 where the storage functional layer 142 and the channel layer 141 are formed).

[0072] Step S152: Form the first photoresist layer on the sacrificial layer.

[0073] Step S153: Remove the first photoresist layer located on the gate line gap area by exposure and development to obtain a patterned first photoresist layer.

[0074] The cross-sectional structure diagram after step S153 is shown below. Figure 10 As shown.

[0075] The patterned first photoresist layer 16 may include a first opening pattern for exposing the sacrificial layer 15 located on the gate gap region. The first photoresist layer 16 may conform to the surface of the sacrificial layer 15 facing away from the substrate 11, such that a portion of the first photoresist layer 16 is recessed into a first groove 15A on the surface of the sacrificial layer 15 in the direction toward the substrate 11, while a second groove 16A is formed on the surface of the first photoresist layer 16 facing away from the substrate 11.

[0076] Step S154: Etch away the sacrificial layer located on the gate gap region and the channel layer in the channel via located on the gate gap region according to the patterned first photoresist layer.

[0077] The top view of the structure after step S154 is shown below. Figure 11 As shown, the cross-sectional structure diagram after step S154 is as follows: Figure 12 As shown, and, Figure 12 Specifically along Figure 11 A schematic diagram of the cross-sectional structure taken by line O-O' in the diagram.

[0078] Specifically, a selective etchant can be used to selectively remove the insulating layer 15 and the channel layer 141 relative to the storage functional layer 142 via the first opening pattern on the first photoresist layer 16.

[0079] Furthermore, it is understood that during the removal of the channel layer 141 in the channel hole 13 located on the gate gap region GLS, when there is a channel hole 13 (e.g., channel hole 13A) at the junction of the gate gap region GLS and the block region K1 / K2, whose orthogonal projection on the substrate 11 is only partially located in the gate gap region GLS, the channel layer 141 and the sacrificial layer 15 in the corresponding channel hole 13A will be completely removed, and in subsequent process steps, the remaining space in the channel hole 13A will be filled by the insulating layer formed in the subsequent process steps to form a virtual channel structure composed of the storage function layer 142 and the insulating layer in the channel hole 13A.

[0080] Specifically, after etching away the sacrificial layer 15 located on the gate gap region (GLS) and the channel layer 141 located in the channel via 13 on the GLS, the remaining first photoresist layer 16 and sacrificial layer 15 can also be removed. Furthermore, a cross-sectional view of the structure after removing the remaining first photoresist layer 16 and sacrificial layer 15 can be shown as follows: Figure 13 As shown.

[0081] Step S16: Form an insulating layer to fill the remaining space in the channel hole.

[0082] The cross-sectional structure diagram after step S16 is shown below. Figure 14As shown. Specifically, the material of the insulating layer 17 may include insulating materials such as silicon oxide. And, it is understood that after the above-mentioned insulating layer 17 is formed, a channel structure 14 consisting of a storage function layer 142, a channel layer 141 and an insulating layer 17 will be formed in the channel hole 13 whose orthogonal projection on the substrate 11 is completely located in the block region K1 / K2. A virtual channel structure 21 consisting of a storage function layer 142 and an insulating layer 17 will be formed in the channel hole 13 whose orthogonal projection on the substrate 11 is completely or partially located in the gate line gap region GLS.

[0083] Accordingly, step S13 can specifically be: removing the stacked structure 12, insulating layer 17, and storage function layer 142 located on the gate line slot region GLS to form the gate line slot 18, and the cross-sectional structure diagram after step S13 is completed can be as follows. Figure 15 As shown.

[0084] Specifically, such as Figure 15 As shown, the bottom surface of the aforementioned gate slit 18 can partially protrude into the substrate 11 in the direction toward the substrate 11 to form a plurality of openings 18A on the substrate 11. Furthermore, it is understood that the openings 18A can correspond one-to-one with the channel holes 13 whose orthogonal projections on the substrate 11 are entirely or partially located in the gate slit region (GLS), and the opening 18A can specifically be the bottom end of its corresponding channel hole 13, or it can be formed by the corresponding channel hole 13 extending further into the substrate 11 in the direction toward the substrate 11 during the etching process of forming the gate slit 18.

[0085] In some specific embodiments, prior to step S16 above, the following may also be included:

[0086] Step S17: Remove the storage function layer 142 from the channel via 13 located on the gate gap region GLS.

[0087] Accordingly, step S13 can be specifically defined as: removing the stacked structure 12 and insulating layer 17 located on the gate line slot region GLS to form the gate line slot 18. Furthermore, a virtual channel structure 21 composed of insulating layer 17 will be correspondingly formed in the channel hole 13 located entirely or partially in the gate line slot region GLS when the orthogonal projection on the substrate 11 is fully or partially located.

[0088] In some embodiments, such as Figure 7 As shown, after step S16 and before step S13, the following may also be included:

[0089] Step S18: A corresponding channel plug is formed in the end of the channel hole 13 away from the substrate 11 on the block region K1 / K2, and the channel plug is connected to the channel layer 141 in the corresponding channel hole 13.

[0090] Specifically, step S18 above may include:

[0091] Step S181: Form a second photoresist layer on the stacked structure 12.

[0092] Step S182: Remove the second photoresist layer located on the block region K1 / K2 by exposure and development to obtain a patterned second photoresist layer, wherein the patterned second photoresist layer may include a second opening pattern, and the second opening pattern is used to expose the stacked structure 12 located on the block region K1 / K2.

[0093] Step S183: Remove the insulating layer 17 located at the end of the channel hole 13 away from the substrate 11 according to the patterned second photoresist layer, so as to form a third groove on the insulating layer 17 located between the opposite sidewalls of the channel layer 141.

[0094] Step S184: Form a channel plug in the third groove.

[0095] Accordingly, the cross-sectional structural diagram after step S13 is completed is shown below. Figure 16 As shown. Furthermore, the channel hole 13 corresponding to the channel plug 19 can specifically be a channel hole 13 whose orthogonal projection on the substrate 11 is entirely located in the block region K1 / K2.

[0096] Specifically, the channel plug 19 can be made of the same material as the channel layer 141 of the channel structure 14, such as polysilicon. Furthermore, in some embodiments, the channel plug 19 can specifically serve as the drain of the channel structure 14. In a specific implementation, polysilicon material can be deposited in the third groove, and the polysilicon material located outside the third groove can be removed by chemical mechanical polishing to obtain the channel plug 19.

[0097] In some embodiments, prior to step S13 described above, the following may also be included:

[0098] Step S19: Remove part of the stacked structure on the stepped area to form a stepped structure.

[0099] Specifically, the aforementioned block regions K1 / K2 may specifically include a connected core region and a step region. For example, the aforementioned first block region K1 may include a core region and a step region connected on the second horizontal direction X. Furthermore, in specific implementations, the aforementioned step structure can be formed by performing multiple "trim-etch" cycles on the partially stacked structure 12 on the step region.

[0100] In the above embodiments, after step S13, the following may also be included:

[0101] Step S20: Form a grid gap structure in the grid gap.

[0102] The top view of the structure after step S20 is shown in the figure below. Figure 17 As shown, the cross-sectional structure diagram after step S20 is as follows: Figure 18 As shown, and, Figure 18 Specifically along Figure 18 A schematic diagram of the cross-sectional structure taken by line O-O' in the diagram.

[0103] Specifically, the gate gap structure 20 can be formed by filling the gate gap 18 with an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials with high dielectric constants). In some alternative embodiments, the gate gap structure 20 with a common source electrode can also be obtained by filling the gate gap 18 with a spacer layer (e.g., an oxide layer) as an insulating layer and a conductive material (e.g., titanium or titanium nitride, polycrystalline silicon, and / or tungsten metal) as a common source electrode.

[0104] Unlike related technologies, the fabrication method of the three-dimensional memory in this embodiment forms a stacked structure on a substrate, the substrate including multiple block regions and gate line slot regions located between adjacent block regions. Then, multiple channel holes are formed on the block regions and gate line slot regions and penetrating the stacked structure. Subsequently, gate line slits are formed on the gate line slot regions to separate the stacked structures on adjacent block regions. In this way, during the etching process of forming channel holes on the block regions, the problem of poor channel hole morphology consistency caused by uneven stress distribution of the stacked structure on the block regions can be avoided. This increases the process window for subsequent processes and helps to improve the uniformity of electrical parameters of memory cells in the three-dimensional memory.

[0105] The three-dimensional memory fabricated according to the above method embodiments of the present invention is as follows: Figure 17 and Figure 18 As shown, the three-dimensional memory may include: a substrate 11, the substrate 11 including a plurality of block regions K1 / K2 and a gate line gap region GLS located between adjacent block regions (e.g., the first block region K1 and the second block region K2); a stacked structure 12 located on the substrate 11; a gate line slit 18 located on the gate line gap region GLS, the gate line slit 18 being used to separate the stacked structure 12 on adjacent block regions K1 / K2; and a plurality of channel structures 14 and a plurality of virtual channel structures 21 located on the block regions K1 / K2 and penetrating the stacked structure 12, the virtual channel structures 21 being connected to the gate line slit 18, and the channel structures 14 not being connected to the gate line slit 18.

[0106] Specifically, the aforementioned channel structure 14 may include a first dielectric pillar (i.e., an insulating layer 17 located within a channel via 13 whose orthogonal projection on the substrate 11 is entirely within the block region K1 / K2 in the above method embodiment), a channel layer 141 surrounding the first dielectric pillar, and a first storage functional layer surrounding the channel layer 141 (i.e., a storage functional layer 142 located within a channel via 13 whose orthogonal projection on the substrate 11 is entirely within the block region K1 / K2 in the above method embodiment). The aforementioned virtual channel structure 21 may include a second dielectric pillar (i.e., an insulating layer 17 located within a channel via 13 whose orthogonal projection on the substrate 11 is entirely or partially within the gate gap region GLS in the above method embodiment). The first and second dielectric pillars may be formed using the same process step.

[0107] In one specific embodiment, such as Figure 17 As shown, the virtual channel structure 21 may further include a second storage function layer surrounding the second dielectric pillar (that is, the storage function layer 142 located within the channel hole 13 in the gate gap region GLS that is projected orthogonally onto the substrate 11, either completely or partially), and the first storage function layer and the second storage function layer may be formed by the same process step.

[0108] In some embodiments, the bottom surface of the gate slit 18 may partially protrude into the substrate 11 in the direction of the substrate 11 to form a plurality of openings 18A on the substrate 11.

[0109] In some embodiments, the three-dimensional memory described above may further include a gate gap structure 20 located in the gate gap 18.

[0110] In some embodiments, the three-dimensional memory may further include a channel plug 19 located at one end of the channel structure 14 away from the substrate 11, the channel plug 19 being connected to the channel layer 141 in the corresponding channel structure 14.

[0111] It should be noted that the various structures of the three-dimensional memory in this embodiment can refer to the specific implementation methods described in the above method embodiments, so they will not be repeated here.

[0112] Unlike related technologies, the three-dimensional memory provided in this embodiment can avoid the problem of poor consistency of the morphology of the channel holes due to the uneven stress distribution of the stacked structure on the block area during the etching process of forming channel holes on the block area. This increases the process window for subsequent processes and helps to improve the uniformity of electrical parameters of the memory cells in the three-dimensional memory.

[0113] Accordingly, such as Figure 19As shown, this embodiment of the invention also provides a storage system 40, which includes a controller 41 and a three-dimensional memory 42. The controller 41 is coupled to the three-dimensional memory 42 and is used to control the three-dimensional memory 42 to store data.

[0114] The three-dimensional memory 42 may be the same as the three-dimensional memory described in any of the embodiments above, and therefore will not be repeated here. The controller 41 controls the three-dimensional memory 42 via channel CH, and the three-dimensional memory 42 can perform operations based on the control of the controller 41 in response to requests from the host 50. The three-dimensional memory 42 receives commands CMD and addresses ADDR from the controller 41 via channel CH and accesses the region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 42 can perform internal operations corresponding to commands on the region selected by the address.

[0115] In some implementations, the memory system 40 may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0116] Specifically, the aforementioned storage system 40 can be used in terminal products such as computers, televisions, set-top boxes, and in-vehicle systems.

[0117] Unlike related technologies, the storage system provided in this embodiment can avoid the problem of poor morphological consistency of the channel holes caused by uneven stress distribution of the stacked structure on the block area during the etching process of forming channel holes on the block area. This increases the process window for subsequent processes and helps to improve the uniformity of electrical parameters of storage cells in three-dimensional memory.

[0118] Accordingly, such as Figure 20 As shown, this embodiment of the invention also provides an electronic device 60, which includes the storage system 61 provided in this embodiment of the invention. Specifically, the electronic device 60 can be any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle equipment, wearable device, or power bank.

[0119] An electronic device provided in this embodiment of the invention has the same beneficial effects as the storage system described above due to the inclusion of the storage system provided in this embodiment of the invention.

[0120] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A stacked structure is formed on a substrate, the substrate including multiple block regions and gate line gap regions located between adjacent block regions; Multiple channel holes are formed on the block region and the grid line gap region and through the stacked structure; A channel structure is formed in the channel hole located in the block region, and a virtual channel structure is formed in the channel hole located in the gate wire gap region; and Remove the stacked structure and the virtual channel structure located in the grid line slot area to form a grid line slot in the grid line slot area, the grid line slot being used to separate the stacked structure on adjacent block areas.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Before forming the grid slits in the grid slit region, the method further includes: A storage function layer and a channel layer are sequentially formed on the inner wall of the channel hole to form a channel structure; Remove the trench layer from the trench holes located in the grid line gap region; An insulating layer is formed to fill the remaining space in the channel hole.

3. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, The process of forming grid slits in the grid slit region specifically includes: Remove the stacked structure, the insulating layer, and the storage function layer located on the gate line slot area to form a gate line slot.

4. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, Before forming the grid slits in the grid slit region, the method further includes: A corresponding channel plug is formed in the block region at the end of the channel hole away from the substrate, and the channel plug is connected to the channel layer in the corresponding channel hole.

5. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, The block region includes a connected core region and a stepped region, and before the grid line slots are formed on the grid line slot region, it also includes: Remove a portion of the stacked structure on the stepped area to form a stepped structure.

6. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The plurality of channel holes extend into the substrate in a direction perpendicular to the substrate.

7. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, After forming the grid wire slots in the grid wire slot region, the method further includes: A grid gap structure is formed in the grid slit.

8. A three-dimensional memory, characterized in that, include: A substrate, the substrate comprising a plurality of block regions and gate line slot regions located between adjacent block regions; Stacked structures located on the substrate; A grid line slit located on the grid line gap region, the grid line slit being used to separate the stacked structures on adjacent block regions; Multiple channel structures and multiple virtual channel structures are located on the block region and penetrate the stacked structure. The virtual channel structures are located between the gate line slots and the channel structures and are connected to the gate line slots, while the channel structures are not connected to the gate line slots.

9. The three-dimensional memory according to claim 8, characterized in that, The bottom surface of the grid slit partially protrudes into the substrate in a direction toward the substrate to form a plurality of openings on the substrate.

10. The three-dimensional memory according to claim 8, characterized in that, The three-dimensional memory also includes a gate gap structure located in the gate slit.

11. The three-dimensional memory according to claim 8, characterized in that, The channel structure includes a first dielectric pillar, a channel layer surrounding the first dielectric pillar, and a first storage function layer surrounding the channel layer. The virtual channel structure includes a second dielectric pillar.

12. The three-dimensional memory according to claim 11, characterized in that, The virtual channel structure also includes a second storage function layer surrounding the second media pillar.

13. The three-dimensional memory according to claim 11, characterized in that, The three-dimensional memory also includes: A channel plug located at the end of the channel structure away from the substrate, the channel plug being connected to the channel layer in the corresponding channel structure.

14. A storage system, characterized in that, The storage system includes a controller and a three-dimensional memory as described in any one of claims 8 to 13, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

15. An electronic device, characterized in that, Includes the storage system described in claim 14.

16. The electronic device according to claim 15, characterized in that, The electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted equipment, wearable device, and power bank.

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