Integrated circuit self-repair method and integrated circuit thereof
By designing a self-repair method inside the integrated circuit, using the logic state correction of the buffer and protection circuit, the damage caused by sudden power supply events is solved, and the optimal state maintenance of the power supply and more complete power protection are achieved.
Patent Information
- Application Number
- CN202010729882.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-07-27
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2040-07-27
AI Technical Summary
The prior art cannot provide power protection and repair functions within the integrated circuit, resulting in sudden power supply events that may lead to damage to the integrated circuit.
Design an integrated circuit self-repair method, which uses the main buffer and the protection circuit to self-repair through the predetermined logical state of at least three buffers, ensuring that the power supply is in the best state, including the setting circuit, the main buffer, the protection circuit and the receiving The control circuit repairs logic state errors caused by emergencies through the transmission and correction of predetermined logic states.
It realizes the power protection and repair functions inside the integrated circuit to avoid damage or cessation of operation caused by power supply emergencies, enhances the stability of power management, and can be combined with external power protection technology to achieve a more complete power protection effect.
Smart Images
Figure CN113991605B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a power protection technology for an integrated circuit (IC), and more particularly to an integrated circuit self-repair method and an integrated circuit thereof. Background Art
[0002] For an integrated circuit to operate normally, a stable power source is one of the necessary conditions. If there is a sudden power current that is too large or too small, or a voltage that is too high or too low, the minor impact is that the power flashes and then returns to normal, but in severe cases, the integrated circuit may be directly damaged and burned, which has a huge impact. In existing power management technology, power protection circuits are usually designed outside the integrated circuit, such as pulse width modulation circuits, linear regulators, etc., to provide the integrated circuit with a complete power protection function. Therefore, for the entire system, the existing circuit protection design provides protection from the outside of the integrated circuit, and cannot directly provide protection and repair of the power setting from the inside of the integrated circuit. Summary of the invention
[0003] In view of this, the present application proposes an integrated circuit self-repair method, comprising: a main register transmits a predetermined logic state to at least three registers and sets the state to the predetermined logic state. According to the predetermined logic state in the at least three registers, the predetermined logic state is output to drive a controlled circuit to perform a function. When an input power emergency occurs and a relatively small number of settings of at least three registers are changed to an opposite logic state, the predetermined logic state is output according to the predetermined logic state of the remaining registers, and the predetermined logic state is fed back to the register that has changed to the opposite logic state, so as to correct the opposite logic state to the predetermined logic state.
[0004] The present application further proposes an integrated circuit, comprising a setting circuit, at least one main buffer, at least one protection circuit and a controlled circuit. The setting circuit generates a transmission protocol with at least one predetermined logic state to the main buffer, and the main buffer is electrically connected to the setting circuit to receive the predetermined logic state according to the transmission protocol; the protection circuit is electrically connected to the main buffer and the setting circuit, and the protection circuit comprises at least three buffers, and the main buffer sets the state of at least three buffers to a predetermined logic state, so that the protection circuit outputs the predetermined logic state; the controlled circuit performs a function according to the predetermined logic state. Among them, when an emergency occurs in an input power supply and causes a relatively small number of settings of at least three buffers to change to an opposite logic state, the protection circuit outputs the predetermined logic state according to the predetermined logic state of the remaining buffers, and transmits the predetermined logic state back to the buffer that has changed to the opposite logic state, so as to correct the opposite logic state to the predetermined logic state.
[0005] According to some embodiments, when an emergency event occurs in the input power supply, the predetermined logic state is output according to the predetermined logic state of the majority of the remaining buffers.
[0006] According to some embodiments, when the predetermined logic state is 1, the opposite logic state is 0.
[0007] According to some embodiments, the main buffer transmits a multi-bit logic state to an encoding unit, and the encoding unit then converts the multi-bit logic state into multiple predetermined logic states and transmits them to the corresponding transmission buffer, so that the buffers each output the predetermined logic state to a decoding unit, and the decoding unit combines the predetermined logic states into multi-bit logic states to drive the controlled circuit to perform the function.
[0008] According to some embodiments, the decoding unit may further transmit the multi-bit logic state to the main register, and then transmit the multi-bit logic state to the controlled circuit through the main register.
[0009] According to some embodiments, when an emergency occurs in the input power supply, when the decoding unit receives the predetermined logic state and the opposite logic state, the decoding unit performs self-correction according to the predetermined logic state of the remaining buffer and the encoding rules of the multi-bit logic state to output the correct multi-bit logic state, and transmits the correct predetermined logic state back to the buffer that has become the opposite logic state to correct the opposite logic state to the predetermined logic state.
[0010] According to some embodiments, when the multi-bit logic state is a double-bit logic state, a double-one-hot encoding rule is used, where 0 is encoded as 0011 and 1 is encoded as 1100.
[0011] According to some embodiments, the multi-bit logic states adopt a multi-one hot encoding rule, and four sets of encodings of the multi-bit logic states include 00_00_00_11, 00_00_11_00, 00_11_00_00, and 11_00_00_00.
[0012] In summary, the present application directly designs the circuit inside the integrated circuit, so that the integrated circuit has the function of power protection and repair, maintains the power supply of the integrated circuit itself in the best state, and avoids the integrated circuit from stopping operation or being damaged due to power emergencies. Furthermore, the present application can be combined with the existing external power protection technology to achieve a more complete power protection function, so that the integrated circuit maintains the best performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 FIG. 4 is a block diagram of an integrated circuit according to an embodiment of the present application.
[0014] Figure 24 is a flow chart of an integrated circuit self-repair method according to an embodiment of the present application.
[0015] Figure 3 FIG. 4 is a block diagram of an integrated circuit according to another embodiment of the present application.
[0016] Figure 4 FIG. 4 is a block diagram of an integrated circuit according to another embodiment of the present application.
[0017] Figure 5 FIG. 4 is a block diagram of an integrated circuit according to another embodiment of the present application.
[0018] Figure 6 FIG. 4 is a block diagram of an integrated circuit according to another embodiment of the present application.
[0019] Figure 7 FIG. 4 is a block diagram of an integrated circuit according to another embodiment of the present application.
[0020] Figure 8 FIG. 4 is a block diagram of an integrated circuit according to another embodiment of the present application.
[0021]
Explanation of symbols
[0022] 10: Integrated Circuits
[0023] 12: Setting the circuit
[0024] 14,14': Main Buffer
[0025] 16,16': Protection circuit
[0026] 18: Controlled circuit
[0027] 20,20': Buffer
[0028] 201,201': First buffer
[0029] 202,202': Second buffer
[0030] 203,203': Third Buffer
[0031] 204,204': Fourth buffer
[0032] 205: Fifth Buffer
[0033] 206: Sixth Buffer
[0034] 207: 7th Buffer
[0035] 208: 8th Buffer
[0036] 22,22': Judgment circuit
[0037] 24,24': coding unit
[0038] 26,26': decoding unit
[0039] 28: First main buffer
[0040] 30: Second main buffer
[0041] S10~S14: Steps DETAILED DESCRIPTION
[0042] The integrated circuit self-repair method provided in the present application is used inside an integrated circuit, and by utilizing the technology of the present application, the integrated circuit can achieve the purpose of self-protection and self-repair, so as to maintain the power supply of the integrated circuit itself in the best state.
[0043] Figure 1 FIG. 1 is a block diagram of an integrated circuit according to an embodiment of the present application. Figure 1 As shown, an integrated circuit 10 includes a setting circuit 12, a main register 14, a protection circuit 16 and a controlled circuit 18. The setting circuit 12 is electrically connected to the main register 14 and the protection circuit 16, and the protection circuit 16 is electrically connected to the controlled circuit 18. In one embodiment, the protection circuit 16 further includes at least three registers 20 (hereinafter referred to as a first register 201, a second register 202 and a third register 203) and a judgment circuit 22. The first register 201, the second register 202 and the third register 203 are electrically connected to the main register 14 and the judgment circuit 22, and the judgment circuit 22 is electrically connected to the controlled circuit 18.
[0044] Figure 2 FIG. 1 is a flow chart of an integrated circuit self-repair method according to an embodiment of the present application. Please also refer to FIG. Figure 1 and Figure 2As shown, a self-repair method is performed in the integrated circuit 10, and the integrated circuit self-repair includes steps S10 to S14. As shown in step S10, the main buffer 14 transmits a predetermined logic state to at least three buffers 20, the first buffer 201, the second buffer 202 and the third buffer 203, and sets their states to the predetermined logic state. As shown in step S12, according to the predetermined logic states in the first buffer 201, the second buffer 202 and the third buffer 203, the judgment circuit 22 outputs the predetermined logic state to the controlled circuit 18 to drive the controlled circuit 18 to perform a function. As shown in step S14, when an emergency occurs in an input power supply and a relatively small number of settings among the first register 201, the second register 202 and the third register 203 are changed to an opposite logic state, for example, the setting of the second register 202 is changed to an opposite logic state, the judgment circuit 22 still outputs the predetermined logic state to the controlled circuit 18 according to the predetermined logic states of the remaining first register 201 and the third register 203, and returns the correct predetermined logic state to the second register 202 that has changed to the opposite logic state, so as to correct the opposite logic state of the second register 202 to the predetermined logic state. Although the second register 202 has lost its setting due to the emergency, the correct logic state can still be judged by the majority of the first register 201 and the third register 203, and the erroneous second register 202 can be repaired to return to the correct predetermined logic state.
[0045] In one embodiment, the predetermined logic state is generated by the setting circuit 12, and the setting circuit 12 transmits the transmission protocol with the predetermined logic state to the main buffer 14, so that the main buffer 14 can set the first buffer 201, the second buffer 202 and the third buffer 203 to the predetermined logic state respectively based on the transmission protocol.
[0046] In one embodiment, when the predetermined logic state is 1, the opposite logic state is 0. Figure 1As shown, at the beginning, the setting circuit 12 transmits the predetermined logic state to 1 to the main buffer 14, and the main buffer 14 then sets the logic states of the first buffer 201, the second buffer 202 and the third buffer 203 to 1. At this time, the logic states of the first buffer 201, the second buffer 202 and the third buffer 203 are all 1, and the judgment circuit 22 judges that the number of 1 (predetermined logic state) is the largest, so it outputs 1 to the controlled circuit 18, so that the controlled circuit 18 performs a specific function. When an unexpected event occurs in the input power (for example, the power flashes), the predetermined logic state of the second buffer 202 changes from 1 to the opposite logic state 0. However, because the first buffer 201 and the third buffer 203 that maintain 1 (the predetermined logic state) are still in the majority, the judgment circuit 22 still judges that the number of 1s is the largest and outputs 1 to the controlled circuit 18, so that the controlled circuit 18 can continue to perform its functions. At the same time, the judgment circuit 22 will transmit 1 back to the first buffer 201, the second buffer 202 and the third buffer 203, so that the erroneous second buffer 202 is corrected back to the correct 1 (the predetermined logic state).
[0047] More than two sets of main buffers 14 and protection circuits 16 may be designed in the integrated circuit 10 to control the controlled circuit 18. Here, two sets are taken as an example, but the present invention is not limited thereto. Figure 3As shown, the integrated circuit 10 includes a setting circuit 12, two main registers 14, 14', two protection circuits 16, 16' and a controlled circuit 18. The setting circuit 12 is electrically connected to the two main registers 14, 14' and the two protection circuits 16, 16'. The main register 14 is electrically connected to the protection circuit 16, the main register 14' is electrically connected to the protection circuit 16', and the two protection circuits 16, 16' are respectively electrically connected to the controlled circuit 18. The protection circuit 16 includes at least three registers 20 (a first register 201, a second register 202, and a third register 203) and a judgment circuit 22. The first register 201, the second register 202, and the third register 203 are electrically connected to the main register 14 and the judgment circuit 22, and the judgment circuit 22 is electrically connected to the controlled circuit 18. Similarly, the protection circuit 16' also includes at least three registers 20' (a first register 201', a second register 202', and a third register 203') and a judgment circuit 22'. The first register 201', the second register 202', and the third register 203' are electrically connected to the main register 14' and the judgment circuit 22', and the judgment circuit 22' is electrically connected to the controlled circuit 18. In this integrated circuit 10, the setting circuit 12 transmits a transmission protocol with a predetermined logic state to the main registers 14 and 14', so that the main registers 14 and 14' can respectively set the first registers 201 and 201', the second registers 202 and 202', and the third registers 203 and 203' to the predetermined logic state based on the transmission protocol. The judgment circuits 22 and 22' respectively output the majority of the predetermined logic states in their respective registers 20 and 20' to the controlled circuit 18 to drive the controlled circuit 18 to perform a function. When an emergency occurs in the input power supply and the settings of a relatively small number of the second registers 202 among the first registers 201, 201', the second registers 202, 202' and the third registers 203, 203' are changed to an opposite logic state, the judgment circuits 22, 22' still output the predetermined logic state to the controlled circuit 18 according to the predetermined logic states of the remaining first registers 201, 201', the second registers 202' and the third registers 203, 203', respectively, and return the correct predetermined logic state to the second register 202' that has changed to the opposite logic state, so as to correct the opposite logic state of the second register 202' to the predetermined logic state. In this integrated circuit 10, although there are two sets of main registers 14, 14' and protection circuits 16, 16', their connection relationship and operation are the same as those of the above-mentioned embodiment, and the difference lies in the different number, so as to provide more bits to achieve the effect of protecting the settings of the integrated circuit 10.
[0048] In one embodiment, see Figure 4As shown, the integrated circuit 10 includes a setting circuit 12, a main buffer 14, a protection circuit 16 and a controlled circuit 18. The setting circuit 12 is electrically connected to the main buffer 14 and the protection circuit 16, and the protection circuit 16 is electrically connected to the controlled circuit 18. The protection circuit 16 includes four buffers 20 (hereinafter referred to as the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204), an encoding unit 24 and a decoding unit 26. The encoding unit 24 is electrically connected to the main buffer 14 and the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204, and the decoding unit 26 is electrically connected to the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204 and the controlled circuit 18. The setting circuit 12 generates a transmission protocol with a multi-bit logic state (including multiple predetermined logic states) to the main buffer 14, and the main buffer 14 then transmits the multi-bit logic state to the encoding unit 24. The encoding unit 24 converts the multi-bit logic state into multiple predetermined logic states and transmits them to the corresponding first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204 and sets their states to the predetermined logic states. The first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204 respectively output their respective predetermined logic states to the decoding unit 26, so that the decoding unit 26 combines these predetermined logic states into a multi-bit logic state and transmits it to the controlled circuit 18 to drive the controlled circuit 18 to perform its function. When an emergency occurs in the input power supply, a relatively small number of settings among the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204 change to an opposite logic state, for example, the setting of the second buffer 202 changes to an opposite logic state, and the decoding unit 26 performs self-correction according to the predetermined logic states of the remaining first buffer 201, the third buffer 203 and the fourth buffer 204 and the encoding rule of the multi-bit logic state to output the correct multi-bit logic state, and transmits the correct predetermined logic state back to the second buffer 202 that has changed to the opposite logic state, so as to correct its opposite logic state to the correct predetermined logic state.
[0049] In one embodiment, when the multi-bit logic state is a double-bit logic state, the present application may adopt a double-one-hot encoding rule, so there are 4 bits, 0 is encoded as 4'b0011, and 1 is encoded as 4'b1100. Figure 4As shown, when the multi-bit logic state is 4'b0011, the predetermined logic states of the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204 are 0, 0, 1 and 1 respectively. If an unexpected event occurs, causing a certain 0 (predetermined logic state) to become 1 (opposite logic state), such as 4'b1011 or 4'b0111, because bit [1:0] are all 1, and according to the encoding rule of the multi-bit logic state, the decoding unit 26 can obtain the correct value of 4'b0011, and can output the correct multi-bit logic state to the controlled circuit 18 and return the correct predetermined logic state to the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204, so as to correct the wrong 1 (opposite logic state) to 0 (predetermined logic state). If an unexpected event occurs, causing a 1 (predetermined logic state) to become a 0 (opposite logic state), such as 4'b0010 or 4'b0001, because there is only one 1 in bit [1:0] and according to the encoding rules of the multi-bit logic state, the decoding unit 26 can obtain the correct value of 4'b0011, and can output the correct multi-bit logic state to the controlled circuit 18 and return the correct predetermined logic state to the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204, so as to correct the erroneous 0 (opposite logic state) to 1 (predetermined logic state).
[0050] Similarly, when the multi-bit logic state is 4'b1100, the predetermined logic states of the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204 are 1, 1, 0 and 0 respectively. If an unexpected event occurs, causing a certain 0 (predetermined logic state) to become 1 (opposite logic state), such as 4'b1110 or 4'b1101, because bit [3:2] are all 1, and according to the encoding rule of the multi-bit logic state, the decoding unit 26 can obtain the correct value of 4'b1100, and can output the correct multi-bit logic state to the controlled circuit 18 and return the correct predetermined logic state to the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204, so as to correct 1 (opposite logic state) to 0 (predetermined logic state). If an unexpected event occurs, causing a 1 (predetermined logic state) to become a 0 (opposite logic state), such as 4'b1000 or 4'b0100, because there is only one 1 in bit [3:2] and according to the encoding rules of the multi-bit logic state, the decoding unit 26 can obtain the correct value of 4'b1100, and can output the correct multi-bit logic state to the controlled circuit 18 and return the correct predetermined logic state to the first buffer 201, the second buffer 202, the third buffer 203 and the fourth buffer 204, so as to correct the 0 (opposite logic state) to 1 (predetermined logic state).
[0051] In another embodiment, the decoding unit 26 is not directly electrically connected to the controlled circuit 18 but is electrically connected to the main buffer 14. Figure 5 As shown, since the decoding unit 26 is electrically connected to the main buffer 14, the decoding unit 26 first transmits the multi-bit logic state to the main buffer 14, and then transmits it to the controlled circuit 18 through the main buffer 14. Except for the different connection relationship of the decoding unit 26, the other detailed connection relationships and operations are the same as Figure 4 The embodiments shown are the same, so reference may be made to the previous description and no further description will be given here.
[0052] In one embodiment, Figure 4 The integrated circuit 10 shown can also be designed to have more than two sets of main buffers 14 and protection circuits 16 to control the controlled circuit 18. Here, two sets are taken as an example, but the present invention is not limited thereto. Figure 6 As shown, the integrated circuit 10 includes, in addition to the original setting circuit 12, the main buffer 14, the protection circuit 16 and the controlled circuit 18, a main buffer 14' and a protection circuit 16'. The main buffer 14' is electrically connected to the setting circuit 12 and the protection circuit 16'. The protection circuit 16' is electrically connected to the controlled circuit 18. The protection circuit 16' includes four buffers 20', an encoding unit 24' and a decoding unit 26'. The four buffers 20' include a first buffer 201', a second buffer 202', a third buffer 203', and a fourth buffer 204'. The encoding unit 24' is electrically connected to the main buffer 14' and the first buffer 201', the second buffer 202', the third buffer 203' and the fourth buffer 204'. The decoding unit 26' is electrically connected to the first buffer 201', the second buffer 202', the third buffer 203', the fourth buffer 204' and the controlled circuit 18. Therefore, the integrated circuit 10 can be protected by the two sets of main registers 14, 14' and the protection circuits 16, 16' and can be self-repaired when an emergency occurs in the input power supply.
[0053] In one embodiment, Figure 5 The integrated circuit 10 shown can also be designed to have more than two sets of main buffers 14 and protection circuits 16 to control the controlled circuit 18. Here, two sets are taken as an example, but the present invention is not limited thereto. Figure 7As shown, the integrated circuit 10 includes a setting circuit 12, two main buffers 14, 14', two protection circuits 16, 16' and a controlled circuit 18. In addition to the original setting circuit 12, the main buffer 14, the protection circuit 16 and the controlled circuit 18, the integrated circuit 10 further includes a main buffer 14' and a protection circuit 16'. The main buffer 14' is electrically connected to the setting circuit 12, the protection circuit 16' and the controlled circuit 18, and the protection circuit 16' includes four buffers 20', a coding unit 24' and The decoding unit 26', the four buffers 20' include a first buffer 201', a second buffer 202', a third buffer 203', and a fourth buffer 204', the encoding unit 24' is electrically connected to the main buffer 14' and the first buffer 201', the second buffer 202', the third buffer 203', and the fourth buffer 204', and the decoding unit 26' is electrically connected to the first buffer 201', the second buffer 202', the third buffer 203', and the fourth buffer 204' and the main buffer 14'. Since the decoding units 26 and 26' are electrically connected to the main buffers 14 and 14' respectively, the decoding units 26 and 26' can transmit the multi-bit logic state to the main buffers 14 and 14', and then transmit it to the controlled circuit 18 through the main buffers 14 and 14'. Therefore, the integrated circuit 10 can be protected by the two sets of main registers 14, 14' and the protection circuits 16, 16' and can be self-repaired when an emergency occurs in the input power supply.
[0054] In one embodiment, see Figure 8As shown, the integrated circuit 10 includes a setting circuit 12, a first main buffer 28, a second main buffer 30, a protection circuit 16 and a controlled circuit 18. The first main buffer 28 and the second main buffer 30 are electrically connected to the setting circuit 12, the protection circuit 16 and the controlled circuit 18. The protection circuit 16 includes eight buffers 20 (hereinafter referred to as the first buffer 201, the second buffer 202, the third buffer 203, the fourth buffer 204, the fifth buffer 205, the sixth buffer 206, the seventh buffer 207 and the eighth buffer 208), an encoding unit 24 and a decoding unit 26. The encoding unit 24 is electrically connected to the first main buffer 28 and the second main buffer 30 and the first buffer 201 to the eighth buffer 208, and the decoding unit 26 is electrically connected to the first buffer 201 to the eighth buffer 208 and the first main buffer 28 and the second main buffer 30. The setting circuit 12 generates a transmission protocol with a multi-bit logic state (including multiple predetermined logic states) to the first main buffer 28 and the second main buffer 30, and then transmits the multi-bit logic state to the encoding unit 24. The encoding unit 24 encodes the multi-bit logic state into multiple predetermined logic states and transmits them to the corresponding first buffer 201 to the eighth buffer 208 and sets their states to the predetermined logic states. The first buffer 201 to the eighth buffer 208 respectively output their respective predetermined logic states to the decoding unit 26, so that the decoding unit 26 combines these predetermined logic states into multi-bit logic states and transmits them to the controlled circuit 18 via the first main buffer 28 and the second main buffer 30 to drive the controlled circuit 18 to perform its function. When an emergency occurs in the input power supply, a relatively small number of settings in the first to eighth registers 201 to 208 are changed to an opposite logic state, for example, the setting of the eighth register 208 is changed to an opposite logic state, and the decoding unit 26 performs self-correction according to the predetermined logic states of the remaining first to seventh registers 201 to 207 and the encoding rules of the multi-bit logic state to output the correct multi-bit logic state, and transmits the correct predetermined logic state back to the eighth register 208 that has changed to the opposite logic state, so as to correct its opposite logic state to the correct predetermined logic state.
[0055] In one embodiment, the multi-bit logic states are encoded using a multi-one hot encoding rule, and the first main register 28 and the second main register 30 are combined into four sets of encodings of the multi-bit logic states, namely, {reg_b, reg_a}=2'b00, encoded as 8'b00_00_00_11; {reg_b, reg_a}=2'b01, encoded as 8'b 00_00_11_00; {reg_b, reg_a}=2'b10, encoded as 8'b 00_11_00_00; and {reg_b, reg_a}=2'b11, encoded as 8'b 11_00_00_00. Taking 8'b00_00_00_11 as an example, when an emergency occurs, a certain 0 (predetermined logic state) becomes 1 (opposite logic state), such as 8'b00_10_00_11. Since bit [1:0] are all 1, and according to the encoding rule of the multi-bit logic state, the decoding unit 26 can obtain the correct value 8'b00_00_00_11. The decoding unit 26 can output the correct multi-bit logic state 8'b00_00_00_11 to the controlled circuit 18 through the first main buffer 28 and the second main buffer 30, and transmit the correct predetermined logic state back to the first buffer 201 to the eighth buffer 208, so as to correct the erroneous 1 (opposite logic state) in the eighth buffer 208 to the correct 0 (predetermined logic state). By analogy, the function of the protection circuit can be utilized to achieve the purpose of self-protection and self-repair.
[0056] Therefore, the present application designs the circuit directly inside the integrated circuit, so that the integrated circuit has the function of power protection and repair, maintains the power supply of the integrated circuit itself in the best state, and avoids the integrated circuit from stopping operation or being damaged due to power emergencies. Furthermore, the present application can also cooperate with the existing external power protection technology to achieve a more complete power protection function, so that the integrated circuit maintains the best performance.
[0057] The embodiments described above are only for illustrating the technical ideas and features of the present application. The purpose is to enable those familiar with the technology to understand the content of the present application and implement it accordingly. They should not be used to limit the patent scope of the present application. That is, all equivalent changes or modifications made according to the spirit disclosed in the present application should still be included in the patent scope of the present application.
Claims
1. A self-repair method for an integrated circuit, characterized in that: Include: A main register transmits a predetermined logic state to at least three registers and sets the states of the at least three registers to the predetermined logic state; Outputting the predetermined logic state according to the predetermined logic state in the at least three registers to drive a controlled circuit to perform a function; and When an unexpected event occurs in an input power source and a relatively small number of settings of the at least three registers are changed to an opposite logic state, the predetermined logic state is output according to the predetermined logic state of the remaining registers, and the predetermined logic state is fed back to the relatively small number of registers that have changed to the opposite logic state, so as to correct the opposite logic state to the predetermined logic state. The main buffer transmits a multi-bit logic state to an encoding unit, and the encoding unit then converts the multi-bit logic state into a plurality of predetermined logic states and transmits them to the corresponding buffers, so that the buffers output the predetermined logic states to a decoding unit to combine the predetermined logic states into the multi-bit logic state to drive the controlled circuit to perform the function.
2. The integrated circuit self-repair method according to claim 1, characterized in that: The predetermined logic state is generated by a setting circuit. The setting circuit transmits a transmission protocol having the predetermined logic state to the main buffer, so that the at least three buffers are set to the predetermined logic state.
3. The integrated circuit self-repair method according to claim 1, characterized in that: When an emergency event occurs in the input power supply, the predetermined logic state is output according to the predetermined logic state of the majority of the remaining registers.
4. The integrated circuit self-repair method according to claim 3, characterized in that: When the predetermined logic state is 1, the opposite logic state is 0.
5. The integrated circuit self-repair method according to claim 1, characterized in that: The decoding unit also transmits the multi-bit logic state to the main buffer, and then transmits it to the controlled circuit.
6. The integrated circuit self-repair method according to claim 1, characterized in that: When an emergency occurs in the input power supply, when the decoding unit receives the remaining majority of the predetermined logic states and the opposite logic state, the decoding unit performs self-correction according to the coding rules of the predetermined logic states of the remaining buffers and the multi-bit logic states to output the correct multi-bit logic state, and transmits the correct predetermined logic state back to the buffer that has become the opposite logic state to correct the opposite logic state to the predetermined logic state.
7. The integrated circuit self-repair method according to claim 1, characterized in that: When the multi-bit logic state is a dual-bit logic state, a dual unique hot encoding rule is adopted, 0 is encoded as 0011, and 1 is encoded as 1100.
8. The integrated circuit self-repair method according to claim 1, characterized in that: The multi-bit logic state adopts a multi-hot encoding rule. The four sets of codes of the multi-bit logic state include 00_00_00_11, 00_00_11_00, 00_11_00_00 and 11_00_00_00.
9. An integrated circuit, characterized in that: Include: a setting circuit for generating a transmission protocol having at least one predetermined logic state; at least one main buffer electrically connected to the setting circuit for receiving the predetermined logic state according to the transmission protocol; At least one protection circuit is electrically connected to the main buffer and the setting circuit, the protection circuit includes at least three buffers, the main buffer sets the states of the at least three buffers to the predetermined logic state, and the protection circuit outputs the predetermined logic state; as well as a controlled circuit that performs a function according to the predetermined logic state; When an emergency occurs in an input power source and a relatively small number of settings of the at least three registers are changed to an opposite logic state, the protection circuit outputs the predetermined logic state according to the predetermined logic state of the remaining registers, and feeds back the predetermined logic state to the relatively small number of registers that have changed to the opposite logic state, so as to correct the opposite logic state to the predetermined logic state. The main buffer transmits a multi-bit logic state to an encoding unit, and the encoding unit then converts the multi-bit logic state into a plurality of predetermined logic states and transmits them to the corresponding buffers, so that the buffers output the predetermined logic states to a decoding unit to combine the predetermined logic states into the multi-bit logic state to drive the controlled circuit to perform the function.