A level conversion circuit, its layout structure, standard cell, and chip

Abstract

An embodiment of the present invention discloses a level conversion circuit, its layout structure, standard cell, and chip, which relate to the field of semiconductor technology and can improve the integration degree of the circuit. The circuit includes: a processing unit, one end of which is connected to the signal to be converted and the other end is connected to a conversion unit, and is used for performing logical inversion on the signal to be converted to obtain an inverted signal to be converted. The processing unit is powered by the power supply of the target voltage domain through a preset voltage follower device. Driven by the power supply of the target voltage domain, the voltage follower device applies a preset voltage of the source voltage domain to the processing unit; a conversion unit, which is respectively connected to the signal to be converted and the processing unit, and outputs a converted signal according to the signal to be converted and the inverted signal to be converted. Among them, the logical level of the signal to be converted belongs to the source voltage domain, and the logical level of the converted signal belongs to the target voltage domain. The conversion unit is powered by the power supply of the target voltage domain.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a level conversion circuit, a layout structure thereof, a standard cell, and a chip. Background Art

[0002] In digital circuits, binary numbers 1 or 0 can be represented by high or low levels, providing a basis for various operations. However, due to the complex and diverse application scenarios, digital circuits often include multiple circuit modules, and different circuit modules often correspond to different power supply voltages, that is, each circuit module has a different voltage domain. Due to the different voltage domains, the high-level potential and / or low-level potential corresponding to each circuit module are also different. For example, for a circuit module with a power supply voltage of 1.2V, 1.2V is the high level, while for a circuit module with a power supply voltage of 2V, 1.2V is considered the low level. If these two circuit modules are directly connected, logical errors may occur.

[0003] In order to enable signal transmission between circuit modules with different power supply voltages, a level conversion circuit can be provided between the circuit modules with different power supply voltages. The level conversion circuit can convert the signal of the input first voltage domain into the signal of the second voltage domain and output it, thus establishing a bridge between the first voltage domain and the second voltage domain.

[0004] However, in the semiconductor process implementation of the level conversion circuit, for a P-substrate circuit, the spacing between the N-well for carrying PMOS (P-type MOS) in the first voltage domain and the N-well for carrying PMOS in the second voltage domain needs to be greater than a specified threshold. Similarly, for an N-substrate circuit, the spacing between the P-well for carrying NMOS (N-type MOS) in the first voltage domain and the P-well for carrying NMOS in the second voltage domain also needs to be greater than a specified threshold. Therefore, in order to meet the minimum spacing requirement, the area of the level conversion circuit often increases, and the integration degree decreases accordingly. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a level conversion circuit, a layout structure thereof, a standard cell, and a chip, which can effectively reduce the area of the level conversion circuit and greatly improve the integration degree of the circuit.

[0006] In a first aspect, an embodiment of the present invention provides a level conversion circuit, including: a processing unit, with one end connected to a signal to be converted and the other end connected to a conversion unit, configured to perform logical inversion on the signal to be converted to obtain an inverted signal to be converted, wherein the processing unit is powered by a power supply in a target voltage domain through a preset voltage follower device, and the voltage follower device is configured to apply a preset voltage in a source voltage domain to the processing unit under the drive of the power supply in the target voltage domain; a conversion unit, connected to the signal to be converted and the processing unit respectively, configured to output a converted signal according to the signal to be converted and the inverted signal to be converted, wherein the logical level of the signal to be converted belongs to the source voltage domain, the logical level of the converted signal belongs to the target voltage domain, and the conversion unit is powered by the power supply in the target voltage domain.

[0007] Optionally, the processing unit includes an inverter, a first end of the inverter is connected to the signal to be converted, a second end of the inverter is connected to the conversion unit, a third end of the inverter is connected to the voltage follower device, and a fourth end of the inverter is grounded.

[0008] Optionally, a first end of the voltage follower device is connected to the preset voltage, a second end is connected to the power supply in the target voltage domain, and a third end is connected to the processing unit, wherein the voltage at the third end is less than or equal to the voltage at the first end.

[0009] Optionally, the voltage follower device includes a transistor.

[0010] Optionally, the level conversion circuit is disposed on a P-type substrate, and the voltage follower device includes an N-type transistor; or the level conversion circuit is disposed on an N-type substrate, and the voltage follower device includes a P-type transistor.

[0011] Optionally, a voltage stabilizing buffer device is further disposed between the preset voltage in the target voltage domain and the voltage follower device.

[0012] Second aspect, embodiments of the present invention further provide a layout structure of a level conversion circuit, including: a layout structure of a processing unit, a layout structure of a conversion unit, and a layout structure of a voltage follower device; the layout structure of the processing unit includes a first well pattern and a first circuit pattern, and at least a part of the first circuit pattern is within the coverage of the first well pattern; the layout structure of the conversion unit includes a second well pattern and a second circuit pattern, and at least a part of the second circuit pattern is within the coverage of the second well pattern; the spacing distance between the first well pattern and the second well pattern is less than a preset distance threshold; the first well pattern and the second well pattern are connected to the power supply pattern of the target voltage domain through a first wiring pattern; the first circuit pattern is connected to the layout structure of the voltage follower device, and the layout structure of the voltage follower device is connected to the power supply pattern of the target voltage domain through a second wiring pattern; the second circuit pattern is connected to the power supply pattern of the target voltage domain through a third wiring pattern; the layout structure of the voltage follower device is further connected to a fourth wiring pattern, and the fourth wiring pattern extends from the source voltage domain.

[0013] Optionally, the layout structure of the voltage follower device is a transistor layout structure.

[0014] Optionally, the transistor layout structure includes a first pole pattern, a second pole pattern, and a third pole pattern; the first pole pattern is connected to the fourth wiring pattern, the second pole pattern is connected to the power supply pattern of the target voltage domain, and the third pole pattern is connected to the first circuit pattern.

[0015] Optionally, a contact hole pattern is provided on the first well pattern or the second well pattern, at least a part of the first wiring pattern covers the contact hole pattern, and the first well pattern and the second well pattern are connected together.

[0016] Optionally, the first circuit pattern includes a first CMOS pattern, and the second circuit pattern includes a second CMOS pattern.

[0017] Optionally, the line width of the fourth wiring pattern is less than a preset line width threshold.

[0018] Optionally, the layout structure of the level conversion circuit further includes a layout structure of a voltage stabilizing buffer device, the fourth wiring pattern extends from the source voltage domain, and is sequentially connected to the layout structure of the voltage stabilizing buffer device and the layout structure of the voltage follower device.

[0019] Third aspect, embodiments of the present invention further provide a standard cell, including at least one level conversion circuit provided by the embodiments of the present invention; each of the level conversion circuits respectively receives its own signal to be converted, and respectively converts its own signal to be converted into a corresponding converted signal for output.

[0020] Optionally, the power supply voltages of the source voltage domains to which the to-be-converted signals received by the level conversion circuits belong are the same or different; the power supply voltages of the destination voltage domains to which the converted signals output by the level conversion circuits belong are the same.

[0021] Optionally, the power supply voltages of the source voltage domains to which the to-be-converted signals received by the level conversion circuits belong are the same, and the voltage follower devices of the level conversion circuits are connected to the same preset voltage.

[0022] In a fourth aspect, an embodiment of the present invention further provides a chip, in which any level conversion circuit provided by the embodiment of the present invention is provided, or any standard cell provided by the embodiment of the present invention is provided.

[0023] For the level conversion circuit, layout structure, standard cell, and chip provided by the embodiment of the present invention, since the processing unit is powered by the power supply of the destination voltage domain through a preset voltage follower device, and the conversion unit is also powered by the power supply of the destination voltage domain, therefore, the voltage conversion circuit provided by the embodiment of the present invention is substantially only powered by the power supply of the destination voltage domain, without the need for the power supply of the source voltage domain, and there is no need to consider the well isolation problem between different voltage domains, thereby effectively reducing the area of the voltage conversion circuit. Moreover, since the voltage follower device can apply the preset voltage of the source voltage domain to the processing unit under the drive of the power supply of the destination voltage domain, so that the actual working voltage of the processing unit conforms to the voltage range of the source voltage domain to achieve level conversion. Therefore, the level conversion circuit provided by the embodiment of the present invention can effectively reduce the circuit area while ensuring the realization of the level conversion function, and greatly improve the integration degree of the circuit. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 is the circuit schematic diagram of the level conversion circuit in the prior art;

[0026] Figure 2 is a schematic structural diagram of a level conversion circuit provided by an embodiment of the present invention;

[0027] Figure 3 is a circuit schematic diagram of a level conversion circuit provided by an embodiment of the present invention;

[0028] Figure 4 isFigure 3 A schematic diagram of a structure of a generation circuit of a preset voltage VDDSCR_TIEH in the level conversion circuit shown;

[0029] Figure 5 Another circuit schematic diagram of the level conversion circuit provided by the embodiment of the present invention;

[0030] Figure 6 A schematic diagram of a structure of a layout structure of the level conversion circuit provided by the embodiment of the present invention;

[0031] Figure 7 A partial schematic diagram of a layout structure of the level conversion circuit in the embodiment of the present invention;

[0032] Figure 8 Another partial schematic diagram of a layout structure of the level conversion circuit in the embodiment of the present invention;

[0033] Figure 9 For Figure 3 A partial schematic diagram of a layout structure of the level conversion circuit shown;

[0034] Figure 10 In the prior art Figure 1 A partial schematic diagram of a layout structure of the level conversion circuit shown. Detailed implementation manners

[0035] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0037] As described in the background art, in the related art, the level conversion circuit is mainly used for converting level signals between different voltage domains. Therefore, the working range usually spans at least two voltage domains and is powered by at least two different power supplies. When there are N-well structures or P-well structures in these voltage domains in the level conversion circuit, in order to prevent the latch-up effect, these N-wells or P-wells need to be connected to the power supplies within their respective voltage domains. Since the voltage domains of the power supplies to which these N-wells or P-wells are connected are different, in order to ensure the stable performance of the chip, when designing the layout, several N-wells located in different voltage domains, or several P-wells located in different voltage domains, need to be spaced apart by more than a specified distance, otherwise the DRC (Design Rule Check) will not pass.

[0038] For example, Figure 1Schematic diagram of a level conversion circuit provided on a P substrate. As Figure 1 shown, A is the input terminal of the level conversion circuit, and Q is the output terminal of the level conversion circuit. VDDSRC is the power supply of the source voltage domain, and VDDDST is the power supply of the destination voltage domain. Circuit module Part1 is powered by VDDSRC, and circuit module Part2 is powered by VDDDST. Among them, there needs to be a distance greater than a specified distance between the N well for carrying PMOS in circuit module Part1 and the N well for carrying PMOS in circuit module Part2. However, this results in a relatively increased area of the level conversion circuit and a corresponding decrease in integration.

[0039] To solve the above problems, the inventor found in the research that through some ingenious designs, the level conversion circuit can achieve level conversion when only powered by one power supply. In this way, the N wells originally in different voltage domains on the P substrate, or the P wells originally in different voltage domains on the N substrate, can be in the same voltage domain, so there is no need to be spaced by a specified distance, thereby effectively improving the integration.

[0040] To enable those skilled in the art to better understand the technical concept, implementation solution, and beneficial technical effects of the embodiments of the present invention, the following will be described in detail through specific embodiments.

[0041] As Figure 2 shown, an embodiment of the present invention provides a level conversion circuit, which may include:

[0042] Processing unit 1, one end is connected to the signal B to be converted, and the other end is connected to conversion unit 2, and is used for logically inverting the signal B to be converted to obtain the inverted signal Binv to be converted. Among them, processing unit 1 is powered by the power supply VDDDST of the destination voltage domain through a preset voltage follower device VFollower, and the voltage follower device VFollower is used to apply the preset voltage VDDSRC_TIEH of the source voltage domain to processing unit 1 under the drive of the power supply VDDDST of the destination voltage domain;

[0043] Conversion unit 2, which is respectively connected to the signal B to be converted and processing unit 1, and is used for outputting the converted signal C according to the signal B to be converted and the inverted signal Binv to be converted. Among them, the logic level of the signal B to be converted belongs to the source voltage domain, and the logic level of the converted signal C belongs to the destination voltage domain. Conversion unit 2 is powered by the power supply VDDDST of the destination voltage domain.

[0044] The level conversion circuit provided by the embodiment of the present invention may include a processing unit 1 and a conversion unit 2. One end of the processing unit 1 is connected to the signal B to be converted, and the other end is connected to the conversion unit 2. The processing unit 1 can perform logical inversion on the signal B to be converted to obtain the inverted signal Binv to be converted. The conversion unit 2 is respectively connected to the signal B to be converted and the processing unit 1, and can output the converted signal C according to the signal B to be converted and the inverted signal Binv to be converted. The logical level of the signal B to be converted belongs to the source voltage domain, and the logical level of the converted signal C belongs to the destination voltage domain, thereby realizing level conversion. In this way, since the processing unit 1 is powered by the power supply VDDDST of the destination voltage domain through a preset voltage follower device VFollower, and the conversion unit 2 is also powered by the power supply VDDDST of the destination voltage domain, the voltage conversion circuit provided by the embodiment of the present invention is substantially only powered by the power supply VDDDST of the destination voltage domain without the power supply of the source voltage domain, and there is no need to consider the well isolation problem between different voltage domains, thus effectively reducing the area of the voltage conversion circuit. Moreover, since the voltage follower device VFollower can apply the preset voltage VDDSRC_TIEH of the source voltage domain to the processing unit 1 under the drive of the power supply VDDDST of the destination voltage domain, so that the actual working voltage of the processing unit 1 conforms to the voltage range of the source voltage domain to realize level conversion. Therefore, the level conversion circuit provided by the embodiment of the present invention can effectively reduce the circuit area while ensuring the realization of the level conversion function, greatly improving the circuit integration degree.

[0045] Specifically, the processing unit 1 can be various circuit structures capable of performing logical inversion operations on the signal B to be converted. For example, as Figure 3 shown, in an embodiment of the present invention, the processing unit 1 may include an inverter, and the inverter may be composed of transistors T1 and T2. The first end of the inverter can be connected to the signal B to be converted, the second end of the inverter can be connected to the conversion unit 2, the third end of the inverter can be connected to the voltage follower device VFollower, and the fourth end of the inverter can be grounded.

[0046] Optionally, the conversion unit 2 can adopt the structure in any existing level conversion circuit as long as it can realize the conversion from the logical level of the source voltage domain to the logical level of the destination voltage domain. For example, as Figure 3 shown, in an embodiment of the present invention, the circuit Part3 realizes the core function of outputting the converted signal C according to the signal B to be converted and the inverted signal Binv to be converted. Of course, in other embodiments of the present invention, Part3 may have other implementation forms, and the embodiments of the present invention do not limit this.

[0047] As mentioned above, the voltage follower VFollower can apply the preset voltage VDDSRC_TIEH of the source voltage domain to the processing unit 1 under the drive of the power supply VDDDST of the target voltage domain. Optionally, the specific structure of the voltage follower VFollower is not limited, as long as the above circuit connection and functions can be realized. Specifically, in an embodiment of the present invention, the first end of the voltage follower VFollower can be connected to the preset voltage VDDSRC_TIEH, the second end can be connected to the power supply VDDDST of the target voltage domain, and the third end can be connected to the processing unit 1. Among them, the voltage at the third end is less than or equal to the voltage at the first end, that is, the voltage at the third end "follows" the voltage at the first end.

[0048] In specific implementation, the voltage follower VFollower can include a voltage follower formed by various transistors (such as depletion / enhancement MOS, triode, finfet MOS, etc.), such as a source follower or an emitter follower. The first end can be the base or gate of the transistor, the second end can be the collector or drain of the transistor, and the third end can be the emitter or source of the transistor. Among them, the emitter (or source) follower is a negative feedback amplifier. In terms of the connection method of the transistor, it is a common collector (or common drain) amplifier. The signal can be input from the base (or gate) and output from the emitter (or source), so it is also called an emitter (or source) outputter. The voltage amplification factor of the emitter (or source) follower is always less than and close to 1. In this way, with the transistor as the core of the voltage follower, the power supply VDDDST of the target voltage domain can be connected through the collector (or drain), and under the drive of the power supply VDDDST of the target voltage domain, the preset voltage VDDSRC_TIEH of the source voltage domain connected to the base (or gate) can be applied to the processing unit 1 through the following action of the emitter (or source).

[0049] Considering that transistors are divided into N-type transistors and P-type transistors, appropriate types of transistors can be selected as the voltage follower VFollower according to the specific structure and process implementation of the level conversion circuit. For example, in an embodiment of the present invention, if the level conversion circuit is provided on a P-type substrate, the voltage follower device can include an N-type transistor; or if the level conversion circuit is provided on an N-type substrate, the voltage follower device can include a P-type transistor.

[0050] It can be understood that in the embodiments of the present invention, although both the processing unit 1 and the conversion unit 2 are powered by the power supply VDDDST of the target voltage domain, a preset voltage VDDSRC_TIEH is introduced from the source voltage domain to the target voltage domain through the voltage follower device VFollower to ensure the normal operation of the processing unit 1. Specifically, in order to ensure that the actual operating voltage of the processing unit 1 conforms to the voltage range of the source voltage domain, in the embodiments of the present invention, the preset voltage VDDSRC_TIEH is specifically defined. For example, in an embodiment of the present invention, the absolute value of the difference between the preset voltage VDDSRC_TIEH and the power supply voltage VDDSRC of the source voltage domain may be less than a preset threshold. Among them, the preset threshold may be a relatively small value, such as 0.1V, 0.2V, etc., and can be specifically set according to different circuit parameters. That is to say, in the embodiments of the present invention, through the voltage follower device VFollower, a preset voltage VDDSRC_TIEH equal to or approximately equal to the power supply voltage VDDSRC of the source voltage domain can be introduced from the source voltage domain to the target voltage domain and applied to the processing unit 1, so that the processing unit 1 can operate normally.

[0051] Furthermore, since the preset voltage VDDSRC_TIEH comes from the source voltage domain and may be far from the target voltage domain, in order to reduce or eliminate the interference and loss of the preset voltage VDDSRC_TIEH during transmission, in an embodiment of the present invention, a voltage stabilizing buffer device may also be provided between the preset voltage VDDSRC_TIEH of the target voltage domain and the voltage follower device VFollower, so that the preset voltage VDDSRC_TIEH coming from afar from the source voltage domain remains stable, avoiding excessive fluctuations and making the circuit function more stable. Optionally, the voltage stabilizing buffer device may include various forms of capacitors, such as the gate capacitance of MOS transistors, etc.

[0052] It should be noted that the level conversion circuit provided in the embodiments of the present invention can convert the level signal of the source voltage domain into the level signal of the target voltage domain. Among them, no special limitation is made on the voltage levels of the source voltage domain and the target voltage domain. That is to say, the power supply voltage of the target voltage domain may be higher than the power supply voltage of the source voltage domain, or the power supply voltage of the target voltage domain may also be equal to the power supply voltage of the source voltage domain, or the power supply voltage of the target voltage domain may also be lower than the power supply voltage of the source voltage domain.

[0053] It should also be noted that the level conversion circuit provided by the embodiment of the present invention is a conversion of a level system, but the output signal itself can be either the same logic as the input signal or the opposite logic to the input signal. That is to say, the logic level of the converted signal can be the same as or opposite to the logic level of the signal to be converted. For example, if the input signal B is a high level in the 1.2V voltage domain, the output signal C can be a high level in the 2.0V voltage domain or a low level in the 2.0V voltage domain.

[0054] Furthermore, after converting the signal in the source voltage domain into a signal in the destination voltage domain, the signal output side of the level conversion circuit can be easily spliced with other circuits or units in the destination voltage domain to achieve various circuit functions.

[0055] The level conversion circuit provided by the embodiment of the present invention will be described in detail below through specific embodiments.

[0056] As Figure 3 shown, the level conversion circuit provided by the embodiment of the present invention may include a processing unit 1 and a conversion unit 2. Among them, the processing unit 1 may include an inverter formed by connecting a P-type transistor T1 and an N-type transistor T2. The input end of the inverter receives the signal B to be converted, and the output end obtains the inverted signal Binv of the signal to be converted. The processing unit 1 is powered by the power supply VDDDST in the destination voltage domain through an N-type transistor T3 (T3 is the voltage follower device). The N-type transistor T3 can apply the preset voltage VDDSRC_TIEH in the source voltage domain to the source electrode of the P-type transistor T1 in the processing unit 1 under the drive of the power supply VDDDST in the destination voltage domain. The conversion unit 2 may include six transistors T4, T5, T6, T7, T8, and T9. Among them, T4, T5, and T6 form a symmetrical structure with T7, T8, and T9. The gates of T5 and T6 receive the inverted signal Binv of the signal to be converted, the gates of T8 and T9 receive the signal B to be converted, the gate of T4 is connected to the drain of T8, and the gate of T7 is connected to the drain of T5.

[0057] When the signal B to be converted = 1, the inverted signal Binv of the signal to be converted = 0, T9 is turned on, T5 is turned on, T6 is turned off, T8 is turned off, point F is at a low level. Therefore, T4 is turned on, that is, both T4 and T5 are turned on, the voltage at point E is at a high level. Therefore, T7 is turned off, that is, both T7 and T8 are turned off, so that point F is stabilized at a low level, that is, C = 0, and C is equal to the logical negation of B.

[0058] When the signal B to be converted = 0, the inverted signal Binv of the signal to be converted = 1, T9 is turned off, T5 is turned off, T6 is turned on, T8 is turned on, point E is at a low level. Therefore, T7 is turned on, that is, both T7 and T8 are turned on, the voltage at point F is at a high level. Therefore, T4 is turned off, that is, both T4 and T5 are turned off, so that point E is stabilized at a low level, and further point F is stabilized at a high level, that is, C = 1, and C is also equal to the logical negation of B.

[0059] If the signal C at the F terminal is taken as the output, while the level conversion circuit realizes level conversion, it also performs an inversion operation on the signal to be converted, that is, the logic level output by the level conversion circuit is opposite to the logic level of the signal to be converted. If it is desired that the logic level output by the level conversion circuit is the same as the logic level of the signal to be converted, an inverter can be connected again at the F terminal to obtain Q, and Q is taken as the output of the level conversion circuit, then Q is equal to B.

[0060] Optionally, the preset voltage VDDSRC_TIEH of the source voltage domain can be obtained by directly connecting to the power supply voltage VDDSRC of the source voltage domain, or can be obtained by connecting to the power supply voltage VDDSRC of the source voltage domain through a resistor, transistor, etc. The embodiments of the present invention do not limit this. Exemplarily, the preset voltage VDDSRC_TIEH of the source voltage domain can be obtained in the manner as Figure 4 shown.

[0061] In order to reduce or eliminate the interference and loss of the preset voltage VDDSRC_TIEH during transmission, in an embodiment of the present invention, between the preset voltage VDDSRC_TIEH of the target voltage domain and the voltage follower device T3, a transistor T10 (i.e., a voltage stabilizing buffer device) can also be provided. The source and drain of T10 are grounded, and the gate is connected to the preset voltage VDDSRC_TIEH, so as to utilize the voltage stabilizing effect of the gate capacitance of the transistor T10 to keep the preset voltage VDDSRC_TIEH coming from a long distance in the source voltage domain stable and avoid excessive fluctuations.

[0062] It should be noted that Figure 3 the shown level conversion circuit is a level conversion circuit based on a P substrate, but the embodiments of the present invention are not limited to this, and the level conversion circuit can also be based on an N substrate. Exemplarily, the level conversion circuit based on an N substrate can be as Figure 5 shown, where VSSSRC_TIEL is the preset voltage of the source voltage domain, and its basic principle is similar to that of the level conversion circuit of the P-type substrate, which will not be elaborated here.

[0063] Correspondingly, the embodiments of the present invention also provide a layout structure of a level conversion circuit, which can effectively reduce the area of the level conversion circuit and greatly improve the integration degree of the circuit.

[0064] As Figure 6 shown, the layout structure of the level conversion circuit provided by the embodiments of the present invention may include:

[0065] a processing unit layout structure 3, a conversion unit layout structure 4, and a voltage follower device layout structure 5;

[0066] The layout structure 3 of the processing unit includes a first well pattern WEL1 and a first circuit pattern CIR1, and at least a part of the first circuit pattern CIR1 is within the coverage of the first well pattern WEL1; the layout structure 4 of the conversion unit includes a second well pattern WEL2 and a second circuit pattern CIR2, and at least a part of the second circuit pattern CIR2 is within the coverage of the second well pattern WEL2; the spacing distance between the first well pattern WEL1 and the second well pattern WEL2 is less than a preset distance threshold;

[0067] The first well pattern WEL1 and the second well pattern WEL2 are connected to the power supply pattern ShapeVDDDST of the target voltage domain through a first wiring pattern LINE1; the first circuit pattern CIR1 is connected to the layout structure 5 of the voltage follower, and the layout structure 5 of the voltage follower is connected to the power supply pattern ShapeVDDDST of the target voltage domain through a second wiring pattern LINE2; the second circuit pattern CIR2 is connected to the power supply pattern ShapeVDDDST of the target voltage domain through a third wiring pattern LINE3; the layout structure 5 of the voltage follower is also connected to a fourth wiring pattern LINE4, and the fourth wiring pattern LINE4 extends from the source voltage domain.

[0068] In the layout structure of the level conversion circuit provided by the embodiment of the present invention, since the first circuit pattern CIR1 is connected to the layout structure 5 of the voltage follower, the layout structure 5 of the voltage follower is connected to the power supply pattern ShapeVDDDST of the target voltage domain through the second wiring pattern LINE2, and the second circuit pattern CIR2 is connected to the power supply pattern ShapeVDDDST of the target voltage domain through the third wiring pattern LINE3, both the first well pattern WEL1 and the second well pattern WEL2 can be connected to the power supply pattern ShapeVDDDST of the target voltage domain through the first wiring pattern LINE1. Therefore, the power supply of the source voltage domain is not provided in the corresponding level conversion circuit, and there is no need to consider the well isolation problem between different voltage domains, thereby effectively reducing the area of the voltage conversion circuit. Moreover, since the layout structure 5 of the voltage follower is also connected to the fourth wiring pattern LINE4, and the fourth wiring pattern LINE4 extends from the source voltage domain, the preset voltage of the source voltage domain can be applied to the processing unit, so that the actual working voltage of the processing unit conforms to the voltage range of the source voltage domain, effectively reducing the circuit area while ensuring the realization of the level conversion function and greatly improving the integration degree of the circuit.

[0069] Optionally, using the layout structure of the level conversion circuit provided by the embodiment of the present invention, the corresponding level conversion circuit can be fabricated on a semiconductor substrate. According to different process requirements, the substrate can be either a P-type substrate or an N-type substrate, and the embodiment of the present invention does not limit this.

[0070] Specifically, the layout structure of the level conversion circuit provided by the embodiment of the present invention may include a processing unit layout structure 3, a conversion unit layout structure 4, and a voltage follower device layout structure 5. The processing unit layout structure 3 can be used to fabricate the processing unit of the level conversion circuit, the conversion unit layout structure 4 can be used to fabricate the conversion unit of the level conversion circuit, and the voltage follower device layout structure 5 can be used to fabricate the voltage follower device of the level conversion circuit. For the specific structures and functions of the processing unit, the conversion unit, and the voltage follower device, reference can be made to the relevant descriptions in the foregoing embodiments.

[0071] In an embodiment of the present invention, the processing unit layout structure 3 may include a first well pattern WEL1 and a first circuit pattern CIR1. Among them, the first circuit pattern CIR1 can be used to form a first circuit structure, the first well pattern WEL1 can be used to form a first well, the first circuit structure can implement specific circuit logics and functions, and at least a part of the first circuit structure is disposed in the first well. Similarly, the conversion unit layout structure 4 may include a second well pattern WEL2 and a second circuit pattern CIR2. Among them, the second circuit pattern CIR2 can be used to form a second circuit structure, the second well pattern WEL2 can be used to form a second well, the second circuit structure can implement specific circuit logics and functions, and at least a part of the second circuit structure is disposed in the second well.

[0072] Optionally, the first circuit pattern and the second circuit pattern can be layout patterns based on various processes and corresponding to various circuit structures. For example, various transistor patterns, resistor patterns, capacitor patterns, etc. In an embodiment of the present invention, the first circuit pattern may include a first CMOS (Complementary Metal-Oxide-Semiconductor) pattern, and the second circuit pattern may include a second CMOS pattern.

[0073] As can be seen from the foregoing embodiments, since both the first well pattern WEL1 and the second well pattern WEL2 can be connected to the power supply pattern ShapeVDDDST of the target voltage domain through the first wiring pattern LINE1, there is no need to set the power supply of the source voltage domain in the corresponding level conversion circuit. In this way, there is no need to consider the well isolation problem between different voltage domains. That is to say, the first well pattern WEL1 and the second well pattern WEL2 can be spaced at any relatively small distance (for example, as Figure 7 shown), or even connected into one piece without a distance (for example, as Figure 8 ). Specifically, in Figure 8 , the first well pattern WEL1 and the second well pattern WEL2 can be made together and connected into one piece without a gap, so that the circuit area can be saved to the greatest extent.

[0074] Furthermore, in the corresponding level conversion circuit, there is no need to set the power supply VDDSRC of the source voltage domain, which can effectively reduce the metal wiring related to VDDSRC, further save the circuit area, and improve the circuit integration. Moreover, when the first well pattern WEL1 and the second well pattern WEL2 are connected together, they can be connected to the power supply VDDDST of the target voltage domain through the same contact hole and the same metal line, thereby further saving the contact hole area and the metal wiring area.

[0075] For example, please refer to Figure 8 again. In an embodiment of the present invention, a contact hole pattern pore may be provided on the first well pattern WEL1, the first wiring pattern LINE1 at least partially covers the contact hole pattern pore, and the first well pattern WEL1 is connected to the second well pattern WEL2. Of course, the contact hole pattern pore may also be provided on the second well pattern WEL2. In this way, the first well pattern WEL1 and the second well pattern WEL2 are connected to the power supply VDDDST (not shown) of the target voltage domain through the same contact hole and the same metal line, thereby further saving the contact hole area and the metal wiring area.

[0076] In an embodiment of the present invention, the layout structure 5 of the voltage follower device may be a transistor layout structure, and the transistor layout structure may include a first pole pattern, a second pole pattern, and a third pole pattern; the first pole pattern may be connected to the fourth wiring pattern LINE4, the second pole pattern may be connected to the power supply pattern ShapeVDDDST of the target voltage domain, and the third pole pattern may be connected to the first circuit pattern CIR1.

[0077] Optionally, the fourth wiring pattern LINE4 may be a signal type metal wiring, and the line width of the signal type metal wiring may be smaller than the line width of the power supply type metal wiring, that is to say, the line width of the fourth wiring pattern LINE4 may be smaller than the preset line width threshold, so as to effectively reduce the area of the metal wiring and further improve the circuit integration.

[0078] From the layout corresponding to the level conversion circuit, the reduction effect of the circuit area can be clearly seen. For example, in an embodiment of the present invention, Figure 3 The partial layout of the level conversion circuit shown may be as Figure 9 shown, and the partial layout of the level conversion circuit shown in the prior art Figure 1 may be as Figure 10 shown. Comparing Figure 9 and Figure 10It can be seen that the level conversion circuit provided by the embodiment of the present invention eliminates the gap between the N-well (NW) of the source voltage domain and the N-well of the destination voltage domain, connects the two N-wells into one piece, and also eliminates the metal wires and contact holes (TAP) required to connect the power supply VDDSRC of the source voltage domain. Therefore, the circuit area can be greatly reduced (about reduced to 50%), effectively improving the circuit integration degree.

[0079] Furthermore, the layout structure of the level conversion circuit provided by the embodiment of the present invention may further include the layout structure of a voltage stabilizing buffer device. The fourth wiring pattern LINE4 can extend from the source voltage domain and be connected to the layout structure of the voltage stabilizing buffer device and the layout structure of the voltage follower device in sequence, so as to stably introduce the signal of the source voltage domain into the level conversion circuit.

[0080] Correspondingly, the embodiment of the present invention further provides a standard cell. One or more level conversion circuits provided by any of the foregoing embodiments may be provided in the standard cell; each level conversion circuit can respectively receive its respective signal to be converted and convert its respective signal to be converted into a corresponding converted signal and output it. Therefore, corresponding beneficial technical effects can also be produced. For details, reference can be made to the foregoing embodiments and will not be elaborated herein.

[0081] Optionally, in the standard cell provided by the embodiment of the present invention, the power supply voltages of the source voltage domains to which the signals to be converted received by each level conversion circuit belong may be the same or different; the power supply voltages of the destination voltage domains to which the converted signals output by each level conversion circuit belong are the same. That is to say, in the standard cell provided by the embodiment of the present invention, signals of multiple same or different source voltage domains can be converted into signals of the same destination voltage domain. For example, signals with power supply voltages of 1.0V, 1.0V, and 2.0V in the source voltage domain can be respectively converted into signals with a power supply voltage of 1.8V in the destination voltage domain. In this way, since the corresponding destination voltage domains of each level conversion circuit are the same, there is no need to specify a distance between the wells in the standard cell, thereby effectively reducing the area of the standard cell and improving the integration degree of the standard cell.

[0082] Optionally, in an embodiment of the present invention, the power supply voltages of the source voltage domains to which the signals to be converted received by each level conversion circuit belong are the same, then the voltage follower devices of each level conversion circuit can be connected to the same preset voltage, thereby further reducing the area of the metal wiring.

[0083] Correspondingly, the embodiment of the present invention further provides a chip. Any level conversion circuit provided by the embodiment of the present invention is provided in the chip, or any standard cell provided by the embodiment of the present invention is provided. Therefore, corresponding beneficial technical effects can also be produced. For details, reference can be made to the foregoing embodiments and will not be elaborated herein.

[0084] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0085] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments.

[0086] In particular, for the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiments.

[0087] For the convenience of description, the above apparatus is described by dividing it into various units / modules according to functions. Of course, when implementing the present invention, the functions of each unit / module can be realized in the same or multiple software and / or hardware.

[0088] Those of ordinary skill in the art can understand that all or part of the processes of implementing the above method embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0089] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A level conversion circuit, characterized in that, Comprising: A processing unit, one end of which is connected to the signal to be converted and the other end is connected to a conversion unit, for performing logical inversion on the signal to be converted to obtain an inverted signal to be converted. Wherein, the processing unit is powered by the power supply of the target voltage domain through a preset voltage follower device, and the voltage follower device is used to apply a preset voltage of the source voltage domain to the processing unit under the drive of the power supply of the target voltage domain; the first end of the voltage follower device is connected to the preset voltage, the second end is connected to the power supply of the target voltage domain, and the third end is connected to the processing unit, wherein the voltage at the third end is less than or equal to the voltage at the first end; the voltage follower device includes a transistor, the first end includes the base or gate of the transistor, the second end includes the collector or drain of the transistor, and the third end includes the emitter or source of the transistor; A conversion unit, connected to the signal to be converted and the processing unit respectively, for outputting a converted signal according to the signal to be converted and the inverted signal to be converted. Wherein, the logic level of the signal to be converted belongs to the source voltage domain, and the logic level of the converted signal belongs to the target voltage domain, and the conversion unit is powered by the power supply of the target voltage domain.

2. The level conversion circuit according to claim 1, characterized in that, The processing unit includes an inverter, the first end of the inverter is connected to the signal to be converted, the second end of the inverter is connected to the conversion unit, the third end of the inverter is connected to the voltage follower device, and the fourth end of the inverter is grounded.

3. The level conversion circuit according to claim 1, characterized in that The level conversion circuit is disposed on a P-type substrate, and the voltage follower device includes an N-type transistor; or the level conversion circuit is disposed on an N-type substrate, and the voltage follower device includes a P-type transistor.

4. The level conversion circuit according to claim 1, wherein A voltage stabilizing buffer device is further disposed between the preset voltage of the target voltage domain and the voltage follower device.

5. A layout structure of a level conversion circuit, characterized in that, Comprising: A layout structure of the processing unit, a layout structure of the conversion unit, and a layout structure of the voltage follower device; The layout structure of the processing unit includes a first well pattern and a first circuit pattern, and at least a part of the first circuit pattern is within the coverage of the first well pattern; the layout structure of the conversion unit includes a second well pattern and a second circuit pattern, and at least a part of the second circuit pattern is within the coverage of the second well pattern; the spacing distance between the first well pattern and the second well pattern is less than a preset distance threshold; The first well pattern and the second well pattern are connected to the power supply pattern of the target voltage domain through a first wiring pattern; the first circuit pattern is connected to the layout structure of the voltage follower device, and the layout structure of the voltage follower device is connected to the power supply pattern of the target voltage domain through a second wiring pattern; the second circuit pattern is connected to the power supply pattern of the target voltage domain through a third wiring pattern; the layout structure of the voltage follower device is further connected to a fourth wiring pattern, and the fourth wiring pattern extends from the source voltage domain; the layout structure of the voltage follower device is a transistor layout structure; the transistor layout structure includes a first pole pattern, a second pole pattern, and a third pole pattern; The first pole pattern is connected to the fourth wiring pattern, the second pole pattern is connected to the power supply pattern of the target voltage domain, and the third pole pattern is connected to the first circuit pattern; the first pole includes the base or gate of the transistor, the second pole includes the collector or drain of the transistor, and the third pole includes the emitter or source of the transistor.

6. The layout structure according to claim 5, characterized in that, A contact hole pattern is provided on the first well pattern or the second well pattern. The first wiring pattern at least partially covers the contact hole pattern, and the first well pattern is connected to the second well pattern.

7. The layout structure according to claim 5, characterized in that The first circuit pattern includes a first CMOS pattern, and the second circuit pattern includes a second CMOS pattern.

8. The layout structure according to claim 5, characterized in that, The line width of the fourth wiring pattern is less than a preset line width threshold.

9. The layout structure according to claim 5, wherein It further includes a layout structure of a voltage stabilizing buffer device. The fourth wiring pattern extends from the source voltage domain and is sequentially connected to the layout structure of the voltage stabilizing buffer device and the layout structure of the voltage following device.

10. A standard cell, characterized in that, It includes at least one level conversion circuit according to any one of claims 1-4; each of the level conversion circuits respectively receives its corresponding signal to be converted and converts and outputs its corresponding converted signal.

11. The standard cell according to claim 10, characterized in that, The power supply voltages of the source voltage domains to which the signals to be converted received by each of the level conversion circuits belong are the same or different; the power supply voltages of the target voltage domains to which the converted signals output by each of the level conversion circuits belong are the same.

12. The standard cell according to claim 10, characterized in that, The power supply voltages of the source voltage domains to which the signals to be converted received by each of the level conversion circuits belong are the same, and the voltage following devices of each of the level conversion circuits are connected to the same preset voltage.

13. A chip, characterized in that, The level conversion circuit according to any one of claims 1-4 is provided in the chip, or the standard cell according to any one of claims 10-12 is provided.

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