Fast-locking phase-locked loop and related fast-locking method

Abstract

A fast-locking phase-locked loop (PLL) and its related fast-locking method are provided. The fast-locking phase-locked loop (PLL) includes a gear-shifting loop filter configured to have a dynamic bandwidth. The gear-shifting loop filter includes a resistor bank and a capacitor bank coupled to the resistor bank, wherein the resistor bank is configured to have a dynamic resistance, and the capacitor bank is configured to have a dynamic capacitance. More specifically, the dynamic resistance switches from a first resistance to a second resistance, and the dynamic capacitance switches from a first capacitance to a second capacitance, so that the dynamic bandwidth switches from a first bandwidth to a second bandwidth.

Description

Technical Field

[0001] The present invention generally relates to a phase-locked loop (PLL), and more particularly, to a fast-locking PLL and its associated fast phase-locking method. Background Art

[0002] To achieve a fast-locking phase-locked loop (PLL), at least one parameter of the fast-locking PLL can be configured to be variable. In the related art, the charge pump current of the PLL can be dynamically switched during the locking operation of the PLL, so as to accelerate the locking operation without sacrificing the noise-related performance of the PLL. For example, at the beginning of the locking operation of the PLL, the charge pump current is controlled to have an initial current, which is greater than the final current. Here, compared with having the final current, the initial current makes the locking operation faster but the noise-related performance is worse; when the locking operation is almost completed (for example, the output frequency of the PLL is close to the target frequency), the charge pump current can be controlled to be the final current to ensure the noise-related performance.

[0003] The way of dynamically switching the charge pump current does improve the speed of the locking operation. However, there are some drawbacks. Generally, the unit cell of the charge pump current source is designed to have a big size to obtain better noise-related performance. When increasing the speed of the locking operation, the number of unit cells must be increased, thus greatly increasing the overall circuit area and current consumption. Therefore, a novel mechanism for fast locking operation and its associated architecture is needed to achieve a fast-locking PLL without introducing any side effects or in a way that is less likely to introduce side effects. Summary of the Invention

[0004] In view of this, an object of the present invention is to provide a fast-locking phase-locked loop (PLL) and its associated fast locking method, for example, a fast-locking PLL based on a variable bandwidth loop filter for dynamic bandwidth control, which can achieve fast locking operation without significantly increasing additional costs.

[0005] At least one embodiment of the present invention provides a fast-locking phase-locked loop (PLL). The fast-locking phase-locked loop (PLL) includes a variable-bandwidth loop filter configured to have a dynamic bandwidth. The variable-bandwidth loop filter includes a resistor bank and a capacitor bank coupled to the resistor bank, wherein the resistor bank is configured to have a dynamic resistance, and the capacitor bank is configured to have a dynamic capacitance. For example, the dynamic resistance switches from a first resistance to a second resistance, and the dynamic capacitance switches from a first capacitance to a second capacitance, so that the dynamic bandwidth switches from a first bandwidth to a second bandwidth.

[0006] In addition to the above-mentioned fast-locking phase-locked loop (PLL), at least one embodiment of the present invention also provides a fast-locking method for a fast-locking phase-locked loop (PLL). The fast-locking method may include: controlling the dynamic resistance by using the resistor bank of the variable-bandwidth loop filter in the fast-locking phase-locked loop (PLL), and controlling the dynamic capacitance by using the capacitor bank of the variable-bandwidth loop filter, so that the variable-bandwidth loop filter has a dynamic bandwidth; switching the dynamic resistance from a first resistance to a second resistance, and switching the dynamic capacitance from a first capacitance to a second capacitance, so that the dynamic bandwidth switches from a first bandwidth to a second bandwidth.

[0007] Embodiments of the present invention can dynamically switch the bandwidth of the loop filter (dynamically switch the bandwidth of the loop filter during the locking operation) by switching the resistance and capacitance of the loop filter within the phase-locked loop (PLL), thereby improving the speed of the locking operation of the phase-locked loop (PLL) without sacrificing the noise-related performance. In addition, embodiments of the present invention do not greatly increase the additional cost. Therefore, the present invention can improve the overall performance without introducing any side effects or in a way that is unlikely to introduce side effects.

[0008] The present invention content is not intended to limit the present invention. The present invention is defined by the claims. Those skilled in the art can undoubtedly understand these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the drawings. The detailed description will be given in the following embodiments with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention can be more fully understood by reading the following detailed description and referring to the examples given in the drawings, wherein:

[0010] Figure 1 is a schematic diagram of a fast-locking phase-locked loop (PLL) shown according to an embodiment of the present invention.

[0011] Figure 2is a schematic diagram showing some details of the voltage buffer shown according to an embodiment of the present invention Figure 1 shown

[0012] Figure 3 is a schematic diagram of a fast-locking phase-locked loop (PLL) shown according to an embodiment of the present invention

[0013] Figure 4 is a schematic diagram of a fast-locking phase-locked loop (PLL) shown according to an embodiment of the present invention

[0014] Figure 5 is shown according to an embodiment of the present invention Figure 4 is a schematic diagram showing some details of the voltage buffer shown

[0015] Figure 6 is a schematic diagram of a unity-gain buffer (UGB) shown according to an embodiment of the present invention

[0016] Figure 7 According to an embodiment of the present invention, the waveforms of the timing of the variable bandwidth control signal, the input voltage, and the output voltage of the UGB are shown

[0017] Figure 8 is a schematic diagram of an auto-zero UGB shown according to an embodiment of the present invention

[0018] Figure 9 According to an embodiment of the present invention, the input voltage and the output voltage of the auto-zero UGB, and the waveforms of the timing of the variable bandwidth control signal and the mode control signal of the auto-zero UGB are shown

[0019] Figure 10 is the workflow of the fast-locking method of the fast-locking phase-locked loop (PLL) shown according to an embodiment of the present invention

[0020] In the following detailed description, for the purpose of illustration, many specific details are set forth in order for those skilled in the art to more thoroughly understand the embodiments of the present invention. However, it is obvious that one or more embodiments can be implemented without these specific details, and different embodiments can be combined according to requirements, and should not be limited to the embodiments listed in the drawings Detailed implementation manners

[0021] The following description is a preferred embodiment of the implementation of the present invention, which is only used to illustrate the technical features of the present invention by way of example and is not used to limit the scope of the present invention. Throughout the specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names to refer to the same element. Therefore, the specification and claims do not use the difference in names as a way to distinguish elements, but use the difference in the functions of elements as the benchmark for distinction. The terms "element", "system" and "device" used in the present invention may be entities related to a computer, where the computer may be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" mentioned in the following description and claims are open-ended terms and should therefore be interpreted as meaning "including, but not limited to...". In addition, the term "coupled" means an indirect or direct electrical connection. Therefore, if a device is described as being coupled to another device in the text, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0022] Wherein, unless otherwise indicated, corresponding numbers and symbols in different drawings of the drawings generally refer to corresponding parts. The drawings drawn clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0023] The term "substantially" or "approximately" as used herein means within an acceptable range, where those skilled in the art can solve the technical problems to be solved and substantially achieve the technical effects to be achieved. For example, "substantially equal" means that, when the correctness of the result is not affected, those skilled in the art can accept a certain error from "exactly equal".

[0024] A phase-locked loop (PLL) includes a phase detector (e.g., a phase frequency detector), a charge pump, a loop filter, a voltage control oscillator (VCO), and a divider. To achieve fast locking of the phase-locked loop (PLL), the bandwidth of the phase-locked loop can be made transformable, or in other words, a phase-locked loop (PLL) with a transformable bandwidth (e.g., a dynamic bandwidth) can be employed. For example, the transformable bandwidth can include a first bandwidth and a second bandwidth, which are sequentially adopted during the locking operation of the phase-locked loop (PLL). For example, the first bandwidth is adopted in a first mode, and the second bandwidth is adopted in a second mode after the first mode, where, compared with the second bandwidth, the first bandwidth is beneficial to the locking speed (e.g., for locking frequency error and phase error), while the second bandwidth can be designed to optimize the performance related to noise, such as the performance related to integrated phase noise (IPN). To better illustrate the fast locking operation of the phase-locked loop (PLL), please refer to the following formulas, which represent the open-loop bandwidth (denoted as "BWPLL(open loop)") K, the damping factor δ, and the closed-loop bandwidth ω of the phase-locked loop (PLL). n :

[0025]

[0026]

[0027]

[0028] It should be noted that I CP represents the charge pump current of the charge pump, and K VCO represents the VCO gain of the voltage control oscillator (VCO), R P represents the resistance of the resistor in the loop filter, and C Prepresents the capacitance of the capacitor within the loop filter, and N represents the divisor of the frequency divider. According to the above expression, the method of changing the frequency bandwidth (e.g., the open-loop frequency bandwidth K or the dead-loop frequency bandwidth ω n ) can be achieved by changing I CP , R P , C P , K VCO and N. Generally, when changing the frequency bandwidth between the first frequency bandwidth and the second frequency bandwidth, the damping factor δ is designed to be unchanged. It should be noted that the transformable frequency bandwidth may include other frequency bandwidths such as the third frequency bandwidth in addition to the exemplified first frequency bandwidth and second frequency bandwidth. Specifically, the embodiments of the present invention do not make limitations.

[0029] For example, I CP in the first mode can be designed to be twice that of I CP in the second mode, and if the damping coefficient δ remains unchanged, the first frequency bandwidth can be times that of the second frequency bandwidth (e.g., R P in the first mode is designed to be times that in the second mode). Since the current source unit of the charge pump usually requires a relatively large circuit area, the method of changing I CP to achieve the transformable frequency bandwidth will greatly increase the additional cost. Thus, the present invention provides another mechanism for achieving the transformable frequency bandwidth. For example, R P in the first mode can be designed to be twice that of R P in the second mode. If the damping coefficient δ remains unchanged, the first frequency bandwidth can be 2 times that of the second frequency bandwidth (e.g., C P in the first mode is designed to be 1 / 4 times that in the second mode).

[0030] Figure 1 is a schematic diagram of the fast-lock phase-locked loop (PLL) 10 shown according to an embodiment of the present invention, where the fast-lock phase-locked loop (PLL) 10 is an example of the above-mentioned phase-locked loop (PLL). As Figure 1As shown, the fast-lock phase-locked loop (PLL) 10 may include a gear-shifting loop filter 100, a phase frequency detector (PFD) with a charge pump (CP) (which may be referred to as "PFD / CP" for simplicity) 11, a voltage control oscillator (VCO) 12, and a divider 13, such as a multi-modulus divider (MMD). In this embodiment, the PFD / CP 11 generates a voltage signal based on the phase difference or frequency difference REF between the reference clock signal CK from a reference clock source (not shown) and the divided clock signal CK MMD from the multi-modulus divider (MMD) 13. The voltage signal is transmitted to the voltage control oscillator (VCO) 12 via a path coupled to the gear-shifting loop filter. Then, the voltage control oscillator (VCO) 12 generates an output clock signal CK VCO according to the received voltage signal, and the multi-modulus divider (MMD) 13 performs a frequency division operation on the output clock signal CK VCO , for example, the frequency of the output clock signal CK VCO can be divided by a certain value (e.g., a value greater than 1) to generate the divided clock signal CK MMD . It should be noted that the embodiments of the present invention aim to provide an implementation of the gear-shifting loop filter 100 (which will be described in detail later), where other components (e.g., PFD / CP 11, voltage control oscillator (VCO) 12, and multi-modulus divider (MMD) 13) can be implemented or replaced by any suitable circuit architecture. For the sake of brevity, the relevant details of these components are omitted here. In addition, Figure 1 the architecture of the fast-lock phase-locked loop (PLL) 10 shown is only for illustrative purposes and does not mean a limitation to the present invention. That is, the gear-shifting loop filter 10 can be applied to any architecture of the fast-lock phase-locked loop (PLL) that includes a loop filter with resistors and / or capacitors.

[0031] In this embodiment, the gear-shifting loop filter 100 is configured to have a dynamic bandwidth (e.g., bandwidth BW1 or bandwidth BW2) to perform an operation with a variable bandwidth (e.g., switching the dynamic bandwidth from bandwidth BW1 to bandwidth BW2). More specifically, the gear-shifting loop filter 100 may include a capacitor set CS1 , a resistor set R S2 and a capacitor set C coupled to the resistor set R S2 . Suppose in the embodiment of S2 . Assume that in Figure 1 the embodiment, the bandwidth BW1 is designed to be γ times the bandwidth BW2, where γ is a positive value greater than 1. In this embodiment, the capacitor set C S1 can be configured to have a fixed capacitance (e.g., implemented by a single capacitor C1 with capacitance "C1"), the resistor set R S2 can be configured to have a dynamic resistance (e.g., resistance "γ×R2" or resistance "R2"), and the capacitor set C S2 can be configured to have a dynamic capacitance (e.g., capacitance "α×C2" or capacitance "C2", where α is preferably designed to be 1 / γ 2 , but the present invention is not limited thereto. The dynamic resistance of the resistor set R S2 and the dynamic capacitance of the capacitor set C S2 can be examples of the above resistance R P and capacitance C P respectively. For example, the dynamic resistance of the resistor set R S2 can be switched from the resistance "γ×R2" to the resistance "R2", and the dynamic capacitance of the capacitor set C S2 can be switched from the capacitance "α×C2" to the capacitance "C2" so that the dynamic bandwidth is switched from the bandwidth BW1 to the bandwidth BW2.

[0032] Specifically, the resistor set R S2 is coupled between a first common node (e.g., node N1) and a second common node (e.g., node N2 of the variable bandwidth loop filter 100). As Figure 1 shown, the resistor set R S2 can include a resistor (γ - 1)R2 (which has a resistance "(γ - 1)×R2") and a resistor R2 (which has a resistance "R2"), where the resistor (γ - 1)R2 and the resistor R2 can be serially coupled, and a switch controlled by a variable bandwidth control signal is connected across the two ends of the resistor (γ - 1)R2. For example, by turning on this switch, the dynamic resistance of the resistor set R S2 can be switched from the resistance "γ×R2" to the resistance "R2", but the present invention is not limited thereto. In some embodiments, the resistor set R with dynamic resistance S2It can be implemented in different ways (e.g., a variable resistor or multiple resistors having at least one switch for controlling the connection of the multiple resistors). Additionally, capacitor bank C S2 can include capacitor αC2 (with capacitance “α×C2”) and capacitor (1 - α)C2 (with capacitance “(1 - α)×C2”), where capacitor αC2 is coupled to resistor bank R through node N2 S2 and, by coupling capacitor (1 - α)C2 to node N2, the dynamic capacitance of capacitor bank C S2 can be switched from capacitance “α×C2” to capacitance “C2”.

[0033] In some embodiments, when performing an operation with a variable bandwidth, capacitor (1 - α)C2 can be coupled to node N2 (i.e., in parallel with capacitor αC2) without any pre - processing. However, this may lead to some drawbacks. For example, when the locking operation of phase - locked loop (PLL) 10 is almost completed, it is desirable that the voltage level at node N2 be around the target level, where the voltage level on capacitor (1 - α)C2 can be different from the voltage level at node N2. Therefore, when capacitor (1 - α)C2 is coupled to node N2, the voltage level at node N2 may be pulled away from this target level. In this case, the locking operation will need to use bandwidth BW2 and take additional time to restore the voltage level at node N2 to this target level. Since bandwidth BW2 is designed to optimize noise - related performance and is relatively disadvantageous and slower in terms of the speed of the locking operation compared to bandwidth BW1, the additional time required to restore the voltage level at node N2 may be long, which is undesirable.

[0034] In Figure 1 the illustrated embodiment, a voltage buffer 110 within variable - bandwidth loop filter 100 can be coupled between node N2 and capacitor (1 - α)C2, where Figure 2 is a schematic diagram showing some details of voltage buffer 110 illustrated according to an embodiment of the present invention Figure 1 The input terminal Vin and output terminal Vout of voltage buffer 110 are coupled Figure 1The node N2 and the capacitor (1-α)C2 as shown can, with the help of the voltage buffer 110, copy the voltage level on the capacitor αC2 (or the node N2) to the capacitor (1-α)C2 before the capacitor (1-α)C2 is connected in parallel with the capacitor αC2 (or rather, before the capacitor (1-α)C2 is directly connected to the capacitor αC2 through a closed switch). As Figure 2 shown, the voltage buffer 110 can include a unity-gain buffer (UGB) 110U, a first switch SW21 controlled by a variable bandwidth control signal and a second switch SW22 controlled by a variable bandwidth control signal . As Figure 2 shown, the unity-gain buffer (UGB) 110U and the serially-coupled first switch SW21 can represent the first signal path between the input terminal Vin and the output terminal Vout of the voltage buffer 110, and the second switch SW22 can represent the second signal path between the input terminal Vin and the output terminal Vout of the voltage buffer 110.

[0035] For better understanding, please refer to Figure 1 for reference Figure 2, wherein, the input terminal Vin is coupled to the node N2, and the output terminal Vout is coupled to the capacitor (1-α)C2. For example, at the start of the locking operation, the fast-locking phase-locked loop (PLL) 10 can operate in a first bandwidth mode (the first bandwidth mode is relatively beneficial to the locking speed). In this first bandwidth mode, the first switch SW21 is turned on and the second switch SW22 is turned off to enable a first signal path between the input terminal Vin and the output terminal Vout. Therefore, at certain time point(s) before the capacitor (1-α)C2 is paralleled with the capacitor αC2, the voltage level on the capacitor αC2 (or the node N2) is copied to the capacitor (1-α)C2 through the unity-gain buffer (UGB) 110U. And after the locking operation is almost completed (for example, the frequency error or phase error detected by the PFD / CP 11 is less than a predetermined value, or the time period from the start of the locking operation reaches a predetermined time period), the phase-locked loop (PLL) 10 can enter a second bandwidth mode from the first bandwidth mode (the second bandwidth mode is relatively beneficial to the noise-related performance). In this second bandwidth mode, the first switch SW21 is turned off and the second switch SW22 is turned on to enable a second signal path between the input terminal Vin and the output terminal Vout. Therefore, the capacitor (1-α)C2 can be coupled to the node N2 through the turned-on second switch SW22 (i.e., the capacitor (1-α)C2 is paralleled with the capacitor αC2) to switch the dynamic bandwidth from the bandwidth BW1 to the bandwidth BW2. In some embodiments, after the fast-locking phase-locked loop (PLL) 10 enters the second bandwidth mode from the first bandwidth mode, the unity-gain buffer (UGB) 110U shown in Figure 2 can be disabled or turned off, but the present invention is not limited thereto. Since the voltage level on the capacitor (1-α)C2 is similar or identical to the voltage level on the capacitor αC2, any possible problems that may occur in embodiments without using the voltage buffer 110 can be solved, and the overall performance (such as the speed of the locking operation) can be optimized. It should be noted that when the first switch SW21 is turned on, since the input impedance of the unity-gain buffer (UGB) 110U is a high impedance, the impedance looking from the node N2 to the capacitor (1-α)C2 is a high impedance. Thus, the capacitor (1-α)C2 and the capacitor αC2 do not form a parallel connection because when looking from the node N2 to the capacitor (1-α)C2, the capacitance of the capacitor (1-α)C2 cannot be seen due to the high input impedance of the unity-gain buffer (UGB) 110U.

[0036] When performing the operation of variable bandwidth, due to the capacitor bank C S1The capacitance is fixed. Therefore, the phase margin of the fast-lock phase-locked loop (PLL) may change. The following formula illustrates the phase margin of the fast-lock phase-locked loop (PLL) 10 in the first bandwidth mode and the phase margin of the fast-lock phase-locked loop (PLL) 10 in the second bandwidth mode

[0037] And,

[0038]

[0039] During the operation of the variable bandwidth, although the phase margin of the fast-lock phase-locked loop (PLL) is not fixed, as long as the phase margin falls within an acceptable range (which will not significantly reduce the overall performance), it is allowed.

[0040] In another embodiment, by switching Figure 1 the capacitor bank C shown S1 , the phase margin can be kept constant to optimize the overall performance of the fast-lock phase-locked loop (PLL). For better illustration, please refer to the following equations, which give the bandwidth ω C (for example, the above bandwidth BW2), the zero frequency ω Z , the pole frequency ω P and the phase margin with respect to the frequency variable ω of the fast-lock phase-locked loop (PLL) operating in the second bandwidth mode (for example, Figure 1 the fast-lock PLL 10 shown

[0041]

[0042] And,

[0043]

[0044] To optimize the overall performance of this fast-lock phase-locked loop (PLL), preferably, the phase margin of the fast-lock phase-locked loop (PLL) operating in the first bandwidth mode is the same as the phase margin of the fast-lock phase-locked loop (PLL) operating in the second bandwidth mode . To keep the phase margin (i.e., make where ω C1 represents the bandwidth of the fast-lock phase-locked loop (PLL), for example, the above bandwidth BW1), it is necessary to make ωC / ω Z = ω C1 / ω Z and ω C / ω P = ω C1 / ω P 。For example, in the first bandwidth mode, when the resistance "R2" is doubled to double the bandwidth ω C (e.g., ω C1 = 2 × ω C ), the capacitor "C2" needs to be reduced to 1 / 4, and the capacitor "C1" needs to be reduced to 1 / 4 so that ω C / ω Z = ω C1 / ω Z and ω C / ω P = ω C1 / ω P 。

[0045] Figure 3 is a schematic diagram of a fast-lock phase-locked loop (PLL) 30 shown according to an embodiment of the present invention. Among them, the fast-lock phase-locked loop (PLL) 30 can be obtained by modifying the architecture of the fast-lock phase-locked loop (PLL) 10 shown in Figure 1 , and more specifically, by modifying the implementation of the capacitor bank C S1 . In the embodiment of Figure 3 , the capacitor bank C S1 can be configured to have a dynamic capacitance (e.g., capacitance "β × C1" or capacitance "C1"), where α = β = 1 / γ 2 . When the dynamic bandwidth is switched from bandwidth BW1 to bandwidth BW2, the dynamic capacitance of the capacitor bank C S1 can be switched from capacitance "β × C1" to capacitance "C1" so that the phase margin of the fast-lock phase-locked loop (PLL) 30 remains unchanged during the operation of the variable bandwidth. As shown in Figure 3 , the capacitor bank C S1 can include capacitor βC1 (which has capacitance "β × C1") and capacitor (1 - β)C1 (which has capacitance "(1 - β) × C1"), where capacitor βC1 is coupled to node N1. For example, by coupling capacitor (1 - β)C1 to node N1 (i.e., by connecting capacitor (1 - β)C1 and capacitor (1 - β)C1 in parallel), the dynamic capacitance of the capacitor bank C S1 can be switched from capacitance "β × C1" to capacitance "C1" so that the phase margin of the fast-lock phase-locked loop (PLL) 30 remains unchanged.

[0046] In some embodiments, when performing an operation with a variable bandwidth, the capacitor (1-β)C1 is coupled to node N1 (i.e., the capacitor (1-β)C1 is in parallel with the capacitor βC1) without any prior processing. For similar reasons mentioned above, this may lead to some drawbacks. For example, when the locking operation of the fast-locking phase-locked loop (PLL) 30 is almost completed, it is desirable that the voltage level on node N1 be near the target level. Among them, the voltage level on the capacitor (1-β)C1 may be different from the voltage level on node N1. Thus, when the capacitor (1-β)C1 is coupled to node N1, the voltage level on node N1 may deviate from the target level. Therefore, the locking operation will require additional time to restore the voltage level on node N1 to the target level through the bandwidth BW2. More particularly, since the bandwidth BW2 is designed to optimize noise-related performance and is relatively disadvantageous in terms of the speed of the locking operation compared to the bandwidth BW1, the additional time required to restore the voltage level on node N2 is especially undesirable. Taking this into account, in Figure 3 In an embodiment, the voltage buffer 120 in the variable bandwidth loop filter 100 may be coupled between node N1 and the capacitor (1-β)C1. By means of the voltage buffer 120, before coupling the capacitor (1-β)C1 to node N1 (i.e., before paralleling the capacitor (1-β)C1 and the capacitor βC1), the voltage level on the capacitor βC1 (or on node N1) can be copied to the capacitor (1-β)C1. The implementation of the voltage buffer 120 may be similar to or the same as the implementation of the voltage buffer 110. For the sake of brevity, the implementation details of the voltage buffer 120 are not described herein again, but the present invention is not limited thereto. As long as the voltage buffer 120 can copy the voltage level on the capacitor βC1 (or on node N1) to the capacitor (1-β)C1 before the capacitor (1-β)C1 is coupled to node N1 (i.e., before paralleling the capacitor (1-β)C1 and the capacitor βC1), any other implementation should also fall within the scope of the present invention.

[0047] To further improve the overall performance, the hardware of the variable bandwidth loop filter can be further modified. In fact, when the locking operation is completed or almost completed, the voltage levels on node N1 and node N2 can be substantially similar or identical to each other. In an embodiment of the present invention, the voltage buffer 110 and the voltage buffer 120 can share the same hardware to reduce additional costs. For better understanding, please refer to Figure 4 , Figure 4FIG. 0 is a schematic diagram of a fast-locking phase-locked loop (PLL) 40 shown according to an embodiment of the present invention. Among them, the fast-locking phase-locked loop (PLL) 40 can be obtained by modifying Figure 3 the architecture of the fast-locking phase-locked loop (PLL) 30 shown, and more specifically, by using only a single voltage buffer (e.g., voltage buffer 130) to achieve the same functions or effects as voltage buffers 110 and 120. For simplicity, in Figure 3 the dashed boxes labeled C S1 , C S2 and R S2 are omitted in Figure 4 . In this embodiment, with the help of voltage buffer 130, before the capacitors (1-α)C2 and (1-β)C1 are respectively coupled to nodes N2 and N1 (i.e., before the capacitors (1-α)C2 and αC2 are connected in parallel, and before the capacitors (1-β)C1 and βC1 are connected in parallel), the voltage levels on the capacitor αC2 (or node N2) can be respectively copied to the capacitors (1-α)C2 and (1-β)C1.

[0048] Figure 5 FIG. 16 is a schematic diagram showing some details of the voltage buffer 130 shown according to an embodiment of the present invention. The voltage buffer 130 can be obtained by modifying Figure 4 the voltage buffer 110 shown. As Figure 2 shown, in addition to the unity-gain buffer (UGB) 110U, the first switch (labeled "SW51" in Figure 5 for better understanding) is controlled by a variable bandwidth control signal Figure 5 , the second switch (labeled "SW52" in for better understanding) is controlled by a variable bandwidth control signal Figure 5 , the voltage buffer 130 may further include a third switch (labeled "SW53" in for better understanding), which is controlled by a variable bandwidth control signal Figure 5 , and a fourth switch (labeled "SW54" in for better understanding) is controlled by a variable bandwidth control signal Figure 5 , and the fourth switch (labeled "SW54" in Control. Specifically, the unity-gain buffer (UGB) 110U and the serially-coupled first switch SW51 can represent the first signal path between the input terminal Vin_C2 and the output terminal Vout_C2 of the voltage buffer 130, and the second switch SW52 can represent the second signal path between the input terminal Vin_C2 and the output terminal Vout_C2 of the voltage buffer 130. The unity-gain buffer (UGB) 110U and the serially-coupled third switch SW53 can represent the third signal path between the input terminal Vin_C2 and the output terminal Vout_C1 of the voltage buffer 130, and the fourth switch SW54 can represent the fourth signal path between the input terminal Vin_C1 and the output terminal Vout_C1 of the voltage buffer 130.

[0049] For better understanding, please refer to Figure 1 in Figure 5 while referring to Figure 4In an embodiment, the input terminal Vin_C2 is coupled to node N2, the input terminal Vin_C1 is coupled to node N1, the output terminal Vout_C2 is coupled to the capacitor (1-α)C2, and the output terminal Vout_C1 is coupled to the capacitor (1-β)C1. For example, at the beginning of the lock operation, the fast-lock phase-locked loop (PLL) 40 may operate in a first bandwidth mode (which is relatively beneficial for the lock speed), where the second switch SW52 and the fourth switch SW54 are turned off, and the first switch SW1 is turned on to enable the first signal path between the input terminal Vin_C2 and the output terminal Vout_C2, and the third switch SW53 is turned on to enable the third signal path between the input terminal Vin_C2 and the output terminal Vout_C1. Therefore, at a certain time point(s) before the capacitors (1-α)C2 and (1-β)C1 are respectively coupled to nodes N2 and N1 (i.e., before the capacitor (1-α)C2 is paralleled with the capacitor αC2, and before the capacitor (1-β)C1 is paralleled with the capacitor βC1), the voltage level on the capacitor αC2 (or at node N2) is copied to the capacitors (1-α)C2 and (1-β)C1 through the unity-gain buffer (UGB) 110U; and after the lock operation is almost completed (for example, the frequency error or phase error detected by the PFD / CP 11 is less than a predetermined value, or the time period starting from the beginning of the lock operation reaches a predetermined time period), the phase-locked loop (PLL) 40 may enter the second bandwidth mode from the first bandwidth mode (the second bandwidth mode is relatively beneficial for noise-related performance), where the first switch SW51 and the third switch SW53 are turned off, and the second switch SW52 is turned on to enable the second signal path between the input terminal Vin_C2 and the output terminal Vout_C2; and the fourth switch SW54 is turned on to enable the fourth signal path between the input terminal Vin_C1 and the output terminal Vout_C1. Therefore, the capacitors (1-α)C2 and (1-β)C1 can be respectively coupled to nodes N2 and N1 to switch the dynamic bandwidth from the bandwidth BW1 to the bandwidth BW2. In some embodiments, after the fast-lock phase-locked loop (PLL) 40 enters the second bandwidth mode from the first bandwidth mode, Figure 5 the unity-gain buffer (UGB) 110U shown in

[0050] may be disabled or turned off, but the present invention is not limited thereto. Figure 5The input terminal Vin_C2, input terminal Vin_C1, output terminal Vout_C2, and output terminal Vout_C1 of the voltage buffer 130 shown in are respectively coupled to node N2, node N1, capacitor (1-α)C2, and capacitor (1-β)C1, as Figure 4 shown, but the present invention is not limited thereto. In another example, Figure 5 The input terminal Vin_C2, input terminal Vin_C1, output terminal Vout_C2, and output terminal Vout_C1 of the voltage buffer 130 shown in are respectively coupled to node N1, node N2, capacitor (1-β)C1, and capacitor (1-α)C2. When the locking operation is completed or almost completed (which corresponds to the time point of performing the variable bandwidth operation), the voltage level on node N1 is substantially similar to or equal to the voltage level on node N2, but the present invention is not limited thereto.

[0051] Figure 6 is a schematic diagram of a unity-gain buffer (UGB) 60 shown according to an embodiment of the present invention. Among them, the unity-gain buffer (UGB) 60 is implemented by an operational amplifier with a negative feedback configuration, which may be an example of the unity-gain buffer (UGB) 110U, but the present invention is not limited thereto. In practice, an operational amplifier may have some non-ideal effects (such as non-linearity), for example, finite gain (such as finite voltage gain) and mismatch. For example, due to process variations, the input terminals V P and V N or input components (such as input-stage transistors) may not be exactly the same as each other. In view of the above, the operational amplifier may have an offset voltage V OS (which corresponds to the voltage difference between the input voltage V IN,UGB and output voltage V OUT,UGB of the unity-gain buffer (UGB) 110U. For example, V OUT,UGB =V IN,UGB +V OS ), for example, the offset voltage V OS is caused by the finite gain and / or input mismatch of the operational amplifier, and, at the moment of the variable bandwidth operation (the moment when the variable bandwidth control signal goes low and the variable bandwidth control signal goes high, as shown by the dashed line marked "Gear-shifting BW"), the offset voltage V OS may pull the voltage level on any one of nodes N1 and N2 (such as V IN,UGB ) away from that at Figure 7The target level obtained before the operation of the variable frequency bandwidth shown. Therefore, the locking operation takes additional time to pull the voltage level back to this target level (for example, it takes longer to lock). In order to apply Figure 6 When implementing the unit gain buffer (UGB) 110U shown, minimize the offset voltage V OS The influence of, the specification requirements of the operational amplifier may be very high. For example, high direct-current (DC) gain, large-sized input components (for example, input transistors that require large channel widths and / or channel lengths) to reduce the offset voltage V OS , and this will greatly increase the cost. More particularly, in order to ensure that the transconductance of the operational amplifier is large enough, the ratio of the channel width to the channel length needs to be large enough, which means that the sizes of both the channel width and the channel length need to be increased to minimize the offset voltage V without sacrificing the transconductance OS .

[0052] Figure 8 is a schematic diagram of an auto-zero unit gain buffer (UGB) 80 shown according to an embodiment of the present invention. Among them, the auto-zero unit gain buffer (UGB) 80 can be an example of the unit gain buffer (UGB) 110U, but the present invention is not limited thereto. As Figure 8 shown, the auto-zero unit gain buffer (UGB) 80 can include an amplifier circuit 80A (for example, an operational amplifier) and a storage capacitor 80C coupled to the amplifier circuit 80A. Among them, the amplifier circuit 80A has an offset voltage (for example, V OS ), for example, the offset voltage V OS is caused by the limited gain or input mismatch of the amplifier circuit 80A, and the storage capacitor 80C can be configured to store the offset voltage V OS . For example, the auto-zero unit gain buffer (UGB) 80 can alternately operate in a calibration mode and a buffer mode. Among them, in the calibration mode of the auto-zero unit gain buffer (UGB) 80, the offset voltage V OS can be stored on the storage capacitor 80C, and in the buffer mode of the auto-zero unit gain buffer (UGB) 80, the input voltage level (for example, input voltage V IN,UGB ) on the input end of the auto-zero unit gain buffer (UGB) 80 is copied to the output end of the auto-zero UGB to become the output voltage V OUT,UGB. More specifically, the auto-zero unit gain buffer (UGB) 80 may include a first control switch (labeled "SW81" in Figure 8 for better understanding) and a second control switch (labeled "SW82" in Figure 8 for better understanding), the first control switch and the second control switch are controlled by the mode control signal , and the auto-zero unit gain buffer (UGB) 80 further includes a third control switch (labeled "SW83" in Figure 8 for better understanding) and a fourth control switch (labeled "SW84" in Figure 8 for better understanding), the third control switch and the fourth control switch are controlled by the mode control signal . Specifically, the first control switch is coupled between the first input terminal (labeled "+", for example, the non-inverting input terminal in Figure 8 ) of the amplifier circuit 80A and the first end of the energy storage capacitor 80C, the second control switch is coupled between the output terminal of the amplifier circuit 80A (which is coupled to the output terminal of the auto-zero unit gain buffer (UGB) 80) and the second input terminal (labeled "-", for example, the inverting input terminal in Figure 8 ), the third control switch is coupled between the input terminal of the auto-zero UGB and the first input terminal of the amplifier circuit 80A, and the fourth control switch is coupled between the first end of the energy storage capacitor 80C and the output terminal of the amplifier circuit 80A, wherein the second end of the energy storage capacitor 80C is coupled to the second input terminal of the amplifier circuit 80A.

[0053] Figure 9 According to an embodiment of the present invention, waveforms of the input voltage V IN,UGB (or the voltage level on any one of nodes N1 and N2), the output voltage V OUT,UGB , the variable bandwidth control signal and the mode control signal are shown. For better understanding, please refer to Figure 8 in combination with Figure 9 . When the mode control signal is at a high level (for example, having a logic value of "1") and the mode control signal is at a low level (for example, having a logic value of "0"), the first control switch and the second control switch are turned on, and the third control switch and the fourth control switch are turned off. At this time, the auto-zero unit gain buffer (UGB) 80 can operate in the calibration mode (labeled "CAL"). In the calibration mode, the energy storage capacitor 80C is coupled between the first input terminal and the second input terminal of the amplifier circuit 80A, and the output terminal of the amplifier circuit is coupled to the second input terminal of the amplifier circuit to cancel the offset voltage VOS Stored on the energy storage capacitor 80C. When the mode control signal is at a high level and the mode control signal is at a low level, the third control switch and the fourth control switch are turned on, and the first control switch and the second control switch are turned off. Among them, the auto-zero unity gain buffer (UGB) 80 can operate in the buffer mode (labeled "BUF"). In the buffer mode, the input terminal of the auto-zero unity gain buffer (UGB) 80 is coupled to the first input terminal of the amplifier circuit 80A, and the energy storage capacitor 80C is coupled between the second input terminal of the amplifier circuit 80A and the output terminal of the auto-zero unity gain buffer (UGB) 80 to copy the input voltage level on the input terminal of the auto-zero unity gain buffer (UGB) 80 to the output terminal of the auto-zero UGB (e.g., V IN,UGB = V OUT,UGB ). It should be noted that the time point when the dynamic bandwidth switches from the bandwidth BW1 to the bandwidth BW2 (e.g., the time point when the operation with variable bandwidth is performed, marked as "Gear-shifting BW" in Figure 7 ) is within the period when the auto-zero UGB operates in the buffer mode. Compared with the embodiment shown in Figure 7 , since the offset voltage V OS can be canceled or reduced at the output terminal of the auto-zero unity gain buffer (UGB) 80, the speed of the locking operation can be increased.

[0054] It should be noted that Figure 8 the connection shown is for illustrative purposes only and does not imply a limitation on the present invention. As long as the auto-zero unity gain buffer (UGB) 80 can cancel or reduce the influence of the offset voltage V OS so that V IN,UGB = V OUT,UGB , the detailed circuit implementation of the auto-zero unity gain buffer (UGB) 80 can be slightly adjusted (vary).

[0055] Figure 10 is the working process of the fast locking method of the fast locking phase-locked loop (PLL) (e.g., any one of the fast locking phase-locked loops (PLL) 10, 30, and 40) shown according to an embodiment of the present invention. It should be noted that Figure 10 the working process shown is for illustrative purposes only and does not imply a limitation on the present invention. In the working process shown in Figure 10 , one or more steps can be added, deleted, or modified. Additionally, if the same or similar results can be obtained, these steps do not have to be executed in the exact order shown in Figure 10 .

[0056] In step 1010, the fast-lock phase-locked loop (PLL) controls the dynamic resistance by using a resistor bank of a variable-bandwidth loop filter within the fast-lock phase-locked loop (PLL), and controls the dynamic capacitance by using a capacitor bank of the variable-bandwidth loop filter, so that the variable-bandwidth loop filter has a dynamic bandwidth.

[0057] In step 1020, the fast-lock phase-locked loop (PLL) switches the dynamic resistance from a first resistance to a second resistance, and switches the dynamic capacitance from a first capacitance to a second capacitance, so that the dynamic bandwidth is switched from a first bandwidth to a second bandwidth.

[0058] Briefly summarized, the fast-lock phase-locked loop (PLL) and the associated fast-lock method provided by embodiments of the present invention can switch resistors and capacitors within a loop filter located within the fast-lock phase-locked loop (PLL) to use different bandwidths during different time periods of the locking operation, thereby optimizing the overall performance. In embodiments where the proposed variable-bandwidth operation requires at least one voltage buffer, any offset voltage of the amplifier circuit within the voltage buffer may affect the overall performance of the fast-lock phase-locked loop (PLL). Therefore, the present invention also provides an auto-zeroing unity-gain buffer (UGB) to ensure that the input voltage and the output voltage of the voltage buffer are the same or almost the same, without being affected by any offset. Compared with the prior art, the embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can improve the overall performance without introducing any side effects or in a manner that is unlikely to introduce side effects.

[0059] Although the present invention has been described by way of examples and in accordance with preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar structures (as would be apparent to those skilled in the art), for example, combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A fast-locking phase-locked loop PLL, characterized in that, Comprising: A variable bandwidth loop filter configured to have a dynamic bandwidth, wherein the variable bandwidth loop filter comprises: A resistor bank configured to have a dynamic resistance; A first capacitor bank coupled to the resistor bank and configured to have a dynamic capacitance; Wherein the dynamic resistance switches from a first resistance to a second resistance, and the dynamic capacitance switches from a first capacitance to a second capacitance, so that the dynamic bandwidth switches from a first bandwidth to a second bandwidth; Wherein the variable bandwidth loop filter further comprises: A second capacitor bank coupled to the resistor bank and configured to have another dynamic capacitance; Wherein when the dynamic bandwidth switches from the first bandwidth to the second bandwidth, the another dynamic capacitance switches from a third capacitance to a fourth capacitance, so that the phase margin of the fast-lock PLL remains unchanged.

2. The fast-lock PLL according to claim 1, wherein The first resistor is γ times the second resistor, the first capacitor is α times the second capacitor, and the third capacitor is β times the fourth capacitor, such that the first bandwidth is γ times the second bandwidth and the phase margin of the fast-lock PLL remains unchanged, where α = β = 1 / γ 2 , and γ is a positive value greater than 1.

3. The fast-lock PLL as claimed in claim 1, wherein The resistor bank is coupled between a first common node and a second common node of the variable bandwidth loop filter, the first common node being the input / output node of the variable bandwidth loop filter, the first capacitor bank comprising a first capacitor and a second capacitor, the first capacitor being coupled to the resistor bank via the second common node, and by paralleling the second capacitor with the first capacitor, the dynamic capacitance switches from the first capacitance to the second capacitance, wherein, by means of a voltage buffer within the variable bandwidth loop filter, the voltage level on the first capacitor is copied to the second capacitor before paralleling the second capacitor with the first capacitor.

4. The fast-locking PLL according to claim 3, characterized in that, The second capacitor bank comprises a third capacitor and a fourth capacitor, the third capacitor being coupled to the first common node; Wherein when the dynamic bandwidth switches from the first bandwidth to the second bandwidth, by coupling the fourth capacitor to the first common node, the another dynamic capacitance switches from a third capacitance to a fourth capacitance so that the phase margin of the fast-lock PLL remains unchanged.

5. The fast-locking PLL according to claim 4, characterized in that, By means of the voltage buffer, the voltage level on the first capacitor is copied to the fourth capacitor before paralleling the fourth capacitor with the third capacitor.

6. The fast-locking PLL according to claim 4, wherein, By means of another voltage buffer within the variable bandwidth loop filter, the voltage level on the third capacitor is copied to the fourth capacitor before paralleling the fourth capacitor with the third capacitor.

7. The fast-locking PLL according to claim 3, wherein The voltage buffer comprises: An auto-zero unity-gain buffer UGB, the auto-zero UGB comprising: An amplifier circuit having an offset voltage; A storage capacitor coupled to the amplifier circuit and configured to store the offset voltage; Wherein, in the calibration mode of the auto-zero UGB, the offset voltage is stored on the storage capacitor; in the buffer mode of the auto-zero UGB, the input voltage level on the input terminal of the auto-zero UGB is copied to the output terminal of the auto-zero UGB.

8. The fast-lock PLL according to claim 7, characterized in that: In the calibration mode, the storage capacitor is coupled between a first input terminal and a second input terminal of the amplifier circuit, and the output terminal of the amplifier circuit is coupled to the second input terminal of the amplifier circuit; And, In this buffer mode, the input terminal of the auto-zeroing UGB is coupled to the first input terminal of the amplifier circuit, and the energy storage capacitor is coupled between the second input terminal of the amplifier circuit and the output terminal of the auto-zeroing UGB; wherein, the output terminal of the auto-zeroing UGB is coupled to the output terminal of the amplifier circuit.

9. The fast-lock PLL according to claim 7, characterized in that, The time point at which the dynamic bandwidth switches from the first bandwidth to the second bandwidth is within the time period when the auto-zeroing UGB operates in the buffer mode.

10. A fast locking method for quickly locking a phase-locked loop PLL, characterized in that, Including: Using the resistor bank of the variable bandwidth loop filter in the fast-lock PLL to control the dynamic resistance, and using the first capacitor bank of the variable bandwidth loop filter to control the dynamic capacitance, so that the variable bandwidth loop filter has a dynamic bandwidth; and, Switching the dynamic resistance from a first resistance to a second resistance, and switching the dynamic capacitance from a first capacitance to a second capacitance, so that the dynamic bandwidth switches from the first bandwidth to the second bandwidth; wherein, the variable bandwidth loop filter further includes a second capacitor bank, the second capacitor bank has another dynamic capacitance, and the fast-lock method further includes: In response to the dynamic bandwidth switching from the first bandwidth to the second bandwidth, switching the another dynamic capacitance from a third capacitance to a fourth capacitance, so that the phase margin of the fast-lock PLL remains unchanged.

11. The quick locking method according to claim 10, characterized in that, The first resistor is γ times the second resistor, the first capacitor is α times the second capacitor, and the third capacitor is β times the fourth capacitor, such that the first bandwidth is γ times the second bandwidth and the phase margin of the fast-lock PLL remains unchanged, where α = β = 1 / γ 2 , and γ is a positive value greater than 1.

12. The quick locking method according to claim 10, characterized in that, The resistor bank is coupled between the first common node and the second common node of the variable bandwidth loop filter, the first common node is the input / output node of the variable bandwidth loop filter, the first capacitor bank includes a first capacitor and a second capacitor, the first capacitor is coupled to the resistor bank via the second common node, and the step of switching the dynamic capacitance from the first capacitance to the second capacitance includes: By means of a voltage buffer within the variable bandwidth loop filter, copying the voltage level on the first capacitor to the second capacitor; and After copying the voltage level on the first capacitor to the second capacitor, connecting the second capacitor in parallel with the first capacitor.

13. The quick locking method according to claim 12, characterized in that, The fast-lock method further includes: Using the second capacitor bank of the variable bandwidth loop filter to control another dynamic capacitance, the second capacitor bank includes a third capacitor and a fourth capacitor, the third capacitor is coupled to the first common node; and In response to switching the dynamic bandwidth from the first bandwidth to the second bandwidth, by connecting the fourth capacitor in parallel with the third capacitor, switching the another dynamic capacitance from a third capacitance to a fourth capacitance, so that the phase margin of the fast-lock PLL remains unchanged.

14. The quick locking method according to claim 13, characterized in that, The step of switching the another dynamic capacitance from the third capacitance to the fourth capacitance further includes: By means of the voltage buffer, copying the voltage level on the first capacitor to the fourth capacitor before connecting the fourth capacitor in parallel with the third capacitor.

15. The quick locking method according to claim 13, characterized in that, The step of switching the another dynamic capacitance from the third capacitance to the fourth capacitance further includes: By means of another voltage buffer within the variable bandwidth loop filter, copying the voltage level on the first capacitor to the fourth capacitor before connecting the fourth capacitor in parallel with the third capacitor.

16. The quick locking method according to claim 12, wherein The voltage buffer includes: an auto-zero unity-gain buffer UGB, the auto-zero UGB includes an amplifier circuit and a storage capacitor coupled to the amplifier circuit, and the step of copying the voltage level on the first capacitor to the second capacitor includes; In the calibration mode of the auto-zero UGB, storing the offset voltage of the amplifier circuit on the storage capacitor; and, In the buffer mode of the auto-zero UGB, copying the input voltage level on the input terminal of the auto-zero UGB to the output terminal of the auto-zero UGB.

17. The fast locking method according to claim 16, wherein: In the calibration mode, the storage capacitor is coupled between the first input terminal and the second input terminal of the amplifier circuit, and the output terminal of the amplifier circuit is coupled to the second input terminal of the amplifier circuit; And, In the buffer mode, the input terminal of the auto-zero UGB is coupled to the first input terminal of the amplifier circuit, and the storage capacitor is coupled between the second input terminal of the amplifier circuit and the output terminal of the auto-zero UGB; wherein, the output terminal of the auto-zero UGB is coupled to the output terminal of the amplifier circuit.

18. The quick locking method according to claim 16, wherein The time point at which the dynamic bandwidth switches from the first bandwidth to the second bandwidth is located in the period when the auto-zero UGB operates in the buffer mode.

Images