Extended tags for speculative and normal execution

Abstract

A cache system comprising: cache sets; registers associated with the cache sets; and logic circuitry coupled to a processor to control the cache sets based on the registers. When a memory address is received from the processor via a connection to an address bus of the system, the logic circuitry may be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches a first extended tag of a first cache set or a second extended tag of a second cache set of the system. Furthermore, the logic circuitry may be configured to execute a command received from the processor via the first cache set in response to the generated extended tag matching the first extended tag, and to execute the command via the second cache set in response to the generated extended tag matching the second extended tag.

Description

[0001] Related applications

[0002] This application claims priority to U.S. patent application Ser. No. 16 / 528,485, filed Jul. 31, 2019, and entitled “EXTENDED TAGS FOR SPECULATIVE AND NORMAL EXECUTIONS,” the entire disclosure of which is hereby incorporated by reference herein. Technical Field

[0003] At least some embodiments disclosed herein relate generally to cache architectures, and more particularly, but not limited to, cache architectures for main and speculative execution by computer processors. Background Art

[0004] A cache is a memory component that stores data closer to the processor than main memory, allowing the processor to access the data stored in the cache. Data may be stored in the cache due to earlier computation or earlier access to the data in main memory. A cache hit occurs when data requested by the processor using a memory address is found in the cache, while a cache miss occurs when the data cannot be found in the cache.

[0005] Generally speaking, a cache is a memory that stores data recently used by a processor. Memory blocks placed in the cache are correspondingly restricted to cache lines of a placement strategy. There are three commonly known placement strategies: direct-mapped, fully associative, and set-associative. In a direct-mapped cache structure, the cache is organized into multiple sets with a single cache line per set. Based on the address of the memory block, a memory block can occupy only a single cache line. For a direct-mapped cache, the cache can be designed as an (n*1) column matrix. In a fully associative cache structure, the cache is organized into a single cache set with multiple cache lines. A memory block can occupy any of the cache lines in a single cache set. A cache with a fully associative structure can be designed as a (1*m) row matrix.

[0006] A set-associative cache is a cache with an intermediate design structure between a direct-mapped cache and a fully associative cache. A set-associative cache can be designed as an (n*m) matrix, where neither n nor m is 1. The cache is divided into n cache sets, and each set contains m cache lines. A memory block can be mapped to a cache set and then placed into any cache line of the set. When considering a continuous hierarchy of set associativity, a set-associative cache can range from a direct-mapped to a fully associative cache. For example, a direct-mapped cache can also be described as a one-way set-associative cache, and a fully associative cache with m blocks can be described as an m-way set-associative cache. Directionally mapped caches, two-way set-associative caches, and four-way set-associative caches are common in cache systems.

[0007] Speculative execution is a computing technique in which a processor executes one or more instructions before a determination is available as to whether such instructions should be executed, based on a speculation that some condition requires such execution.

[0008] A memory address in a computing system identifies a memory location in the computing system. A memory address is a fixed-length sequence of digits that is conventionally displayed and manipulated as an unsigned integer. The length of the digit or sequence of bits can be considered the width of the memory address. Memory addresses can be used for certain structures of a central processing unit (CPU), such as the instruction pointer (or program counter) and memory address registers. The size or width of such structures of the CPU generally determines the length of the memory addresses used in such a CPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0010] Figures 1A to 1E Various ways of splitting a memory address into portions that can be used with execution types to control the operation of a cache are presented in accordance with some embodiments of the present disclosure.

[0011] Figure 2 、 3A 3B show example aspects of example computing devices, each including a cache system having interchangeable caches for first and second types of execution, according to some embodiments of the present disclosure.

[0012] Figure 4 、 5A5B specifically show example aspects of example computing devices, each including a cache system having interchangeable caches for main-type and speculative-type execution, according to some embodiments of the present disclosure.

[0013] Figure 6 、 7A , 7B, 8A, 8B, 9A and 9B show example aspects of example computing devices according to some embodiments of the present disclosure, each computing device including a cache system having interchangeable cache sets for first and second types of execution (e.g., main type and speculative type execution).

[0014] Figure 10 Specifically presented are example aspects of an example computing device including a cache system having interchangeable cache sets for main-type and speculative-type execution, in accordance with some embodiments of the present disclosure.

[0015] Figure 11A and 11B Background synchronization circuitry for synchronizing contents between a primary cache and a shadow cache to preserve contents cached in the primary cache in preparation for receiving contents in the shadow cache is described according to some embodiments of the present disclosure.

[0016] Figure 12 Demonstrating some embodiments of the present disclosure Figure 11A and 11B Example operation of an example synchronous circuit system.

[0017] Figure 13 、 14A , 14B, 14C, 15A, 15B, 15C, and 15D show example aspects of an example computing device having a cache system with interchangeable cache sets including a spare cache set to accelerate speculative execution according to some embodiments of the present disclosure.

[0018] Figure 16 and 17 Example aspects of an example computing device having a cache system with interchangeable cache sets with extended tags that utilize different types of execution (eg, speculative and non-speculative execution) by a processor are presented in accordance with some embodiments of the present disclosure.

[0019] Figure 18 Example aspects of an example computing device having a cache system with interchangeable cache sets utilizing circuitry to map physical cache set outputs to logical cache set outputs are presented in accordance with some embodiments of the present disclosure.

[0020] Figure 19 、 20and 21 show some embodiments of the present disclosure with a method for utilizing Figure 18 An example aspect of an example computing device of a cache system of interchangeable cache sets in which circuitry maps physical cache set outputs to logical cache set outputs.

[0021] Figure 22 and 23 Methods for using interchangeable cache sets for speculative and non-speculative execution by a processor are presented according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] The present disclosure includes techniques for interchangeably using multiple caches or cache sets of caches with different types of execution performed by connected processors. The types of execution may include speculative and non-speculative execution threads. Non-speculative execution may be referred to as main execution or normal execution.

[0023] To achieve enhanced security, when a processor performs conditional speculative execution of instructions, the processor can be configured to use a shadow cache during the speculative execution of the instructions, where the shadow cache is separate from the main cache used during the main or ordinary execution of the instructions. Some techniques for using a shadow cache to improve security can be found in U.S. patent application Ser. No. 16 / 028,930, filed on July 6, 2018, and entitled "Shadow Cache for Securing Conditional Speculative Instruction Execution," the entire disclosure of which is hereby incorporated by reference herein. The present disclosure includes techniques that allow the following operations: a cache to be dynamically configured as a shadow cache or a main cache; a unified set of cache resources to be dynamically allocated for use in a shadow cache or for use in a main cache; and the allocation to be changed during the execution of an instruction.

[0024] In some embodiments, a system may include a memory system (e.g., including main memory), a processor, and a cache system coupled between the processor and the memory system. The cache system may have cache sets. Furthermore, the caches in the cache sets may be designed in a variety of ways. For example, the caches in the cache sets may include cache sets that are connected by cache set associativity (which may include physical or logical cache set associativity).

[0025] In some embodiments, a cache of a system may be variable between being configured for a first type of execution of instructions by a processor and being configured for a second type of execution of instructions by the processor. The first type may be non-speculative execution of instructions by the processor. The second type may be speculative execution of instructions by the processor.

[0026] In some embodiments, a cache set of caches may be variable between being configured for a first type of execution of instructions by a processor and being configured for a second type of execution of instructions by the processor. The first type may be non-speculative execution of instructions by the processor. And, the second type may be speculative execution of instructions by the processor.

[0027] In some embodiments, speculative execution occurs when a processor executes one or more instructions based on speculation that some condition necessitates their execution before a determination is made as to whether such instructions should be executed. Non-speculative execution (or primary execution, or ordinary execution) occurs when instructions are executed sequentially according to their program sequence.

[0028] In some embodiments, a cache set of a system may include at least a first cache and a second cache. In this example, the system may include a command bus configured to receive a read command or a write command from a processor. The system may also include an address bus configured to receive a memory address from the processor for accessing the memory in response to the read command or the write command. Furthermore, the system may include a data bus configured to: communicate data to the processor for reading; and receive data from the processor for writing to the memory. Memory access requests from the processor may be defined by the command bus, the address bus, and the data bus.

[0029] In some embodiments, a common command and address bus may replace the command and address bus described herein. Additionally, in such embodiments, a common connection to a common command and address bus may replace the corresponding connection to the command and address bus described herein.

[0030] The system may also include an execution type signal line configured to receive an execution type from the processor. The execution type may be an indication of normal or non-speculative execution or an indication of speculative execution.

[0031] The system may also include a configurable data bit configured to be set to a first state (e.g., "0") or a second state (e.g., "1") to change usage of the first cache and the second cache relative to non-speculative execution and speculative execution.

[0032] The system may further include logic circuitry configured to, when a configurable data bit is set to a first state and an execution type signal line receives an indication of non-speculative execution, select a first cache from the processor for a memory access request. The logic circuitry may further be configured to, when the configurable data bit is set to the first state and the execution type signal line receives an indication of speculative execution, select a second cache from the processor for a memory access request. The logic circuitry may further be configured to, when the configurable data bit is set to a second state and the execution type signal line receives an indication of non-speculative execution, select the second cache from the processor for a memory access request. The logic circuitry may further be configured to, when the configurable data bit is set to the second state and the execution type signal line receives an indication of speculative execution, select the first cache from the processor for a memory access request.

[0033] The system may also include a speculation state signal line configured to receive a speculation state from the processor. The speculation state may be an acknowledgement or rejection of a condition having nested instructions that are initially executed by speculative execution and subsequently executed by non-speculative execution when the speculation state is an acknowledgement of the condition.

[0034] The logic circuit may also be configured to select the second cache as identified by the first state of the configurable data bit and restrict the first cache from being used or changed as identified by the first state of the configurable data bit when the signal received by the execution type signal line changes from an indication of non-speculative execution to an indication of speculative execution.

[0035] Furthermore, the logic circuit may be configured to, when the execution type signal line receives an indication of non-speculative execution, change the configurable data bit from a first state to a second state and select the second cache for the memory access request. This may occur when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of non-speculative execution, and when the speculation state received by the speculation state signal line is a confirmation of the condition.

[0036] The logic circuitry may also be configured to maintain the first state of the configurable data bit and select the first cache for the memory access request when the execution type signal line receives an indication of non-speculative execution. This may occur when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of non-speculative execution, and when the speculation state received by the speculation state signal line is a rejection of the condition. Furthermore, the logic circuitry may be configured to invalidate and discard contents of the second cache when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of non-speculative execution, and when the speculation state received by the speculation state signal line is a rejection of the condition.

[0037] The system may also include a second command bus configured to communicate read or write commands to a main memory connected to the cache system. The read or write commands may be received by the cache system from the processor. The system may also include a second address bus configured to communicate a memory address to the main memory. The cache system may receive a memory address from the processor. The system may also include a second data bus configured to communicate data to the main memory for writing to the memory and receive data from the main memory for communication to the processor for reading by the processor. Memory access requests from the cache system to the main memory may be defined by the second command bus, the second address bus, and the second data bus.

[0038] As mentioned, caches within cache sets can be designed in a variety of ways, and one of those ways includes partitioning a cache into sets of cache sets by cache set associativity (which can include physical or logical cache set associativity). The benefit of cache design with set associativity is that a single cache with set associativity can have multiple cache sets within the single cache, and therefore, different portions of the single cache can be allocated for use by the processor without allocating the entire cache. Thus, a single cache can be used more efficiently. This is particularly true when the processor executes multiple types of threads or has multiple execution types. For example, cache sets within a single cache can be used interchangeably with different execution types, rather than using interchangeable caches. Common examples of cache partitioning include having two, four, or eight cache sets within a cache.

[0039] Furthermore, a set-associative cache design is superior to other common cache designs when the processor is executing both the main thread and speculative threads. Since speculative execution can use less additional cache capacity than normal or non-speculative execution, the selection mechanism can be implemented at the cache set level and thus reserve less than the entire cache (i.e., a portion of the cache) for speculative execution. A cache with set associativity can have multiple cache sets within a set (e.g., a partitioning of the cache into two, four, or eight cache sets). For example, if Figure 7A , there are at least four cache sets in the cache of the cache system (e.g., see cache sets 702, 704, and 706). Normal or non-speculative execution, which typically requires most of the cache capacity, may have a larger number of cache sets delegated to it. Also, speculative execution with modifications to non-speculative execution may use one cache set or a smaller number of cache sets because speculative execution typically involves fewer instructions than non-speculative execution.

[0040] like Figure 6 As shown in FIG. 10 , a cache system may include multiple caches for a processor (e.g., Figure 6 ), and the caches of the cache system may include cache sets (e.g., caches 602a, 602b, and 602c depicted in FIG. 1 ). Figure 6 Cache sets 610a, 610b, and 610c are depicted in FIG. 4 to further divide the organization of the cache system. This example includes a cache system with set associativity.

[0041] At the cache set level of the cache, the first cache set (see, for example, Figure 7A 、 Figure 8A and 9A ) can hold content for use with a first type of execution or a second type of execution by the processor. For example, the first cache set can hold content for use with a non-speculative type or a speculative type of execution by the processor. Additionally, the second cache set (e.g., see Figure 7A 、 Figure 8A and 9A Cache sets 704 or 706) depicted in can store contents for use with a first type of execution or a second type by the processor.

[0042] For example, in a first time instance, a first cache set is used for normal or non-speculative execution, and a second cache set is used for speculative execution. In a second time instance, the second cache set is used for normal or non-speculative execution, and the first cache set is used for speculative execution. The manner in which cache sets are delegated / swapped for non-speculative and speculative execution may use set associativity via a cache set index within or external to the memory address tag, or via a cache set indicator within the memory address tag that is different from the cache set index (e.g., see Figure 7A 、 7B , 8A, 8B, 9A and 9B).

[0043] If at least Figure 1B 、 1C As shown in Figures 1A, 1D, 1E, 7A, 7B, 8A, 8B, 9A, and 9B, a cache set index or cache set indicator may be included in the cache block addressing to implement cache set addressing and associativity. The cache block addressing may be stored in a memory (e.g., SRAM, DRAM, etc., depending on the design of the computing device, i.e., the design of a processor register, a cache system, another intermediate memory, a main memory, etc.).

[0044] like Figure 6 、 7A, 7B, 8A, 8B, 9A, 9B and 10, each cache set of the cache (e.g., level 1, level 2 or level 3 cache) has a corresponding register (e.g., shown in Figure 6 and 10 Registers 610a, 610b, or 610c in, or as shown in Figure 7A 、 7B , 8A, 8B, 9A and 9B) and a set index (e.g., see the registers 712, 714 or 716 shown in Figure 7A 、 7B , 8A, 8B, 9A, and 9B) that can be swapped between corresponding registers to implement swapping of cache sets for non-speculative and speculative execution of the processor (or, generally, for first and second types of execution of the processor). For example, with respect to Figure 7A and 7B , during a first time period, a first type of execution may use cache sets 702 and 704, and a second type of execution may use cache set 706. Then, during a second time period, the first type of execution may use cache sets 704 and 706, and the second type of execution may use cache set 702. It should be noted that this is just one example use of cache sets, and it should be understood that any of an unlimited number of cache sets may be used by the first or second type of execution depending on the time period or the set index or indicator stored in the register.

[0045] In some embodiments, several cache sets may be initially allocated for use in a first type of execution (e.g., non-speculative execution). During a second type of execution (e.g., speculative execution), one of the cache sets initially used for the first type of execution (e.g., a reserved cache set) may be used in the second type of execution. Essentially, the cache set allocated for the second type of execution may initially be a free cache set awaiting use, or may be selected from several cache sets used for the first type of execution (e.g., a cache set less likely to be further used for further execution of the first type).

[0046] Generally speaking, in some embodiments, a cache system includes multiple cache sets. The multiple cache sets may include a first cache set, a second cache set, and a plurality of registers, each associated with the multiple cache sets. The multiple registers may include a first register associated with the first cache set and a second register associated with the second cache set. The cache system may also include a connection to a command bus coupled between the cache system and the processor, a connection to an address bus coupled between the cache system and the processor, and a connection to a data bus coupled between the cache system and the processor. The cache system may also include logic circuitry coupled to the processor to control the multiple cache sets based on the plurality of registers.

[0047] In such an embodiment, the cache system may be configured to be coupled between the processor and the memory system. And, when a memory address is received from the processor via the connection to the address bus, the logic circuitry may be configured to generate a set index (e.g., see the table shown in FIG. Figure 7A 、 7B , 8A, 8B, 9A and 9B generate set indexes 730, 732, 830, 832, 930 and 932). In addition, when the connection to the address bus receives a memory address from the processor, the logic circuitry may be configured to determine whether the generated set index matches the contents stored in the first register or the contents stored in the second register. In addition, the logic circuitry may be configured to implement the command received in the connection to the command bus via the first cache set in response to the generated set index matching the contents stored in the first register, and to implement the command via the second cache set in response to the generated set index matching the contents stored in the second register. In addition, in response to determining that a data set of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry may be configured to allocate the first cache set for caching the data set and store the generated set index in the first register. The generated set index may include a predetermined segment of bits in the memory address.

[0048] The cache system may also include a connection to an execution type signal line from the processor that identifies the execution type (see, for example, Figure 6 and 10 d depicted in FIG. 1 ). In such an embodiment, the generated set index may be further generated based on the type identified by the execution type signal line. Furthermore, the generated set index may include a predetermined segment of bits in the memory address and bits representing the type identified by the execution type signal line (e.g., the generated set index may include a predetermined segment of bits in the memory address 102e and bits representing the type shown in FIG. Figure 1EOne or more bits of a type identified by the execution type signal line of execution type 110e in, or derived from the predetermined fragment and the one or more bits).

[0049] Furthermore, when the first and second registers are in a first state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via the first cache set when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via the second cache set when the execution type is the second type. Furthermore, when the first and second registers are in a second state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via another cache set other than the first cache set among the plurality of cache sets when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via another cache set other than the second cache set among the plurality of cache sets when the execution type is the second type. In this example, each of the plurality of registers may be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuitry may be configured to change the contents stored in the first register and the contents stored in the second register.

[0050] In some embodiments, the first type is configured to indicate non-speculative execution of the instruction by the processor; and the second type is configured to indicate speculative execution of the instruction by the processor. In such embodiments, the cache system may further include a connection to a speculation state signal line from the processor that identifies the state of speculative execution of the instruction by the processor (e.g., see the example shown in FIG. Figure 10 The connection to the speculation status signal line may be configured to receive a status of speculative execution, and the status of speculative execution may indicate whether a result of speculative execution is to be accepted or rejected. Each of the plurality of registers may be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuit may be configured to change the contents stored in the first register and the contents stored in the second register if the status of speculative execution indicates that a result of speculative execution is to be accepted (e.g., see the example shown in FIG. 1 ). Figure 7A and Figure 7B Between, displayed in Figure 8A and Figure 8B Between and displayed in Figure 9A and Figure 9B and (c) a change in contents stored in the register between the execution type and the execution type. Furthermore, when the execution type changes from the second type to the first type, the logic circuitry may be configured to maintain the contents stored in the first register and the contents stored in the second register without change if the status of the speculative execution indicates that a result of the speculative execution is to be rejected.

[0051] Additionally, the cache systems described herein (e.g., cache systems 200, 400, 600, and 1000) may each include or be connected to background synchronization circuitry (e.g., see the system shown in FIG. Figure 11A and 11B The background synchronization circuitry 1102 in FIG. 1104 may be configured to synchronize caches or sets of caches prior to reconfiguring a shadow cache as a primary cache and / or reconfiguring a primary cache as a shadow cache.

[0052] For example, the contents of a cache or cache set initially delegated for speculative execution (e.g., an additional cache or backup cache set delegated for speculative execution) may be synchronized with a corresponding cache or cache set used by normal or non-speculative execution (to have the cache contents of normal execution), such that if the speculation is confirmed, the cache or cache set initially delegated for speculative execution can immediately join the cache set used for primary or non-speculative execution. Furthermore, the initial cache set corresponding to the cache or cache set initially delegated for speculative execution may be removed from the group of cache sets used for primary or non-speculative execution. In such an embodiment, circuitry (e.g., circuitry including background synchronization circuitry) may be configured to synchronize caches or cache sets in the background to reduce the impact of cache set synchronization on the processor's cache usage. Furthermore, synchronization of the caches or cache sets may continue until the speculation is abandoned, or until the speculation is confirmed and synchronization is complete. Synchronization may optionally include synchronization with memory (e.g., writeback).

[0053] In some embodiments, a cache system may include a first cache and a second cache, as well as connections to a command bus coupled between the cache system and a processor, an address bus coupled between the cache system and the processor, a data bus coupled between the cache system and the processor, and an execution type signal line from the processor that identifies an execution type (e.g., see cache systems 200 and 400). Such a cache system may also include logic circuitry coupled to control the first cache and the second cache based on the execution type, and the cache system may be configured to be coupled between the processor and a memory system. Furthermore, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache is configured to service a command from the command bus for accessing the memory system, the logic circuitry may be configured to copy a portion of the contents cached in the first cache to the second cache (e.g., see operation 1202). Furthermore, the logic circuitry may be configured to copy the portion of the contents cached in the first cache to the second cache independently of a current command received on the command bus.

[0054] Additionally, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache is configured to service commands from the command bus for accessing the memory system, the logic circuitry may be configured to service subsequent commands from the command bus using the second cache in response to the execution type changing from the first type to a second type indicating speculative execution of instructions by the processor (e.g., see operation 1208). In such an example, the logic circuitry may be configured to complete synchronizing a portion of the contents from the first cache to the second cache before servicing subsequent commands after the execution type changes from the first type to the second type (e.g., see operation 1208). Figure 12 ). The logic circuitry may also be configured to continue synchronizing portions of the content from the first cache to the second cache when servicing subsequent commands (eg, see operation 1210).

[0055] In such an embodiment, the cache system may further include configurable data bits, wherein the logic circuit is further coupled to control the first cache and the second cache based on the configurable data bits. In addition, in such an embodiment, the cache system may further include a plurality of cache sets. For example, the first cache and the second cache may together include a plurality of cache sets, and the plurality of cache sets may include the first cache set and the second cache set. The cache system may also include a plurality of registers respectively associated with the plurality of cache sets. The plurality of registers may include a first register associated with the first cache set and a second register associated with the second cache set. Furthermore, in such an embodiment, the logic circuit may be further coupled to control the plurality of cache sets based on the plurality of registers.

[0056] In some embodiments, a cache system may include multiple cache sets, the multiple cache sets including a first cache set and a second cache set. The cache system may also include multiple registers associated with the multiple cache sets, the multiple registers including a first register associated with the first cache set and a second register associated with the second cache set. In such an embodiment, the cache system may include multiple caches, the multiple caches including a first cache and a second cache, and the first cache and the second cache may together include at least a portion of the multiple cache sets. Such a cache system may also include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, and a connection to an execution type signal line from the processor that identifies an execution type, as well as logic circuitry coupled to control the multiple cache sets based on the execution type.

[0057] In such an embodiment, the cache system may be configured to be coupled between the processor and the memory system. Furthermore, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache set is configured to service a command from a command bus for accessing the memory system, the logic circuitry may be configured to copy a portion of contents cached in the first cache set to the second cache set. The logic circuitry may also be configured to copy the portion of contents cached in the first cache set to the second cache set independently of a current command received on the command bus.

[0058] Furthermore, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache set is configured to service commands from the command bus for accessing the memory system, the logic circuitry may be configured to service subsequent commands from the command bus using the second cache set in response to the execution type changing from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuitry may also be configured to complete synchronizing a portion of the contents from the first cache set to the second cache set before servicing subsequent commands after the execution type changes from the first type to the second type. The logic circuitry may also be configured to continue synchronizing the portion of the contents from the first cache set to the second cache set when servicing subsequent commands. Furthermore, the logic circuitry may be further coupled to control the plurality of cache sets based on a plurality of registers.

[0059] In addition to using a shadow cache to ensure speculative execution and synchronizing content between the main and shadow caches to preserve content cached in the main cache in preparation for accepting content from the shadow cache, backup cache sets can also be used to accelerate speculative execution. Furthermore, backup cache sets can be used to accelerate speculative execution without using a shadow cache. The use of backup cache sets is suitable for shadow cache implementations because data stored in cache sets used as shadow caches can be verified and therefore used for normal execution, and some cache sets used as main caches may not be ready for use as shadow caches. Therefore, one or more cache sets can be used as backup cache sets to avoid delays waiting for cache set availability. In other words, once speculation is confirmed, the contents of the cache set used as shadow cache are confirmed to be valid and up-to-date; therefore, the cache set previously used as the shadow cache for speculative execution is used for normal execution. However, some of the cache sets initially used as normal caches may not be ready for subsequent speculative execution. Therefore, one or more cache sets can be used as backup caches to avoid delays waiting for cache set availability and accelerate speculative execution.

[0060] In some embodiments, if synchronization from a cache set in the normal cache to the corresponding cache set in the shadow cache has not yet completed, the cache set in the normal cache cannot be immediately released for use by the next speculative execution. In this case, if no backup cache set exists, the next speculative execution must wait until synchronization is complete so that the corresponding cache set in the normal cache can be released. This is just one example of when a backup cache set is beneficial and can be added to an embodiment. Furthermore, there are many other situations where a cache set in the normal cache cannot be immediately released, so a backup cache set can be useful.

[0061] Furthermore, in some embodiments, speculative execution may reference memory regions that do not overlap with memory regions in cache sets used for normal cache. Due to the results of speculative execution, cache sets in both the shadow cache and the normal cache may all reside in the normal cache. This may also cause delays, as the cache system takes time to free up cache sets to support the next speculative execution. To free up cache sets, the cache system may identify cache sets, such as the least used cache sets, and synchronize the cache sets with the memory system. If the cache has newer data than the memory system, the data may be written to the memory system.

[0062] Additionally, systems using a standby cache set may also employ background synchronization circuitry, such as Figure 11A and 11B . In some embodiments, the background synchronization circuitry 1102 may be part of the logic circuitry 606 or 1006. When the initial speculation is confirmed, the cache set used in the initial speculation may be swapped to join the cache set used for the main execution. Instead of using the cache set from the previous main execution that is being used in the case of speculation failure, the backup cache set may be immediately made available for the next speculative execution. In addition, the backup cache set may be updated for the next speculative execution via the background synchronization circuitry. And, due to the background synchronization, the backup cache set may be ready for use when the cache set currently used for speculative execution is ready to be accepted for normal execution. In this way, there is no delay in waiting for the use of the next cache set for the next speculative execution. In preparation for the next speculative execution, the backup cache set may be synchronized to the normal cache set that is likely to be used for the next speculative execution or the least used cache set in the system.

[0063] In addition to using shadow caches, synchronizing the contents between the main cache and the shadow cache, and using alternate cache sets, extended tags can also be used to improve the use of interchangeable caches and cache sets for different types of execution (e.g., speculative and non-speculative execution) by the processor. There are many different ways to use extended tags to address cache sets and cache blocks within a cache system. Two example ways are shown in Figure 16 and 17 middle.

[0064] Generally speaking, cache sets and cache blocks can be selected via memory addresses. In some examples, selection is via set associativity. Figure 16 and 17The two instances in use set association. Figure 16 In , set associativity is implicitly defined (e.g., by an algorithm that can be used to determine which tags should be in which cache set for a given execution type). Figure 17 In [ ] , set associativity is implemented via the bits of the cache set index in the memory address. In addition, Figure 16 and 17 Some of the functionality described in can be implemented without using set associativity (but this is not described in Figure 16 and 17 (depicted in).

[0065] In some embodiments, comprising Figure 16 and 17 In the embodiment of FIG. 1 , a block index may be used as an address within an individual cache set to identify a specific cache block within the cache set. Also, an extended tag may be used as the address of the cache set. The block index of the memory address may be used for each cache set to obtain a cache block and a tag associated with the cache block. In addition, as Figure 16 and 17 As shown in , the tag comparison circuit can compare the extended tag generated from the cache set with the extended cache tag generated from the memory address and the current execution type. The output of the comparison can be a cache hit or a miss. The construction of the extended tag ensures that there is at most one hit among the cache sets. If there is a hit, then the cache block from the selected cache set provides the output. Otherwise, the data associated with the memory address is not cached in any of the cache sets or is output from any of the cache sets. In short, Figure 16 and 17 The extended tag depicted in is used to select a cache set, and the block index is used to select a cache block and its tag within the cache set.

[0066] In addition, if Figure 17 As shown in FIG, the combination of tags and cache set indexes in the system can provide functionality comparable to that of using only tags (e.g., Figure 16 ). However, in Figure 17 By separating the tag and the cache set index, the cache set does not have to store redundant copies of the cache set index, since the cache set can be associated with a cache set register to hold the cache set index. Figure 16 In , a cache set does need to store a redundant copy of the cache set indicator in each of the blocks in the cache set. Figure 16In the embodiment depicted in FIG, the tags have the same cache set indicator, so the indicator can be stored in a register for the cache set (e.g., see FIG. Figure 17 The benefit of using a cache set register is that the length of the tag can be shorter than an embodiment without a cache set register.

[0067] Shown in Figure 16 and 17 Both embodiments in have cache set registers configured to store execution types, so that corresponding cache sets can be used to implement different execution types (e.g., speculative and non-speculative execution types). Figure 17 The embodiment in the embodiment includes a register further configured to store an execution type and a cache set index. When the execution type is combined with the cache set index to form an extended cache set index, the extended cache set index can be used to select one of the cache sets without relying on addressing via the cache block's tags. Furthermore, when comparing the tag from the selected cache set with the tag in the address to determine a hit or miss, the two-step selection can be similar to a conventional two-step selection using the cache set index, or can be combined with the extended tag to support the interchange of cache sets of different execution types.

[0068] In addition to using extended tags and other techniques disclosed herein to improve the use of interchangeable caches and cache sets for different types of execution by a processor, circuitry included in or connected to a cache system can be used to map physical outputs from cache sets of a cache hardware system to logical main caches and logical shadow caches for normal and speculative execution, respectively, by the processor. The mapping can be based on at least one control register (e.g., a physical-to-logical-set-mapping (PLSM) register).

[0069] Furthermore, disclosed herein is a method for providing a system having a plurality of circuits with a plurality of mapping circuits (such as those shown in FIG. Figure 18A computing device that includes a cache system of interchangeable cache sets (mapping circuitry 1830 in the processor) that maps physical cache set outputs to logical cache set outputs. A processor coupled to the cache system can execute two types of threads, such as speculative and non-speculative execution threads. Speculative threads execute speculatively with conditions that have not yet been evaluated. The data for the speculative threads may be in a logical shadow cache. The data for the non-speculative threads may be in a logical main cache or a regular cache. Subsequently, when the result of the evaluated condition becomes available, when the condition requires the execution of the thread or the thread is removed, the system can retain the result of executing the speculative thread. Through the mapping circuitry, the hardware circuitry used for the shadow cache can be repurposed as hardware circuitry for the main cache by changing the contents of a control register. Thus, for example, if a speculative thread needs to be executed, then there is no need to synchronize the main cache with the shadow cache.

[0070] In conventional caches, each cache set is statically associated with a specific value of "index S" / "block index L." In the cache system disclosed herein, any cache set can be used for any index value S / L and any purpose in the main cache or shadow cache. A cache set is available in a cache set register associated with the cache set and can be defined by the data in the cache set register. Selection logic can then be used to select the appropriate result based on the index value of S / L and the manner in which the cache set is being used.

[0071] For example, four cache sets (cache set 0 through set 3) may initially be used as primary caches with S / L = 00, 01, 10, and 11, respectively. Assuming speculative execution does not change the cache sets defined by 01, 10, and 11, the fourth cache set may be used as a speculative cache with S / L = 00. If the results of speculative execution are needed, the mapping data may be changed to indicate that primary caches with S / L = 00, 01, 10, and 11 are used for the fourth cache set, cache set 1, cache set 2, and cache set 3, respectively. Cache set 0 may then be released or invalidated for subsequent use in speculative execution. If the next speculative execution requires changing cache set S / L to 01, cache set 0 may be used as a shadow cache (e.g., content copied from cache set 1 and used to look up addresses with S / L equal to '01').

[0072] Furthermore, the cache system and processor not only swap back and forth between the intended main thread and the intended speculative threads.Consider the speculative execution of the following pseudo program.

[0073] Instruction A;

[0074] If condition = true,

[0075] Then instruction B;

[0076] End the conditional loop;

[0077] Directive C; and

[0078] Instruction D.

[0079] For the pseudo program, the processor can run two threads.

[0080] Thread A:

[0081] Instruction A;

[0082] Directive C; and

[0083] Instruction D.

[0084] Thread B:

[0085] Instruction A;

[0086] Instruction B;

[0087] Directive C; and

[0088] Instruction D.

[0089] Execution of instruction B is speculative because it depends on the test result of "condition = true" rather than "condition = false". Execution of instruction B is required only when condition = true. When the result of the test "condition = true" becomes available, execution of thread A reaches instruction D, and execution of thread A can reach instruction C. If the test result requires execution of instruction B, then the cache contents of thread B are correct and the cache contents of thread A are incorrect. All changes made in the cache according to thread B should then be retained, and the processor can continue execution of instruction C using the cache with the results of executing instruction B; and thread A is terminated. Since the changes made according to thread B are in the shadow cache, the contents of the shadow cache should be accepted as the main cache. If the test result does not require execution of instruction B, then the results of thread B are discarded (e.g., the contents of the shadow cache are discarded or invalidated).

[0090] The cache sets used for the shadow and normal caches can be swapped or changed based on mapping circuitry and control registers (e.g., physical-to-logical-set-mapping (PLSM) registers). In some embodiments, the cache system may include multiple cache sets, the multiple cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system may also include a connection to a command bus coupled between the cache system and the processor, and a connection to an address bus coupled between the cache system and the processor. The cache system may also include a control register and mapping circuitry coupled to the control register to map corresponding physical outputs of the multiple cache sets to the first logical cache and the second logical cache based on a state of the control register. The cache system may be configured to be coupled between the processor and the memory system.

[0091] When the connection to the address bus receives a memory address from the processor and when the control register is in a first state, the mapping circuitry may be configured to: map the first physical output to the first logical cache for a first type of execution by the processor to implement commands received from the command bus for accessing the memory system via the first cache set during the first type of execution; and map the second physical output to the second logical cache for a second type of execution by the processor to implement commands received from the command bus for accessing the memory system via the second cache set during the second type of execution. Furthermore, when the connection to the address bus receives a memory address from the processor and when the control register is in a second state, the mapping circuitry may be configured to: map the first physical output to the second logical cache for implementing commands received from the command bus for accessing the memory system via the first cache set during the second type of execution; and map the second physical output to the first logical cache for implementing commands received from the command bus for accessing the memory system via the second cache set during the first type of execution.

[0092] In some embodiments, the first logical cache is a normal cache for non-speculative execution by the processor, and the second logical cache is a shadow cache for speculative execution by the processor.

[0093] In addition, in some embodiments, the cache system may further include a plurality of registers respectively associated with a plurality of cache sets, the plurality of registers including a first register associated with a first cache set and a second register associated with a second cache set. The cache system may also include logic circuitry coupled to the processor to control the plurality of cache sets based on the plurality of registers. When a memory address is received from the processor via the connection to the address bus, the logic circuitry may be configured to generate a set index from at least the memory address, and to determine whether the generated set index matches the content stored in the first register or the content stored in the second register. Furthermore, the logic circuitry may be configured to implement a command received in the connection to the command bus via the first cache set in response to the generated set index matching the content stored in the first register, and to implement the command via the second cache set in response to the generated set index matching the content stored in the second register.

[0094] In some embodiments, the mapping circuitry may be part of or connected to the logic circuitry, and the state of the control register may control the state of a cache set in the plurality of cache sets. In some embodiments, the state of the control register may control the state of a cache set in the plurality of cache sets by changing a valid bit of each block in the cache set.

[0095] In addition, in some examples, the cache system may further include a connection to a speculation state signal line from the processor that identifies a state of speculative execution of instructions by the processor. The connection to the speculation state signal line may be configured to receive the state of speculative execution, and the state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to change the state of the first and second cache sets via the control register if the state of speculative execution indicates that the result of speculative execution will be accepted (e.g., when speculative execution will become the main execution thread). And, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to maintain the state of the first and second cache sets unchanged via the control register if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0096] In some embodiments, the mapping circuit is part of or connected to the logic circuit, and the state of the control register can control the state of a cache register in the plurality of cache registers via the mapping circuit. In such an example, the cache system may further include a connection to a speculative state signal line from the processor that identifies the state of speculative execution of instructions by the processor. The connection to the speculative state signal line can be configured to receive the state of speculative execution, and the state of speculative execution indicates whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuit can be configured to change the state of the first and second registers via the control register if the state of speculative execution indicates that the result of speculative execution will be accepted. And, when the execution type changes from speculative execution to non-speculative execution, the logic circuit can be configured to maintain the state of the first and second registers unchanged via the control register if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0097] In addition, the present disclosure includes techniques for ensuring speculative instruction execution using multiple interchangeable caches, each of which is interchangeable as a shadow cache or a main cache. Speculative instruction execution can be performed in a processor of a computing device. The processor can execute two different types of threads of instructions. One of the threads can be executed speculatively (e.g., under a condition that has not yet been evaluated). The data for the speculative thread can be in a logical cache that acts as a shadow cache. The data for the main thread can be in a logical cache that acts as a main cache. Subsequently, when the result of the evaluated condition becomes available, the processor can retain the result of executing the speculative thread when the condition requires the execution of the thread, or remove the result. The hardware circuit of the cache that acts as a shadow cache can be repurposed as the hardware circuit of the main cache by changing the contents of a register. Therefore, if a speculative thread needs to be executed, then there is no need to synchronize the main cache with the shadow cache.

[0098] The technology disclosed herein also relates to the use of a unified cache structure that can be used to implement primary and shadow caches with improved performance. In the unified cache structure, a set of registers can be used to dynamically remap the results of cache sets to swap between the primary cache and the shadow cache. When speculative execution succeeds, the cache set used with the shadow cache has the correct data and can be remapped to the corresponding cache set for the primary cache. This eliminates the need to copy data from the shadow cache to the primary cache, as used by other techniques that use shadow and primary caches.

[0099] Generally speaking, a cache can be configured as multiple block sets. Each block set can have multiple blocks, and each block can hold several bytes. A memory address can be split into three segments for accessing the cache: a tag, a block index (which can be used to address a set within the multiple sets), and a cache block (which can be used to address a byte in a byte block). For each block in a set, the cache not only stores the data from the memory, but also stores a tag for the address from which the data was loaded and a field indicating whether the contents of the block are valid. Data can be retrieved from the cache using the block index (e.g., set ID) and the cache block (e.g., byte ID). The tag in the retrieved data is compared with the tag portion of the address. A matching tag means that the data is cached for that address. Otherwise, it means that the data can be cached for another address that maps to the same location in the cache.

[0100] In the case of a technique using multiple interchangeable caches, the physical cache sets of the interchangeable caches are not hardwired as primary or shadow caches. A physical cache set can be used as either a primary or shadow cache set. Furthermore, a register set can be used to specify whether a physical cache set is currently being used as a primary or shadow cache set. Generally speaking, a mapping can be configured to translate the output of a physical cache set into the logical output of a corresponding cache set represented by a block index (e.g., set ID) and a primary or shadow state. Remapping allows any available physical cache to be used as a shadow cache.

[0101] In some embodiments, the unified cache architecture can remap shadow caches (e.g., speculative caches) to primary caches and can remap primary caches to speculative caches. It should be understood that the design can include any number of caches or cache sets that can be interchanged between primary caches or cache sets or speculative caches or cache sets.

[0102] It should be understood that there is no physical distinction in the hardwiring between a primary cache or cache set and a speculative cache or cache set. Furthermore, in some embodiments, there is no physical distinction in the hardwiring of the logical units described herein. It should be understood that interchangeable caches or cache sets do not have different cache capacities and structures. Otherwise, such caches or cache sets would not be interchangeable. Furthermore, a physical cache set can be dynamically configured as primary or speculative, e.g., without a priori determination.

[0103] Furthermore, it should be understood that interchangeability occurs at the cache hierarchy level rather than the cache block level. Interchangeability at the cache block level may allow the main cache and shadow cache to have different capacities; and therefore, not interchangeable.

[0104] Furthermore, in some embodiments, when speculation by the processor succeeds and a cache is being used as a primary cache and another cache is being used as a speculative or shadow cache, the valid bits associated with the cache index block of the primary cache are all set to indicate invalid (e.g., by a "0" bit value to indicate invalid). In such embodiments, the initial state of all valid bits of the speculative cache indicates invalid, but then changes to indicate valid due to the successful speculation. In other words, the previous state of the primary cache is invalidated, and the previous state of the speculative cache is set from invalid to valid and accessible to the primary thread.

[0105] In some embodiments, the PLSM register for the primary cache may be changed from indicating the primary cache to indicating the speculative cache. Changing the indication from the primary cache to the speculative cache by the PLSM register may be performed by the PLSM register receiving a valid bit indicating an invalid primary cache after a successful speculation. For example, after a successful speculation, and in the case where the first cache is initially the primary cache and the second cache is initially the speculative cache, an invalid indication of bit "0" may replace the least significant bit in the 3-bit PLSM register for the first cache, which may change "011" to "010" (or change "3" to "2"). Furthermore, for the 3-bit PLSM register for the second cache, a valid indication of bit "1" may replace the least significant bit in the PLSM register, which may change "010" to "011" (or change "2" to "3"). Thus, as shown in the example, a PLSM register that was initially used for the first cache (e.g., the primary cache) and initially selected the first cache may be changed to select the second cache (e.g., the speculative cache) after a successful speculation. Furthermore, as shown in the example, a PLSM register that was originally used for and initially selected the second cache (e.g., the speculative cache) is changed to select the first cache (e.g., the primary cache) after a successful speculation. With this design, the main thread of the processor may first access the cache that was initially designated as the primary cache, and then, after a successful speculation by the processor, access the cache that was initially designated as the speculative cache. Furthermore, a speculative thread of the processor may first access the cache that was initially designated as the speculative cache, and then, after a successful speculation by the processor, access the cache that was initially designated as the primary cache.

[0106] Figure 1AMemory address 102a is shown segmented into a tag portion 104a, a block index portion 106a, and a block offset portion 108a. According to some embodiments of the present disclosure, an execution type 110a may be combined with portions of the memory address to control cache operations. The total number of bits used to control addressing in a cache system according to some embodiments disclosed herein is A bits. Furthermore, the sum of the bits used for portions 104a, 106a, and 108a and the execution type 110a is equal to A bits. The tag portion 104a is K bits, the block index portion 106a is L bits, the block offset portion 108a is M bits, and the execution type 110a is one or more T bits.

[0107] For example, for a given execution type, data for all memory addresses having the same block index portion 106a and block offset portion 108a may be stored in the same physical location in the cache. When data at memory address 102a is stored in the cache, tag portion 104a also stores a block containing the memory address to identify which of the addresses having the same block index portion 106a and block offset portion 108a is currently cached at that location in the cache.

[0108] Data at a memory address may be cached in different locations in the unified cache structure for different types of execution. For example, data may be cached in the main cache during non-speculative execution; and then cached in the shadow cache during speculative execution. The execution type 110a may be combined with the tag portion 104a to select from a cache that may be dynamically configured for use in both main and speculative execution without restriction. There may be many different ways of implementing the use of the combination of the execution type 110a and the tag portion 104a to make the selection. For example, Figure 2 and 4 The logic circuit 206 depicted in FIG. 1 may use the execution type 110 a and / or the tag portion 104 a .

[0109] In a relatively simple embodiment, execution type 110a can be combined with tag portion 104a to form an extended tag when determining whether a cache location contains data for memory address 102a or data for the current type of execution of an instruction. For example, a cache system can use tag portion 104a to select a cache location without distinguishing between execution types; and when tag portion 104a is combined with execution type 110a to form an extended tag, the extended tag can be used in a manner similar to selecting cache locations for different types of execution (e.g., speculative execution and non-speculative execution), allowing shadow cache techniques to be implemented to enhance security. Furthermore, because information about the execution type associated with cached data is shared across many cache locations (e.g., within a cache set, or within a cache having multiple cache sets), it is not necessary to store the execution type for each location; and a selection mechanism (e.g., a switch, filter, or multiplexer, such as a data multiplexer) can be used to implement the selection based on the execution type. Alternatively, physical caches or physical cache sets used for different types of execution can be remapped to logical caches pre-associated with the different types of execution, respectively. Thus, the use of the logical cache may be selected based on the execution type 110a.

[0110] Figure 1B Another way of dividing the memory address 102b into parts to control cache operations is shown. The memory address 102b is divided into a tag portion 104b, a cache set index portion 112b, a block index portion 106b, and a block offset portion 108b. The total bits of the memory address 102b are A bits. And, the sum of the bits used for the four parts is equal to the A bits of the address 102b. The tag portion 104b is K bits, the block index portion 106b is L bits, the block offset portion 108b is M bits, and the cache set index portion 112b is S bits. Therefore, for the address 102b, its A bits = K bits + L bits + M bits + S bits. According to Figure 1B The segmentation of memory addresses 102b allows for the enforcement of set associativity when caching data.

[0111] For example, multiple cache sets may be configured in a cache, where each cache set may be addressed using a cache set index 112b. Data sets associated with the same cache set index may be cached in the same cache set. Tag portions 104b of data blocks cached in a cache set may be stored in the cache in association with the data blocks. When an address 102b is used to retrieve data from a cache set identified using a cache set index 112b, the tag portion of the data block stored in the cache set may be retrieved and compared with tag portion 104b to determine whether there is a match between the tag 104b of the address 102b of the access request and the tag 104b stored in the cache set identified by the cache set index 112b and for the cache block identified by the block index 106b. If there is a match (e.g., a cache hit), the cache block stored in the cache set is for memory address 112b; otherwise, the cache block stored in the cache set is for another memory address having the same cache set index 112b and the same block index 106b as memory address 102b, resulting in a cache miss. In response to the cache miss, the cache system accesses main memory to retrieve the data block based on address 102b. To implement shadow caching techniques, cache set index 112b can be combined with execution type 110a to form an extended cache set index. Thus, an extended cache set index that identifies both the cache set index and the execution type can be used to address cache sets for different types of executions with different cache set indices.

[0112] exist Figure 1B , a cache set index portion 112b is extracted from a predetermined portion of address 102b. Data stored at memory addresses having different set indexes may be cached in different cache sets of a cache to enforce set associativity when caching data. A cache set of a cache may be selected using a cache set index (e.g., portion 112b of address 102b). Alternatively, Figure 1C The partitioning scheme described in

[0045] implements cache set associativity via tag 104c containing a cache set indicator. Optionally, the cache set indicator is calculated from tag 104c and used as a cache set index to address a cache set. Alternatively, set associativity may be implemented directly via tag 104c such that for a cache hit, the cache set storing tag 104c is selected; and when no cache set stores tag 104c, a cache miss is determined. Alternatively, address 102d may be as follows: Figure 1D104d for cache operations, wherein the tag portion 104d includes a cache set index 112d, wherein the cache set is not explicitly and separately addressed using the cache set index. For example, to implement the shadow cache technique, the combination of the execution type 110e and the tag 104e with an embedded cache set indicator ( Figure 1E ) can be used to select a cache set for the correct execution type and storing the same tag 104e for a cache hit. A cache miss is determined when no cache set has a matching execution type and stores the same tag 104e.

[0113] In addition, if Figure 1C As shown in Figure 1C Another way to control cache operation is depicted by partitioning the memory address 102c into parts. The memory address 102c is partitioned into a tag portion 104c having a cache set indicator, a block index portion 106c, and a block offset portion 108c. The total number of bits of the memory address 102c is A bits. And, the sum of the bits for the three parts is equal to the A bits of the address 102c. The tag portion 104c is K bits, the block index portion 106c is L bits, and the block offset portion 108c is M bits. Therefore, for the address 102c, its A bits = K bits + L bits + M bits. As mentioned, according to Figure 1C The segmentation of memory addresses 102c allows for the enforcement of set associativity when caching data.

[0114] In addition, if Figure 1D As shown in Figure 1D Another way to control cache operation by partitioning a memory address 102d into parts is depicted. The memory address 102d is partitioned into a tag portion 104d with a cache set index 112d, a block index portion 106d, and a block offset portion 108d. The total number of bits of the memory address 102d is A bits. Also, the sum of the bits for the three portions is equal to the A bits of the address 102d. The tag portion 104d is K bits, the block index portion 106d is L bits, and the block offset portion 108d is M bits. Thus, for the address 102d, its A bits = K bits + L bits + M bits. As mentioned, according to Figure 1D The segmentation of memory addresses 102d allows for the enforcement of set associativity when caching data.

[0115] In addition, if Figure 1E As shown in Figure 1E Another way of partitioning the memory address 102e into portions to control cache operations is depicted. Figure 1EMemory address 102e is shown partitioned into a tag portion 104e having a cache set indicator, a block index portion 106e, and a block offset portion 108e. According to some embodiments of the present disclosure, an execution type 110e may be combined with portions of the memory address to control cache operations. The total number of bits used to control addressing in a cache system according to some embodiments disclosed herein is A bits. Furthermore, the sum of the bits used for portions 104e, 106e, and 108e and the execution type 110e is equal to A bits. The tag portion 104e is K bits, the block index portion 106e is L bits, the block offset portion 108e is M bits, and the execution type 110e is T bits.

[0116] Figure 2 、 3A and 3B show example aspects of example computing devices according to some embodiments of the present disclosure, each computing device including a cache system having a cache that can perform swaps for a first type and a second type (e.g., for implementing shadow cache techniques with enhanced security).

[0117] Figure 2 Specifically shown are aspects of an example computing device including a cache system 200 having multiple caches (e.g., see caches 202a, 202b, and 202c). The example computing device is also shown with a processor 201 and a memory system 203. The cache system 200 is configured to be coupled between the processor 201 and the memory system 203.

[0118] The cache system 200 is shown as including a connection 204a to a command bus 205a coupled between the cache system and the processor 201. The cache system 200 is shown as including a connection 204b to an address bus 205b coupled between the cache system and the processor 201. Figure 1A 、 1B , 1C, 1D, and 1E may each be communicated via an address bus 205b depending on the implementation of the cache system 200. The cache system 200 is also shown as including a connection 204c to a data bus 205c coupled between the cache system and the processor 201. The cache system 200 is also shown as including a connection 204d to an execution type signal line 205d from the processor 201 that identifies the execution type.

[0119] Not present Figure 2 As shown in FIG, the cache system 200 may include configurable data bits. The configurable data bits may be included in the Figure 3A The data 312 in the first state in or for the data 312 and may be included in the data shown in Figure 3BThe data 314 in the second state in or for the data 314. Memory access requests from and memory usage by the processor may be controlled via the command bus 205a, the address bus 205b, and the data bus 205c.

[0120] In some embodiments, cache system 200 may include a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b). Figure 2 , cache system 200 may include logic circuitry 206 coupled to processor 201. Furthermore, in such embodiments, logic circuitry 206 may be configured to control a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b) based on configurable data bits.

[0121] When the configurable data bit is in a first state (e.g., see Figure 3A 312), the logic circuit 206 may be configured to implement a command received from the command bus 205a for accessing the memory system 203 via the first cache when the execution type is the first type. In addition, when the configurable data bit is in the first state (e.g., see Figure 3A 312 depicted in FIG), the logic circuit 206 may be configured to implement a command received from the command bus 205a for accessing the memory system 203 via the second cache when the execution type is the second type.

[0122] When the configurable data bit is in the second state (see, for example, Figure 3B 314), the logic circuit 206 may be configured to implement a command received from the command bus 205a for accessing the memory system 203 via the second cache when the execution type is the first type. In addition, when the configurable data bit is in the second state (e.g., see Figure 3B 314 depicted in FIG), the logic circuit 206 may be configured to implement a command received from the command bus 205a for accessing the memory system 203 via the first cache when the execution type is the second type.

[0123] In some embodiments, when the execution type changes from the second type to the first type, the logic circuit 206 is configured to toggle the configurable data bit.

[0124] In addition, if Figure 2As shown in FIG, cache system 200 further includes a connection 208a to a second command bus 209a coupled between the cache system and memory system 203. Cache system 200 also includes a connection 208b to a second address bus 209b coupled between the cache system and memory system 203. Cache system 200 also includes a connection 208c to a second data bus 209c coupled between the cache system and memory system 203. When the configurable data bit is in a first state, when the execution type is a first type (e.g., non-speculative), logic circuit 206 is configured to provide a command for accessing memory system 203 via the first cache to second command bus 209a. When the configurable data bit is in a first state, when the execution type is a second type (e.g., speculative), logic circuit 206 is further configured to provide a command for accessing memory system 203 via the second cache to second command bus 209a.

[0125] When the configurable data bit is in the second state, when the execution type is the first type, the logic circuit 206 is configured to provide a command for accessing the memory system 203 via the second cache to the second command bus 209a. In addition, when the configurable data bit is in the second state, when the execution type is the second type, the logic circuit 206 is configured to provide a command for accessing the memory system 203 via the first cache to the second command bus 209a.

[0126] In some embodiments, connection 204a to command bus 205a is configured to receive a read command or a write command from processor 201 for accessing memory system 203. Furthermore, connection 204b to address bus 205b can be configured to receive a memory address from processor 201 for accessing memory system 203 for a read command or a write command. Furthermore, connection 204c to data bus 205c can be configured to communicate data to processor 201 for reading data in response to a read command. Furthermore, connection 204c to data bus 205c can also be configured to receive data from processor 201 for writing to memory system 203 in response to a write command. Furthermore, connection 204d to execution type signal line 205d can be configured to receive an identification of an execution type from processor 201 (e.g., an identification of a non-speculative or speculative type of execution by the processor).

[0127] In some embodiments, logic circuit 206 may be configured to select a first cache for a memory access request (e.g., one of the commands received from a command bus for accessing a memory system) from processor 201 when the configurable data bit is in a first state and connection 204d to execution type signal line 205d receives an indication of a first type (e.g., non-speculative). Furthermore, logic circuit 206 may be configured to select a second cache for a memory access request from processor 201 when the configurable data bit is in a first state and connection 204d to execution type signal line 205d receives an indication of a second type (e.g., speculative). Furthermore, logic circuit 206 may be configured to select the second cache for a memory access request from processor 201 when the configurable data bit is in a second state and connection 204d to execution type signal line 205d receives an indication of the first type. Furthermore, the logic circuit 206 may be configured to select the first cache for the memory access request from the processor 201 when the configurable data bit is in the second state and the connection 204d to the execution type signal line 205d receives the second type of indication.

[0128] Figure 3A Specifically shown are aspects of an example computing device including a cache system (e.g., cache system 200) having multiple caches (e.g., see caches 302 and 304). The example computing device is also shown having registers 306 that store data 312 that may include configurable bits. Registers 306 may be connected to or part of logic circuitry 206. Figure 3A , it is shown that during a first time instance ("time instance X"), register 306 stores data 312, which may be a configurable bit in a first state. Content 308a received from a first cache (e.g., cache 302) during the first time instance includes content for a first type of execution. Also, content 310a received from a second cache (e.g., cache 304) during the first time instance includes content for a second type of execution.

[0129] Figure 3B Specifically shown are aspects of an example computing device including a cache system (e.g., cache system 200) having multiple caches (e.g., see caches 302 and 304). The example computing device is also shown having registers 306 that store data 314 that may include configurable bits. Figure 3B, it is shown that during a second time instance ("time instance Y"), register 306 stores data 314, which may be a configurable bit in a second state. Content 308b received from a first cache (e.g., cache 302) during the second time instance includes content for the second type of execution. Also, content 310b received from a second cache (e.g., cache 304) during the second time instance includes content for the first type of execution.

[0130] The illustrated lines 320 connecting register 306 to caches 302 and 304 may be part of logic circuitry 206 .

[0131] In some embodiments, instead of using configurable bits to control the use of the caches of cache system 200, another form of data can be used to control the use of the caches of the cache system. For example, logic circuit 206 can be configured to control the first cache (e.g., see cache 202a) and the second cache (e.g., see cache 202b) based on different data stored in register 306 that is not a configurable bit. In this example, when register 306 stores first data or is in a first state, the logic circuit can be configured to: implement commands received from the command bus for accessing the memory system via the first cache when the execution type is the first type; and implement commands received from the command bus for accessing the memory system via the second cache when the execution type is the second type. Furthermore, when register 306 stores second data or is in a second state, the logic circuit can be configured to: implement commands received from the command bus for accessing the memory system via the second cache when the execution type is the first type; and implement commands received from the command bus for accessing the memory system via the first cache when the execution type is the second type.

[0132] Figure 4 、 5A 5B show example aspects of example computing devices according to some embodiments of the present disclosure, each computing device including a cache system having interchangeable caches for main or normal type execution (e.g., non-speculative execution) and speculative execution.

[0133] Figure 4 Specifically showing the inclusion of multiple caches (see, for example, Figure 4 Aspects of an example computing device of a cache system 400 including caches 202a, 202b, and 202c depicted in FIG. Figure 4 In FIG, the example computing device is also shown as having a processor 401 and a memory system 203. Figure 4As shown, cache system 400 is similar to cache system 200 , but cache system 400 also includes a connection 402 to a speculation state signal line 404 from processor 401 that identifies the state of speculative execution of instructions by processor 401 .

[0134] Similarly, cache system 400 is shown as including a connection 204a to a command bus 205a coupled between the cache system and processor 401. System 400 also includes a connection 204b to an address bus 205b coupled between the cache system and processor 401. Figure 1A 、 1B , 1C, 1D, and 1E may each be communicated via an address bus 205b depending on the implementation of the cache system 400. The system 400 also includes a connection 204c to a data bus 205c coupled between the cache system and the processor 401. It also includes a connection 204d to an execution type signal line 205d from the processor 401 that identifies a non-speculative execution type or a speculative execution type. Figure 4 As shown in FIG, the cache system 400 may also include configurable data bits. The configurable data bits may be included in the Figure 5A The data 312 in the first state in or for the data 312 and may be included in the data shown in Figure 5B The data 314 in the second state or the data 314 in the second state.

[0135] In some embodiments, cache system 400 may include a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b). In such embodiments, Figure 4 , cache system 400 may include logic circuitry 406 coupled to processor 401. Furthermore, in such an embodiment, logic circuitry 406 may be configured to control a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b) based on a configurable data bit. When the configurable data bit is in a first state (e.g., see cache 202a), the cache 406 may be configured to control a first cache (e.g., see cache 202b). Figure 5A ), the logic circuit 406 may be configured to: implement the command received from the command bus 205a for accessing the memory system 203 via the first cache when the execution type is non-speculative; and implement the command received from the command bus 205a for accessing the memory system 203 via the second cache when the execution type is speculative. When the configurable data bit is in the second state (e.g., see Figure 5B314), the logic circuit 406 may be configured to implement the command received from the command bus 205a for accessing the memory system 203 via the second cache when the execution type is non-speculative. In addition, when the configurable data bit is in the second state (e.g., see Figure 5B 314 depicted in FIG), the logic circuit 406 may be configured to implement a command received from the command bus 205a for accessing the memory system 203 via the first cache when the execution type is a speculative type.

[0136] In some embodiments, for example Figure 4 , the first type may be configured to indicate non-speculative execution of the instruction by the processor. In this example, the second type may be configured to indicate speculative execution of the instruction by the processor. In this embodiment, cache system 400 may further include a connection 402 to a speculation status signal line 404 from processor 401 that identifies the status of speculative execution of the instruction by the processor. Connection 402 to speculation status signal line 404 may be configured to receive the status of speculative execution, and the status of speculative execution may indicate whether the result of the speculative execution will be accepted or rejected.

[0137] Furthermore, when the execution type changes from the second or speculative type to the first or non-speculative type, the logic circuitry 406 of the system 400 may be configured to toggle the configurable data bit if the state of speculative execution indicates that the result of the speculative execution will be accepted. Furthermore, when the execution type changes from the second or speculative type to the first or non-speculative type, the logic circuitry 406 of the system 400 may be configured to maintain the configurable data bit unchanged if the state of speculative execution indicates that the result of the speculative execution will be rejected.

[0138] Figure 5A Specifically shown are aspects of an example computing device including a cache system (e.g., cache system 400) having multiple caches (e.g., see caches 302 and 304). The example computing device is also shown having registers 306 storing data 312 that may include configurable bits. Figure 5A , it is shown that during a first time instance ("time instance X"), register 306 stores data 312, which may be a configurable bit in a first state. This is similar to Figure 3A , except that content 502a received from a first cache (e.g., cache 302) during a first time instance includes content for non-speculative execution. And, content 504a received from a second cache (e.g., cache 304) during a first time instance includes content for speculative execution.

[0139] Figure 5BSpecifically shown are aspects of an example computing device including a cache system (e.g., cache system 400) having multiple caches (e.g., see caches 302 and 304). The example computing device is also shown having registers 306 storing data 314 that may include configurable bits. Figure 5B , it is shown that during a second time instance ("time instance Y"), register 306 stores data 314, which may be a configurable bit in a second state. This is similar to Figure 3B , except that content 502b received from the first cache (e.g., cache 302) during the second time instance includes content for speculative execution. And, content 504b received from the second cache (e.g., cache 304) during the second time instance includes content for non-speculative execution.

[0140] In addition, similarly, Figure 5A and 5B , the illustrated lines 320 connecting registers 306 to caches 302 and 304 may be part of the logic circuitry 406 of cache system 400 .

[0141] In some embodiments, instead of using configurable bits to control the use of the caches of cache system 400, another form of data can be used to control the use of the caches of cache system 400. For example, logic circuitry 406 in system 400 can be configured to control a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b) based on different data stored in register 306 that is not a configurable bit. In this example, when register 306 stores first data or is in a first state, the logic circuitry can be configured to: implement commands received from the command bus for accessing the memory system via the first cache when the execution type is non-speculative; and implement commands received from the command bus for accessing the memory system via the second cache when the execution type is speculative. Furthermore, when register 306 stores second data or is in the second state, the logic circuit may be configured to: when the execution type is a non-speculative type, implement a command received from the command bus for accessing the memory system via the second cache; and when the execution type is a speculative type, implement a command received from the command bus for accessing the memory system via the first cache.

[0142] Some embodiments may include a cache system, and the cache system may include multiple caches, including a first cache and a second cache. The system may also include a connection to a command bus configured to receive a read command or a write command from a processor connected to the cache system for reading from or writing to a memory system. The system may also include a connection to an address bus configured to receive a memory address from the processor for accessing the memory system for a read command or a write command. The system may also include a connection to a data bus configured to: convey data to the processor for the processor to read the data for a read command; and receive data from the processor to write to the memory system for a write command. In this example, a memory access request from the processor and the memory used by the processor may be defined by the command bus, the address bus, and the data bus. The system may also include an execution type signal line configured to receive an identified execution type from the processor. The execution type is a first execution type or a second execution type (e.g., normal or non-speculative execution or speculative execution).

[0143] The system may also include a configurable data bit configured to be set to a first state (eg, "0") or a second state (eg, "1") to control selection of the first cache and the second cache for use by the processor.

[0144] The system may further include logic circuitry configured to select a first cache for use by the processor when the configurable data bit is in a first state and the execution type signal line receives an indication of a first type of execution. The logic circuitry may further be configured to select a second cache for use by the processor when the configurable data bit is in the first state and the execution type signal line receives an indication of a second type of execution. The logic circuitry may further be configured to select the second cache for use by the processor when the configurable data bit is in a second state and the execution type signal line receives an indication of the first type of execution. The logic circuitry may further be configured to select the first cache for use by the processor when the configurable data bit is in a second state and the execution type signal line receives an indication of the second type of execution.

[0145] In some embodiments, the first type of execution is speculative execution of instructions by the processor, and the second type of execution is non-speculative execution of instructions by the processor (e.g., normal or main execution). In such an example, the system may further include a connection to a speculation state signal line configured to receive a speculation state from the processor. The speculation state may be acceptance or rejection of a condition having nested instructions that are initially executed by speculative execution of the processor and subsequently executed by normal execution of the processor when the speculation state is acceptance of the condition.

[0146] In some embodiments, the logic circuit is configured to switch the configurable data bit from a first state to a second state when the speculative state received by the speculative state signal line is acceptance of the condition. The logic circuit may also be configured to maintain the state of the configurable data bit when the speculative state received by the speculative state signal line is rejection of the condition.

[0147] In some embodiments, the logic circuit is configured to select the second cache, as identified by the first state of the configurable data bit, and restrict use of the first cache, as identified by the first state of the configurable data bit, when the signal received by the execution type signal line changes from indicating normal execution to indicating speculative execution. With this change, the logic circuit can ignore / bypass the speculation state because the processor, during speculative execution, does not know whether instructions preformed under speculative execution should be executed by the main processor.

[0148] The logic circuit may also be configured to maintain the first state of the configurable data bit and select the first cache for the memory access request when the execution type signal line receives an indication of normal execution, when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of normal execution, and when the speculation state received by the speculation state signal line is a rejection of the condition.

[0149] In some embodiments, the logic circuit is configured to invalidate and discard the contents of the second cache when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of normal execution, and when the speculation state received by the speculation state signal line is a rejection of the condition.

[0150] In some embodiments, the system further includes a connection to a second command bus configured to communicate a read command or a write command to a memory system (e.g., including main memory). The read command or the write command may be received by the cache system from the processor. The system may also include a connection to a second address bus configured to communicate a memory address to the memory system. The memory address may be received by the cache system from the processor. The system may also include a connection to a second data bus configured to communicate data to the memory system for writing to the memory system and to receive data from the memory system for communication to the processor for reading by the processor. For example, a memory access request from the cache system to the memory system may be defined by the second command bus, the second address bus, and the second data bus.

[0151] In some embodiments, when the configurable data bit is in a first state, the logic circuit is configured to: provide a command for accessing the memory system via the first cache to the second command bus when the execution type is the first type; and provide a command for accessing the memory system via the second cache to the second command bus when the execution type is the second type. Furthermore, when the configurable data bit is in a second state, the logic circuit may be configured to: provide a command for accessing the memory system via the second cache to the second command bus when the execution type is the first type; and provide a command for accessing the memory system via the first cache to the second command bus when the execution type is the second type.

[0152] Some embodiments may include a system comprising a processor, a memory system, and a cache system coupled between the processor and the memory system. The cache system of the system may include a plurality of caches, the plurality of caches including a first cache and a second cache. The cache system of the system may also include a connection to a command bus coupled between the cache system and the processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, and a connection to an execution type signal line from the processor that identifies an execution type.

[0153] The cache system of the system may also include a configurable data bit, and logic circuitry coupled to the processor to control the first cache and the second cache based on the configurable data bit. When the configurable data bit is in a first state, the logic circuitry may be configured to: implement a command received from a command bus for accessing the memory system via the first cache when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via the second cache when the execution type is the second type. Furthermore, when the configurable data bit is in a second state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via the second cache when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via the first cache when the execution type is the second type.

[0154] In such a system, the first type may be configured to indicate non-speculative execution of instructions by the processor, and the second type may be configured to indicate speculative execution of instructions by the processor. In addition, the cache system of the system may further include a connection to a speculation state signal line from the processor that identifies the state of speculative execution of instructions by the processor. The connection to the speculation state signal line may be configured to receive the state of speculative execution, and the state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from the second type (speculative type) to the first type (non-speculative type), the logic circuit may be configured to switch the configurable data bit if the state of speculative execution indicates that the result of speculative execution will be accepted. And, when the execution type changes from the second type (speculative type) to the first type (non-speculative type), the logic circuit may be configured to maintain the configurable data bit unchanged if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0155] Figure 6 、 7A , 7B, 8A, 8B, 9A and 9B show example aspects of example computing devices according to some embodiments of the present disclosure, each computing device including a cache system having interchangeable cache sets for first type and second type execution (e.g., for implementing shadow cache techniques with enhanced security and / or for main type and speculative type execution).

[0156] Figure 6 Specifically shown are aspects of an example computing device including a cache system 600 having a plurality of caches (e.g., see caches 602a, 602b, and 602c), wherein at least one of the caches is implemented with cache set associativity. The example computing device is also shown having a processor 601 and a memory system 603. The cache system 600 is configured to be coupled between the processor 601 and the memory system 603.

[0157] The cache system 600 is shown as including a connection 604a to a command bus 605a coupled between the cache system and the processor 601. The cache system 600 is shown as including a connection 604b to an address bus 605b coupled between the cache system and the processor 601. Figure 1A 、 1B, 1C, 1D, and 1E may each be communicated via an address bus 605b, depending on the implementation of the cache system 600. The cache system 600 is shown as including a connection 604c to a data bus 605c coupled between the cache system and the processor 601. The cache system 600 is also shown as including a connection 604d to an execution type signal line 605d from the processor 601 that identifies the execution type. The connections 604a, 604b, 604c, and 604d may provide a communicative coupling between the buses 605a, 605b, 605c, and 605d and the logic circuitry 606 of the cache system 600.

[0158] In addition, if Figure 6 As shown in FIG, cache system 600 further includes a connection 608a to a second command bus 609a coupled between the cache system and the memory system 603. Cache system 600 also includes a connection 608b to a second address bus 609b coupled between the cache system and the memory system 603. Cache system 600 also includes a connection 608c to a second data bus 609c coupled between the cache system and the memory system 603.

[0159] Cache system 600 also includes multiple cache sets (eg, see cache sets 610a, 610b, and 610c). The cache sets may include a first cache set (eg, see cache set 610a) and a second cache set (eg, see cache set 610b).

[0160] In addition, if Figure 6 As shown in FIG, cache system 600 further includes a plurality of registers (e.g., see registers 612a, 612b, and 612c) respectively associated with a plurality of cache sets. The registers (or cache set registers) may include a first register (e.g., see register 612a) associated with a first cache set (e.g., see cache set 610a) and a second register (e.g., see register 612a) associated with a second cache set (e.g., see cache set 610b). Each of the plurality of registers (e.g., see registers 612a, 612b, and 612c) may be configured to store a set index.

[0161] like Figure 6 as well as Figure 10As shown in FIG, cache 602a and caches 602b through 602c (Caches 1 through N) are not fixed structures. However, it should be understood that in some embodiments, the caches may be fixed structures. Each of the depicted caches can be considered a logical grouping of cache sets, and this logical grouping is illustrated by the dashed lines representing each logical cache. Cache sets 610a through 610c (Cache Sets 1 through N) can be based on the contents of registers 610a through 610c (Registers 1 through N). Cache Sets 1 through N can be a collection of cache sets within a cache system that is shared among Cache 1 and Cache 2 through N. Cache 1 can be a subset of that set; Cache 2 can be another non-overlapping subset. The member cache sets in each of the caches can change based on the contents of Registers 1 through N.

[0162] Depending on the embodiment, cache set 1 (in the conventional sense) may or may not communicate with its register 1. The dashed line is also shown in Figure 7A 、 7B , 8A, 8B, 9A and 9B to indicate the cache set and Figure 7A 、 7B , 8A, 8B, 9A, and 9B. The contents of Register 1 determine how cache set 1 is addressed (e.g., which cache set index will cause cache set 1 to be selected for output data). In some embodiments, there is no direct interaction between cache set 1 and its corresponding Register 1. Depending on the embodiment, logic circuitry 606 or 1006 interacts with both the cache sets and the corresponding registers.

[0163] In some embodiments, logic circuitry 606 may be coupled to processor 601 to control multiple cache sets (e.g., cache sets 610a, 610b, and 610c) based on multiple registers (e.g., registers 612a, 612b, and 612c). In such embodiments, cache system 600 may be configured to be coupled between processor 601 and memory system 603. Furthermore, when connection 604b to address bus 605b receives a memory address from processor 601, logic circuitry 606 may be configured to generate a set index from at least the memory address and determine whether the generated set index matches the contents stored in a first register (e.g., register 612a) or the contents stored in a second register (e.g., register 612b). The logic circuit 606 may also be configured to implement a command received in the connection 604a to the command bus 605a via a first cache set (e.g., cache set 610a) in response to a generated set index matching the contents stored in the first register (e.g., register 612a), and to implement the command via a second cache set (e.g., cache set 610b) in response to a generated set index matching the contents stored in the second register (e.g., register 612b).

[0164] In some embodiments, cache system 600 may include a first cache (e.g., see cache 602a) and a second cache (e.g., see cache 602b). Figure 2 , cache system 600 may include logic circuitry 606 coupled to processor 601. Furthermore, in such an embodiment, logic circuitry 606 may be configured to control a first cache (e.g., see cache 602a) and a second cache (e.g., see cache 602b) based on configurable data bits and / or corresponding registers (e.g., see registers 612a, 612b, and 612c).

[0165] In some embodiments, in response to determining that a data set in memory system 603 associated with a memory address is not currently cached in cache system 600 (e.g., not cached in cache 602a of the system), logic circuitry 606 is configured to allocate a first cache set (e.g., cache set 610a) for caching the data set and store a generated set index in a first register (e.g., register 612a). In this and other embodiments, the cache system may include a connection to an execution type signal line from a processor (e.g., processor 601) that identifies an execution type (e.g., connection 604d to execution type signal line 605). Furthermore, in this and other embodiments, the generated set index is further generated based on the type identified by the execution type signal line. Furthermore, the generated set index may include a predetermined fraction of bits from the memory address and bits representing the type identified by execution type signal line 605d.

[0166] Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in the first state, the logic circuit 606 may be configured to implement a command received from the command bus 605a for accessing the memory system 601 via the first cache set (e.g., cache set 610a) when the execution type is the first type. Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in the first state, the logic circuit 606 may be configured to implement a command received from the command bus 605a for accessing the memory system 601 via the second cache set (e.g., cache set 610b) when the execution type is the second type.

[0167] Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in the second state, the logic circuit 606 may be configured to, when the execution type is the first type, implement a command received from the command bus 605a for accessing the memory system 601 via another cache set other than the first cache set among the plurality of cache sets (e.g., cache set 610b or 610c). Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in the second state, the logic circuit 606 may be configured to, when the execution type is the second type, implement a command received from the command bus 605a for accessing the memory system 601 via another cache set other than the second cache set among the plurality of cache sets (e.g., cache set 610a or 610c, or cache set 610a or 610c, or cache set 610b ... Figure 6 another cache set not depicted in the figure) to access the command of the memory system 601.

[0168] In some embodiments, each of the plurality of registers (e.g., see registers 612a, 612b, and 612c) may be configured to store a set index, and when the execution type changes from the second type to the first type (e.g., from a non-speculative type of execution to a speculative type of execution), the logic circuit 606 may be configured to change the contents stored in the first register (e.g., register 612a) and the contents stored in the second register (e.g., register 612b). Figure 7A and 7B 、 Figure 8A and 8B and Figure 9A and 9B An example of changes in the contents stored in a first register (eg, register 612a) and the contents stored in a second register (eg, register 612b) is described in FIG.

[0169] Figure 7A 、 7B , 8A, 8B, 9A, and 9B each specifically illustrate aspects of an example computing device including a cache system having multiple cache sets (e.g., see caches 702, 704, and 706), wherein the cache sets are implemented via cache set associativity. The respective cache system in each of these figures is also illustrated as having a plurality of registers associated with each cache set. The plurality of registers includes at least register 712, register 714, and register 716. The plurality of registers includes at least one additional register not shown in the figures. Register 712 is shown as being associated with or connected to cache set 702, register 714 is shown as being associated with or connected to cache set 704, and register 716 is shown as being associated with or connected to cache set 706.

[0170] Not present Figure 7A 、 7B , 8A, 8B, 9A, and 9B, each of the respective cache systems may also include connections to a command bus coupled between the cache system and the processor, connections to an address bus coupled between the cache system and the processor, and connections to a data bus coupled between the cache system and the processor. Each of the cache systems may also include logic circuitry coupled to the processor to control multiple cache sets (e.g., cache sets 702, 704, and 706) based on multiple registers (e.g., registers 712, 714, and 716).

[0171] As Figure 7A 、 7B, 8A, 8B, 9A and 9B, when a connection to an address bus of the cache system receives a memory address from a processor (e.g., see memory address 102b, 102c or 102d), the logic circuitry of the cache system may be configured to generate a set index (e.g., see set index 722, 724, 726 or 728) from the memory address (e.g., see set index generation 730, 732, 830, 832, 930 or 932).

[0172] Specifically, if Figure 7A As shown, at least registers 712, 714, and 716 are configured to be in a first state. When a connection to the cache system's address bus receives a memory address 102b from a processor, logic circuitry of the cache system generates a set index 722, 724, or 726 based on at least set index generation 730a, 730b, or 730c, respectively, and an instance of cache set index 112b for address 102b. Set index generation 730a, 730b, or 730c may be used to store set index 722, 724, or 726 in register 712, 714, or 716, respectively. Set index generation 730a, 730b, or 730c may also be used to use the most recently generated set index in a comparison with the contents already stored in register 712, 714, or 716, respectively. Set index generation 730a, 730b, or 730c occurs when the registers are configured to be in the first state. Configuration of the first state may be achieved through set index generation and storage.

[0173] Specifically, if Figure 7B As shown, at least registers 712, 714, and 716 are configured to be in a second state. When a connection to the cache system's address bus receives memory address 102b from a processor, logic circuitry of the cache system generates set index 726, 722, or 728 based on at least set index generation 732a, 732b, or 732c, respectively, and an instance of cache set index 112b for address 102b. Set index generation 732a, 732b, or 732c may be used to store set index 726, 722, or 728 in register 712, 714, or 716, respectively. Set index generation 732a, 732b, or 732c may also be used to use the most recently generated set index in a comparison with the contents already stored in register 712, 714, or 716, respectively. Set index generation 732a, 732b, or 732c occurs when the registers are configured to be in the second state. The configuration of the second state may be achieved through set index generation and storage.

[0174] Specifically, if Figure 8AAs shown in FIG. 1 , at least registers 712, 714, and 716 are configured to be in a first state. When a connection to an address bus of the cache system receives a memory address 102c from a processor, logic circuitry of the cache system generates a set index 722, 724, or 726 based on at least a set index generation 830a, 830b, or 830c, respectively, and an instance of a tag 104c for address 102b having a cache set indicator. Set index generation 830a, 830b, or 830c may be used to store the set index 722, 724, or 726 in register 712, 714, or 716, respectively. Set index generation 830a, 830b, or 830c may also be used to use a most recently generated set index in a comparison of the most recently generated set index with the contents already stored in register 712, 714, or 716, respectively. Set index generation 830a, 830b, or 830c occurs when the registers are configured to be in the first state.

[0175] Specifically, if Figure 8B As shown in FIG. 1 , at least registers 712, 714, and 716 are configured to be in a second state. When a connection to the cache system's address bus receives a memory address 102c from a processor, logic circuitry of the cache system generates a set index 726, 722, or 728 based on at least a set index generation 832a, 832b, or 832c, respectively, and an instance of a tag 104c for address 102b having a cache set indicator. Set index generation 832a, 832b, or 832c may be used to store set index 726, 722, or 728 in register 712, 714, or 716, respectively. Set index generation 832a, 832b, or 832c may also be used to use a most recently generated set index in a comparison of a most recently generated set index with the contents already stored in register 712, 714, or 716, respectively. Set index generation 832a, 832b, or 832c occurs when the registers are configured to be in the second state.

[0176] Specifically, if Figure 9AAs shown in FIG. 1 , at least registers 712, 714, and 716 are configured to be in a first state. When a connection to the cache system's address bus receives a memory address 102d from a processor, logic circuitry of the cache system generates a set index 722, 724, or 726 based on at least a set index generation 930a, 930b, or 930c, respectively, and an instance of the cache set index 112d in the tag 104d of address 102b. Set index generation 930a, 930b, or 930c may be used to store the set index 722, 724, or 726 in register 712, 714, or 716, respectively. Set index generation 930a, 930b, or 930c may also be used to use the most recently generated set index in a comparison of the most recently generated set index with the contents already stored in register 712, 714, or 716, respectively. Set index generation 930a, 930b, or 930c occurs when the registers are configured to be in the first state.

[0177] Specifically, if Figure 7B As shown in FIG. 1 , at least registers 712, 714, and 716 are configured to be in a second state. When a connection to the cache system's address bus receives a memory address 102d from a processor, logic circuitry of the cache system generates a set index 726, 722, or 728 based on at least a set index generation 932a, 932b, or 932c, respectively, and an instance of the cache set index 112d in the tag 104d of address 102b. Set index generation 932a, 932b, or 932c may be used to store the set index 726, 722, or 728 in register 712, 714, or 716, respectively. Set index generation 932a, 932b, or 932c may also be used to use the most recently generated set index in a comparison of the most recently generated set index with the contents already stored in register 712, 714, or 716, respectively. Set index generation 932a, 932b, or 932c occurs when the registers are configured to be in the second state.

[0178] In passing Figure 7A and 7B In some embodiments of the cache system implementations described in , 8A and 8B, or 9A and 9B, when a memory address is received from a processor via a connection to the address bus, the logic circuitry may be configured to determine whether a generated set index matches the contents stored in one of the registers (e.g., registers 712, 714, and 716). The contents stored in the register may be from a previous generation of the set index and storage of the set index in the register.

[0179] In addition, through Figure 7A and 7BIn some embodiments of the cache system implementations described in , 8A and 8B, or 9A and 9B, the logic circuitry may be configured to implement a command received in connection with the command bus via a first cache set in response to a generated set index matching the contents stored in an associated first register, and to implement the command via a second cache set in response to a generated set index matching the contents stored in an associated second register. Furthermore, in response to determining that a data set of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry may be configured to allocate the first cache set for caching the data set and store the generated set index in the first register. The generated set index may comprise a predetermined fraction of bits from the memory address.

[0180] Furthermore, in such an embodiment, when the first and second registers are in a first state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via the first cache set when the execution type of the processor is the first type; and implement a command received from the command bus for accessing the memory system via the second cache set when the execution type is the second type. Furthermore, when the first and second registers are in a second state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via another cache set other than the first cache set among the plurality of cache sets when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via another cache set other than the second cache set among the plurality of cache sets when the execution type is the second type. In such an example, each of the plurality of registers may be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuitry may be configured to change the contents stored in the first register and the contents stored in the second register.

[0181] Figure 10 Specifically showing the inclusion of multiple caches (see, for example, Figure 10 602a, 602b, and 602c) depicted in , wherein at least one of the caches is implemented with cache set associativity (e.g., see cache sets 610a, 610b, and 601c). Figure 10 In FIG, the example computing device is also shown as having a processor 1001 and a memory system 603. Figure 10As shown, cache system 1000 is similar to cache system 600 , but cache system 1000 also includes a connection 1002 to a speculation state signal line 1004 from processor 1001 that identifies the state of speculative execution of instructions by processor 1001 .

[0182] Similarly, cache system 1000 is shown as including a connection 604a to a command bus 605a coupled between the cache system and processor 1001. System 1000 also includes a connection 604b to an address bus 605b coupled between the cache system and processor 1001. Figure 1A 、 1B , 1C, 1D, and 1E may each be communicated via an address bus 605b depending on the implementation of the cache system 1000. The system 1000 also includes a connection 604c to a data bus 605c coupled between the cache system and the processor 1001. It also includes a connection 604d to an execution type signal line 605d from the processor 1001 that identifies a non-speculative execution type or a speculative execution type.

[0183] Similarly, cache system 1000 is also shown as including logic circuit 1006 , which may be similar to logic circuit 606 , but whose circuitry is coupled to connection 1002 with speculative state signal line 1004 .

[0184] In some embodiments, logic circuitry 1006 may be coupled to processor 1001 to control a plurality of cache sets (e.g., cache sets 610a, 610b, and 610c) based on a plurality of registers (e.g., registers 612a, 612b, and 612c). Each of the plurality of registers (e.g., see registers 612a, 612b, and 612c) may be configured to store a set index.

[0185] In such an embodiment, cache system 1000 may be configured to be coupled between processor 1001 and memory system 603. Furthermore, when connection 604b to address bus 605b receives a memory address from processor 1001, logic circuit 1006 may be configured to generate a set index from at least the memory address and determine whether the generated set index matches the contents stored in a first register (e.g., register 612a) or the contents stored in a second register (e.g., register 612b). Logic circuit 1006 may also be configured to implement a command received via connection 604a to command bus 605a via a first cache set (e.g., cache set 610a) in response to the generated set index matching the contents stored in the first register (e.g., register 612a), and to implement the command via a second cache set (e.g., cache set 610b) in response to the generated set index matching the contents stored in the second register (e.g., register 612b).

[0186] Additionally, cache system 1000 is shown to include a cache system similar to Figure 6 The corresponding connections shown in FIG. 608a, 608b and 608c are shown in FIG. Figure 6 and 10 , when the first and second registers (e.g., registers 612a and 612b) are in the first state, the logic circuit 606 or 1006 may be configured to provide a command for accessing the memory system 603 via the first cache set (e.g., cache set 610a) to the second command bus 609a when the execution type is the first type (e.g., non-speculative type). Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in the first state, the logic circuit 606 or 1006 may be configured to provide a command for accessing the memory system via the second cache set (e.g., cache set 610b) to the second command bus 609a when the execution type is the second type (e.g., speculative type).

[0187] Additionally, when the first and second registers (e.g., registers 612a and 612b) are in the second state, the logic circuit 606 or 1006 may be configured to, when the execution type is the first type, execute the execution of the data via a cache set other than the first cache set (e.g., cache set 610b or 610c, or Figure 610) to access the memory system 603 is provided to the second command bus 609a. In addition, when the first and second registers (e.g., registers 612a and 612b) are in the second state, the logic circuit 606 or 1006 can be configured to, when the execution type is the second type, execute the command for accessing the memory system 603 via a cache set other than the second cache set (e.g., cache set 610a or 610c, or Figure 6 Commands to access the memory system 603 (or another cache set not depicted in FIG. 10 ) are provided to the second command bus 609 a.

[0188] In some embodiments, such as shown in Figure 10 , the first type may be configured to indicate non-speculative execution of instructions by processor 1001; and the second type may be configured to indicate speculative execution of instructions by the processor. Figure 10 , cache system 1000 further includes a connection 1002 to a speculation status signal line 1004 from processor 1001 that identifies a status of speculative execution of instructions by the processor. Connection 1002 to speculation status signal line 1004 may be configured to receive the status of the speculative execution, and the status of the speculative execution may indicate whether a result of the speculative execution will be accepted or rejected.

[0189] In such an embodiment, each of the plurality of registers (e.g., registers 612a, 612b, and 612c) may be configured to store a set index, and when the execution type changes from a speculative execution type to a non-speculative execution type, the logic circuit 1006 may be configured to change the contents stored in the first register (e.g., register 612a) and the contents stored in the second register (e.g., register 612b) if the status of the speculative execution type indicates that the result of the speculative execution will be accepted. Furthermore, when the execution type changes from a speculative type to a non-speculative type, the logic circuit 1006 may be configured to maintain the contents stored in the first register and the contents stored in the second register without change if the status of the speculative execution type indicates that the result of the speculative execution will be rejected.

[0190] Some embodiments may include a cache system comprising a plurality of cache sets, the plurality of cache sets having at least a first cache set and a second cache set. The cache system may also include a plurality of registers respectively associated with the plurality of cache sets. The plurality of registers may include at least a first register associated with the first cache set configured to store a set index, and a second register associated with the second cache set configured to store a set index. The cache system may also include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, and a connection to an execution type signal line from the processor that identifies an execution type.

[0191] The cache system may further include logic circuitry coupled to the processor to control the plurality of cache sets based on the plurality of registers. Furthermore, the cache system may be configured to be coupled between the processor and the memory system. When the first and second registers are in a first state, the logic circuitry may be configured to: when the execution type is the first type, implement a command received from the command bus for accessing the memory system via the first cache set; and when the execution type is the second type, implement a command received from the command bus for accessing the memory system via the second cache set. Furthermore, when the first and second registers are in a second state, the logic circuitry may be configured to: when the execution type is the first type, implement a command received from the command bus for accessing the memory system via another cache set other than the first cache set among the plurality of cache sets; and when the execution type is the second type, implement a command received from the command bus for accessing the memory system via another cache set other than the second cache set among the plurality of cache sets.

[0192] The connection to the address bus may be configured to receive a memory address from the processor, and the memory address may include a set index.

[0193] In some embodiments, when the first and second registers are in a first state, a first set index associated with the first cache set is stored in the first register, and a second set index associated with the second cache set is stored in the second register. When the first and second registers are in a second state, the first set index may be stored in another register of the plurality of registers other than the first register, and the second set index may be stored in another register of the plurality of registers other than the second register. In this example, when a memory address is received from a processor via a connection to an address bus, the logic circuitry may be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches the contents stored in the first register or the contents stored in the second register. Furthermore, the logic circuitry may be further configured to execute a command received via the connection to the command bus in response to the generated set index matching the contents stored in the first register, and to execute the command via the second cache set in response to the generated set index matching the contents stored in the second register.

[0194] In response to determining that a data set of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry may be configured to allocate a first cache set for caching the data set and store a generated set index in a first register.

[0195] In some embodiments, the generated set index is further generated based on the execution type identified by the execution type signal line. In such an example, the generated set index may include a predetermined segment of bits in the memory address and a bit representing the execution type identified by the execution type signal line.

[0196] Some embodiments may include a system comprising a processor, a memory system, and a cache system. The cache system may include: a plurality of cache sets comprising a first cache set and a second cache set; and a plurality of registers respectively associated with the plurality of cache sets, the plurality of registers comprising a first register associated with the first cache set and a second register associated with the second cache set. The cache system may also include a connection to a command bus coupled between the cache system and the processor, a connection to an address bus coupled between the cache system and the processor, and a connection to a data bus coupled between the cache system and the processor.

[0197] The cache system may also include logic circuitry coupled to the processor to control the plurality of cache sets based on the plurality of registers. When a memory address is received from the processor via the connection to the address bus, the logic circuitry may be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches the contents stored in the first register or the contents stored in the second register. Furthermore, the logic circuitry may be configured to execute a command received via the connection to the command bus via the first cache set in response to the generated set index matching the contents stored in the first register, and execute the command via the second cache set in response to the generated set index matching the contents stored in the second register.

[0198] The cache system may further include a connection to an execution type signal line from the processor that identifies an execution type. The generated set index may be further generated based on the type identified by the execution type signal line. The generated set index may include a predetermined segment of bits in the memory address and a bit representing the type identified by the execution type signal line.

[0199] Figure 11A and 11B Background synchronization circuitry for synchronizing contents between a primary cache and a shadow cache to preserve contents cached in the primary cache in preparation for receiving contents in the shadow cache is described according to some embodiments of the present disclosure. Figure 11A and 11B The cache system in includes a background synchronization circuit system 1102. For example, cache 1124 and cache 1126 may be Figure 2 or caches 202a and 202b in 4, or Figure 6 or caches 602a and 602b in 10. Background synchronization circuitry 1102 may be part of logic circuits 206, 406, 606, or 1006.

[0200] Figure 11AThis illustrates a scenario where cache 1124 is used as a primary cache during non-speculative execution and cache 1126 is used as a shadow cache during speculative execution. Background synchronization circuitry 1102 is configured to synchronize 1130 the contents of the cache from cache 1124 to cache 1126, so that if conditional speculative execution is determined to be necessary, cache 1126 can be used as the primary cache during subsequent non-speculative execution; and cache 1124 can be used as a shadow cache during further instances of speculative execution. Synchronizing 1130 the contents of the cache from cache 1124 to cache 1126 copies the results of the previous execution to cache 1126, so that the results of the execution are not lost when cache 1124 is subsequently used as a shadow cache. The contents of the cache from cache 1124 may be cached in cache 1124 but not yet flushed to memory (e.g., memory 203 or 603). In addition, some of the memory contents cached in cache 1124 with the same copy may also be copied from cache 1124 to cache 1126, so that when cache 1126 is subsequently used as the primary cache, the contents previously cached in cache 1124 are also available in cache 1126. This can speed up access to the previously cached contents. Copying contents between cache 1124 and cache 1126 is faster than retrieving data from memory to the cache system.

[0201] In some embodiments, if a program references a variable during normal execution, the variable may be cached. In this instance, if the variable is referenced during speculation while writing through the cache, the value in main memory is valid and correct. If the variable is referenced during speculation while writing back to the cache, the value in main memory may be cached. Figure 11A The foregoing example features described; and the valid value of the variable may be in cache 1124.

[0202] exist Figure 11A In the scenario described in

[15] , a processor (e.g., processor 201, 401, 601, or 1001) may execute a first instruction set in a non-speculative execution mode. During execution of the first instruction set, the processor may access a memory address to load data (e.g., instructions and operands) from memory and store computation results. Since cache 1124 serves as a primary cache, the contents of data and / or computation results may be cached in cache 1124. For example, cache 1124 may store computation results that have not yet been written back to memory; and cache 1124 may store loaded data (e.g., instructions and operands) that may be used in subsequent execution of instructions.

[0203] In preparation for use as a shadow cache in speculative execution of the second instruction set, background synchronization circuitry 1102 copies the contents of the cache from cache 1124 to cache 1126 in synchronization 1130. At least a portion of the copy operation may occur in the background, independent of the processor accessing memory via the cache system. For example, while the processor is accessing a first memory address in non-speculative execution of the first instruction set, background synchronization circuitry 1102 may copy the contents cached in cache 1124 for the second memory address to cache 1126. In some cases, the copy operation may occur in the background concurrently with memory access via the cache system. For example, while the processor is accessing a first memory address to store a computation result in non-speculative execution of the first instruction set, background synchronization circuitry may copy the computation result to cache 1126 as cached contents for the first memory address.

[0204] In one embodiment, background synchronization circuitry 1102 is configured to complete a synchronization operation before enabling cache 1126 for speculative execution of the second instruction set. Thus, when cache 1126 is enabled for speculative execution of the second instruction set, valid content in cache 1124 may also be found in cache 1126. However, the synchronization operation may delay the use of cache 1126 as a shadow cache. Alternatively, background synchronization circuitry 1102 is configured to prioritize synchronization of dirty content from cache 1124 to cache 1126. Dirty content may be where data in the cache has been modified but data in main memory has not been modified.

[0205] Dirty content cached in cache 1124 may be newer than the content stored at the corresponding one or more addresses in memory. For example, when a processor stores a computation result at an address, cache 1124 may cache the computation result at the address without immediately writing the computation result to memory at the address. When the computation result at the address is written back to memory, the cached content is no longer considered dirty. Cache 1124 stores data to track dirty content cached in cache 1124. Background synchronization circuitry 1102 may automatically copy dirty content from cache 1124 to cache 1126 to enable cache 1126 to function as a shadow cache.

[0206] Optionally, before completing the synchronization operation, background synchronization circuitry 1102 may allow cache 1126 to function as a shadow cache during conditional speculative execution of the second instruction set. During the period in which cache 1126 is functioning as a shadow cache during speculative execution, background synchronization circuitry 1102 may continue synchronization operation 1130 to copy cache contents from cache 1124 to cache 1126. Background synchronization circuitry 1102 is configured to complete at least synchronization of dirty contents from cache 1124 to cache 1126 before allowing cache 1126 to be accepted as the primary cache. For example, following an indication that execution of the second instruction set is desired, background synchronization circuitry 1102 determines whether dirty contents in cache 1124 have been synchronized to cache 1126; if not, then the use of cache 1126 as the primary cache is deferred until the synchronization is complete.

[0207] In some embodiments, background synchronization circuitry 1102 may continue its synchronization operations even after accepting cache 1126 as the primary cache but before cache 1124 is used as a shadow cache in conditional speculative execution of the third instruction set.

[0208] Before completing synchronization operation 1130, the cache system may configure cache 1124 as a secondary cache between cache 1126 and memory during speculative execution, so that when the contents of a memory address are not found in cache 1126, the cache system checks cache 1124 to determine whether the contents are in cache 1124; and if so, copies the contents from cache 1124 to cache 1126 (rather than loading directly from memory). When the processor stores data at the memory address and caches the data in cache 1126, the cache system checks to invalidate the contents cached in cache 1124 as a secondary cache.

[0209] After cache 1126 is reconfigured as the primary cache after accepting the results of speculative execution of the second instruction set, background synchronization circuitry 1102 may begin synchronizing 1132 the contents of the cache from cache 1126 to cache 1124, as shown in FIG. Figure 11B As described in .

[0210] After speculative execution of the second instruction set, if the speculative status from the processor indicates that the results of the execution of the second instruction set should be rejected, cache 1124 still functions as the primary cache and the contents of cache 1126 may be invalidated. Invalidation may include cache 1126 marking all of its entries as empty; thus, any subsequent speculation begins with an empty speculative cache.

[0211] Background synchronization circuitry 1102 may again synchronize 1130 the contents of the cache from cache 1124 to cache 1126 in preparation for speculative execution of the third instruction set.

[0212] In some embodiments, each of cache 1124 and cache 1126 has dedicated and fixed sets of cache sets; and configurable bits are used to control the use of caches 1124 and 1126 as a primary cache and a shadow cache, respectively, such as Figure 3A 、 3B , 5A and 5B.

[0213] In other embodiments, cache 1124 and cache 1126 may share a pool of cache sets, some of which may be dynamically allocated to cache 1124 and cache 1126, such as Figures 6 to 10 When cache 1124 is used as a primary cache and cache 1126 is used as a shadow cache, cache 1126 may have a smaller number of cache sets than cache 1124. Some of the cache sets in cache 1126 may be shadows of a portion of the cache sets in cache 1124, so that when it is determined to accept the result of speculative execution, the portion of the cache sets in cache 1124 may be reconfigured for use as a shadow cache in the next speculative execution; and the remaining portion of the cache sets not affected by the speculative execution may be reallocated from cache 1124 to cache 1126, so that the contents of the cache in the unaffected portion may be further used in subsequent non-speculative execution.

[0214] Figure 12 Demonstrating some embodiments of the present disclosure Figure 11A and 11B Example operation of background synchronization circuit system 1102.

[0215] like Figure 12 As shown in FIG, at operation 1202, the cache system configures the first cache as a primary cache and the second cache as a shadow cache. For example, when a dedicated cache with a fixed hardware structure is used as the first cache and the second cache, a configurable bit can be used to configure the first cache as a primary cache and the second cache as a shadow cache, such as Figures 2 to 5B Alternatively, it can be as follows Figures 6 to 10 The approach described in

[0044] uses registers to allocate cache sets from a pool of cache sets into and out of the first cache and the second cache.

[0216] At operation 1204, the cache system determines whether the current execution type has changed from non-speculative to speculative. For example, when the processor accesses memory via the cache system 200, the processor further provides an indication of whether the current memory access is associated with conditional speculative execution. For example, the indication may be provided on signal line 205d configured to specify the execution type.

[0217] If the current execution type has not changed from non-speculative to speculative, the cache system uses the first cache as the primary cache to service the memory access request from the processor at operation 1206. When the memory access changes the contents of the cache in the first cache, the background synchronization circuitry 1102 may copy the contents cached in the first cache to the second cache at operation 1208. For example, the background synchronization circuitry 1102 may be Figure 2 Logic circuit 206, Figure 4 406 in Figure 6 606 and / or Figure 10 The background synchronization circuitry 1102 may prioritize the copying of dirty content cached in the first cache.

[0218] exist Figure 12 , operations 1204 to 1208 are repeated until the cache system 200 determines that the current execution type is changed to speculative.

[0219] Optionally, the background synchronization circuit system 1102 is configured to continue copying the contents cached in the first cache to the second cache in operation 1210 to complete synchronization of at least the dirty contents from the first cache to the second cache, and then to allow the cache system to service memory requests from the processor during speculative execution using the second cache in operation 1212.

[0220] Optionally, the background synchronization circuitry 1102 may continue synchronization operations while the cache system services memory requests from the processor using the second cache during speculative execution in operation 1212 .

[0221] At operation 1214, the cache system determines whether the current execution type has changed to non-speculative. If the current execution type is still speculative, operations 1210 and 1212 may be repeated.

[0222] In response to determining at operation 1214 that the current execution type has changed to non-speculative, the cache system determines whether to accept the result of the speculative execution. The result of the speculative execution corresponds to a change in the contents of the cache in the second cache. For example, the processor 401 may determine whether to accept the result of the speculative execution. Figure 4The estimated state signal line 404 or Figure 10 The speculation status signal line 1004 in provides an indication of whether the results of speculative execution should be accepted.

[0223] If, in operation 1216, the cache system determines that the result of speculative execution is to be rejected, the cache system may discard the contents of the cache currently cached in the second cache (e.g., by setting an invalid bit in a cache block in the second cache) in operation 1222. Subsequently, in operation 1244, the cache system may maintain the first cache as the primary cache and the second cache as the shadow cache; and in operation 1208, the background synchronization circuitry 1102 may copy the contents of the cache from the first cache to the second cache. While execution remains non-speculative, operations 1204 through 1208 may be repeated.

[0224] If, in operation 1216, the cache system determines that the results of speculative execution will be accepted, the background synchronization circuitry 1102 is configured to further copy the contents cached in the first cache to the second cache in operation 1218 to complete synchronization of at least the dirty contents from the first cache to the second cache before allowing the cache system to reconfigure the first cache as a shadow cache. In operation 1220, the cache system configures the first cache as a shadow cache and the second cache as a primary cache in a manner somewhat similar to operation 1202. When configuring the first cache as a shadow cache, the cache system may invalidate its contents and then synchronize the contents of the cache in the second cache to the first cache in a manner somewhat similar to operations 1222, 1224, 1208, and 1204.

[0225] For example, when a dedicated cache having a fixed hardware structure is used as the first cache and the second cache, the configurable bits may be changed to configure the first cache as a shadow cache and the second cache as a main cache in operation 1220. Alternatively, when a dedicated cache having a fixed hardware structure is used as the first cache and the second cache is used as the main cache, the configurable bits may be changed to configure the first cache as a shadow cache and the second cache as the main cache in operation 1220. Figures 6 to 10 When registers are used to allocate cache sets from a pool of cache sets to the first cache and the second cache in the manner described in , cache sets that were originally in the first cache but not affected by speculative execution can be allocated to the first cache via their associated registers (e.g., Figure 6 and 10, registers 612a and 612b described in [ 15 ] are reconfigured to join the second cache. Cache sets that were originally in the first cache (but now empty of data content due to the contents of the second cache) can be reconfigured as in the new first cache. Optionally, additional cache sets can be allocated from the available pool of cache sets and added to the new first cache. Optionally, some of the cache sets with stale cache content can be placed back into the available pool of cache sets for future allocation (e.g., for addition to the second cache acting as a primary cache or the first cache acting as a shadow cache).

[0226] In this specification, the present disclosure has been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications may be made thereto without departing from the broader spirit and scope as set forth in the appended claims. Accordingly, the present specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0227] For example, an embodiment may include a cache system comprising: a first cache; a second cache; a connection to a command bus coupled between the cache system and a processor; a connection to an address bus coupled between the cache system and the processor; a connection to a data bus coupled between the cache system and the processor; a connection to an execution type signal line from the processor that identifies an execution type; and logic circuitry coupled to control the first cache and the second cache based on the execution type. In such an embodiment, the cache system is configured to be coupled between the processor and a memory system. Furthermore, when the execution type is a first type indicating non-speculative execution of an instruction by the processor and the first cache is configured to service a command from the command bus for accessing the memory system, the logic circuitry is configured to copy a portion of the contents cached in the first cache to the second cache.

[0228] In such an embodiment, the logic circuitry may be configured to copy the portion of the contents cached in the first cache to the second cache independent of a current command received in the command bus.

[0229] Furthermore, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache is configured to service commands from the command bus for accessing the memory system, the logic circuitry may be configured to service subsequent commands from the command bus using the second cache in response to the execution type changing from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuitry may also be configured to complete synchronizing portions of the contents from the first cache to the second cache before servicing subsequent commands after the execution type changes from the first type to the second type. The logic circuitry may also be configured to continue synchronizing portions of the contents from the first cache to the second cache while servicing subsequent commands.

[0230] In such an embodiment, the cache system may further include a configurable data bit, and the logic circuit may be further coupled to control the first cache and the second cache based on the configurable data bit. When the configurable data bit is in a first state, the logic circuit may be configured to: implement a command received from the command bus for accessing the memory system via the first cache when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via the second cache when the execution type is the second type. Furthermore, when the configurable data bit is in a second state, the logic circuit may be configured to: implement a command received from the command bus for accessing the memory system via the second cache when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via the first cache when the execution type is the second type. The logic circuit may also be configured to toggle the configurable data bit when the execution type changes from the second type to the first type.

[0231] In such an embodiment, the cache system may further include: a connection to a speculation status signal line from the processor that identifies a status of speculative execution of instructions by the processor. The connection to the speculation status signal line is configured to receive the status of the speculative execution. The status of the speculative execution indicates whether a result of the speculative execution will be accepted or rejected. When the execution type changes from the second type to the first type, the logic circuit may be configured to: toggle the configurable data bit if the status of the speculative execution indicates that the result of the speculative execution will be accepted; and maintain the configurable data bit unchanged if the status of the speculative execution indicates that the result of the speculative execution will be rejected.

[0232] Furthermore, in this embodiment, the first cache and the second cache collectively include: a plurality of cache sets, including a first cache set and a second cache set; and a plurality of registers associated with each of the plurality of cache sets, including a first register associated with the first cache set and a second register associated with the second cache set. In this example, the logic circuitry may be further coupled to control the plurality of cache sets based on the plurality of registers. Furthermore, when a memory address is received from a processor via a connection to an address bus, the logic circuitry may be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches the contents stored in the first register or the contents stored in the second register. The logic circuitry may also be configured to execute a command received via a connection to a command bus, in response to the generated set index matching the contents stored in the first register, via the first cache set, and execute the command via the second cache set, in response to the generated set index matching the contents stored in the second register. Furthermore, in response to determining that a data set of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry may be configured to allocate the first cache set for caching the data set and store the generated set index in the first register.

[0233] Additionally, in such embodiments having cache sets, the cache system may further include a connection to an execution type signal line from the processor that identifies an execution type, and further generate a generated set index based on the type identified by the execution type signal line. The generated set index may include a predetermined segment of bits from a memory address and a bit representing the type identified by the execution type signal line. Furthermore, when the first and second registers are in a first state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via the first cache set when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via the second cache set when the execution type is the second type. Furthermore, when the first and second registers are in a second state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via another cache set other than the first cache set among the plurality of cache sets when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via another cache set other than the second cache set among the plurality of cache sets when the execution type is the second type.

[0234] In such an embodiment having a cache set, each of the plurality of registers may be configured to store a set index. Furthermore, when the execution type changes from the second type to the first type, the logic circuitry may be configured to change the contents stored in the first register and the contents stored in the second register. Furthermore, the first type may be configured to indicate non-speculative execution of the instruction by the processor, and the second type may be configured to indicate speculative execution of the instruction by the processor. In such an example, the cache system may further include a connection to a speculation state signal line from the processor that identifies the state of speculative execution of the instruction by the processor. The connection to the speculation state signal line is configured to receive the state of speculative execution, and the state of speculative execution indicates whether the result of the speculative execution will be accepted or rejected. When the execution type changes from the second type to the first type, the logic circuitry may be configured to: change the contents stored in the first register and the contents stored in the second register if the state of speculative execution indicates that the result of the speculative execution will be accepted; and maintain the contents stored in the first register and the contents stored in the second register without change if the state of speculative execution indicates that the result of the speculative execution will be rejected.

[0235] Furthermore, for example, an embodiment may include a cache system comprising: generally, a plurality of cache sets and a plurality of registers associated with each of the plurality of cache sets. The plurality of cache sets include a first cache set and a second cache set, and the plurality of registers include a first register associated with the first cache set and a second register associated with the second cache set. Similarly, in such an embodiment, the cache system may include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, a connection to an execution type signal line from the processor that identifies an execution type, and logic circuitry coupled to control the plurality of cache sets based on the execution type. The cache system may also be configured to be coupled between the processor and a memory system. Furthermore, when the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache set is configured to service a command from the command bus to access the memory system, the logic circuitry may be configured to copy a portion of the contents cached in the first cache set to the second cache set.

[0236] In such an embodiment having cache sets, the logic circuitry may be configured to copy a portion of the contents cached in the first cache set to the second cache set independently of a current command received on the command bus. When the execution type is a first type indicating non-speculative execution of instructions by the processor and the first cache set is configured to service commands from the command bus for accessing the memory system, the logic circuitry may be configured to use the second cache set to service subsequent commands from the command bus in response to the execution type changing from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuitry may also be configured to complete synchronizing the portion of the contents from the first cache set to the second cache set before servicing subsequent commands after the execution type changes from the first type to the second type. The logic circuitry may also be configured to continue synchronizing the portion of the contents from the first cache set to the second cache set while servicing subsequent commands.

[0237] Furthermore, in such an embodiment having cache sets, the logic circuitry may be further coupled to control the plurality of cache sets based on a plurality of registers. When a memory address is received from a processor via a connection to an address bus, the logic circuitry may be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches the contents stored in a first register or the contents stored in a second register. The logic circuitry may also be configured to implement a command received via a connection to a command bus in response to the generated set index matching the contents stored in the first register, and to implement the command via a second cache set in response to the generated set index matching the contents stored in the second register. Furthermore, in response to determining that a data set of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry may be configured to allocate a first cache set for caching the data set and store the generated set index in the first register.

[0238] Additionally, in such embodiments having cache sets, the cache system may further include a connection to an execution type signal line from the processor that identifies an execution type, and may further generate a generated set index based on the type identified by the execution type signal line. The generated set index may include a predetermined segment of bits from a memory address and a bit representing the type identified by the execution type signal line. When the first and second registers are in a first state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via the first cache set when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via the second cache set when the execution type is the second type. Furthermore, when the first and second registers are in a second state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via another cache set other than the first cache set among the plurality of cache sets when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via another cache set other than the second cache set among the plurality of cache sets when the execution type is the second type.

[0239] In such an embodiment having a cache set, each of the plurality of registers may be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuit may be configured to change the contents stored in the first register and the contents stored in the second register. Furthermore, the first type may be configured to indicate non-speculative execution of the instruction by the processor, and the second type may be configured to indicate speculative execution of the instruction by the processor.

[0240] In such an embodiment having a cache set, the cache system may further include a connection to a speculation status signal line from the processor that identifies a status of speculative execution of instructions by the processor. The connection to the speculation status signal line is configured to receive the status of speculative execution, and the status of speculative execution indicates whether a result of speculative execution will be accepted or rejected. When the execution type changes from the second type to the first type, the logic circuit may be configured to: if the status of speculative execution indicates that the result of speculative execution will be accepted, change the content stored in the first register and the content stored in the second register; and if the status of speculative execution indicates that the result of speculative execution will be rejected, maintain the content stored in the first register and the content stored in the second register without changing them.

[0241] Furthermore, in such embodiments with cache sets, the cache sets may be divided among a plurality of caches within the cache system. For example, the cache sets may be divided among a first and a second cache in the plurality of caches.

[0242] Figure 13 、 14A , 14B, 14C, 15A, 15B, 15C and 15D illustrate a plurality of caches having a plurality of caches including a spare cache set (e.g., see the embodiment shown in FIG. 1 ). Figure 14A and 15A d) to accelerate speculative execution of interchangeable cache sets (e.g., see cache sets 1310a, 1310b, 1310c, and 1310d) in a cache system (e.g., see the cache system shown in FIG. Figure 13 An example aspect of an example computing device of the cache system 1000 in FIG.

[0243] In addition to using shadow caches to ensure speculative execution and synchronizing the contents between the main cache and the shadow cache to save the contents cached in the main cache in preparation for accepting the contents in the shadow cache, the backup cache set can also be used to accelerate speculative execution (e.g., see Figure 14A and 15A The backup cache set 1310d depicted in FIG. Figure 15B and 15C The cache set 1310b depicted in FIG. Figure 15D 1310c). The backup cache set can also be used to accelerate speculative execution without using the shadow cache. Data stored in the cache set used as the shadow cache can be verified and thus used for normal execution (e.g., see FIG. Figure 14A and 15A The cache set 1310c depicted in FIG. Figure 15B and 15C The cache set 1310d depicted in FIG. Figure 15D , each of which is a cache set that is available for speculative execution and is a shadow cache, and then available for normal execution after content verification). Also, some cache sets that are used as primary caches for normal or non-speculative execution (e.g., see FIG. Figure 14A and 15A Cache set 1310b as depicted in FIG. Figure 15B and 15C The cache set 1310c depicted in FIG. Figure 15D 1310d) may not be ready to be used as a shadow cache for speculative execution. Therefore, one or more cache sets may be used as backup cache sets to avoid delays waiting for cache set availability (e.g., see FIG. Figure 14A and15A Cache set 1310d as depicted in FIG, and as Figure 15B and 15C The cache set 1310b depicted in FIG. Figure 15D Cache set 1310c) depicted in .

[0244] Once the speculation is confirmed, the contents of the cache set used as the shadow cache are confirmed to be valid and up-to-date; and therefore, the previous cache set used as the shadow cache for speculative execution is used for normal execution. Figure 14A and 15A The cache set 1310c depicted in FIG. Figure 15B and 15C The cache set 1310d depicted in FIG. Figure 15D , each of which is a cache set that can be used for speculative execution and is a shadow cache, and then can be used for normal execution after content verification. However, some of the cache sets that are initially used as normal caches may not be ready for subsequent speculative execution. For example, see Figure 14A and 15A Cache set 1310b as depicted in FIG. Figure 15B and 15C The cache set 1310c depicted in FIG. Figure 15D Each of the cache sets 1310d depicted in FIG. 1 is used as part of the normal cache but may not be ready for subsequent speculative execution. Thus, one or more cache sets may be used as backup cache sets to avoid the delay of waiting for cache set availability and to speed up speculative execution. For example, see FIG. Figure 14A and 15A Cache set 1310d as depicted in FIG, and as Figure 15B and 15C The cache set 1310b depicted in FIG. Figure 15D Cache sets 1310c are depicted in , each of which serves as a backup cache set.

[0245] In some embodiments, where the cache system has background synchronization circuitry (e.g., see background synchronization circuitry 1102), if synchronization from a cache set in the normal cache to a corresponding cache set in the shadow cache has not yet been completed (e.g., see the background synchronization circuitry shown in FIG. Figure 11AIf synchronization 1130 in the normal cache is not available, the cache set in the normal cache cannot be immediately released for use in the next speculative execution. In this case, if there is no backup cache set, the next speculative execution must wait until synchronization is complete so that the corresponding cache set in the normal cache can be released. This is just one example of when a backup cache set is beneficial. There are many other situations where a cache set in the normal cache cannot be immediately released.

[0246] Furthermore, for example, speculative execution may refer to a memory system (e.g., see Figure 6 、 10 13) does not have overlapping memory areas with the memory areas in the cache sets cached in the normal cache. Due to the results of the speculative execution, the cache sets in the shadow cache and the normal cache are now all in the normal cache. This can also cause delays because it takes time for the cache system to release the cache sets to support the next speculative execution. In order to release the cache sets, the cache system needs to identify the cache sets, such as the least used cache sets, and synchronize the cache sets with the memory system. If the cache has newer data than the memory system, then the data needs to be written to the memory system.

[0247] Alternatively, use a backup cache set (see, for example, Figure 14A and 15A Cache set 1310d as depicted in FIG, and as Figure 15B and 15C The cache set 1310b depicted in FIG. Figure 15D A system that uses cache sets 1310c as depicted in FIG. 1300 may also use background synchronization circuitry (e.g., background synchronization circuitry 1102). When an initial speculation is confirmed, the cache sets used in the initial speculation may be swapped (e.g., see FIG. 1301 ). Figure 14A and 15A 1310c) to join the cache set for primary execution (e.g., see Figure 14A , B and C and as shown Figure 15A , B, C, and D, which are cache sets of sets in the cache sets used for primary or non-speculative execution). Instead of using the cache set from the previous primary execution that is being used for the case of speculation failure (e.g., see Figure 14A and 15A Cache set 1310b as depicted in FIG. Figure 15B and 15CThe cache set 1310c depicted in FIG. Figure 15D d), can immediately make the standby cache set available for the next speculative execution (e.g., see Figure 14A and 15A Cache set 1310d as depicted in FIG, and as Figure 15B and 15C The cache set 1310b depicted in FIG. Figure 15D 1310c). The standby cache set may be updated for the next speculative execution, for example, via the background synchronization circuitry 1102. Also, due to background synchronization, when the cache set currently used for speculative execution (e.g., Figure 14A and 15A When the cache set 1310c shown in FIG. 1 is ready to be accepted for normal execution, the standby cache set (e.g., Figure 14A and 15A The spare cache set 1310d shown in FIG can be ready for use. In this way, there is no delay in waiting for the use of the next cache set for the next speculative execution. In preparation for the next speculative execution, the spare cache set (e.g., Figure 14A and 15A 1310c) is synchronized to a normal cache set (e.g., as shown in FIG. Figure 14A and 15A The cache set 1310b shown in ) or the least used cache set in the system.

[0248] Figure 13 Example aspects of an example computing device having a cache system 1000 with interchangeable cache sets (eg, see cache sets 1310a, 1310b, 1310c, and 1310d) including spare cache sets to accelerate speculative execution are shown in accordance with some embodiments of the present disclosure. Figure 13 The computing device in is similar to Figure 10 For example, the computing device shown in Figure 13 The apparatus in includes a processor 1001 , a memory system 603 , a cache system 1000 , and connections 604 a to 604 d and 609 a to 609 c , as well as a connection 1002 .

[0249] exist Figure 13, cache system 1000 is shown as having cache sets (e.g., cache sets 1310a, 1310b, 1310c, and 1310d). Cache system 1000 is also shown as having a connection 604d to an execution type signal line 605d from processor 1001 that identifies the execution type, and a connection 1002 to a signal line 1004 from processor 1001 that identifies the state of speculative execution.

[0250] Cache system 1000 is also shown to include logic circuitry 1006 configurable to allocate a first subset of the cache set when the execution type is a first type indicating non-speculative execution of instructions by processor 1001 (e.g., see FIG. Figure 13 602a) for caching in a cache operation. The logic circuit 1006 may also be configured to allocate a second subset of the cache set (e.g., see FIG. 100b ) when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. Figure 13 602b) for caching in a cache operation. The logic circuit 1006 may also be configured to retain at least one cache set or a third subset of cache sets (e.g., see FIG. 602b) when the execution type is the second type. Figure 13 Cache 602c shown in FIG.

[0251] The logic circuit 1006 may also be configured to reconfigure the second subset for caching in a cache operation when the execution type is the first type and when the execution type changes from the second type to the first type and the state of the speculative execution indicates that the result of the speculative execution will be accepted (e.g., see FIG. Figure 13 602b shown in FIG. ). Furthermore, the logic circuit 1006 may be further configured to allocate at least one cache set or the third subset for caching in a cache operation when the execution type changes from the first type to the second type and when the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted (e.g., see FIG. Figure 13 602c shown in FIG. ). The logic circuit 1006 may also be configured to retain at least one cache set or a third subset (e.g., see FIG. 100b ) when the execution type is the second type and when the at least one cache set is the least used cache set among the plurality of cache sets. Figure 13 Cache 602c shown in FIG.

[0252] In some embodiments, a cache system may include one or more mapping tables that can map the cache sets described herein. Furthermore, in such embodiments, logic circuitry, such as the logic circuitry described herein, can be configured to allocate and reconfigure subsets of cache sets, such as caches in the cache system, according to the one or more mapping tables. The mappings can be used as an alternative to or in addition to the cache set registers described herein.

[0253] In some embodiments, such as at least Figure 13 、 14A As shown in FIG14C and FIG15A through FIG15D , the cache system 1000 may include cache set registers (e.g., see cache set registers 1312a, 1312b, 1312c, and 1312d) associated with cache sets, respectively (e.g., see cache sets 1310a, 1310b, 1310c, and 1310d). In such an embodiment, the logic circuit 1006 may be configured to allocate and reconfigure subsets of cache sets (e.g., see FIG14C ). Figure 13 Caches 602a, 602b, and 602c shown in FIG.

[0254] Furthermore, in some embodiments, Figures 15A to 15D , the first subset of cache sets may include a first cache set, the second subset of cache sets may include a second cache set, and the third subset may include a third cache set. In such an embodiment, the cache set registers may include a first cache set register associated with the first cache set, the first cache set register being configured to initially store a first cache set index such that the first cache set is used for non-speculative execution (e.g., see FIG. Figure 15A 1504b stored in the cache set register 1312b shown in FIG. 1504b). The cache set registers may also include a second cache set register associated with a second cache set, the second cache set register configured to initially store a second cache set index such that the second cache set is used for non-speculative execution (e.g., see FIG. Figure 15A 1312c). The cache set registers may also include a third cache set register associated with a third cache set, the third cache set register being configured to initially store a third cache set index such that the third cache set serves as a backup cache set (e.g., see FIG. Figure 15A1504d stored in the cache set register 1312d).

[0255] Furthermore, in such an embodiment, the logic circuit 1006 may be configured to generate a set index (e.g., see set indexes 1504a, 1504b, 1504c, and 1504d) based on a memory address received from the address bus 605b from the processor 1001 and an identification of speculative execution or non-speculative execution received from the execution type signal line 605d identifying the execution type from the processor. Furthermore, the logic circuit 1006 may be configured to determine whether the set index matches the contents stored in the first cache set register, the second cache set register, or the third cache set register.

[0256] Furthermore, in such an embodiment, the logic circuit 1006 may be configured to store the first cache set index in the second cache set register or another cache set register associated with another cache set in the second subset of the plurality of cache sets, such that when the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted, the second cache set or another cache set in the second subset is used for non-speculative execution. For example, see the diagram depicting the cache set index 1504b stored in the second cache set register 1312c. Figure 15B , so that the second cache set 1310c can be used for non-speculative execution. In addition, the logic circuit 1006 can be configured to store the second cache set index in a third cache set register or another cache set register associated with another cache set in the at least one cache set, so that when the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted, the third cache set or another cache set in the at least one cache set is used for speculative execution. For example, see the figure depicting the cache set index 1504c stored in the third cache set register 1312d. Figure 15B , making the third cache set 1310d available and usable for speculative execution. The logic circuit 1006 may also be configured to store the third cache set index in the first cache set register or another cache set register associated with another cache set in the first subset of the plurality of cache sets, so that when the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted, the first cache set or another cache set in the first subset is used as a backup cache set. For example, see the diagram depicting the cache set index 1504d stored in the first cache set register 1312b. Figure 15B , so that the first cache set 1310b is used as a backup cache set.

[0257] Figure 14A 、 14B 14C and 14C illustrate a cache having a plurality of caches including a backup cache set (e.g., see FIG. Figure 14A and 14B The backup cache set 1310d shown in FIG. Figure 14C 1310b) to accelerate speculative execution of interchangeable cache sets (e.g., see cache sets 1310a, 1310b, 1310c, and 1310d). In particular, Figure 14A The cache sets are shown in a first state in which cache sets 1310a and 1310b are available for non-speculative execution, cache set 1310c is available for speculative execution, and cache set 1310d is used as a backup cache set. Figure 14B The cache sets are shown in a second state in which cache sets 1310a, 1310b, and 1310c are available for non-speculative execution and cache set 1310c is available and usable for speculative execution. Figure 14C The cache sets are shown in a third state in which cache sets 1310a and 1310c are available for non-speculative execution, cache set 1310d is available for speculative execution, and cache set 1310b is used as a backup cache set.

[0258] Figure 15A 、 15B , 15C and 15D each show example aspects of an example computing device having a cache system 1000 with interchangeable cache sets (e.g., see cache sets 1310a, 1310b, 1310c and 1310d) that include spare cache sets to accelerate speculative execution in accordance with some embodiments of the present disclosure.

[0259] Specifically, Figure 15A The cache sets are shown in a first state in which cache sets 1310a and 1310b are available for non-speculative execution (or a first type of execution), cache set 1310c is available for speculative execution (or a second type of execution), and cache set 1310d is used as a backup cache set. Figure 15AAs shown in FIG, in this first state, logic circuit 1006 may be configured to store cache set index 1504b in cache set register 1312b, so that content 1502b in cache set 1310b is used for non-speculative execution. Additionally, in this first state, logic circuit 1006 may be configured to store cache set index 1504c in cache set register 1312c, so that cache set 1310c is available and can be used for speculative execution. Logic circuit 1006 may also be configured to store cache set index 1504d in cache set register 1312d, so that cache set 1310d is used as a backup cache set in this first state.

[0260] Figure 15B The cache sets are shown in a second state in which cache sets 1310a and 1310c are available for non-speculative execution, cache set 1310d is available for speculative execution, and cache set 1310b is used as a backup cache set. Figure 15B The second state depicted in occurs when the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted. Figure 15B As shown in FIG, in this second state, the logic circuit 1006 can be configured to store the cache set index 1504b in the cache set register 1312c, so that the contents 1502b in the cache set 1310c are used for non-speculative execution. Additionally, in this second state, the logic circuit 1006 can be configured to store the cache set index 1504c in the cache set register 1312d, so that the cache set 1310d is available for speculative execution. The logic circuit 1006 can also be configured to store the cache set index 1504d in the cache set register 1312b, so that the cache set 1310b is used as a backup cache set in this second state.

[0261] Figure 15C The cache sets are shown mostly in a second state, where cache sets 1310a and 1310c are available for non-speculative execution and cache set 1310b is used as a backup cache set. Figure 15C , cache set 1310d is shown being used for speculative execution rather than just being available. Figure 15C As shown in FIG. 5 , in this second state, the logic circuit 1006 may be configured to store the cache set index 1504c in the cache set register 1312d so that the content 1502c held in the cache set 1310d is also available for speculative execution.

[0262] Figure 15D The cache sets are shown in a third state in which cache sets 1310a and 1310d are available for non-speculative execution, cache set 1310b is available for speculative execution, and cache set 1310c is used as a backup cache set. In subsequent cycles after the second state, Figure 15D The third state depicted in occurs when the execution type changes again from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted. Figure 15D As shown in FIG, in this third state, logic circuit 1006 may be configured to store cache set index 1504b in cache set register 1312d, so that content 1502b in cache set 1310d is used for non-speculative execution. Additionally, in this third state, logic circuit 1006 may be configured to store cache set index 1504c in cache set register 1312b, so that cache set 1310b is available for speculative execution. Logic circuit 1006 may also be configured to store cache set index 1504d in cache set register 1312c, so that cache set 1310c is used as a backup cache set in this third state.

[0263] As Figures 15A to 15D As shown, the cache sets are interchangeable and the cache sets used as backup cache sets are also interchangeable.

[0264] In such an embodiment, when a memory address is received from processor 1001 via connection 604b to address bus 605b, logic circuitry 1006 may be configured to generate a set index from at least memory address 102b based on the cache set index 112b of the address (e.g., see set index generation 1506a, 1506b, 1506c, and 1506d, which generate set indexes 1504a, 1504b, 1504c, and 1504d, respectively). Furthermore, when a memory address is received from processor 1001 via connection 604b to address bus 605b, logic circuitry 1006 may be configured to determine whether the generated set index matches the contents stored in one of the registers (which may be stored set index 1504a, 1504b, 1504c, or 1504d). Furthermore, logic circuitry 1006 may be configured to execute a command received via connection 604a to command bus 605a via the cache set in response to the generated set index matching the contents stored in the corresponding register. Furthermore, in response to determining that a data set of the memory system associated with the memory address is not currently cached in the cache system, the logic circuit 1001 may be configured to allocate a cache set for caching the data set and store a generated set index in a corresponding register. The generated set index may include a predetermined segment of bits in the memory address, such as Figures 15A to 15B As shown in .

[0265] Furthermore, in such an embodiment, the logic circuit 1006 may be configured to generate a set index (e.g., see set indexes 1504a, 1504b, 1504c, and 1504d) based on a memory address (e.g., memory address 102b) received from the address bus 605b from the processor 1001 and an identification of speculative execution or non-speculative execution received from the execution type signal line 605d identifying the execution type from the processor. Furthermore, the logic circuit 1006 may be configured to determine whether the set index matches the contents stored in the cache set register 1312b, the cache set register 1312c, or the cache set register 1312d.

[0266] In some embodiments, a cache system may include a plurality of cache sets, a connection to an execution type signal line from a processor that identifies an execution type, a connection to a signal line from the processor that identifies a state of speculative execution, and logic circuitry. The logic circuitry may be configured to: allocate a first subset of the plurality of cache sets for caching in a cache operation when the execution type is a first type indicating non-speculative execution of instructions by the processor; and allocate a second subset of the plurality of cache sets for caching in a cache operation when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuitry may also be configured to retain at least one cache set (or a third subset of the plurality of cache sets) when the execution type is the second type. When the execution type changes from the second type to the first type and the state of speculative execution indicates that the results of speculative execution will be accepted, the logic circuitry may also be configured to reconfigure the second subset for caching in a cache operation when the execution type is the first type. Furthermore, when the execution type changes from the second type to the first type and the state of the speculative execution indicates that the result of the speculative execution will be accepted, the logic circuit may also be configured to allocate at least one cache set (or a third subset of the plurality of cache sets) for caching in a cache operation when the execution type changes from the first type to the second type.

[0267] In such an embodiment, the logic circuit may be configured to retain at least one cache set (or a third subset of the multiple cache sets) when the execution type is the second type and the at least one cache set (or a third subset of the multiple cache sets) contains the least used cache set among the multiple cache sets.

[0268] Furthermore, in such embodiments, the cache system may include one or more mapping tables that map the plurality of cache sets. In such instances, the logic circuitry is configured to allocate and reconfigure subsets of the plurality of cache sets according to the one or more mapping tables.

[0269] Furthermore, in such an embodiment, the cache system may include a plurality of cache set registers, each associated with the plurality of cache sets. In such an example, the logic circuitry is configured to allocate and reconfigure subsets of the plurality of cache sets based on the plurality of cache set registers. In such an example, a first subset of the plurality of cache sets may include a first cache set, a second subset of the plurality of cache sets may include a second cache set, and at least one cache set (or a third subset of the plurality of cache sets) may include a third cache set. Furthermore, the plurality of cache set registers may include a first cache set register associated with the first cache set, the first cache set register configured to initially store a first cache set index, such that the first cache set is used for non-speculative execution. The plurality of cache set registers may also include a second cache set register associated with the second cache set, the second cache set register configured to initially store a second cache set index, such that the second cache set is used for speculative execution. The plurality of cache set registers may also include a third cache set register associated with a third cache set, the third cache set register configured to initially store a third cache set index such that the third cache set serves as a backup cache set.

[0270] In such an embodiment, the logic circuitry may be configured to generate a set index based on a memory address received from an address bus from a processor and an identification of speculative execution or non-speculative execution received from an execution type signal line from the processor that identifies the execution type. Furthermore, the logic circuitry may be configured to determine whether the set index matches the contents stored in the first cache set register, the second cache set register, or the third cache set register. When the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted, the logic circuitry may be further configured to store the first cache set index in the second cache set register or another cache set register associated with another cache set in a second subset of the plurality of cache sets, so that the second cache set or another cache set in the second subset is used for non-speculative execution. When the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted, the logic circuitry may be further configured to store the second cache set index in a third cache set register or another cache set register associated with another cache set in the at least one cache set (or a third subset of the plurality of cache sets), so that the third cache set or another cache set in the at least one cache set (or a third subset of the plurality of cache sets) is used for speculative execution. When the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted, the logic circuitry may be further configured to store the third cache set index in the first cache set register or another cache set register associated with another cache set in the first subset of the plurality of cache sets, so that the first cache set or another cache set in the first subset is used as a backup cache set.

[0271] In some embodiments, a cache system may include a plurality of cache sets including a first subset of cache sets, a second subset of cache sets, and a third subset of cache sets. The cache system may also include a connection to an execution type signal line from a processor that identifies an execution type, a connection to a signal line from the processor that identifies a state of speculative execution, and logic circuitry. The logic circuitry may be configured to: allocate the first subset of the plurality of cache sets for caching in a cache operation when the execution type is a first type indicating non-speculative execution of instructions by the processor; and allocate the second subset of the plurality of cache sets for caching in a cache operation when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuitry may also be configured to retain the third subset of the plurality of cache sets when the execution type is the second type. When the execution type changes from the second type to the first type and the state of speculative execution indicates that the results of speculative execution will be accepted, the logic circuitry may also be configured to reconfigure the second subset for caching in a cache operation when the execution type is the first type. When the execution type changes from the second type to the first type and the status of the speculative execution indicates that the results of the speculative execution will be accepted, the logic circuitry may be further configured to allocate the third subset for caching in a cache operation when the execution type changes from the first type to the second type.

[0272] In some embodiments, a cache system may include multiple caches, including a first cache, a second cache, and a third cache. The cache system may also include a connection to an execution type signal line from a processor that identifies an execution type, a connection to a signal line from the processor that identifies a state of speculative execution, and logic circuitry. The logic circuitry may be configured to: allocate the first cache for caching in a cache operation when the execution type is a first type indicating non-speculative execution of instructions by the processor; and allocate the second cache for caching in a cache operation when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuitry may also be configured to retain the third cache when the execution type is the second type. When the execution type changes from the second type to the first type and the state of speculative execution indicates that the results of speculative execution will be accepted, the logic circuitry may also be configured to reconfigure the second cache for caching in a cache operation when the execution type is the first type. Furthermore, the logic circuitry may be configured to allocate the third cache for caching in a cache operation when the execution type changes from the first type to the second type.

[0273] Figure 16 and 17Example aspects of an example computing device having a cache system with interchangeable cache sets (e.g., see cache sets 1610a, 1610b, 1710a, and 1710b) utilizing extended tags (e.g., see extended tags 1640a, 1640b, 1740a, and 1740b) for different types of execution (e.g., speculative and non-speculative execution) by a processor are shown in accordance with some embodiments of the present disclosure. Additionally, Figure 16 and 17 Describes addressing cache systems (e.g., Figure 6 、 10 1 and 13. Furthermore, the manner in which cache sets and cache blocks may be selected via memory addresses, such as memory address 102e or 102b and memory addresses 102a, 102c, or 102d (shown in FIG. 1), is shown.

[0274] Figure 16 and 17 The two examples in use set associativity, and cache systems such as cache systems 600 and 1000 can be implemented using set associativity. Figure 16 In , set associativity is implicitly defined (e.g., by an algorithm that can be used to determine which tags should be in which cache set for a given execution type). Figure 17 In [ ] , set associativity is implemented via the bits of the cache set index in the memory address. In addition, Figure 16 and 17 The functionality described in can be implemented without using set association (although this is not depicted), for example by separately showing Figure 2 and 4 The cache systems 200 and 400 are implemented in FIG.

[0275] exist Figure 16 and 17In the embodiment of the present invention, block indices (e.g., see block indices 106e and 106b) can be used as addresses within individual cache sets (e.g., see cache sets 1610a, 1610b, 1710a, and 1710b) to identify specific cache blocks in the cache sets (e.g., see cache blocks 1624a, 1624b, 1628a, 1628b, 1724a, 1724b, 1728a, and 1728b). Also, extended tags (e.g., extended tags 1640a, 1640b, 1740a, 1740b, 1650, and 1750) can be used as addresses of cache sets. A block index (e.g., see block indexes 106e and 106b) of a memory address (e.g., see memory addresses 102e and 102b) may be used in each cache set (e.g., see cache sets 1610a, 1610b, 1710a, and 1710b) to obtain a cache block (e.g., see cache blocks 1624a, 1624b, 1628a, 1628b, 1724a, 1724b, 1728a, and 1728b) and a tag associated with the cache block (e.g., see corresponding tags 1622a, 1622b, 1626a, 1626b, 1722a, 1722b, 1726a, and 1726b).

[0276] In addition, if Figure 16 and 17 As shown in FIG, tag comparison circuits (e.g., tag comparison circuits 1660a, 1660b, 1760a, and 1760b) can compare extended tags generated from cache sets (e.g., extended tags 1640a, 1640b, 1740a, and 1740b) with extended cache tags (e.g., extended tag 1650) from a memory address (e.g., see memory addresses 102e and 102b) and a current execution type (e.g., see execution types 110e and 110b) to determine a cache hit or miss. The construction of the extended tags ensures that there is at most one hit among the cache sets (e.g., see cache sets 1610a, 1610b, 1710a, and 1710b). If there is a hit, then the cache block from the selected cache set (e.g., see cache blocks 1624a, 1624b, 1628a, 1628b, 1724a, 1724b, 1728a, and 1728b) provides the output. Otherwise, the data associated with the memory address (e.g., memory address 102e or 102b) is not cached in or output from any of the cache sets. In short, Figure 16 and 17 The extended tag depicted in is used to select a cache set, and the block index is used to select a cache block and its tag within the cache set.

[0277] In addition, if Figure 16 and 17 , memory addresses are partitioned differently (e.g., see addresses 102e and 102b); and therefore, the control of cache operations according to address is also different. However, there are some similarities. For example, Figure 16 and 17 A system in which cache set usage is controlled via set associativity. Control of cache operations may include controlling whether a cache set is used for a first or second type of execution (e.g., non-speculative and speculative execution) by a processor, and such control may be controlled to some extent or entirely via set associativity.

[0278] exist Figure 16 In FIG, the extended tag 1650 of the memory address 102e has an execution type 110e and a tag 104e having a cache set indicator that implements set associativity. Figure 17 , the extended tag 1750 for memory address 102b has an execution type 110e, a cache set index 112b, and a tag 104b. In this example, the cache set index 112b implements set associativity rather than a cache set indicator in the tag. Different partitioning of the memory address slightly changes how the extended tags (e.g., extended tags 1640a, 1640b, 1650, 1740a, 1740b, and 1750) control cache operations via set associativity.

[0279] In the case of memory address segmentation, in an example, the extended tag from the memory address and execution type (e.g., see extended tags 1650 and 1750) is compared with the extended tag for the cache set (e.g., see extended tags 1640a, 1640b, 1740a, and 1740b) to control cache operations implemented via the cache set. Depending on whether the extended tags input to the comparison circuit match or do not match, the tag comparison circuit (e.g., tag comparison circuits 1660a, 1660b, 1760a, and 1760b) can output a hit or a miss. The extended tags of the cache sets (e.g., see extended tags 1640a, 1640b, 1740a, and 1740b) can be derived from the execution types (e.g., see execution types 1632a, 1632b, 1732a, and 1732b) stored in registers (e.g., see registers 1612a, 1612b, 1712a, and 1712b) and the block tags (e.g., see tags 1622a, 1622b, 1626a, 1626b, 1722a, 1722b, 1726a, and 1726b) from the first cache set (e.g., see cache sets 1610a, 1610b, 1710a, and 1710b). And, as Figure 16 and 17 , the execution type is different in each register of the cache set. For the example shown, a first cache set (e.g., cache set 1610a or 1710a) can be used for a first type of execution (e.g., non-speculative execution), and a second cache set (e.g., cache set 1610b or 1710b) can be used for a second type of execution (e.g., speculative execution).

[0280] exist Figure 17 In FIG. 1 , the combination of tag 104 b and cache set index 112 b is provided and illustrated in FIG. Figure 16 Similar functionality to tag 104e in . However, in Figure 17 In , by separating the tag 104b and the cache set index 112b, the cache sets do not have to store redundant copies of the cache set index 112b because the cache sets (e.g., see cache sets 1710a and 1710b) can be associated with cache set registers (e.g., see registers 1732a and 1732b) to store the cache set index (e.g., see cache set indexes 1732a and 1732b). Figure 16, a cache set (e.g., see cache sets 1610a and 1610b) does need to store redundant copies of the cache set indicator in each of its blocks (e.g., see blocks 1624a, 1624b, 1628a, and 1628b) because the cache set's associated registers are not configured to store cache set indexes.

[0281] In other words, since tags 1622a, 1622b, etc. have the same cache set indicator, the indicator may be stored once in the register for the cache set (e.g., see cache set registers 1712a and 1712b). Figure 17 The arrangement depicted in Figure 16 One of the benefits of the arrangement depicted in . In addition, Figure 17 The lengths of the labels 1722a, 1722b, 1726a, and 1726b in FIG. 1 are similar to those shown in FIG. Figure 16 The tags in FIG. 16 are shorter than those in FIG. 16 (e.g., see 1622a, 1622b, 1626a, and 1626b) due to Figure 17 The cache set registers depicted in FIG. 1 (eg, registers 1710 a and 1710 b ) store both a cache set index and an execution type.

[0282] When the execution type is combined with the cache set index to form an extended cache set index, the extended cache set index can be used to select one of the cache sets. The tag from the selected cache set is then compared with the tag in the address to determine a hit or miss. The two-step selection can be similar to a conventional two-step selection using the cache set index, or can be used in combination with the extended tag to support more efficient interchange of cache sets for different execution types (e.g., speculative and non-speculative execution types).

[0283] In some embodiments, a cache system (e.g., cache system 600 or 1000) may include multiple cache sets (e.g., cache sets 610a-610c, 1010a-1010c, 1310a-1310d, 1610a-1610b, or 1710a-1710b). The multiple cache sets may include a first cache set and a second cache set (e.g., see cache sets 1610a-1610b and sets 1710a-1710b). The cache system may also include multiple registers (e.g., registers 612a-612c, 1012a-1012c, 1312a-1312d, 1612a-1612b, or 1712a-1712b) associated with the multiple cache sets, respectively. The plurality of registers may include a first register associated with a first cache set, and a second register associated with a second cache set (eg, see registers 1612a-1612b and registers 1712a-1712b).

[0284] The cache system may also include a connection (e.g., see connection 604a) to a command bus (e.g., see command bus 605a) coupled between the cache system and a processor (e.g., see processors 601 and 1001). The cache system may also include a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) coupled between the cache system and the processor.

[0285] The cache system may also include logic circuitry coupled to the processor to control the plurality of cache sets based on the plurality of registers (e.g., see logic circuitry 606 and 1006). When a memory address is received from the processor via the address bus (e.g., see memory addresses 102a through 102e shown in FIG. 1 and 102f shown in FIG. 2 , respectively), the cache system may further include logic circuitry coupled to the processor to control the plurality of cache sets based on the plurality of registers (e.g., see logic circuitry 606 and 1006). Figure 16 and 17 When receiving addresses 102e and 102b in the memory bus, the logic circuitry may be configured to generate an extended tag (e.g., see extended tags 1650 and 1750) from at least the memory address. Furthermore, when receiving a memory address from the processor via the connection to the address bus, the logic circuitry may be configured to determine whether the generated extended tag (e.g., see extended tags 1650 and 1750) matches a first extended tag (e.g., see extended tags 1640a and 1740a) of a first cache set (e.g., see cache sets 1610a and 1710a) or a second extended tag (e.g., see extended tags 1640b and 1740b) of a second cache set (e.g., see cache sets 1610b and 1710b).

[0286] The logic circuit (e.g., see logic circuits 606 and 1006) may also be configured to implement a command received in a connection (e.g., see connection 604a) to a command bus (e.g., see command bus 605a) via a first cache set (e.g., see cache sets 1610a and 1710a) in response to a generated extended tag (e.g., see extended tags 1650 and 1750) matching a first extended tag (e.g., see extended tags 1640a and 1740a), and to implement the command via a second cache set (e.g., see cache sets 1610b and 1710b) in response to a generated extended tag matching a second extended tag (e.g., see extended tags 1640b and 1740b).

[0287] The logic circuit (e.g., see logic circuits 606 and 1006) may also be configured to generate a first extended tag (e.g., see extended tags 1640a and 1740a) from a cache address of a first cache set (e.g., see cache sets 1610a and 1710a) (e.g., see the block marked as 'tag' in extended tags 1640a and 1740a, and tags 1622a, 1622b, 1722a, 1722b, etc.) and the contents stored in a first register (e.g., see registers 1612a and 1712a) (e.g., see the block marked as 'execution type' in extended tags 1640a and 1740a and the block marked as 'cache set index' in extended tags 1740a, as well as execution type 1632a and cache set index 1732a). The logic circuit may also be configured to generate a second extended tag (e.g., see extended tags 1640b and 1740b) from a cache address of a second cache set (e.g., see cache sets 1610b and 1710b) (e.g., see the block marked as 'tag' in extended tags 1640b and 1740b, and tags 1626a, 1626b, 1726a, 1726b, etc.) and the contents stored in a second register (e.g., see registers 1612b and 1712b) (e.g., see the block marked as 'execution type' in extended tags 1640b and 1740b and the block marked as 'cache set index' in extended tags 1740b, as well as execution type 1632b and cache set index 1732b).

[0288] In some embodiments, the cache system (e.g., cache system 600 or 1000) may further include a connection (e.g., see connection 604d) to an execution type signal line (e.g., see execution type signal line 605d) from a processor (e.g., see processors 601 and 1001) that identifies the execution type. In such embodiments, the logic circuit (e.g., see logic circuits 606 and 1006) may be configured to retrieve the execution type from a memory address (e.g., see the execution type signal line 605d shown in FIG. 10 , respectively). Figure 16 and 17 102e and 102b in the memory address) and the execution type identified by the execution type signal line (see, for example, the execution type signal line shown in FIG. Figure 16 and 17 The execution type 110e in the example generates an extended tag (e.g., see extended tags 1650 and 1750). In addition, in such an embodiment, the content stored in each of the first register and the second register (e.g., see registers 1612a, 1612b, 1712a, and 1712b) may include an execution type (e.g., see first execution type 1632a and second execution type 1632b).

[0289] In some embodiments, to determine whether the generated extended tag (e.g., see extended tags 1650 and 1750) matches the first extended tag of the first cache set (e.g., see extended tags 1640a and 1740a) or the second extended tag of the second cache set (e.g., see extended tags 1640b and 1740b), logic circuitry (e.g., see logic circuitry 606 and 1006) may be configured to compare the first extended tag (e.g., see extended tags 1640a and 1740a) with the generated extended tag (e.g., see extended tags 1650 and 1750) to determine a cache hit or miss for the first cache set (e.g., see cache sets 1610a and 1710a). Specifically, as Figure 16 and 17 As shown in FIG, a first tag comparison circuit (e.g., see tag comparison circuits 1660a and 1760a) is configured to receive a first extended tag (e.g., see extended tag 1640a and 1740a) and a generated extended tag (e.g., see extended tags 1650 and 1750) as inputs. The first tag comparison circuit (e.g., see tag comparison circuits 1660a and 1760a) is further configured to compare the first extended tag with the generated extended tag to determine a cache hit or miss for the first cache set. The first tag comparison circuit (e.g., see tag comparison circuits 1660a and 1760a) is further configured to output the determined cache hit or miss for the first cache set (e.g., see outputs 1662a and 1762a).

[0290] Furthermore, to determine whether the generated extended tag matches the first extended tag of the first cache set or the second extended tag of the second cache set, the logic circuitry may be configured to compare the second extended tag (e.g., see extended tags 1640b and 1740b) with the generated extended tag (e.g., see extended tags 1650 and 1750) to determine a cache hit or miss for the second cache set (e.g., see cache sets 1610b and 1710b). Specifically, as Figure 16 and 17 As shown in FIG, a second tag comparison circuit (e.g., see tag comparison circuits 1660b and 1760b) is configured to receive as input a second extended tag (e.g., see extended tags 1640b and 1740b) and a generated extended tag (e.g., see extended tags 1650 and 1750). The second tag comparison circuit (e.g., see tag comparison circuits 1660b and 1760b) is further configured to compare the second extended tag with the generated extended tag to determine a cache hit or miss for the second cache set. The second tag comparison circuit (e.g., see tag comparison circuits 1660b and 1760b) is further configured to output the determined cache hit or miss for the second cache set (e.g., see outputs 1662b and 1762b).

[0291] In some embodiments, the logic circuit (e.g., see logic circuits 606 and 1006) may be further configured to receive an output from a first cache set (e.g., see cache sets 1610a and 1710a) when the logic circuit determines that the generated extended tag (e.g., see extended tags 1640a and 1740a) matches a first extended tag of the first cache set (e.g., see extended tags 1640a and 1740a). The logic circuit may be further configured to receive an output from a second cache set (e.g., see cache sets 1610a and 1710a) when the logic circuit determines that the generated extended tag (e.g., see cache sets 1610a and 1710a) matches a second extended tag of the second cache set (e.g., see extended tags 1640a and 1740a).

[0292] In some embodiments, the cache address of a first cache set includes the first tag (e.g., see tags 1622a, 1622b, 1722a, and 1722b) of the cache blocks (e.g., see cache blocks 1628a, 1628b, 1728a, and 1728b) in the first cache set (e.g., see cache sets 1610a and 1710a). In such embodiments, the cache address of a second cache set includes the second tag (e.g., see tags 1626a, 1626b, 1726a, and 1726b) of the cache blocks (e.g., see cache blocks 1628a, 1628b, 1728a, and 1728b) in the second cache set (e.g., see cache sets 1610b and 1710b). Furthermore, in such embodiments, generally, a block index is used as an address within an individual cache set. For example, in such an embodiment, the logic circuits (e.g., see logic circuits 606 and 1006) may be configured to use a first block index from a memory address (e.g., see the first block index shown in FIG. Figure 16 and 17 102b) to obtain a first cache block in the first cache set and a tag associated with the first cache block (e.g., see cache blocks 1624a, 1624b, 1724a, and 1724b and corresponding associated tags 1622a, 1622b, 1722a, and 1722b). In addition, logic circuitry (e.g., see logic circuits 606 and 1006) may be configured to use a second block index from the memory address (e.g., see the block indexes 106e and 106b shown in FIG. 102b, respectively). Figure 16 and 17 The memory block 102e and 102b are obtained by using block indices 106e and 106b from memory addresses 102e and 102b in the memory block 102e to obtain a second cache block in the second cache set and a tag associated with the second cache block (e.g., see cache blocks 1628a, 1628b, 1728a, and 1728b and corresponding associated tags 1626a, 1626b, 1726a, and 1726b).

[0293] In some embodiments (e.g. Figure 16), when the first and second cache sets (e.g., see cache sets 1610a and 1610b) are in a first state, a cache address of the first cache set (e.g., see tags 1622a, 1622b, etc.) includes a first cache set indicator associated with the first cache set. The first cache set indicator may be a first cache set index. In such an embodiment, when the first and second cache sets are in the first state, a cache address of the second cache set (e.g., see tags 1626a, 1626b, etc.) includes a second cache set indicator associated with the second cache set. The second cache set indicator may be a second cache set index.

[0294] In addition, in the presentation Figure 16 In the embodiment of FIG. 1 , when the first and second cache sets (eg, see cache sets 1610a and 1610b) are in the second state (this is not Figure 16 ), a cache address of the first cache set includes a second cache set indicator associated with the second cache set. Additionally, when the first and second cache sets are in the second state, the cache address of the second cache set includes the first cache set indicator associated with the first cache set. This change in content within the cache address implements interchangeability between the cache sets.

[0295] On display at Figure 16 In the case of the embodiment in FIG. 1 , the cache set indicator is repeated in the tag of each cache block in the cache set, and therefore, the tag is more specific than the tag. Figure 17 The cache set depicted in has a longer tag for each cache block. Figure 17 In , instead of repeating the cache set index in the tag of each cache block, the set index is stored in a cache set register associated with the cache set (eg, see registers 1712a and 1712b).

[0296] In some embodiments (e.g. Figure 17In the embodiment described in (e.g., see cache sets 1710a and 1710b) when the first and second cache sets are in the first state, cache addresses of the first cache set (e.g., see tags 1722a, 1722b, etc.) may not include a first cache set indicator associated with the first cache set. Instead, the first cache set indicator is shown as being stored in first cache set register 1712a (e.g., see first cache set index 1732a stored in cache set register 1712a). This can reduce the size of tags for cache blocks in the first cache set because the cache set indicator is stored in a register associated with the first cache set. Furthermore, when the first and second cache sets are in the first state, cache addresses of the second cache set (e.g., see tags 1726a, 1726b, etc.) may not include a second cache set indicator associated with the second cache set. Alternatively, the second cache set indicator is shown as being stored in the second cache set register 1712 b (e.g., see second cache set index 1732 b stored in cache set register 1712 b). This can reduce the size of the tags for cache blocks in the second cache set because the cache set indicator is stored in a register associated with the second cache set.

[0297] In addition, in the presentation Figure 17 In the embodiment of FIG. 1 , when the first and second cache sets (eg, see cache sets 1710a and 1710b) are in the second state (this is not Figure 17 ), a cache address of the first cache set (e.g., see tags 1722a, 1722b, etc.) may not include the second cache set indicator associated with the second cache set. Instead, the second cache set indicator will be stored in first cache set register 1712a. Furthermore, when the first and second cache sets are in the second state, a cache address of the second cache set (e.g., see tags 1726a, 1726b, etc.) may not include the first cache set indicator associated with the first cache set. Instead, the first cache set indicator will be stored in second cache set register 1712b. This change in the contents of the cache set registers may implement interchangeability between the cache sets.

[0298] In some embodiments, as Figure 17, when the first and second registers (e.g., see registers 1712a and 1712b) are in a first state, the content stored in the first register (e.g., see register 1712a) may include a first cache set index (e.g., see cache set index 1732a) associated with the first cache set (e.g., see cache set 1710a). And, the content stored in the second register (e.g., see register 1712b) may include a second cache set index (e.g., see cache set index 1732b) associated with the second cache set (e.g., see cache set 1710a). In this embodiment, although not shown in FIG. Figure 17 , but when the first and second registers are in the second state, the contents stored in the first register may include a second cache set index associated with the second cache set, and the contents stored in the second register may include a first cache set index associated with the first cache set.

[0299] In some embodiments (e.g. Figure 16 In the embodiments shown in FIG. 1 and, for example, embodiments having a connection to an execution type signal line that identifies an execution type, the cache system (e.g., see cache system 1000) may further include a connection (e.g., see connection 1002) to a speculation state signal line (e.g., see speculation state signal line 1004) from a processor (e.g., see processor 1001) that identifies a state of speculative execution of instructions by the processor. In such embodiments, the connection to the speculation state signal line may be configured to receive a state of speculative execution. The state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to change the state of the first and second cache sets (e.g., see cache sets 1610a and 1610b) if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to maintain the states of the first and second cache sets (e.g., see cache sets 1610a and 1610b) without change if the state of the speculative execution indicates that the result of the speculative execution will be rejected.

[0300] Similarly to some extent, in some embodiments (e.g. Figure 17In the embodiments shown in and, for example, embodiments having a connection to an execution type signal line that identifies an execution type, the cache system may further include a connection to a speculation state signal line from the processor that identifies a state of speculative execution of instructions by the processor. In such embodiments, the connection to the speculation state signal line may be configured to receive a state of speculative execution. The state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to change the states of the first and second cache sets (e.g., see cache sets 1610a and 1610b) if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to change the states of the first and second registers (e.g., see registers 1712a and 1712b) if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to maintain the state of the first and second registers (e.g., see registers 1712a and 1712b) unchanged if the state of the speculative execution indicates that the result of the speculative execution will be rejected.

[0301] In some embodiments, a cache system may include multiple cache sets, the multiple cache sets including a first cache set and a second cache set. The cache system may also include multiple registers associated with the multiple cache sets, the multiple registers including a first register associated with the first cache set and a second register associated with the second cache set. The cache system may further include a connection to a command bus coupled between the cache system and a processor, a connection to an address bus coupled between the cache system and the processor, and logic circuitry coupled to the processor to control the multiple cache sets based on the multiple registers. The logic circuitry may be configured to generate a first extended tag from a cache address of the first cache set and contents stored in a first register, and to generate a second extended tag from a cache address of the second cache set and contents stored in a second register. The logic circuitry may also be configured to determine whether the first extended tag of the first cache set or the second extended tag of the second cache set matches a generated extended tag generated based on a memory address received from the processor. Furthermore, the logic circuitry may be configured to implement a command received in connection with the command bus via the first cache set in response to the generated extended tag matching the first extended tag, and to implement the command via the second cache set in response to the generated extended tag matching the second extended tag.

[0302] In this embodiment, the cache system may further include a connection to an address bus coupled between the cache system and the processor. When the connection to the address bus receives a memory address from the processor, the logic circuitry may be configured to generate an extended tag from at least the memory address. Furthermore, the cache system may include a connection to an execution type signal line from the processor that identifies an execution type. In this example, the logic circuitry may be configured to generate an extended tag from the memory address and the execution type identified by the execution type signal line. Furthermore, the contents stored in each of the first register and the second register may include the execution type.

[0303] Additionally, to determine whether the generated extended tag matches the first extended tag of the first cache set or the second extended tag of the second cache set, the logic circuitry may be configured to: compare the first extended tag with the generated extended tag to determine a cache hit or miss for the first cache set; and compare the second extended tag with the generated extended tag to determine a cache hit or miss for the second cache set. Furthermore, the logic circuitry may be configured to: receive an output from the first cache set when the logic circuitry determines that the generated extended tag matches the first extended tag of the first cache set; and receive an output from the second cache set when the logic circuitry determines that the generated extended tag matches the second extended tag of the second cache set. In this and other embodiments, the cache address of the first cache set may include the first tag of a cache block in the first cache set, and the cache address of the second cache set may include the second tag of a cache block in the second cache set.

[0304] In some embodiments, a cache system may include multiple cache sets, the multiple cache sets including a first cache set and a second cache set. The cache system may also include multiple registers associated with each of the multiple cache sets, the multiple registers including a first register associated with the first cache set and a second register associated with the second cache set. Furthermore, the cache system may include a connection to a command bus coupled between the cache system and a processor, a connection to an execution type signal line from the processor that identifies an execution type, a connection to an address bus coupled between the cache system and the processor, and logic circuitry coupled to the processor to control the multiple cache sets based on the multiple registers. When the connection to the address bus receives a memory address from the processor, the logic circuitry may be configured to: generate an extended tag from the memory address and the execution type identified by the execution type signal line; and determine whether the generated extended tag matches a first extended tag of the first cache set or a second extended tag of the second cache set. Furthermore, the logic circuitry may be configured to execute a command received in the connection to the command bus via the first cache set in response to the generated extended tag matching the first extended tag, and to execute the command via the second cache set in response to the generated extended tag matching the second extended tag.

[0305] Figure 18 1820b and 1820c) with interchangeable cache sets (e.g., see cache sets 1810a, 1810b, and 1810c) that map physical cache set outputs (e.g., see physical outputs 1820a, 1820b, and 1820c) to logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c) using mapping circuitry 1830 in accordance with some embodiments of the present disclosure (e.g., see cache sets 1810a, 1810b, and 1810c, respectively). Figure 6 and 10 Instance aspects of an instance computing device of the cache systems 600 and 1000 in FIG.

[0306] As shown, the cache system may include a plurality of cache sets (e.g., see cache sets 1810a, 1810b, and 1810c). The plurality of cache sets includes a first cache set (e.g., see cache set 1810a) configured to provide a first physical output (e.g., see physical output 1820a) upon a cache hit, and a second cache set (e.g., see cache set 1810b) configured to provide a second physical output (e.g., see physical output 1820b) upon a cache hit. The cache system may also include a connection (e.g., see command bus 605a) coupled between the cache system and a processor (e.g., see processors 601 and 1001). Figure 6 and 10 6. The cache system may also include a connection (eg, see connection 604b) to an address bus (eg, see address bus 605b) coupled between the cache system and the processor.

[0307] Shown in Figure 18 In the embodiment, the cache system includes a control register 1832 (e.g., a physical to logical-set-mapping (PLSM) register 1832) and a mapping circuit 1830, wherein the mapping circuit 1830 is coupled to the control register to map corresponding physical outputs (e.g., see physical outputs 1820a, 1820b, and 1820c) of a plurality of cache sets (e.g., see cache sets 1810a, 1810b, and 1810c) to a first logical cache (e.g., a normal cache) and a second logical cache (e.g., a shadow cache) as corresponding logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c). The mapping of the physical outputs (e.g., see physical outputs 1820a, 1820b, and 1820c) to the logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c) by the mapping circuit 1830 is based on the state of the control register 1832. Figure 18 , at least logical outputs 1840a and 1840b are mapped to a first logical cache for a first type of execution, and at least logical output 1840c is mapped to a second logical cache for a second type of execution. Not shown, a cache system may be configured to be coupled between a processor and a memory system (e.g., see memory system 603).

[0308] When a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when control register 1832 is in a first state (shown in FIG. Figure 18 ), mapping circuitry 1830 may be configured to map a first physical output (e.g., see physical output 1820a) to a first logical cache (e.g., see logical output 1840a) for a first type of execution by the processor to implement a command received from a command bus (e.g., see command bus 605a) for accessing a memory system (e.g., see memory system 601) via a first cache set (e.g., cache set 1820a) during the first type of execution (e.g., non-speculative execution).

[0309] Furthermore, when a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when control register 1832 is in a first state (shown in FIG. Figure 18 ), mapping circuitry 1830 may be configured to map a second physical output (e.g., see physical output 1820b) to a second logical cache (e.g., see logical output 1840b) for a second type of execution by the processor to implement a command received from the command bus (e.g., see command bus 605a) for accessing the memory system (e.g., see memory system 601) via the second cache set (e.g., cache set 1820b) during the second type of execution (e.g., speculative execution).

[0310] When a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when control register 1832 is in a second state (not shown), Figure 18 ), mapping circuitry 1830 is configured to map a first physical output (e.g., see physical output 1820a) to a second logical cache (e.g., see logical output 1840b) to implement a command received from a command bus (e.g., see command bus 605a) for accessing a memory system (e.g., see memory system 601) via the first cache set (e.g., cache set 1820a) during a second type of execution (e.g., speculative execution).

[0311] Furthermore, when a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when control register 1832 is in a second state (not shown), Figure 18 ), mapping circuitry 1830 is configured to map a second physical output (e.g., see physical output 1820b) to a first logical cache (e.g., see logical output 1840a) to implement a command received from a command bus (e.g., see command bus 605a) for accessing a memory system (e.g., see memory system 601) via the second cache set (e.g., cache set 1820b) during a first type of execution (e.g., non-speculative execution).

[0312] In some embodiments, the first logical cache is a normal cache for non-speculative execution by the processor, and the second logical cache is a shadow cache for speculative execution by the processor.

[0313] Mapping circuit 1830 addresses issues related to execution type. Mapping circuit 1830 provides a solution to how execution type relates to mapping physical cache sets to logical cache sets. If mapping circuit 1830 is used, a memory address (e.g., see address 102b) can be applied in each cache set (e.g., see cache sets 1810a, 1810b, and 1810c) to generate a physical output (e.g., see physical outputs 1820a, 1820b, and 1820c). The physical output (e.g., see physical outputs 1820a, 1820b, and 1820c) includes a tag and cache block (e.g., see block index 106b) found using the block index of the memory address. Mapping circuit 1830 can reroute the physical output (e.g., see physical outputs 1820a, 1820b, and 1820c) to one of the logical outputs (e.g., see logical outputs 1840a, 1840b, and 1840c). The cache system can perform tag comparisons at either the physical output or the logical output. If the tag comparison is performed at the physical output, a tag hit or miss at the physical output is routed through the mapping circuit 1830 to produce a hit or miss at the logical output. Otherwise, the tag itself is routed through the mapping circuit 1830; and a tag comparison is performed at the logical output to produce a corresponding tag hit or miss result.

[0314] like Figure 18As described in , the logic outputs are predefined for speculative execution and non-speculative execution. Therefore, the current execution type (e.g., see execution type 110e) can be used to select which part of the logic output will be used. For example, since the logic output 1840c is predefined for Figure 18 So if the current execution type is normal execution, then its result can be discarded. Otherwise, if the current execution type is speculative, then the result from Figure 18 The results of the first portion of the logic outputs (e.g., outputs 1840a and 1840b) may be blocked.

[0315] On display at Figure 18 In an embodiment, if the current execution type is speculative, a hit or miss result from the logic output for non-speculative execution may be ANDed with a '0' to force a cache miss; and a hit or miss result from the logic output for non-speculative execution may be ANDed with a '1' to keep the result unchanged. Execution type 110e may be configured such that speculative execution = 0 and non-speculative execution = 1, and tag hit or miss results from non-speculative outputs 1840a to 1840b may be ANDed with the execution type (e.g., execution type 110e) to produce a hit or miss that considers both the matching tag and the execution type. Furthermore, a tag hit or miss result from 1840c may be ANDed with the inverse of execution type 110e to produce a hit or miss.

[0316] Figure 19 and 20 Demonstrating some embodiments of the present disclosure with a method for utilizing Figure 18 The circuit in (mapping circuit 1830) outputs the physical cache set (e.g., see Figure 18 The physical outputs 1820a, 1820b, and 1820c depicted in FIG. Figure 19 Interchangeable cache sets (e.g., see logical outputs 1840a, 1840b, and 1840c) that map physical outputs 1820a in FIG. 1 to logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c) in FIG. Figures 18 to 21 1810a, 1810b, and 1810c) of a cache system (e.g., shown in FIG. Figure 6 and 10 Instance aspects of an instance computing device of the cache systems 600 and 1000 in FIG.

[0317] Specifically, Figure 19Shown are a first cache set 1810a, a first cache set register 1812a, tags 1815a for the first cache set (which includes a current tag and a cache set index), tags and set index 1850 from address 102b (which includes current tag 104b and current cache set index 112b from memory address 102b), and tag comparison circuitry 1860a for the first cache set 1810a. Additionally, Figure 19 A first cache set 1810a is shown having cache blocks and associated tags (e.g., see cache blocks 1818a and 1818b, and tags 1816a and 1816b), and a first cache set register 1812a that holds a cache set index 1813a for the first cache set. Additionally, Figure 19 The tag comparison circuit 1860b is shown for the second cache set 1810b. The figure shows that the physical output 1820a from the first cache set 1810a is output to the mapping circuit 1830. The second cache set 1810b and other cache sets of the system may also provide their corresponding physical outputs to the mapping circuit 1830 (although this is not shown in FIG. Figure 19 (depicted in).

[0318] Figure 20 The system is shown providing physical outputs to multiple cache sets of the mapping circuit 1830 (e.g., see physical outputs 1820a, 1820b, and 1820c provided by cache sets 1810a, 1810b, and 1810c, respectively, as shown in FIG. Figure 20 ). Figure 20 Portions of the mapping circuit 1830 are also depicted (eg, see multiplexers 2004a, 2004b, and 2004c and PLSM registers 2006a, 2006b, and 2006c). Figure 20 Also shown is a first cache 1810a having at least cache blocks 1818a and 1818b and associated tags 1816a and 1816b. Also shown is a second cache 1810b having at least cache blocks 1818c and 1818d and associated tags 1816c and 1816d.

[0319] Figure 19Also shown are multiplexers 1904a and 1904b and PLSM registers 1906a and 1906b, which may be part of logic circuitry (e.g., see logic circuits 606 and 1006) and / or mapping circuitry (e.g., see mapping circuitry 1830). Each of multiplexers 1904a and 1904b receives at least a hit or miss result 1862a and 1862b from tag comparison circuits 1860a and 1860b, which each compare a corresponding tag of a cache set (e.g., see the tag of first cache set 1815a) with a tag and set index from a memory address (e.g., see tag and set index 1850). In some examples, an equivalent multiplexer may exist for each tag comparison for each cache set in the system. Each of the multiplexers (e.g., see multiplexers 1904a and 1904b) can output a selected hit or miss result based on the state of the multiplexer's corresponding PLSM register (e.g., see PLSM registers 1906a and 1906b). The PLSM register that controls the selection of the multiplexer for outputting a cache hit or miss from the cache set comparison can be controlled by a master PLSM register (e.g., control register 1832) when such a register is part of the mapping circuit 1830.

[0320] In some embodiments, the PLSM registers (e.g., see PLSM registers 1906a and 1906b, and Figure 21 Each of the PLSM registers 2110a, 2110b, and 2110c depicted in FIG2 may be a one-, two-, or three-bit register, or any bit length register, depending on the particular implementation. Such PLSM registers may be used (e.g., by a multiplexer) to select the appropriate physical tag comparison result or the correct result for one of the logical units that outputs a hit or miss.

[0321] exist Figure 20 In the case of PLSM registers 2006a, 2006b, and 2006c depicted in FIG, such registers may be used (e.g., by a multiplexer) to select a cache set (e.g., see FIG. Figure 20 1810a, 1810b, and 1810c) shown in FIG (see, for example, the cache sets 1810a, 1810b, and 1810c shown in FIG). Figure 20 1820a, 1820b, and 1820c in FIG. 1820b). Such PLSM registers may also each be a one-, two-, or three-bit register, or any bit length register, depending on the specific implementation. Additionally, control register 1832 may be a one-, two-, or three-bit register, or any bit length register, depending on the specific implementation.

[0322] In some embodiments, selection of a physical output from a cache set or selection of a cache hit or miss is performed by a multiplexer (e.g., see the Figure 19 Multiplexers 1904a and 1904b in Figure 20 Multiplexers 2004a, 2004b, and 2004c in, and shown in Figure 21 The multiplexers 2110a, 2110b, and 2110c are arranged in the system with at least one multiplexer per output type and per logic unit or per cache set. As shown in the figure, in some embodiments, if there are n cache sets or logic comparison units, there are n n-to-1 multiplexers.

[0323] like Figure 19 As shown in FIG. 1 , the computing device may include a first multiplexer (e.g., multiplexer 1904a) configured to multiplex a first hit or miss result or a second hit or miss result (e.g., see PLSM register 1906a) into a first PLSM register according to the contents received by the first PLSM register (e.g., see PLSM register 1906a). Figure 19 The computing device may also include a second multiplexer (e.g., multiplexer 1904b) configured to output the second hit or miss result or the first hit or miss result (e.g., see PLSM register 1906b) to the processor according to the content received by the second PLSM register (e.g., see PLSM register 1906b). Figure 19 The hit or miss outputs 1862b and 1862a) shown in are output to the processor.

[0324] In some embodiments, the control register (such as shown in Figure 18 The control register 1832 in the PLSM register receives the contents of the PLSM register. For example, in some embodiments, when the contents received by the first PLSM register indicate a first state, the first multiplexer outputs a first hit or miss result, and when the contents received by the first PLSM register indicate a second state, the first multiplexer outputs a second hit or miss result. In addition, when the contents received by the second PLSM register indicate the first state, the second multiplexer may output the second hit or miss result. Furthermore, when the contents received by the second PLSM register indicate the second state, the second multiplexer may output the first hit or miss result.

[0325] like Figure 20, the computing device may include a first multiplexer (e.g., multiplexer 2004a) configured to output a first physical output 1820a of the first cache set or a second physical output 1820b of the second cache set to the processor according to the content received by a first PLSM register (e.g., PLSM register 2006a). The computing device may include a second multiplexer (e.g., multiplexer 2004b) configured to output the first physical output 1820a of the first cache set or the second physical output 1820b of the second cache set to the processor according to the content received by a second PLSM register (e.g., PLSM register 2006b).

[0326] In some embodiments, the control register (such as shown in Figure 18 The control register 1832 in the PLSM register receives the contents of the PLSM register. For example, in some embodiments, when the contents received by the first PLSM register indicate a first state, the first multiplexer outputs a first physical output 1820a, and when the contents received by the first PLSM register indicate a second state, the first multiplexer outputs a second physical output 1820b. Furthermore, when the contents received by the second PLSM register indicate the first state, the second multiplexer may output the second physical output 1820b. Furthermore, when the contents received by the second PLSM register indicate the second state, the second multiplexer may output the first physical output 1820a.

[0327] In some embodiments, block selection may be based on a combination of a block index and a master setting or a shadow setting.Such parameters may control PLSM registers.

[0328] In some embodiments (such as shown in Figure 19 and 20 In the example shown in FIG, only one address (e.g., tag and index) is fed into the interchangeable cache sets (e.g., cache sets 1810a, 1810b, and 1810c). In such an embodiment, if a cache set misses, there is a signal to control which cache set to update based on the memory.

[0329] When the cache set is in the first state, multiplexer 1904a is controlled by PLSM register 1906a to provide a hit or miss output for cache set 1810a, and thus provides a hit or miss status for the cache set for main execution or normal execution. When the cache set is in the first state, multiplexer 1904b is controlled by PLSM register 1906b to provide a hit or miss output for cache set 1810b, and thus provides a hit or miss status for the cache set for speculative execution. On the other hand, when the cache set is in the second state, multiplexer 1904a is controlled by PLSM register 1906a to provide a hit or miss output for cache set 1810b, and thus provides a hit or miss status for the cache set for main execution or normal execution. When the cache set is in the second state, multiplexer 1904b is controlled by PLSM register 1906b to provide a hit or miss output for cache set 1810a, and thus provide a hit or miss status for the cache set for speculative execution.

[0330] Similar to the selection of a hit or miss signal, data retrieved from the interchangeable cache may be selected to produce a result for the processor (e.g., in the event of a hit), as shown in FIG. Figure 20 Physical outputs 1820a, 1820b and 1820c in.

[0331] For example, in a first state of the cache set, when cache set 1810a is used as a primary cache set and cache set 1810b is used as a shadow cache set, multiplexer 2004a is controlled by PLSM register 2006a to select physical output 1820a of cache set 1810a for non-speculative execution of the primary cache or the normal logical cache. Furthermore, for example, in a second state of the cache set, when cache set 1810b is used as a primary cache set and cache set 1810a is used as a shadow cache set, multiplexer 2004a is controlled by PLSM register 2006a to select physical output 1820b of cache set 1810b for non-speculative execution of the primary cache or the normal logical cache. In this example, in a first state of the cache sets, when cache set 1810a is used as the primary cache set and cache set 1810b is used as the shadow cache set, multiplexer 2004b is controlled by PLSM register 2006b to select physical output 1820b of cache set 1810b as the shadow logical cache for speculative execution. Furthermore, for example, in a second state of the cache sets, when cache set 1810a is used as the primary cache set and cache set 1810b is used as the shadow cache set, multiplexer 2004b is controlled by PLSM register 2006b to select physical output 1820a of cache set 1810a as the shadow logical cache for speculative execution.

[0332] In some embodiments, the cache system may further include a plurality of cache sets (e.g., see Figures 18 to 21 1810a, 1810b, and 1810c) are associated with a plurality of registers (e.g., see Figure 19 1812a shown in FIG. 1810b). The registers may include a first register (e.g., see register 1812a) associated with a first cache set (e.g., see cache set 1810a), and a second register (not shown in FIG. 1810b) associated with a second cache set (e.g., see cache set 1810b). Figures 18 to 21 Depicted in but Figure 6 and 10). The cache system may also include logic circuitry (e.g., see logic circuitry 606 and 1006) coupled to a processor (e.g., see logic circuitry 601 and 1001) to control a plurality of cache sets based on a plurality of registers. When a memory address is received from the processor via a connection (e.g., see connection 604b) to an address bus (e.g., see address bus 605b), the logic circuitry may be configured to generate a set index from at least the memory address and determine whether the generated set index matches the contents stored in the first register or the contents stored in the second register. Furthermore, the logic circuitry may be configured to implement a command received via a connection (e.g., see connection 604a) to a command bus (e.g., see command bus 605a) via a first cache set in response to the generated set index matching the contents stored in the first register, and to implement the command via a second cache set in response to the generated set index matching the contents stored in the second register.

[0333] In some embodiments, the mapping circuit (e.g., see mapping circuit 1830) may be part of or connected to the logic circuit, and the state of a control register (e.g., see control register 1832) may control the state of a cache set in the plurality of cache sets. In some embodiments, the state of the control register may control the state of a cache set in the plurality of cache sets by changing the valid bit of each block in the cache set (e.g., see Figures 21 to 23 ).

[0334] In addition, in some examples, the cache system may further include a connection (e.g., see connection 1002) to a speculation state signal line (e.g., see speculation state signal line 1004) from the processor that identifies the state of speculative execution of instructions by the processor. The connection to the speculation state signal line may be configured to receive the state of speculative execution, and the state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry (e.g., see logic circuits 606 and 1006) may be configured to change the state of the first and second cache sets via a control register (e.g., see control register 1832) if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to maintain the state of the first and second cache sets unchanged via the control register if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0335] In some embodiments, a mapping circuit (e.g., see mapping circuit 1830) is part of or connected to a logic circuit (e.g., see logic circuits 606 and 1006), and the state of a control register (e.g., see control register 1832) can control a cache register (e.g., see control register 1832) in a plurality of cache registers via the mapping circuit. Figure 19 1812a). In this example, the cache system may further include a connection (e.g., see connection 1002) to a speculation state signal line (e.g., see speculation state signal line 1004) from the processor that identifies the state of speculative execution of instructions by the processor. The connection to the speculation state signal line can be configured to receive the state of speculative execution, and the state of speculative execution indicates whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuit can be configured to change the state of the first and second registers via the control register if the state of speculative execution indicates that the result of speculative execution will be accepted. And, when the execution type changes from speculative execution to non-speculative execution, the logic circuit can be configured to maintain the state of the first and second registers unchanged via the control register if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0336] Figure 21 A method for displaying a cache memory having an interchangeable cache set (such as that shown in FIG. 1 ) according to some embodiments of the present disclosure is shown. Figure 18 Cache sets in FIG, including cache sets 1810a, 1810b, and 1810c) are shown as example aspects of an example computing device of a cache system. Cache sets (e.g., cache sets 1810a, 1810b, and 1810c) are shown as utilizing the example shown in FIG. Figure 18 Circuitry in (mapping circuitry 1830) maps physical cache set outputs to logical cache set outputs.

[0337] Figure 21 The portion depicted in FIG is a portion of a computing device including a memory (e.g., main memory), a processor (e.g., see processor 1001), and at least three interchangeable cache sets (e.g., see interchangeable cache sets 1810a, 1810b, and 1810c). The processor is configured to execute a main thread and a speculative thread.

[0338] like Figure 21 As shown in FIG, a first cache set (e.g., cache set 1810a) can be coupled between a memory and a processor and can include a first plurality of blocks for a main thread in a first state of the cache set (e.g., see FIG. Figure 212101a, 2101b, and 2101c in the cache set). Each block in the first plurality of blocks may include cached data, a first valid bit, and a block address including an index and a tag. Furthermore, the processor (alone or in conjunction with the cache controller) may be configured to change each first valid bit from indicating valid to indicating invalid when speculation by the speculative thread succeeds, such that in the first state of the cache set, the first plurality of blocks become accessible to the speculative thread and blocked to the main thread.

[0339] like Figure 21 As shown in FIG, a second cache set (e.g., cache set 1810b) may be coupled between main memory and the processor and may include a second plurality of blocks for the speculative thread in the first state of the cache set (e.g., see FIG. Figure 21 101d, 2101e, and 2101f in the cache set). Each block in the second plurality of blocks may include cached data, a second valid bit, and a block address including an index and a tag. Furthermore, the processor (alone or in conjunction with the cache controller) may be configured to change each second valid bit from indicating invalid to indicating valid when speculation by the speculative thread succeeds, such that in the second state of the cache set, the second plurality of blocks become accessible to the main thread and blocked to the speculative thread.

[0340] In some embodiments, as Figure 21 As shown in , a block in the first plurality of blocks may correspond to a corresponding block in the second plurality of blocks. Also, a block in the first plurality of blocks may correspond to a corresponding block in the second plurality of blocks by having the same block address as the corresponding block in the second plurality of blocks.

[0341] In addition, if Figure 21 As shown in FIG, the computing device may include a first physical-to-logical-map-set-map (PLSM) register (e.g., PLSM register 1 2108a) configured to receive a first valid bit of a block in a first plurality of blocks. The first valid bit may indicate the validity of cached data of the block in the first plurality of blocks. It may also indicate whether the block in the first plurality of blocks or a corresponding block in the second plurality of blocks is to be used in a main thread.

[0342] In addition, if Figure 21 As shown in FIG, the computing device may include a second PLSM register (e.g., PLSM register 2 2108b) configured to receive a second valid bit for a block in the second plurality of blocks. The second valid bit indicates the validity of cached data for the block in the second plurality of blocks. It may also indicate whether the block in the second plurality of blocks or the corresponding block in the first plurality of blocks is to be used in the main thread.

[0343] In addition, if Figure 21As shown in FIG, the computing device may include a logic unit 2104a for a first cache set, the logic unit 2104a configured to determine whether a block in the first plurality of blocks is a hit or a miss. The logic unit 2104a is shown to include a comparator 2106a and an AND gate 2107a. The comparator 2106a may determine whether there is a match between the tag of the block and the corresponding tag of the address in the memory. And, if the tags match and the valid bit of the block is valid, the AND gate 2107a outputs an indication that the block is a hit. Otherwise, the AND gate 2107a outputs an indication that the block is a miss. In other words, the logic unit 2104a for the first cache is configured to output a first hit or miss result based on the determination made by the logic unit.

[0344] In addition, if Figure 21 As shown in FIG, the computing device may include a logic unit 2104b for a second cache set, the logic unit 2104b configured to determine whether a block in the second plurality of blocks is a hit or a miss. Logic unit 2104b is shown to include a comparator 2106b and an AND gate 2107b. Comparator 2106b may determine whether there is a match between the tag of the block and the corresponding tag of the address in the memory. Furthermore, if the tags match and the valid bit of the block is valid, AND gate 2107b outputs an indication that the block is a hit. Otherwise, AND gate 2107b outputs an indication that the block is a miss. In other words, logic unit 2104b for the second cache is configured to output a second hit or miss result based on the determination made by the logic unit.

[0345] In addition, if Figure 21 As shown in , the computing device may include a first multiplexer (e.g., multiplexer 2110a) configured to output a first hit or miss result or a second hit or miss result to a processor based on a first valid bit received by a first PLSM register. The computing device may also include a second multiplexer (e.g., multiplexer 2110b) configured to output a second hit or miss result or the first hit or miss result to the processor based on a second valid bit received by a second PLSM register. In some embodiments, when the first valid bit received by the first PLSM register indicates valid, the first multiplexer outputs the first hit or miss result, and when the first valid bit received by the first PLSM register indicates invalid, the first multiplexer outputs the second hit or miss result. Furthermore, when the second valid bit received by the second PLSM register indicates valid, the second multiplexer outputs the second hit or miss result. And, when the second valid bit received by the second PLSM register indicates invalid, the second multiplexer outputs the first hit or miss result.

[0346] In some embodiments, block selection may be based on a combination of a block index and a main setting or a shadow setting.

[0347] In some embodiments, only one address (e.g., tag and index) is fed into the interchangeable cache sets (e.g., cache sets 1810a, 1810b, and 1810c). In such embodiments, if a cache set generates a miss, there is a signal that controls which cache set to update based on the memory. Similar to the selection of the hit or miss signal, data retrieved from the interchangeable cache can be selected to generate a result for the processor (e.g., in the event of a hit). For example, in the first state of the cache sets, if cache set 1810a is used as the primary cache set and cache set 1810b is used as the shadow cache set, multiplexer 2110a is controlled by PLSM register 2108a to select the hit or miss output of cache set 1804a and the hit or miss state of the primary cache set. Also, multiplexer 2110b is controlled by PLSM register 2108b to provide a hit or miss output for cache set 1810b, and therefore a hit or miss status for the shadow cache set.

[0348] In this embodiment, when the cache set is in the second state, when cache set 1810a is used as a shadow cache and cache set 1810b is used as a primary cache, multiplexer 2110a can be controlled by PLSM register 2108b to select a hit or miss output of cache set 1810b and a hit or miss status of the primary cache. Furthermore, multiplexer 2110b can be controlled by PLSM register 2108b to provide a hit or miss output of cache set 1810a, and thus provide a hit or miss status of the shadow cache.

[0349] Thus, multiplexer 2110a can output whether the primary cache has a cache hit or miss for the address; and multiplexer 2110b can output whether the shadow cache has a cache hit or miss for the same address. Depending on whether the address is speculative, one of the outputs can then be selected. When there is a cache miss, the address is used in memory to load data into the corresponding cache. PLSM registers can similarly implement updates to the corresponding cache set 1810a or set 1810b.

[0350] In some embodiments, during speculative execution of a first instruction by a speculative thread in a first state of the cache set, effects of the speculative execution are stored in a second cache set (e.g., cache set 1810b). During speculative execution of the first instruction, the processor may be configured to assert a signal indicating speculative execution configured to block changes to the first cache set (e.g., cache set 1810a). When the signal is asserted by the processor, the processor may be further configured to block the second cache set (e.g., cache set 1810b) from updating memory.

[0351] When the state of the cache set changes to the second state, in response to determining that execution of the first instruction will be performed by the main thread, the second cache set (instead of the first cache set) is used with the first instruction. In response to determining that execution of the first instruction will not be performed by the main thread, the first cache set is used with the first instruction.

[0352] In some embodiments, in a first state, during speculative execution of a first instruction, the processor accesses memory via a second cache set (e.g., cache set 1810b). Furthermore, during speculative execution of one or more instructions, access to the contents of the second cache is limited to the speculative execution of the first instruction by the processor. During speculative execution of the first instruction, the processor may be prohibited from making changes to the first cache set (e.g., cache set 1810a).

[0353] In some embodiments, the contents of the first cache set (eg, cache set 1810a) and / or the second cache set (eg, cache set 1810b) may be accessible via a cache coherence protocol.

[0354] Figure 22 and 23 Methods 2200 and 2300 are shown, respectively, for using interchangeable cache sets for speculative and non-speculative execution by a processor according to some embodiments of the present disclosure. In particular, methods 2200 and 2300 may be used by Figure 21 In addition, the calculation device described in Figures 18 to 20 The computing device described in and any of the computing devices disclosed herein perform a somewhat similar method; however, such computing device will control the cache state, cache set state, or cache set register state via another parameter other than the valid bit of the block address. For example, in Figure 16 In , the state of a cache set is controlled via a cache set indicator within the tag of a block of the cache set. And, for example, in Figure 17In this example, the state of the cache set is controlled via the state of the cache set register associated with the cache set. In this example, the state is controlled via the cache set index stored in the cache set register. On the other hand, for the cache set registers associated with the cache set, the state of the cache set is controlled via the state of the cache set register associated with the cache set. Figures 21 to 23 The disclosed embodiments control the state of a cache set via the valid bits of a block address within the cache set.

[0355] The method 2200 includes, at block 2202, executing a main thread and a speculative thread by a processor (e.g., processor 1001). The method 2200 includes, at block 2204, executing a first cache set (e.g., cache set 1001) of a cache system coupled between a memory system and a processor. Figure 21 A first plurality of blocks (eg, Figure 21 101c). Each block in the first plurality of blocks may include cached data, a first valid bit, and a block address with an index and a tag. Method 2200, at block 2206, includes providing a second plurality of blocks (e.g., blocks 2101d, 2101e, and 2101f) for the speculative thread in a second cache set (e.g., cache set 1810b) of a cache system coupled between the memory system and the processor. Each block in the second plurality of blocks may include cached data, a second valid bit, and a block address with an index and a tag.

[0356] At block 2207, the method 2200 continues by identifying, for example, by a processor, whether speculation by the speculative thread successfully causes the first plurality of blocks to become accessible to the speculative thread and blocked to the main thread, and causes the second plurality of blocks to become accessible to the main thread and blocked to the speculative thread. Figure 22 , if the speculation by the speculative thread fails, the processor does not change the validity bits of the first and second pluralities of blocks and retains the same validity values ​​as before determining whether the speculative thread succeeded at block 2207. Thus, the state of the cache set is not changed from the first state to the second state.

[0357] At block 2208, the method 200 continues by changing each first valid bit from indicating valid to indicating invalid by the processor (alone or in conjunction with the cache controller) when the speculation by the speculative thread succeeds, such that the first plurality of blocks becomes accessible to the speculative thread and blocked for the main thread. Furthermore, at block 2210, the method 200 continues by changing each second valid bit from indicating invalid to indicating valid by the processor (alone or in conjunction with the cache controller) when the speculation by the speculative thread succeeds, such that the second plurality of blocks becomes accessible to the main thread and blocked for the speculative thread. Thus, the state of the cache set does not change from the first state to the second state.

[0358] In some embodiments, during speculative execution of a first instruction by a speculative thread, effects of the speculative execution are stored in a second cache set. In such embodiments, during speculative execution of the first instruction, a processor may assert a signal indicating that speculative execution of changes to the first cache may be blocked. Furthermore, when the signal is asserted by the processor, the processor may block the second cache from updating memory. This occurs while the cache set is in a first state.

[0359] Furthermore, in this embodiment, in response to determining that execution of the first instruction will be performed by the main thread, the second cache set (rather than the first cache set) is used with the first instruction. In response to determining that execution of the first instruction will not be performed by the main thread, the first cache set is used with the first instruction. This occurs when the cache set is in the second state.

[0360] In some embodiments, during speculative execution of a first instruction, the processor accesses memory via a second cache. Furthermore, during speculative execution of one or more instructions, access to contents of the second cache is limited to speculative execution of the first instruction by the processor. In such embodiments, during speculative execution of the first instruction, the processor is prohibited from altering the first cache.

[0361] In some embodiments, the contents of the first cache may be accessed via a cache coherence protocol.

[0362] exist Figure 23 , method 2300 includes operations at boxes 2202, 2204, 2206, 2207, 2208 and 2210 of method 2200.

[0363] Method 2300, at block 2302, includes generating a physical-to-logical-map-set-map (PLSM) register (e.g., as shown in FIG. Figure 21The method 2300 may further include receiving, at block 2304, a first valid bit for a block in the first plurality of blocks by a second PLSM register (e.g., PLSM register 2108a). The first valid bit may indicate the validity of cached data for the block in the first plurality of blocks. Additionally, the method 2300 may include receiving, at block 2304, a second valid bit for a block in the second plurality of blocks by a second PLSM register (e.g., PLSM register 2108b). The second valid bit may indicate the validity of cached data for the block in the second plurality of blocks.

[0364] At block 2306, method 2300 includes, by a first logical unit for a first cache set (e.g., Figure 21 23. The method 2300 further comprises determining, by a second logic unit (e.g., logic unit 2104b) for a second cache set, whether a block in the second plurality of blocks is a hit or a miss. At block 2307, the method 2300 continues with the first logic unit outputting a first hit or miss result based on the determination. Furthermore, at block 2308, the method 2300 includes determining, by a second logic unit (e.g., logic unit 2104b) for a second cache set, whether a block in the second plurality of blocks is a hit or a miss. At block 2309, the method 2300 continues with the second logic unit outputting a second hit or miss result based on the determination.

[0365] At block 2310, the method 2300 begins with a first multiplexer (e.g., Figure 21 The multiplexer 2110a depicted in FIG2 outputs a first hit or miss result or a second hit or miss result to the processor according to a first valid bit received by the first PLSM register. In some embodiments, when the first valid bit received by the first PLSM register indicates valid, the first multiplexer outputs the first hit or miss result, and when the first valid bit received by the first PLSM register indicates invalid, the first multiplexer outputs the second hit or miss result.

[0366] Then, at block 2312, a second multiplexer (e.g., multiplexer 2110b) outputs the second hit or miss result or the first hit or miss result to the processor based on the second valid bit received by the second PLSM register. In some embodiments, when the second valid bit received by the second PLSM register indicates valid, the second multiplexer outputs the second hit or miss result. And, when the second valid bit received by the second PLSM register indicates invalid, the second multiplexer outputs the first hit or miss result.

[0367] Some embodiments may include a central processing unit having processing circuitry configured to execute a main thread and a speculative thread. The central processing unit may also include or be connected to a first cache set configured as a cache system coupled between main memory and the processing circuitry, the first cache set having a first plurality of blocks for the main thread. Each block in the first plurality of blocks may include cached data, a first valid bit, and a block address including an index and a tag. The processing circuitry (alone or in conjunction with a cache controller) may be configured to change each first valid bit from indicating valid to indicating invalid when speculation by the speculative thread succeeds, such that the first plurality of blocks becomes accessible to the speculative thread and blocked to the main thread. The central processing unit may also include or be connected to a second cache set configured as a cache system coupled between main memory and the processing circuitry, the second cache set including a second plurality of blocks for the speculative thread. Each block in the second plurality of blocks may include cached data, a second valid bit, and a block address including an index and a tag. The processing circuitry (alone or in conjunction with the cache controller) may be configured to, when speculation by the speculative thread succeeds, change each second valid bit from indicating invalid to indicating valid, such that the second plurality of blocks become accessible to the main thread and blocked to the speculative thread, and wherein the blocks in the first plurality of blocks correspond to respective blocks in the second plurality of blocks by having the same block address as the respective blocks in the second plurality of blocks.

[0368] The techniques disclosed herein are applicable to at least computer systems in which a processor is separate from memory and the processor communicates with the memory and storage via a communication bus and / or a computer network. Furthermore, the techniques disclosed herein are applicable to computer systems in which processing capabilities are integrated into the memory / storage. For example, processing circuitry including the execution units and / or registers of a typical processor may be implemented within an integrated circuit and / or integrated circuit package of a memory medium to perform processing within the memory device. Thus, the processors discussed above and illustrated in the figures (e.g., see processors 201, 401, 601, and 1001) are not necessarily central processing units in a von Neumann architecture. The processor may be a unit integrated into the memory to overcome the von Neumann bottleneck, which limits computing performance due to throughput limitations caused by latency when data moves between a central processing unit configured separately according to the von Neumann architecture and the memory.

[0369] The description and drawings of this disclosure are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in some cases, well-known or conventional details are not described to avoid obscuring the description. References to one embodiment or an embodiment in this disclosure are not necessarily references to the same embodiment; furthermore, such references mean at least one embodiment.

[0370] In the foregoing specification, the present disclosure has been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A cache system comprising: Multiple cache collections, including: a first cache set; and a second cache set; a plurality of registers, each of which is associated with the plurality of cache sets, wherein the plurality of registers comprises: a first register associated with the first cache set; and a second register associated with the second cache set; a connection to a command bus coupled between the cache system and a processor; a connection to an address bus coupled between the cache system and the processor; and a logic circuit coupled to the processor to control the plurality of cache sets based on the plurality of registers; wherein when the connection to the address bus receives a memory address from the processor, the logic circuit is configured to: generating an extended tag from at least the memory address; and determining whether the generated extended tag matches a first extended tag of the first cache set or a second extended tag of the second cache set; and wherein the logic circuitry is configured to implement a command received in the connection to the command bus via the first cache set in response to the generated extended tag matching the first extended tag, and to implement the command via the second cache set in response to the generated extended tag matching the second extended tag.

2. The cache system of claim 1 , wherein the logic circuit is configured to: generating the first extended tag from a cache address of the first cache set and content stored in the first register; and The second extended tag is generated from the cache address of the second cache set and the content stored in the second register.

3. The cache system according to claim 2, further comprising: a connection to an execution type signal line from a processor, the execution type signal line identifying the execution type; wherein the logic circuit is configured to generate the extended tag from the memory address and the execution type identified by the execution type signal line; and The content stored in each of the first register and the second register includes an execution type. The cache system according to claim 3 , wherein: To determine whether the generated extended tag matches the first extended tag of the first cache set or the second extended tag of the second cache set, the logic circuit is configured to: comparing the first extended tag to the generated extended tag to determine a cache hit or miss for the first cache set; and The second extended tag is compared to the generated extended tag to determine a cache hit or miss for the second cache set.

5. The cache system of claim 4 , wherein the logic circuit is configured to: receiving an output from the first cache set when the logic circuit determines that the generated extended tag matches the first extended tag of the first cache set; and When the logic circuit determines that the generated extended tag matches the second extended tag of the second cache set, an output is received from the second cache set.

6. The cache system according to claim 5, wherein the cache address of the first cache set comprises a first tag of a cache block in the first cache set; and The cache address of the second cache set includes a second tag of a cache block in the second cache set.

7. The cache system of claim 6, wherein the logic circuit is configured to: obtaining a first cache block in the first cache set and a tag associated with the first cache block using a first block index from the memory address; and A second cache block in the second cache set and a tag associated with the second cache block are obtained using a second block index from the memory address.

8. A cache system according to claim 3, wherein when the first cache set and the second cache set are in a first state, the cache address of the first cache set includes a first cache set indicator associated with the first cache set, and the cache address of the second cache set includes a second cache set indicator associated with the second cache set.

9. The cache system of claim 8, wherein when the first cache set and the second cache set are in a second state, the cache address of the first cache set includes the second cache set indicator, and the cache address of the second cache set includes the first cache set indicator.

10. The cache system according to claim 9, further comprising: a connection to a speculation status signal line from the processor, the speculation status signal line identifying a state of speculative execution of instructions by the processor, wherein the connection to the speculation status signal line is configured to receive the state of speculative execution, and wherein the state of speculative execution indicates whether a result of speculative execution is to be accepted or rejected; and Wherein, when the execution type changes from the speculative execution to the non-speculative execution, the logic circuit is configured to: If the state of speculative execution indicates that a result of speculative execution will be accepted, changing the state of the first cache set and the second cache set; as well as If the state of speculative execution indicates that a result of speculative execution is to be rejected, then the state of the first cache set and the second cache set is maintained unchanged.

11. The cache system of claim 3 , wherein when the first register and the second register are in a first state, the content stored in the first register includes a first cache set index associated with the first cache set, and the content stored in the second register includes a second cache set index associated with the second cache set.

12. The cache system of claim 11 , wherein when the first register and the second register are in a second state, the content stored in the first register includes the second cache set index associated with the second cache set, and the content stored in the second register includes the first cache set index associated with the first cache set.

13. The cache system of claim 12, further comprising: a connection to a speculation status signal line from the processor, the speculation status signal line identifying a state of speculative execution of instructions by the processor, wherein the connection to the speculation status signal line is configured to receive the state of speculative execution, and wherein the state of speculative execution indicates whether a result of speculative execution is to be accepted or rejected; and Wherein, when the execution type changes from the speculative execution to the non-speculative execution, the logic circuit is configured to: If the state of speculative execution indicates that a result of speculative execution is to be accepted, changing the state of the first register and the second register; and If the state of speculative execution indicates that a result of speculative execution is to be rejected, then the state of the first register and the second register is maintained unchanged.

14. A cache system comprising: Multiple cache collections, including: a first cache set; and a second cache set; a plurality of registers, each of which is associated with the plurality of cache sets, wherein the plurality of registers comprises: a first register associated with the first cache set; and a second register associated with the second cache set; a connection to a command bus coupled between the cache system and a processor; a connection to an address bus coupled between the cache system and the processor; and logic circuitry coupled to the processor to control the plurality of cache sets based on the plurality of registers; and Wherein the logic circuit is configured as follows: generating a first extended tag from a cache address of the first cache set and the contents stored in the first register; generating a second extended tag from a cache address of the second cache set and the contents stored in the second register; determining whether the first extended tag of the first cache set or the second extended tag of the second cache set matches a generated extended tag generated from a memory address received from the processor; and A command received in the connection to the command bus is implemented via the first cache set in response to the generated extended tag matching the first extended tag, and the command is implemented via the second cache set in response to the generated extended tag matching the second extended tag.

15. The cache system of claim 14, further comprising: a connection to an address bus coupled between the cache system and the processor; as well as Wherein when the connection to the address bus receives the memory address from the processor, the logic circuit is configured to generate the extended tag from at least the memory address.

16. The cache system of claim 15, further comprising: a connection to an execution type signal line from a processor, the execution type signal line identifying the execution type; wherein the logic circuit is configured to generate the extended tag from the memory address and the execution type identified by the execution type signal line; and The content stored in each of the first register and the second register includes an execution type.

17. The cache system according to claim 16, wherein: To determine whether the first extended tag of the first cache set or the second extended tag of the second cache set matches a generated extended tag generated from a memory address received from the processor, the logic circuit is configured to: comparing the first extended tag to the generated extended tag to determine a cache hit or miss for the first cache set; and The second extended tag is compared to the generated extended tag to determine a cache hit or miss for the second cache set.

18. The cache system of claim 17, wherein the logic circuit is configured to: receiving an output from the first cache set when the logic circuit determines that the generated extended tag matches the first extended tag of the first cache set; and When the logic circuit determines that the generated extended tag matches the second extended tag of the second cache set, an output is received from the second cache set.

19. The cache system according to claim 18, wherein the cache address of the first cache set comprises a first tag of a cache block in the first cache set, The cache address of the second cache set includes a second tag of a cache block in the second cache set.

20. A cache system comprising: Multiple cache collections, including: a first cache set; and a second cache set; a plurality of registers, each of which is associated with the plurality of cache sets, wherein the plurality of registers comprises: a first register associated with the first cache set; and a second register associated with the second cache set; a connection to a command bus coupled between the cache system and a processor; a connection to an execution type signal line from a processor, the execution type signal line identifying the execution type; a connection to an address bus coupled between the cache system and the processor; and a logic circuit coupled to the processor to control the plurality of cache sets based on the plurality of registers; wherein when the connection to the address bus receives a memory address from the processor, the logic circuit is configured to: generating an extended tag from the memory address and the execution type identified by the execution type signal line; and determining whether the generated extended tag matches a first extended tag of the first cache set or a second extended tag of the second cache set; and wherein the logic circuitry is configured to implement a command received in the connection to the command bus via the first cache set in response to the generated extended tag matching the first extended tag, and to implement the command via the second cache set in response to the generated extended tag matching the second extended tag.

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