Failure graph acquisition method and acquisition device

Abstract

A method and device for acquiring a failure pattern, wherein the method for acquiring a failure pattern includes: obtaining a chip test result image in a wafer, wherein the chip test result image is marked with a number of failure test points; calculating the vectors between every two points of all failure test points; defining a number of failure test points with the same vector as the same group; separating a number of pending failure patterns from each group; and obtaining a failure pattern based on the number of pending failure patterns. The above steps can accurately and quickly obtain a failure pattern, and the failure pattern is used to determine whether there is a problem with a test machine. If a failure pattern is obtained, it can be determined that there is a problem with the test environment of the test machine, so that the tester can adjust the test environment of the test machine (such as modifying the test program), thereby preventing the occurrence of false detection by the test machine and improving the accuracy of electrical testing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing, and in particular to a method and device for acquiring a failure pattern. Background Art

[0002] The manufacturing process of integrated circuits can usually be divided into wafer processing, wafer testing, packaging and final testing. Before chip packaging, it is usually necessary to conduct an electrical performance test (CP, Circuit Probe) on the integrated circuit on the wafer to determine whether the integrated circuit is good. After completing the packaging process, the integrated circuit must undergo another electrical test (FT, Final Test) to screen out defective products caused by poor packaging technology, and further improve the yield of the final product. In the prior art, a wafer test card with several probes is usually used, and the probes of the wafer test card are brought into contact with the integrated circuit of the wafer, and a test signal is applied to the integrated circuit to determine whether its electrical performance is good.

[0003] A wafer usually refers to the silicon wafer used to make integrated circuits. After all the integrated circuits on the wafer are manufactured, the wafer will contain several dies. Each dies corresponds to a chip. Each chip contains a large number of memory addresses. When performing the electrical performance test (CP, Circuit Probe) of the wafer, the electrical performance of the memory addresses in each chip on the wafer will be tested. Memory addresses that do not meet the electrical performance requirements of the electrical performance test will be marked as invalid memory addresses.

[0004] The accuracy of existing methods for testing the electrical properties of wafers still needs to be improved. Summary of the invention

[0005] The technical problem to be solved by the present invention is to improve the accuracy of a method for testing the electrical properties of a wafer.

[0006] The present invention provides a method for obtaining a failure graph, comprising:

[0007] Obtaining a chip test result image in a wafer, wherein a plurality of failed test points are marked in the chip test result image;

[0008] Calculate the vector between every two points of all failed test points;

[0009] Define several failure test points with the same vector as the same group;

[0010] From each group, several pending failure patterns are separated;

[0011] A failure pattern is obtained based on the several pending failure patterns.

[0012] Optionally, the wafer has a plurality of chips, each of the chips has a plurality of memory addresses, and one chip corresponds to a chip test result image.

[0013] Optionally, the process of obtaining the chip test result image is: performing an electrical performance test on each memory address in the chip to obtain a number of electrical test results; arranging the several electrical test results according to the memory addresses to obtain a row and column arrangement image, wherein the row and column arrangement graphic is the chip test result image, and one of the failure test points in the chip test result image corresponds to a memory address.

[0014] Optionally, the process of obtaining the chip test result image is: performing an electrical performance test on each memory address in the chip to obtain a number of electrical test results; arranging the several electrical test results according to the memory addresses to obtain a row and column arrangement image; compressing the row and column arrangement pattern to obtain a compressed pattern, wherein the compressed image is a chip test result image, and one of the failure test points in the chip test result image corresponds to multiple memory addresses.

[0015] Optionally, the compression process is: compressing multiple adjacent electrical test results in the row and column arrangement image into one point, if one of the multiple electrical test results is failed, then the point formed after compression is a failed test point.

[0016] Optionally, the vector is a two-dimensional coordinate vector or a polar coordinate vector.

[0017] Optionally, a distributed computing server equipped with a graphics processor is used to perform vector calculations.

[0018] Optionally, a clustering algorithm is used to separate several pending failure graphs from each group.

[0019] Optionally, the process of obtaining a failure pattern based on the several pending failure patterns includes: calculating the number of occurrences corresponding to the several pending failure patterns; sorting them from large to small according to the number of occurrences, and taking one or more pending failure patterns with a corresponding number of occurrences ≥ 2 times in the chip test result image as failure patterns, or taking one or more pending failure patterns with the number of occurrences ranked in the top 40% as failure patterns.

[0020] Optionally, the method further includes: after obtaining the failure pattern, checking the test environment of the corresponding test machine, wherein the test environment includes a test program.

[0021] The present invention also provides a device for acquiring a failure pattern, comprising:

[0022] A chip test result image obtaining unit is used to obtain a chip test result image in a wafer, wherein a plurality of failure test points are marked in the chip test result image;

[0023] A vector calculation unit is used to calculate the vector between every two points of all failure test points;

[0024] A group confirmation unit, used for defining a number of failure test points with the same vector as the same group;

[0025] A pending failure pattern confirmation unit is used to separate a number of pending failure patterns from each group;

[0026] The failure pattern obtaining unit is used to obtain a failure pattern based on the several types of pending failure patterns.

[0027] Optionally, the wafer has a plurality of chips, each of the chips has a plurality of memory addresses, and one chip corresponds to a chip test result image.

[0028] Optionally, the process of obtaining the test result image by the chip test result image acquisition unit is: performing an electrical performance test on each memory address in the chip to obtain a number of electrical test results; arranging the several electrical test results according to the memory addresses to obtain a row and column arrangement image, wherein the row and column arrangement graphic is the chip test result image, and one of the failure test points in the chip test result image corresponds to a memory address.

[0029] Optionally, the process of the chip test result image acquisition unit obtaining the test result image is: performing an electrical performance test on each memory address in the chip to obtain a number of electrical test results; arranging the several electrical test results according to the memory addresses to obtain a row and column arrangement image; compressing the row and column arrangement pattern to obtain a compressed pattern, wherein the compressed image is a chip test result image, and one of the failure test points in the chip test result image corresponds to multiple memory addresses.

[0030] Optionally, the compression process is: compressing multiple adjacent electrical test results in the row and column arrangement image into one point, if one of the multiple electrical test results is failed, then the point formed after compression is a failed test point.

[0031] Optionally, the vector is a two-dimensional coordinate vector or a polar coordinate vector.

[0032] Optionally, the vector computing unit is a distributed computing server equipped with a graphics processor.

[0033] Optionally, the group confirmation unit separates several pending failure graphs from each group through a clustering algorithm.

[0034] Optionally, the process of obtaining the failure pattern by the failure pattern obtaining unit includes: calculating the number of occurrences corresponding to the several pending failure patterns; sorting them from large to small according to the number of occurrences, and taking one or more pending failure patterns with a corresponding number of occurrences ≥ 2 times in the chip test result image as failure patterns, or taking one or more pending failure patterns with the number of occurrences ranked in the top 40% as failure patterns.

[0035] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0036] The method for obtaining a failure pattern of the present invention includes: obtaining a chip test result image in a wafer, wherein a plurality of failure test points are marked in the chip test result image; calculating the vectors of every two points between all failure test points; defining a plurality of failure test points with the same vector as the same group; separating a plurality of pending failure patterns from each group; and obtaining a failure pattern based on the plurality of pending failure patterns. The above steps can accurately and quickly obtain a failure pattern, and the failure pattern is used to determine whether there is a problem with the test machine. If a failure pattern is obtained, it can be determined that there is a problem with the test environment of the test machine, so that the tester can adjust the test environment of the test machine (such as modifying the test program), thereby preventing the occurrence of false detection by the test machine and improving the accuracy of electrical testing.

[0037] Furthermore, the process of obtaining the chip test result image is as follows: performing an electrical performance test on each memory address in the chip to obtain a number of electrical test results; arranging the several electrical test results according to the memory addresses to obtain a row and column arrangement image; compressing the row and column arrangement pattern to obtain a compressed pattern, wherein the compressed image is the chip test result image, and one of the failure test points in the chip test result image corresponds to multiple memory addresses, which greatly reduces the amount of calculation for subsequent vector calculations and improves efficiency.

[0038] Furthermore, a distributed computing server with a graphics processor is used to perform vector calculations to further improve the speed and efficiency of vector calculations.

[0039] Further, the process of obtaining the failure pattern based on the several pending failure patterns includes: calculating the number of occurrences corresponding to the several pending failure patterns; sorting them from large to small according to the number of occurrences, and taking one or more pending failure patterns with a corresponding number of occurrences ≥ 2 times in the chip test result image as failure patterns, or taking one or more pending failure patterns with the number of occurrences ranked in the top 40% as failure patterns, so as to improve the efficiency and accuracy of failure pattern determination. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1-Figure 5It is a structural schematic diagram of a process of acquiring a failure graph according to an embodiment of the present invention;

[0041] Figure 6 It is a structural schematic diagram of a device for acquiring a failure pattern according to an embodiment of the present invention;

[0042] Figure 7 It is a structural schematic diagram of a system for monitoring a test machine according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] As mentioned in the background art, the test accuracy of the existing method for testing the electrical properties of wafers still needs to be improved.

[0044] The study found that further inspection of the electrical test results of existing wafers revealed that not every marked failed chip is failed, and the electrical performance of some failed chips still meets the performance requirements, that is, these failed chips were mismeasured.

[0045] Further research found that these falsely detected failed chips were arranged in a certain regular pattern on the wafer. Further research found that these falsely detected failed chips were caused by test environment problems (such as test procedures) of the test machine.

[0046] To this end, the present invention provides a method and device for acquiring a failure pattern, wherein the method for acquiring a failure pattern includes: obtaining a chip test result image in a wafer, wherein a plurality of failure test points are marked in the chip test result image; calculating the vectors of every two points between all failure test points; defining a plurality of failure test points with the same vector as the same group; separating a plurality of pending failure patterns from each group; and obtaining a failure pattern based on the plurality of pending failure patterns. Through the aforementioned steps, a failure pattern can be accurately and quickly obtained, and the failure pattern is used to determine whether there is a problem with the test machine. If a failure pattern is obtained, it can be determined that there is a problem with the test environment of the test machine, so that the tester can adjust the test environment of the test machine (such as modifying the test program), thereby preventing the occurrence of false detection by the test machine and improving the accuracy of electrical testing.

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0048] The following is combined with Figure 1-Figure 5 The method for obtaining a failure pattern according to an embodiment of the present invention is described in detail.

[0049] refer to Figure 1 , a chip test result image 100 in a wafer is obtained, wherein the chip test result image 100 is marked with a plurality of failed test point 101 chips.

[0050] There are several chips in the wafer, each of which has several memory addresses, and one chip corresponds to a chip test result image. The chip can be a memory chip, and the memory chip has a storage array, and the storage array has several array-arranged storage units, each storage unit has a corresponding memory address, and the corresponding storage unit can be written, read or erased according to the storage address. In a specific embodiment, the chip can be a volatile memory chip, including a random access memory (RAM), a dynamic random access memory (DRAM), a static random access memory (SRAM), etc., and a non-volatile memory chip, including a NAND flash memory, an ONR flash memory or a resistor variable memory. In other embodiments, the chip can also be a non-memory chip, such as a logic chip.

[0051] The wafer test result image 100 is a distribution diagram corresponding to one or more memory addresses where the electrical test result fails after the electrical performance test is performed on the chips in the wafer. When acquiring the failure graph, the number of the wafer test result images 100 can be one or more. When acquiring the wafer test result image 100, the electrical performance test must be performed on each memory address in the chip.

[0052] In one embodiment, the process of obtaining the chip test result image 100 is: providing a wafer, on which a plurality of chips are formed; the process of obtaining the chip test result image is: performing an electrical performance test on each memory address in the chip to obtain a plurality of electrical test results; arranging the plurality of electrical test results according to the memory addresses to obtain a row and column arrangement image, wherein the row and column arrangement pattern is the chip test result image, and one of the failure test points in the chip test result image corresponds to a memory address.

[0053] The electrical performance test is CP (Circuit Probe) or FT (Final test). When performing the electrical performance test, each memory address on the chip must be subjected to an electrical performance test. After the electrical performance test, a row and column arrangement image is obtained according to the test results of the electrical performance. The row and column arrangement image corresponds to the memory address on the chip, that is, each memory address on the chip will have a test result display point at the corresponding position on the row and column arrangement image. Specifically, if the electrical performance test result of a certain memory address meets the electrical performance requirements, the memory address is considered to be a normal memory address, and the corresponding position of the row and column arrangement image is marked as a normal point or not marked. If the electrical performance test result of a certain memory address does not meet the electrical performance requirements, the memory address is considered to be a memory address where the electrical performance test fails, and the corresponding position in the row and column arrangement image is marked as a failure point. The memory address where the electrical performance fails includes the mistested memory address caused by the test environment of the test machine. In one embodiment, the obtained row and column arrangement pattern is directly used as the chip test result image 100, the normal points in the row and column arrangement image are used as normal test points in the chip test result image 100, and the failure points in the row and column arrangement image are used as failure test points in the chip test result image 100.

[0054] Research has found that since the number of memory addresses in a chip may be large (possibly millions, tens of millions or hundreds of millions), if the obtained row and column arrangement pattern is directly used as the chip test result image 100, the amount of calculation in the subsequent vector calculation will be very large, reducing the efficiency of obtaining the failure pattern, and the erroneous test caused by the test environment of the test machine will have a certain repeatability. Therefore, in another embodiment, the process of obtaining the chip test result image 100 is: performing an electrical performance test on each memory address in the chip to obtain a number of electrical test results; arranging the electrical test results according to the memory address to obtain a row and column arrangement image; compressing the row and column arrangement pattern to obtain a compressed pattern, the compressed image is the chip test result image, and one of the failure test points in the chip test result image corresponds to multiple memory addresses, which greatly reduces the amount of calculation for subsequent vector calculations and improves efficiency.

[0055] In one embodiment, the compression process is: compressing multiple adjacent electrical test results in the row and column arrangement image into one point, if one of the multiple electrical test results is failed, then the point formed after compression is a failed test point. Specifically, the row-column arrangement image has a number of normal points and / or failure points corresponding to a number of memory addresses, and the normal points and / or failure points are arranged in rows and columns. When compressed, all points in the N*M square matrix are compressed into one point (N is equal to or not equal to M, 2≤N≤1000, 2≤M≤1000, if there is at least one point in the N*M square matrix that is a failure point, then the point formed after the compression of the N*M square matrix is ​​marked as a failure test point, if there is no failure point in the N*M square matrix, then the point formed after the compression of the N*M square matrix is ​​marked as a normal test point. In a specific embodiment, for example, a chip has 2^30 memory addresses, and after compression, there are only 6000-10000 corresponding memory addresses. In other embodiments, other methods can also be used for compression.

[0056] In a specific embodiment, the electrical performance test process is performed on an existing test machine, and the chip test result image can also be obtained by performing corresponding image processing on the chip test result by the existing test machine.

[0057] In this embodiment, the obtained chip test result image 100 is as follows: Figure 1 As shown, the chip test result image 100 is a compressed image, and each failure test point 101 corresponds to a plurality of memory addresses on the chip. Figure 1 The middle outer frame represents the outline of a chip, and each small square represents a failed test point 101. Since normal test points will not be involved in subsequent calculations, in order to reduce the interference of subsequent calculations and improve the accuracy of calculations, normal test points are marked with blanks on the chip test result image 100. In other embodiments, the failed test points on the chip test result image 100 can be marked with other graphic marks or grayscale. It should be noted that Figure 1 The chip test result image 100 shown is only used as an example to facilitate the description of the solution of the present invention, and it should not limit the protection scope of the present invention.

[0058] refer to Figure 2 , calculate the vector between every two points of all failed test points 101.

[0059] A vector is determined between every two failure test points 101 among all the failure test points 101 (the vector represents the direction and distance between the two failure test points 101), so each failure test point 101 has multiple vectors relative to other failure test points 101 in the chip test result image 100, that is, each failure test point 101 has multiple vectors. For example, when there are 800 failure test points 101 on the chip test result image 100, each failure test point 101 can obtain at most 799 vectors.

[0060] Figure 2 The partial vectors corresponding to the partial failure test points 101 are shown in FIG. Figure 2 The dashed lines 11, 21, 22, 23, and 24 with arrows in the middle represent Figure 2 Vectors corresponding to some failed test points 101 on .

[0061] When performing vector calculations, a two-dimensional coordinate system or a polar coordinate system can be used, so that the vector obtained through calculation is a two-dimensional coordinate vector or a polar coordinate vector.

[0062] In one embodiment, a distributed computing server equipped with a graphics processor is used to perform vector calculations, that is, multiple computing servers process chip test result images in parallel to further improve the speed and efficiency of vector calculations.

[0063] refer to Figure 3 and Figure 4 , several failure test points with the same vector are defined as the same group.

[0064] The same vector is a vector with the same direction and distance.

[0065] Since the vector calculation is performed for each failed test point 101 on the chip test result image 100, although each failed test point 101 may have multiple corresponding vectors, as long as a failed test point 101 has the same vector as other test points 101, the failed test points 101 with the same vector are defined as a group. Several failed test points 101 on the chip test result image 100 can define many groups.

[0066] In one embodiment, when defining the same group, each failure test point 101 with the same vector on the chip test result image 100 can be marked as the same group, and different groups can be marked with different group marks. Specifically, a combination of letters, words or numbers can be used for marking. For example, letters A, B, C... can be used to represent different groups, and group 1, group 2, and group 3 can be used to represent different groups.

[0067] In other embodiments, each failed test point 101 with the same vector on the chip test result image 100 may be extracted or segmented as a group, and the positions of the extracted or segmented failed test points 101 remain corresponding to the positions of the failed test points in the chip test result image 100 . Figure 3 and Figure 4 Based on Figure 2 Different groups are defined in the failure test point 101 having the same vector, Figure 3 Group 1 is shown. Figure 4 Group 2 is shown. Figure 3 Several failed test points 101 in the group 1 shown have the same first vector 11. Figure 4 Several failure test points 101 in have the same second vector 12. It should be noted that, Figure 3 and Figure 4 The groups shown in the figure are for illustration only and should not limit the protection scope of the present invention.

[0068] refer to Figure 5 , several pending failure graphs are separated from each group.

[0069] The above steps define several groups, each of which has several failure test points 101 with the same vector. A failure test point 101 in each group can be independently distributed or can be adjacent to multiple other failure test points 101 at the same time, and multiple adjacent failure test points can form a corresponding graph.

[0070] In this embodiment, a clustering algorithm is used to separate several types of pending failure graphs from each group. Figure 5 Based on Figure 3 and Figure 4 The three types of pending failure graphs separated from cluster 1 and cluster 2 include a first type of pending failure graph 31 , a second type of pending failure graph 32 and a third type of pending failure graph 33 .

[0071] The clustering algorithm may be, for example, a K-MEANS algorithm, a K-MEDIODS algorithm, a Clara algorithm, a Clarans algorithm, or the like.

[0072] The clustering algorithm described in this embodiment adopts the K-MEANS algorithm, and the specific steps include:

[0073] (1) A number of failure test points 101 in a certain group are set as a point set S, which needs to be divided into S_1, S_2, ..., S_K categories, where each category in S_1, S_2, ..., S_K represents a pending failure pattern;

[0074] (2) Set the size of K and randomly select K points as the initial center points;

[0075] (3) Calculate the distance between each point and the K center points, select the nearest center point, and divide it into the cluster centered on the center point;

[0076] (4) Recalculate the center points of K new clusters;

[0077] (5) If the center point remains unchanged, the K-Means process ends. Otherwise, repeat steps (3) and (4).

[0078] After a number of pending failure patterns are separated from each group, the method further includes the step of obtaining a failure pattern based on the number of pending failure patterns.

[0079] The failure pattern is determined based on taking one or more pending failure patterns with a large number of occurrences as failure patterns.

[0080] Specifically, in one embodiment, the process of obtaining a failure pattern based on the several pending failure patterns includes: calculating the number of occurrences corresponding to the several pending failure patterns; sorting them from large to small according to the number of occurrences, and using one or more pending failure patterns with a corresponding number of occurrences ≥ 2 times in the chip test result image as failure patterns, or using one or more pending failure patterns with the number of occurrences ranked in the top 40% as failure patterns, so as to improve the efficiency and accuracy of failure pattern determination.

[0081] In a specific embodiment, one or more pending failure patterns with a corresponding number of occurrences of 3, 4, 5, 7, 8, 9, 10, 20, 50, 100, or 1000 can be used as failure patterns. In this embodiment, a pending failure pattern with a corresponding number of occurrences ≥ 4 is used as a failure pattern. For details, please refer to Figure 5 , Figure 5 The first pending failure pattern 31 appears 4 times, and the first pending failure pattern 31 is used as the failure pattern. In other embodiments, the number of times can be reasonably set according to actual conditions.

[0082] In another embodiment, one or more pending failure patterns whose occurrences are ranked in the top 40%, 20%, 10%, 8%, 6% or 5% are used as failure patterns. Figure 5 ,if Figure 5The three pending failure patterns (the first pending failure pattern 31, the second pending failure pattern 32 and the third pending failure pattern 33) shown in the figure are divided into groups corresponding to a number of chips, and the corresponding occurrence times of the first pending failure pattern 31, the second pending failure pattern 32 and the third pending failure pattern 33 are obtained. For example, the first pending failure pattern 31 appears 50 times, the second pending failure pattern 32 appears 30 times, and the third pending failure pattern 32 appears 20 times. They are sorted from large to small according to the number of occurrences. The first pending failure pattern 31 is in the first 40%, and the first specific failure pattern 32 is used as the failure pattern. In other embodiments, the percentage can be reasonably set according to actual conditions.

[0083] Since the false detection of the electrical performance of the test machine caused by the test environment problem (testing the normal memory address as a failed memory address) has certain regularities, the failure pattern can be accurately and quickly obtained through the aforementioned steps in the present application. The failure pattern is used to determine whether there is a problem with the test machine. If the failure pattern is obtained, it can be determined that there is a problem with the test environment of the test machine, so that the tester can adjust the test environment of the test machine (such as modifying the test program), thereby preventing the occurrence of false detection of the test machine and improving the accuracy of electrical testing.

[0084] An embodiment of the present invention further provides a method for monitoring a test machine, comprising:

[0085] Acquire a failure graph using the method described in the above embodiment;

[0086] Performing an electrical performance test on each memory address of a chip to be tested on a wafer to be tested to obtain a chip test result image corresponding to the chip to be tested;

[0087] It is determined whether there is a failure pattern on the chip test result image corresponding to the chip to be tested. If there is a failure pattern, the test environment of the test machine is checked.

[0088] The obtained failure pattern can be stored in an experience database of the test machine, and according to the aforementioned failure pattern acquisition method, different wafers to be tested on the production line can be selected as chips in real time or irregularly, so that the failure pattern can be updated in real time, regularly or irregularly, further improving the efficiency of monitoring the test machine and further improving the accuracy of electrical testing.

[0089] In one embodiment, it is determined whether there is a failure pattern on the chip test result image corresponding to the wafer to be tested by matching the pattern on the chip test result image corresponding to the chip to be tested with the failure pattern.

[0090] The test environment includes a test program.

[0091] The inspection of the test environment includes modifying the test program. It should be noted that the limitations or descriptions of the same or similar parts of this embodiment (the method for monitoring the test machine) and the previous embodiment (the method for obtaining the failure pattern) will not be repeated in this implementation. Please refer to the limitations or descriptions of the corresponding parts of the previous embodiment for details.

[0092] An embodiment of the present invention also provides a device for obtaining a failure pattern, please refer to Figure 6 , the failure pattern acquisition device 300 includes:

[0093] The chip test result image obtaining unit 301 is used to obtain a chip test result image in a wafer, wherein a plurality of failure test points are marked in the chip test result image;

[0094] A vector calculation unit 302, used to calculate the vectors between every two points of all failure test points;

[0095] A group confirmation unit 303, used to define a number of failure test points with the same vector as the same group;

[0096] The pending failure pattern confirmation unit 304 is used to separate a plurality of pending failure patterns from each group;

[0097] The failure pattern obtaining unit 305 is configured to obtain a failure pattern based on the plurality of pending failure patterns.

[0098] The wafer has a plurality of chips, each of the chips has a plurality of memory addresses, and one chip corresponds to a chip test result image.

[0099] In one embodiment, the process of the chip test result image obtaining unit 301 obtaining the test result image is: performing an electrical performance test on each memory address in the chip to obtain a number of electrical test results; arranging the several electrical test results according to the memory addresses to obtain a row and column arrangement image, wherein the row and column arrangement pattern is the chip test result image, and one of the failure test points in the chip test result image corresponds to a memory address.

[0100] In another embodiment, the process of the chip test result image obtaining unit 301 obtaining the test result image is: performing an electrical performance test on each memory address in the chip to obtain a number of electrical test results; arranging the several electrical test results according to the memory addresses to obtain a row and column arrangement image; compressing the row and column arrangement pattern to obtain a compressed pattern, wherein the compressed image is a chip test result image, and one of the failure test points in the chip test result image corresponds to multiple memory addresses.

[0101] In one embodiment, the compression process is: compressing multiple adjacent electrical test results in the row and column arrangement image into one point, if one of the multiple electrical test results is failed, then the point formed after compression is a failed test point.

[0102] The vector is a two-dimensional coordinate vector or a polar coordinate vector.

[0103] The group confirmation unit 303 separates several pending failure patterns from each group through a clustering algorithm.

[0104] In one embodiment, the process of the failure pattern obtaining unit 305 obtaining the failure pattern includes: calculating the number of occurrences corresponding to the several pending failure patterns; sorting them from large to small according to the number of occurrences, and taking one or more pending failure patterns with a corresponding number of occurrences ≥ 2 times in the chip test result image as failure patterns, or taking one or more pending failure patterns with the number of occurrences ranked in the top 40% as failure patterns.

[0105] In one embodiment, the vector computing unit 302 may include a distributed computing server coupled with a graphics processor.

[0106] It should be noted that the limitations or descriptions of the same or similar parts of this embodiment (failure pattern acquisition device) and the previous embodiment (failure pattern acquisition method) will not be repeated in this implementation. Please refer to the limitations or descriptions of the corresponding parts of the previous embodiment for details.

[0107] An embodiment of the present invention also provides a system for monitoring a test machine, please refer to Figure 7 ,include:

[0108] The aforementioned failure pattern acquisition device 300 is used to acquire a failure pattern;

[0109] The test machine 400 performs an electrical performance test on each memory address of a chip to be tested on a wafer to be tested to obtain a chip test result image corresponding to the chip to be tested;

[0110] The judging unit 401 judges whether there is a failure pattern on the chip test result image corresponding to the chip to be tested, and if there is a failure pattern, checks the test environment of the test machine.

[0111] In a specific embodiment, the judgment unit 401 and the chip test result image acquisition unit 301 in the failure pattern acquisition device 300 can be integrated in the test machine 400 .

[0112] In one embodiment, the judgment unit 401 judges whether there is a failure pattern on the chip test result image corresponding to the wafer to be tested by matching the pattern on the chip test result image corresponding to the chip to be tested with the failure pattern.

[0113] The test environment includes a test program.

[0114] The checking of the test environment includes modifying the test program.

[0115] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for obtaining a failure graph, characterized in that: include: Obtaining a chip test result image in a wafer, wherein a plurality of failed test points are marked in the chip test result image; The wafer has a plurality of chips, each of which has a plurality of memory addresses, and each chip has a corresponding chip test result image; the chip test result image is obtained by: performing an electrical performance test on each memory address in the chip to obtain a plurality of electrical test results; Arranging a plurality of electrical test results according to memory addresses to obtain a row and column arrangement image, wherein the image obtained is a chip test result image, and one of the failure test points in the chip test result image corresponds to one memory address; Calculate the vector between every two points of all failed test points; Define several failure test points with the same vector as the same group; From each group, several pending failure patterns are separated; A failure pattern is obtained based on the several pending failure patterns.

2. The method for obtaining a failure pattern according to claim 1, characterized in that: After a row and column arrangement image is obtained by arranging a number of electrical test results according to the memory address, the method further includes compressing the row and column arrangement image to obtain a compressed image, where the compressed image is a chip test result image.

3. The method for obtaining a failure pattern according to claim 2, characterized in that: The compression process is: compressing multiple adjacent electrical test results in the row and column arrangement image into one point, if one of the multiple electrical test results is failed, the point formed after compression is a failed test point.

4. The method for obtaining a failure pattern according to claim 1, characterized in that: The vector is a two-dimensional coordinate vector or a polar coordinate vector.

5. The method for obtaining a failure pattern according to claim 1, wherein: Distributed computing servers equipped with graphics processors are used for vector calculations.

6. The method for obtaining a failure pattern according to claim 1, characterized in that: Several pending failure graphs are separated from each group through a clustering algorithm.

7. The method for obtaining a failure pattern according to claim 1, characterized in that: The process of obtaining the failure pattern based on the several pending failure patterns includes: calculating the number of occurrences corresponding to the several pending failure patterns; sorting them from large to small according to the number of occurrences, and taking one or more pending failure patterns with a corresponding number of occurrences ≥ 2 times in the chip test result image as failure patterns, or taking one or more pending failure patterns with the number of occurrences ranked in the top 40% as failure patterns.

8. The method for obtaining a failure pattern according to claim 1, characterized in that: Also includes: After the failure pattern is obtained, the test environment of the corresponding test machine is checked, and the test environment includes a test program.

9. A device for acquiring a failure pattern, characterized in that: include: A chip test result image obtaining unit is used to obtain a chip test result image in a wafer, wherein a plurality of failure test points are marked in the chip test result image; The wafer has a plurality of chips, each of which has a plurality of memory addresses, and each chip has a corresponding chip test result image; the chip test result image is obtained by: performing an electrical performance test on each memory address in the chip to obtain a plurality of electrical test results; Arranging a plurality of electrical test results according to memory addresses to obtain a row and column arrangement image, wherein the image obtained is a chip test result image, and one of the failure test points in the chip test result image corresponds to one memory address; A vector calculation unit is used to calculate the vector between every two points of all failure test points; A group confirmation unit, used for defining a number of failure test points with the same vector as the same group; A pending failure pattern confirmation unit is used to separate a number of pending failure patterns from each group; The failure pattern obtaining unit is used to obtain a failure pattern based on the several types of pending failure patterns.

10. The device for acquiring failure patterns according to claim 9, characterized in that: After obtaining a row and column arrangement image by arranging a number of electrical test results according to the memory address, the method further includes: compressing the row and column arrangement image to obtain a compressed image, wherein the compressed image is a chip test result image.

11. The device for acquiring a failure pattern according to claim 10, characterized in that: The compression process is: compressing multiple adjacent electrical test results in the row and column arrangement image into one point, if one of the multiple electrical test results is failed, the point formed after compression is a failed test point.

12. The device for acquiring failure patterns according to claim 9, characterized in that: The vector is a two-dimensional coordinate vector or a polar coordinate vector.

13. The device for acquiring failure patterns according to claim 9, characterized in that: The vector computing unit is a distributed computing server equipped with a graphics processor.

14. The device for acquiring failure patterns according to claim 9, characterized in that: The group confirmation unit separates several pending failure graphs from each group through a clustering algorithm.

15. The device for acquiring failure patterns according to claim 9, characterized in that: The process of obtaining the failure pattern by the failure pattern obtaining unit includes: calculating the number of occurrences corresponding to the several pending failure patterns; sorting them from large to small according to the number of occurrences, and taking one or more pending failure patterns with a corresponding number of occurrences ≥ 2 times in the chip test result image as failure patterns, or taking one or more pending failure patterns with the number of occurrences ranked in the top 40% as failure patterns.

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