Wafer level packaging structure and manufacturing method

Abstract

The invention belongs to the field of wafer-level packaging technology, in particular to a wafer-level packaging structure, comprising a molding body, a chip groove and an annular groove are provided at the bottom of the molding body, the chip groove is located on the inner side of the annular groove, a chip is provided in the chip groove, an electrode is provided at the bottom of the chip, a metal wiring layer is provided at the bottom of the molding body, a capping layer is provided at the bottom of the molding body, an insulating layer is provided at the bottom of the capping layer, an under-bump metal layer is arranged on the insulating layer, an under-bump metal layer is provided between the insulating layer and the capping layer, the top of the under-bump metal layer is respectively connected to the electrode and the metal wiring layer, and a solder ball is provided at the bottom of the under-bump metal layer; the invention simplifies the packaging process, has a small packaging size, is simple in process and is compatible with existing processes, improves packaging efficiency, reduces packaging cost, has strong practicality, is safe and reliable, sets a heat dissipation structure for the chip, improves the heat dissipation efficiency of the chip, ensures the stable operation of the chip, and improves the quality of the packaging mechanism.

Description

Technical Field

[0001] The present invention relates to the field of wafer-level packaging technology, and in particular to a wafer-level packaging structure and a manufacturing method. Background Art

[0002] Wafer-level chip packaging (WL-CSP) technology is a technology that packages and tests the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is consistent with the bare die. Wafer-level chip size packaging technology changes traditional packaging, such as ceramic leadless chip carriers, organic leadless chip carriers and digital camera module models, and conforms to the market's requirements for increasingly light, thin, short, small and low-priced microelectronic products. The chip size after wafer-level chip size packaging has reached a high degree of miniaturization, and the chip cost is significantly reduced as the chip size decreases and the wafer size increases. Wafer-level chip size packaging technology is a technology that can integrate IC design, wafer manufacturing, packaging testing, and basic board manufacturing. It is a hot spot in the current packaging field and a trend of future development.

[0003] The existing wafer-level packaging structure has defects in the heat dissipation of the chip after the chip is installed. The packaging structure has low heat dissipation efficiency for the chip on the wafer, relying on the thermal conductivity of the material itself, and the heat dissipation efficiency is low. The existing packaging structure is relatively complex and the process operation is complicated. Therefore, we propose a wafer-level packaging structure and a manufacturing method to solve the above problems. Summary of the invention

[0004] The purpose of the present invention is to provide a wafer-level packaging structure and a manufacturing method to solve the problems raised in the above-mentioned background technology.

[0005] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a wafer-level packaging structure, comprising a molding body, a chip groove and an annular groove are provided at the bottom of the molding body, the chip groove is located on the inner side of the annular groove, a chip is provided in the chip groove, an electrode is provided at the bottom of the chip, a metal wiring layer is provided at the bottom of the molding body, a capping layer is provided at the bottom of the molding body, an insulating layer is provided at the bottom of the capping layer, an under-bump metal layer is installed on the insulating layer, an under-bump metal layer is provided between the insulating layer and the capping layer, the top of the under-bump metal layer is respectively connected to the electrode and the metal wiring layer, a solder ball is provided at the bottom of the under-bump metal layer, a through hole one is provided on the capping layer, a through hole two connected to the through hole one is provided on the insulating layer, the through hole one is connected to the annular groove, and a heat sink is provided between the chip groove and the annular groove.

[0006] Preferably, the cross-sections of the through hole 1 and the through hole 2 are both circular structures, and the cross-sectional diameters of the through hole 1 and the through hole 2 are the same.

[0007] Preferably, the electrode and the bottom of the metal wiring layer are located in the same plane.

[0008] Preferably, there are multiple heat sinks, and multiple mounting holes for mounting the heat sinks are provided between the chip groove and the annular groove, and the lengths of the multiple mounting holes are different.

[0009] A method for manufacturing a wafer-level packaging structure comprises the following steps:

[0010] S1. Forming a chip groove and an annular groove in the molding body;

[0011] S2. Open a plurality of mounting holes between the chip slot and the annular slot, and install the heat sink in the mounting holes;

[0012] S3, installing a chip in the chip slot, and then setting a metal wiring layer at the bottom of the molding body;

[0013] S4, providing an opening 1 for placing an electrode on the chip and an opening 2 for placing a metal wiring layer in the capping layer, and then providing a through hole 1 and a connecting hole for placing an under-bump metal layer, wherein the connecting hole is connected to the opening 1 and the opening 2;

[0014] S5, disposing the capping layer at the bottom of the molding plastic body;

[0015] S6, taking the insulating layer to open a second through hole connected to the first through hole, and installing an under-bump metal layer connected to the electrode and the metal wiring layer;

[0016] S7, installing the insulating layer on the bottom of the capping layer, and making the top of the under bump metal layer enter the connecting hole, the under bump metal layer is in contact with the electrode and the metal wiring layer respectively, and the through hole 1 is connected with the through hole 2;

[0017] S8. Make solder balls on the under-bump metal layer.

[0018] Preferably, opening one, opening two, through hole one and through hole two are formed by a laser drilling process.

[0019] Preferably, an adapting hole is opened on the insulating layer, the under bump metal layer is installed in the adapting hole, and the top of the under bump metal layer passes through the adapting hole.

[0020] Beneficial effects of the present invention:

[0021] The under-bump metal layer is directly connected to the electrode and the metal wiring layer, and a solder ball is provided at the bottom of the under-bump metal layer, which simplifies the intermediate connection mechanism, reduces material costs, simplifies the packaging process, has a small package size, a simple process and is compatible with existing processes, improves packaging efficiency, reduces packaging costs, is highly practical, and is safe and reliable.

[0022] By setting an annular groove around the chip groove and then realizing heat conduction between the chip groove and the annular groove through a heat sink, it is convenient to transfer the heat around the chip to the annular groove, and then dissipate the heat through through holes one and two, a heat dissipation structure is set for the chip, the heat dissipation efficiency of the chip is improved, the stable operation of the chip is ensured, and the quality of the packaging structure is improved.

[0023] The present invention simplifies the packaging process, has a small packaging size, is simple in process and is compatible with existing processes, improves packaging efficiency, reduces packaging costs, is highly practical, safe and reliable, sets a heat dissipation structure for the chip, improves the heat dissipation efficiency of the chip, ensures the stable operation of the chip, and improves the quality of the packaging mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of the present invention;

[0025] Figure 2 It is a bottom view structural schematic diagram of the molding body of the present invention.

[0026] In the figure: 1. molding compound; 2. chip slot; 3. chip; 4. electrode; 5. metal wiring layer; 6. under-bump metal layer; 7. solder ball; 8. annular groove; 9. heat sink; 10. through hole 1; 11. through hole 2; 12. capping layer; 13. insulating layer. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0028] Reference Figure 1-2 The wafer-level packaging structure includes a molding body 1, a chip groove 2 and an annular groove 8 are provided at the bottom of the molding body 1, the chip groove 2 is located on the inner side of the annular groove 8, a chip 3 is provided in the chip groove 2, an electrode 4 is provided at the bottom of the chip 3, a metal wiring layer 5 is provided at the bottom of the molding body 1, a capping layer 12 is provided at the bottom of the molding body 1, an insulating layer 13 is provided at the bottom of the capping layer 12, an under bump metal layer 6 is arranged between the insulating layer 13 and the capping layer 12, the top of the under bump metal layer 6 is respectively connected to the electrode 4 and the metal wiring layer 5, a solder ball 7 is provided at the bottom of the under bump metal layer 6, a through hole 10 is provided on the capping layer 12, a through hole 2 11 connected to the through hole 10 is provided on the insulating layer 13, the through hole 10 is communicated with the annular groove 8, and a heat sink 9 is provided between the chip groove 2 and the annular groove 8.

[0029] In this embodiment, the cross-sections of through hole 10 and through hole 2 11 are both circular structures, the cross-sectional diameters of through hole 10 and through hole 2 11 are the same, the bottom of electrode 4 and metal wiring layer 5 are located in the same plane, there are multiple heat sinks 9, and multiple mounting holes for mounting the heat sink 9 are provided between the chip slot 2 and the annular slot 8, and the lengths of the multiple mounting holes are different.

[0030] A method for manufacturing a wafer-level packaging structure comprises the following steps:

[0031] S1, forming a chip groove 2 and an annular groove 8 in a molded plastic body 1;

[0032] S2, a plurality of mounting holes are opened between the chip slot 2 and the annular slot 8, and the heat sink 9 is installed in the mounting holes;

[0033] S3, a chip 3 is installed in the chip slot 2, and then a metal wiring layer 5 is provided at the bottom of the molding plastic body 1;

[0034] S4, an opening 1 for placing an electrode on the chip 3 and an opening 2 for placing the metal wiring layer 5 are provided in the capping layer 12, and then a through hole 10 and a connecting hole for placing the under-bump metal layer 6 are provided, and the connecting hole is connected with the opening 1 and the opening 2;

[0035] S5, disposing the capping layer 12 at the bottom of the molding compound body 1;

[0036] S6, take the insulating layer 13 to open the second through hole 11 connected with the first through hole 10, and install the under bump metal layer 6 connected with the electrode 4 and the metal wiring layer 5;

[0037] S7, installing the insulating layer 13 on the bottom of the capping layer 12, and making the top of the under-bump metal layer 6 enter the connecting hole, the under-bump metal layer 6 is in contact with the electrode 4 and the metal wiring layer 5 respectively, and the through hole 10 is connected with the through hole 2 11;

[0038] S8. Make solder balls 7 on the under bump metal layer 6.

[0039] In this embodiment, the laser drilling process forms opening 1, opening 2, through hole 10 and through hole 2 11. An adapting hole is formed on the insulating layer 13, and the UBM layer 6 is installed in the adapting hole, and the top of the UBM layer 6 passes through the adapting hole.

[0040] The present invention is directly connected with the electrode 4 and the metal wiring layer 5 through the under-bump metal layer 6, and a solder ball 7 is arranged at the bottom of the under-bump metal layer 6, which simplifies the intermediate connection mechanism, reduces the material cost, simplifies the packaging process, has a small packaging size, a simple process and is compatible with the existing process, improves the packaging efficiency, reduces the packaging cost, has strong practicality, and is safe and reliable. By arranging an annular groove 8 around the chip groove 3, and then realizing the heat conduction between the chip groove 3 and the annular groove 8 through the heat sink 9, it is convenient to transfer the heat around the chip 3 to the annular groove 8, and then dissipate the heat through the through hole 10 and the through hole 2 11, a heat dissipation structure is arranged for the chip 3, the heat dissipation efficiency of the chip 3 is improved, the stable operation of the chip is ensured, and the quality of the packaging mechanism is improved. The present invention simplifies the packaging process, has a small packaging size, a simple process and is compatible with the existing process, improves the packaging efficiency, reduces the packaging cost, has strong practicality, and is safe and reliable. A heat dissipation structure is arranged for the chip 3, the heat dissipation efficiency of the chip 3 is improved, the stable operation of the chip is ensured, and the quality of the packaging mechanism is improved.

[0041] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0043] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A wafer-level packaging structure, comprising a molding compound body (1), characterized in that: The bottom of the molded plastic body (1) is provided with a chip groove (2) and an annular groove (8), the chip groove (2) is located inside the annular groove (8), a chip (3) is arranged in the chip groove (2), the bottom of the chip (3) is provided with an electrode (4), the bottom of the molded plastic body (1) is provided with a metal wiring layer (5), the bottom of the molded plastic body (1) is provided with a capping layer (12), the bottom of the capping layer (12) is provided with an insulating layer (13), an under-bump metal layer (6) is mounted on the insulating layer (13), and the under-bump metal layer (6) is provided on the under-bump metal layer (13). The layer passes through the insulating layer (13) and extends into the capping layer (12); the top of the under-bump metal layer (6) is respectively connected to the electrode (4) and the metal wiring layer (5); the bottom of the under-bump metal layer (6) is provided with a solder ball (7); the capping layer (12) is provided with a through hole 1 (10); the insulating layer (13) is provided with a through hole 2 (11) connected to the through hole 1 (10); the through hole 1 (10) is connected to the annular groove (8); and a heat sink (9) is provided between the chip groove (2) and the annular groove (8).

2. The wafer-level packaging structure according to claim 1, characterized in that: The cross-sections of the through hole 1 (10) and the through hole 2 (11) are both circular structures, and the cross-section diameters of the through hole 1 (10) and the through hole 2 (11) are the same.

3. The wafer-level packaging structure according to claim 1, characterized in that: The electrode (4) and the bottom of the metal wiring layer (5) are located in the same plane.

4. The wafer-level packaging structure according to claim 1, characterized in that: There are a plurality of heat sinks (9), and a plurality of mounting holes for mounting the heat sinks (9) are provided between the chip slot (2) and the annular slot (8), and the plurality of mounting holes have different lengths.

5. A method for manufacturing a wafer-level packaging structure, characterized in that: The following steps are involved: S1, respectively forming a chip groove (2) and an annular groove (8) in a molded plastic body (1); S2, opening a plurality of mounting holes between the chip slot (2) and the annular slot (8), and installing the heat sink (9) in the mounting holes; S3, installing a chip (3) in the chip slot (2), and then providing a metal wiring layer (5) at the bottom of the molding plastic body (1); S4, providing an opening 1 for placing an electrode on the chip (3) and an opening 2 for placing a metal wiring layer (5) on the capping layer (12), and then providing a through hole 1 (10) and a connecting hole for placing an under-bump metal layer (6), wherein the connecting hole is connected to the opening 1 and the opening 2; S5, placing a sealing layer (12) on the bottom of the molded plastic body (1); S6, taking the insulating layer (13), opening a second through hole (11) connected to the first through hole (10), and installing an under-bump metal layer (6) connected to the electrode (4) and the metal wiring layer (5); S7, installing the insulating layer (13) on the bottom of the capping layer (12), and at the same time making the top of the under-bump metal layer (6) enter the connecting hole, the under-bump metal layer (6) is in contact with the electrode (4) and the metal wiring layer (5), respectively, and the through hole 1 (10) is connected to the through hole 2 (11); S8. Making solder balls (7) on the under-bump metal layer (6).

6. The method for manufacturing a wafer-level packaging structure according to claim 5, characterized in that: Opening 1, opening 2, through hole 1 (10) and through hole 2 (11) are formed by a laser drilling process.

7. The method for manufacturing a wafer-level packaging structure according to claim 5, characterized in that: An adapting hole is provided on the insulating layer (13), the under bump metal layer (6) is installed in the adapting hole, and the top of the under bump metal layer (6) passes through the adapting hole.

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