Semiconductor device structure and preparation method thereof

Abstract

The present invention relates to a semiconductor device structure and a preparation method thereof. The vertical power metal oxide semiconductor field effect transistor comprises: a substrate of a first conductivity type; an epitaxial layer of a first conductivity type; a gate structure; a well region of a second conductivity type; a source region of a first conductivity type; a first Schottky contact layer, located on a side of the gate structure away from the well region of the second conductivity type, and located on a surface of an epitaxial layer of a first conductivity type away from a substrate of the first conductivity type or located in the epitaxial layer of the first conductivity type; a source metal layer and a drain metal layer. The semiconductor device structure has excellent efficiency and stability, and at the same time, the raw material cost is low and the preparation process is simple.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device structure and a preparation method thereof. Background Art

[0002] Metal oxide semiconductor field effect transistor (MOSFET) is an important semiconductor device, which is widely used in analog circuits and digital circuits. In order to make the metal oxide semiconductor field effect transistor obtain higher efficiency and better stability, a Schottky diode is usually connected in parallel between the source and drain of the MOSFET.

[0003] There are three traditional parallel connection methods: (1) installing the Schottky diode and the metal oxide semiconductor field effect transistor in parallel on the circuit board; (2) packaging the Schottky chip and the metal oxide semiconductor field effect transistor chip in parallel in the same semiconductor device, and achieving parallel connection by wire bonding; (3) designing the metal oxide semiconductor field effect transistor and the Schottky diode in different partitions of the same chip, and achieving parallel connection by wire bonding. However, in the above traditional parallel connection methods, the Schottky diode will occupy a large amount of silicon surface area, resulting in a significant increase in raw material costs and complex integration processes. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device structure and a preparation method thereof to address the above problems. The semiconductor device structure has excellent efficiency and stability, and at the same time, the raw material cost is low and the preparation process is simple.

[0005] The present invention provides a semiconductor device structure, comprising:

[0006] a substrate of a first conductivity type;

[0007] An epitaxial layer of a first conductivity type, located on a surface of a substrate of the first conductivity type;

[0008] A gate structure, located on a surface of the epitaxial layer of the first conductivity type away from the substrate of the first conductivity type;

[0009] A well region of a second conductivity type is located in the epitaxial layer of the first conductivity type and extends from one side of the gate structure to below the gate structure; the second conductivity type is different from the first conductivity type;

[0010] A source region of the first conductivity type is located in a well region of the second conductivity type;

[0011] A first Schottky contact layer is located on a side of the gate structure away from the well region of the second conductivity type and is located on a surface of the epitaxial layer of the first conductivity type away from the substrate of the first conductivity type or is located in the epitaxial layer of the first conductivity type;

[0012] a source metal layer, contacting the source region of the first conductivity type, the well region of the second conductivity type, and the first Schottky contact layer; and

[0013] The drain metal layer is disposed on a surface of the first conductive type substrate away from the first conductive type epitaxial layer.

[0014] In one embodiment, the semiconductor device structure further includes a second Schottky contact layer, which is located on a side of the gate structure away from the well region of the second conductivity type and is located in the epitaxial layer of the first conductivity type.

[0015] In one embodiment, a central axis of the second Schottky contact layer coincides with a central axis of the first Schottky contact layer.

[0016] In one embodiment, the gate structure includes a gate oxide layer and a polysilicon layer stacked together, the gate oxide layer is located on a surface of the first conductivity type epitaxial layer away from the first conductivity type substrate, and the polysilicon layer is located on a surface of the gate oxide layer away from the first conductivity type epitaxial layer.

[0017] In one embodiment, the semiconductor device structure further includes:

[0018] an insulating layer, located on a surface of the gate structure away from the epitaxial layer of the first conductivity type,

[0019] A gate electrode layer penetrates the insulating layer and is connected to the polysilicon layer in the gate structure.

[0020] In one embodiment, the semiconductor device structure includes a unit cell array composed of at least one unit cell, wherein the unit cell includes a substrate of the first conductivity type, an epitaxial layer of the first conductivity type, the gate structure, a well region of the second conductivity type, a source region of the first conductivity type, the first Schottky contact layer, the source metal layer, and the drain metal layer;

[0021] There are two gate structures, which are symmetrically distributed on both sides of the central axis of the single unit cell; the source region of the first conductivity type is located outside the gate structure, and the first Schottky contact layer is located between the two gate structures.

[0022] In one embodiment, the unit cell array includes more than two unit cells, and each of the second unit cells has the same structure.

[0023] A method for preparing the semiconductor device structure as described above comprises the following steps:

[0024] providing a substrate of a first conductivity type;

[0025] forming an epitaxial layer of the first conductivity type on any surface of the substrate of the first conductivity type;

[0026] forming a gate structure on a surface of the epitaxial layer of the first conductivity type away from the substrate of the first conductivity type;

[0027] forming a well region of a second conductivity type in the epitaxial layer of the first conductivity type;

[0028] forming a source region of the first conductivity type in the well region of the second conductivity type;

[0029] A first Schottky contact layer is formed on a surface of the epitaxial layer of the first conductivity type away from the substrate of the first conductivity type or in the epitaxial layer of the first conductivity type on a side of the gate structure away from the well region of the second conductivity type; and

[0030] A source metal layer and a drain metal layer are formed; the source metal layer is in contact with the source region of the first conductivity type, the well region of the second conductivity type and the first Schottky contact layer; the drain metal layer is covered on the surface of the first conductivity type substrate away from the first conductivity type epitaxial layer.

[0031] In one embodiment, the method further includes the following steps: forming a second Schottky contact layer in the epitaxial layer of the first conductivity type on a side of the gate structure away from the well region of the second conductivity type.

[0032] In one embodiment, the step of forming a gate structure on the surface of the first conductive type epitaxial layer away from the first conductive type substrate includes: sequentially forming a gate oxide material layer and a polysilicon material layer on the surface of the first conductive type epitaxial layer away from the first conductive type substrate, and etching the gate oxide material layer and the polysilicon material layer to obtain a gate structure including a gate oxide layer and a polysilicon layer.

[0033] In the semiconductor device structure of the present invention, the first Schottky contact layer can be used as the anode metal electrode of the Schottky diode, and the drain metal layer can be used as the cathode metal electrode of the Schottky diode, thereby integrating the structure of the Schottky diode into the semiconductor device structure, thereby improving the reverse characteristics and recovery characteristics of the parasitic diode in the semiconductor device structure, reducing electromagnetic interference, improving the efficiency and reliability of the system, and achieving the effect of energy saving and consumption reduction.

[0034] In addition, since the Schottky diode is integrated into the semiconductor device structure, on the one hand, it can reduce the gate-drain charge of the semiconductor device structure, improve the switching speed of the semiconductor device structure, and reduce switching losses; on the other hand, it can reduce the gate-drain charge, reduce gate jitter, and improve the efficiency and reliability of the semiconductor device structure; on the third hand, it can effectively save silicon surface area, reduce the raw material cost of the semiconductor device structure, and simplify the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic structural diagram of a semiconductor device structure according to a first embodiment of the present invention;

[0036] Figure 2 A schematic structural diagram of a semiconductor device structure according to a second embodiment of the present invention;

[0037] Figure 3 A schematic structural diagram of a semiconductor device structure according to a third embodiment of the present invention;

[0038] Figure 4 A schematic structural diagram of a semiconductor device structure according to a fourth embodiment of the present invention.

[0039] In the figure, 10 is a single cell; 101 is a substrate of a first conductivity type; 102 is an epitaxial layer of a first conductivity type; 103 is a well region of a second conductivity type; 104 is a source region of a first conductivity type; 105 is a gate structure; 1051 is a gate oxide layer; 1051a is a first gate oxide layer; 1051b is a second gate oxide layer; 1052 is a polysilicon layer; 1052a is a first polysilicon layer; 1052b is a second polysilicon layer; 106 is an insulating layer; 106a is a first insulating layer; 106b is a second insulating layer; 107 is a source metal layer; 108 is a first Schottky contact layer; 1081 is a first metal layer; 109 is a second Schottky contact layer; 1091 is a second metal layer; 1010 is a drain metal layer. DETAILED DESCRIPTION

[0040] In order to facilitate the understanding of the present invention, the semiconductor device structure and the preparation method thereof provided by the present invention will be described more comprehensively with reference to the relevant embodiments below. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0043] like Figure 1 As shown, the semiconductor device structure of the first embodiment provided by the present invention includes a substrate 101 of a first conductive type, an epitaxial layer 102 of a first conductive type, a gate structure 105, a well region 103 of a second conductive type, a source region 104 of a first conductive type, a first Schottky contact layer 108, a source metal layer 107 and a drain metal layer 1010.

[0044] Specifically, in this embodiment, the semiconductor device structure includes a unit cell array composed of at least one unit cell 10, and the unit cell 10 includes a substrate 101 of a first conductive type, an epitaxial layer 102 of a first conductive type, a gate structure 105, a well region 103 of a second conductive type, a source region 104 of a first conductive type, a first Schottky contact layer 108, a source metal layer 107 and a drain metal layer 1010; there are two gate structures 105, and they are symmetrically distributed on both sides of the central axis of the unit cell 10; the source region 104 of the first conductive type is located on the outside of the gate structure 105, and the first Schottky contact layer 108 is located between the two gate structures 105.

[0045] In one embodiment, the unit cell array includes more than two unit cells, and the structure of each second unit cell is the same.

[0046] The first conductive type substrate 101 can be formed based on a silicon substrate, and the silicon substrate can be grown by a CZ single crystal method. For example, an N-type substrate can be obtained by performing N-type doping on a silicon substrate; a P-type substrate can be obtained by performing P-type doping on a silicon substrate. The doping concentration of the first conductive type substrate 101 can be determined as needed, for example, the resistivity of the first conductive type substrate 101 can be between 0.5 mΩ×cm and 5 mΩ×cm.

[0047] The epitaxial layer 102 of the first conductive type is located on the surface of the substrate 101 of the first conductive type, for example, an N-type epitaxial layer, a P-type epitaxial layer. The epitaxial layer 102 of the first conductive type covers the entire surface area of ​​the substrate 101 of the first conductive type. The thickness and doping concentration of the epitaxial layer 102 of the first conductive type can be determined according to the withstand voltage requirements of the semiconductor device structure. The thickness of the epitaxial layer 102 of the first conductive type can range from 2μm to 150μm.

[0048] The gate structure 105 is located on a surface of the first conductive type epitaxial layer 102 away from the first conductive type substrate 101. Specifically, the gate structure 105 includes a gate oxide layer 1051 and a polysilicon layer 1052 that are stacked. The gate oxide layer 1051 is located on a surface of the first conductive type epitaxial layer 102 away from the first conductive type substrate 101, and the polysilicon layer 1052 is located on a surface of the gate oxide layer 1051 away from the first conductive type epitaxial layer 102.

[0049] In one embodiment, the semiconductor device structure also includes an insulating layer 106 and a gate electrode layer, wherein the insulating layer 106 is located on the surface of the gate structure 105 away from the first conductivity type epitaxial layer 102, and the gate electrode layer penetrates the insulating layer 106 and is connected to the polysilicon layer 1052 in the gate structure 105.

[0050] It can be understood that the single cell 10 includes a first gate structure and a second gate structure, the first gate structure includes a first gate oxide layer 1051a, a first polysilicon layer 1052a and a first insulating layer 106a; the second gate structure includes a second gate oxide layer 1051b, a second polysilicon layer 1052b and a second insulating layer 106b. The gate oxide layer 1051a and the second gate oxide layer 1051b have the same shape and thickness, and the first polysilicon layer 1052a and the second polysilicon layer 1052b have the same shape and thickness.

[0051] The well region 103 of the second conductivity type is located in the epitaxial layer 102 of the first conductivity type, and extends from one side of the gate structure 105 to the bottom of the gate structure 105; the second conductivity type is different from the first conductivity type, specifically, the second conductivity type can be P type or N type; when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type; in one embodiment, the depth of the well region 103 of the second conductivity type is 2μm-150μm.

[0052] The source region 104 of the first conductivity type is located in the well region 103 of the second conductivity type.

[0053] The source metal layer 107 is in contact with the source region 104 of the first conductivity type, the well region 103 of the second conductivity type and the first Schottky contact layer 108 . The source metal layer 107 can lead out the source to form a source metal electrode.

[0054] The drain metal layer 1010 is covered on the surface of the first conductive type substrate 101 away from the first conductive type epitaxial layer 102 . The drain metal layer 1010 leads out the drain to form a drain electrode, which is convenient for processes such as wire bonding and welding.

[0055] In particular, the first Schottky contact layer 108 is located on a side of the gate structure 105 away from the second conductive type well region 103, and is located on a surface of the first conductive type epitaxial layer 102 away from the first conductive type substrate 101. It can be understood that the first Schottky contact layer 108 is formed by the first metal layer 1081 and the first conductive type epitaxial layer 102.

[0056] Therefore, the structure of a Schottky diode is integrated in the semiconductor device structure of the present invention, wherein the first Schottky contact layer 108 serves as the anode metal electrode of the Schottky diode, and the drain metal layer 1010 serves as the cathode metal electrode of the Schottky diode, thereby improving the reverse characteristics and recovery characteristics of the parasitic diode in the semiconductor device structure, reducing electromagnetic interference, and improving the efficiency and reliability of the system, thereby achieving the effect of energy saving and consumption reduction.

[0057] In addition, since the Schottky diode is integrated into the semiconductor device structure, on the one hand, it can reduce the gate-drain charge of the semiconductor device structure, improve the switching speed of the semiconductor device structure, and reduce switching losses; on the other hand, it can reduce the gate-drain charge, reduce gate jitter, and improve the efficiency and reliability of the semiconductor device structure; on the third hand, it can effectively save silicon surface area, reduce the raw material cost of the semiconductor device structure, and simplify the preparation process.

[0058] like Figure 2The structure schematic diagram of the semiconductor device structure of the second embodiment provided by the present invention is shown. Compared with the semiconductor device structure of the first embodiment, the difference of this embodiment is that, in this embodiment, the semiconductor device structure also includes a second Schottky contact layer 109, and the second Schottky contact layer 109 is located on the side of the gate structure 105 away from the well region 103 of the second conductivity type, and is located in the epitaxial layer 102 of the first conductivity type. It can be understood that the second Schottky contact layer 109 is formed by the second metal layer 1091 and the epitaxial layer 102 of the first conductivity type. It should be noted that the material of the second metal layer can refer to the first metal layer 1081, and the material of the second metal layer 1091 and the material of the first metal layer 1081 can be the same or different.

[0059] In order to ensure better anti-interference capability, voltage resistance consistency and stable performance of the semiconductor device structure, in one embodiment, the central axis of the second Schottky contact layer 109 coincides with the central axis of the first Schottky contact layer 108 .

[0060] like Figure 3 FIG. 1 is a schematic structural diagram of a semiconductor device structure according to a third embodiment of the present invention. In this embodiment, the first Schottky contact layer 108 is located in the epitaxial layer 102 of the first conductivity type.

[0061] In this embodiment, the first Schottky contact layer 108 is bonded to the source metal layer 107 .

[0062] In this embodiment, the material, thickness, etc. of the first metal layer 1081 in the first Schottky contact layer 108 can refer to the semiconductor device structure of the first embodiment.

[0063] like Figure 4 Shown is a schematic structural diagram of a semiconductor device structure of a fourth embodiment provided by the present invention. Compared with the semiconductor device structure of the third embodiment, this embodiment is different in that, in this embodiment, the semiconductor device structure also includes a second Schottky contact layer 109, which is located in the first conductive type epitaxial layer 102.

[0064] In this embodiment, the material, thickness, etc. of the second metal layer 1091 in the second Schottky contact layer 109 can refer to the semiconductor device structure of the third embodiment.

[0065] The present invention also provides a method for preparing the semiconductor device structure as described above, comprising the following steps:

[0066] S1, providing a substrate 101 of a first conductivity type;

[0067] S2, forming an epitaxial layer 102 of the first conductivity type on any surface of the substrate 101 of the first conductivity type;

[0068] S3, forming a gate structure 105 on a surface of the first conductivity type epitaxial layer 102 away from the first conductivity type substrate 101;

[0069] S4, forming a well region 103 of a second conductivity type in the epitaxial layer 102 of the first conductivity type;

[0070] S5, forming a source region 104 of the first conductivity type in the well region 103 of the second conductivity type;

[0071] S6, forming a first Schottky contact layer 108 on a side of the gate structure 105 away from the second conductivity type well region 103, on a surface of the first conductivity type epitaxial layer 102 away from the first conductivity type substrate 101 or in the first conductivity type epitaxial layer 102; and

[0072] S7, forming a source metal layer 107 and a drain metal layer 1010; the source metal layer 107 contacts the first conductive type source region 104, the second conductive type well region 103 and the first Schottky contact layer 108; the drain metal layer 1010 is covered on the surface of the first conductive type substrate 101 away from the first conductive type epitaxial layer 102.

[0073] In step S1, the first conductive type substrate 101 can be formed based on a silicon substrate. In one embodiment, providing the first conductive type substrate 101 includes: performing N-type doping on the silicon substrate to obtain an N-type substrate; or performing P-type doping on the silicon substrate to obtain a P-type substrate.

[0074] In step S2 , the first conductivity type epitaxial layer 102 may be formed by an epitaxial growth method such as chemical vapor deposition. During the epitaxial growth, the resistivity of the first conductivity type epitaxial layer 102 may be controlled by controlling the doping dose.

[0075] In step S3, the step of forming a gate structure 105 on the surface of the first conductive type epitaxial layer 102 away from the first conductive type substrate 101 includes: sequentially forming a gate oxide material layer and a polysilicon material layer on the surface of the first conductive type epitaxial layer 102 away from the first conductive type substrate 101, and etching the gate oxide material layer and the polysilicon material layer to obtain a gate structure 105 including a gate oxide layer 1051 and a polysilicon layer 1052.

[0076] Before step S4, the method further includes the following steps: using a patterned mask layer to define a first Schottky contact layer 108 region and a second conductivity type well region 103 region.

[0077] In step S4, the step of forming a second conductivity type well region 103 in the first conductivity type epitaxial layer 102 includes: according to the defined second conductivity type well region 103 area, injecting second conductivity type impurities into the first conductivity type epitaxial layer 102 that is not covered by the gate region pattern and is not defined as a Schottky contact area, and forming the second conductivity type well region 103 through annealing.

[0078] It can be understood that when the second conductivity type is P type, in one embodiment, the impurities include at least one of phosphine (PH3) or phosphorus trichloride (PCl3); when the second conductivity type is N type, the impurities include at least one of diborane (B2H6) or boron trichloride (BCl3).

[0079] It should be noted that the doping concentration of the second conductivity type impurities depends on the withstand voltage and the turn-on voltage of the semiconductor device structure.

[0080] Step S5 specifically includes the following steps: defining the shape of the source region by a mask process, then injecting impurities of the first conductivity type, and performing annealing to form the source region 104 of the first conductivity type.

[0081] In one embodiment, after step S5, the following steps are also included: forming an insulating layer 106 on the surface of the gate structure 105 away from the first conductive type epitaxial layer 102, and on the surface of a portion of the source region away from the first conductive type epitaxial layer 102, and providing a gate electrode layer on the insulating layer 106 that penetrates the first conductive type epitaxial layer 102; the material of the insulating layer 106 includes at least one of silicon dioxide or silicon nitride, and the insulating layer 106 is made by methods such as chemical vapor deposition.

[0082] The step of providing a gate electrode layer on the insulating layer 106 that penetrates the first conductivity type epitaxial layer 102 includes: depositing an oxide layer on the surface of the insulating layer 106 away from the gate structure 105, and then performing photolithography and etching contact holes based on a defined contact hole pattern to form a gate electrode layer.

[0083] In step S6, the first metal layer 1081 of the first Schottky contact layer 108 and the source metal layer 107 can be formed simultaneously by depositing metal, or the metal can be first deposited to form the first metal layer 1081 of the first Schottky contact layer 108, and then the metal can be deposited to form the source metal layer 107. In one embodiment, the material of the first metal layer 1081 in the first Schottky contact layer 108 includes at least one of aluminum, titanium, titanium nitride or tungsten.

[0084] In one embodiment, the step of forming the Schottky contact layer includes: depositing metal tungsten, titanium nitride and metal titanium in sequence in the first Schottky contact layer 108 region according to the defined first Schottky contact layer 108 region to form a first metal layer 1081 .

[0085] In step S7 , the source metal layer 107 and the drain metal layer 1010 can be made by methods such as metal material deposition.

[0086] In one embodiment, the method for preparing a semiconductor device structure further includes the following steps: forming a second Schottky contact layer 109 in the first conductivity type epitaxial layer 102 on a side of the gate structure 105 away from the second conductivity type well region 103 .

[0087] The present invention is further described in detail below in conjunction with specific examples and comparative examples. It is understood that the instruments and raw materials used in the following examples are relatively specific and may not be limited thereto in other specific examples.

[0088] Example 1

[0089] Embodiment 1 provides a semiconductor device structure, including a unit cell array composed of a plurality of unit cells 10 arranged in parallel in a strip shape, each unit cell 10 including:

[0090] N+ type substrate 101;

[0091] N-type epitaxial layer 102, located on the surface of N+ type substrate 101;

[0092] The gate structure 105 is located on the surface of the N-type epitaxial layer 102 away from the N+ type substrate 101. There are two gate structures 105, which are symmetrically distributed on both sides of the central axis of the single unit cell 10. Each gate structure 105 includes a stacked gate oxide layer 1051 and a polysilicon layer 1052. The gate oxide layer 1051 is located on the surface of the N-type epitaxial layer 102 away from the N+ type substrate 101, and the polysilicon layer 1052 is located on the surface of the gate oxide layer 1051 away from the N-type epitaxial layer 102.

[0093] An insulating layer 106 , located on a surface of the gate structure 105 away from the N-type epitaxial layer 102 ;

[0094] A gate electrode layer, penetrating the insulating layer 106 and connected to the polysilicon layer 1052 in the gate structure 105;

[0095] P-type well regions, there are two P-type well regions, both of which are located in the N-type epitaxial layer 102 and extend from one side of the gate structure 105 to below the gate structure 105;

[0096] An N+ type source region is located in the P type well region; the N+ type source region is located outside the gate structure 105;

[0097] The first Schottky contact layer 108 is located between the two gate structures 105 and on the surface of the N-type epitaxial layer 102 away from the N+ substrate 101. The first Schottky contact layer 108 is formed by the first metal layer 1081 and the N-type epitaxial layer 102. The first metal layer 1081 includes a tungsten connection layer, a titanium nitride barrier layer and a titanium bonding layer stacked in sequence, and the titanium bonding layer is bonded to the N-type epitaxial layer 102;

[0098] The source metal layer 107 contacts the N+ type source region, the P type well region and the tungsten connection layer in the first Schottky contact layer 108; and

[0099] The drain metal layer 1010 is disposed on a surface of the N+ type substrate 101 away from the N− type epitaxial layer 102 .

[0100] Example 2

[0101] The semiconductor device structure provided in Example 2 refers to Example 1, except that the single cell 10 also includes a second Schottky contact layer 109, and the second Schottky contact layer 109 is arranged in the N-type epitaxial layer 102. The second Schottky contact layer 109 is formed by the second metal layer 1091 and the N-type epitaxial layer 102, and the central axis of the second Schottky contact layer 109 coincides with the central axis of the first Schottky contact layer 108.

[0102] Example 3

[0103] The structure of the semiconductor device provided in Example 3 is similar to that in Example 1, except that the first Schottky contact layer 108 is disposed in the N-type epitaxial layer 102 .

[0104] Example 4

[0105] The structure of the semiconductor device provided in Example 4 is similar to that in Example 2, except that the first Schottky contact layer 108 is disposed in the N-type epitaxial layer 102 .

[0106] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor device structure, characterized in that: include: The semiconductor device structure includes a unit cell array composed of at least one unit cell, wherein the unit cell includes a substrate of a first conductivity type, an epitaxial layer of a first conductivity type, a gate structure, a well region of a second conductivity type, a source region of a first conductivity type, a first Schottky contact layer, a second Schottky contact layer, a source metal layer, and a drain metal layer; There are two gate structures, which are symmetrically distributed on both sides of the central axis of the single unit cell; the source region of the first conductivity type is located outside the gate structure, and the first Schottky contact layer is located between the two gate structures; The epitaxial layer of the first conductivity type is located on the surface of the substrate of the first conductivity type; The gate structure is located on a surface of the epitaxial layer of the first conductivity type away from the substrate of the first conductivity type; The well region of the second conductivity type is located in the epitaxial layer of the first conductivity type and extends from one side of the gate structure to below the gate structure; the second conductivity type is different from the first conductivity type; The source region of the first conductivity type is located in the well region of the second conductivity type; The first Schottky contact layer is located on a side of the gate structure away from the well region of the second conductivity type, and is located on a surface of the epitaxial layer of the first conductivity type away from the substrate of the first conductivity type or is located in the epitaxial layer of the first conductivity type; The second Schottky contact layer is located at a side of the gate structure away from the well region of the second conductivity type and is located in the epitaxial layer of the first conductivity type; The source metal layer is in contact with the source region of the first conductivity type, the well region of the second conductivity type, and the first Schottky contact layer; and The drain metal layer is disposed on a surface of the first conductive type substrate away from the first conductive type epitaxial layer.

2. The semiconductor device structure according to claim 1, characterized in that: The central axis of the second Schottky contact layer coincides with the central axis of the first Schottky contact layer.

3. The semiconductor device structure according to claim 1 or 2, characterized in that: The gate structure includes a gate oxide layer and a polysilicon layer stacked together. The gate oxide layer is located on a surface of the first conductivity type epitaxial layer away from the first conductivity type substrate, and the polysilicon layer is located on a surface of the gate oxide layer away from the first conductivity type epitaxial layer.

4. The semiconductor device structure according to claim 3, characterized in that: The semiconductor device structure further includes: an insulating layer, located on a surface of the gate structure away from the epitaxial layer of the first conductivity type, A gate electrode layer penetrates the insulating layer and is connected to the polysilicon layer in the gate structure.

5. The semiconductor device structure according to claim 4, characterized in that: The unit cell array includes more than two unit cells, and each unit cell has the same structure.

6. A method for preparing a semiconductor device structure according to any one of claims 1 to 5, characterized in that: The following steps are involved: providing a substrate of a first conductivity type; forming an epitaxial layer of the first conductivity type on any surface of the substrate of the first conductivity type; forming a gate structure on a surface of the epitaxial layer of the first conductivity type away from the substrate of the first conductivity type; forming a well region of a second conductivity type in the epitaxial layer of the first conductivity type; forming a source region of the first conductivity type in the well region of the second conductivity type; A first Schottky contact layer is formed on a surface of the epitaxial layer of the first conductivity type away from the substrate of the first conductivity type or in the epitaxial layer of the first conductivity type on a side of the gate structure away from the well region of the second conductivity type; as well as forming a source metal layer and a drain metal layer; the source metal layer is in contact with the source region of the first conductivity type, the well region of the second conductivity type and the first Schottky contact layer; The drain metal layer covers a surface of the first conductive type substrate away from the first conductive type epitaxial layer.

7. The method for preparing a semiconductor device structure according to claim 6, characterized in that: The following steps are also included: A second Schottky contact layer is formed in the epitaxial layer of the first conductivity type on a side of the gate structure away from the well region of the second conductivity type.

8. The method for preparing a semiconductor device structure according to claim 6, characterized in that: The step of forming a gate structure on the surface of the first conductive type epitaxial layer away from the first conductive type substrate includes: sequentially forming a gate oxide material layer and a polysilicon material layer on the surface of the first conductive type epitaxial layer away from the first conductive type substrate, and etching the gate oxide material layer and the polysilicon material layer to obtain a gate structure including a gate oxide layer and a polysilicon layer.

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