NAND Flash Memory Device and Method of Manufacturing the Same

Abstract

The present invention provides a method for manufacturing a NAND flash memory, comprising: providing a substrate, and forming at least two floating gate layers on the substrate, with an opening provided between adjacent floating gate layers, a first sidewall being formed on the floating gate layer, the first sidewall covering the sidewalls and the top of the floating gate layer; forming a control gate material layer, the control gate material layer filling the opening and covering the first sidewall; performing an etching process on the control gate material layer to form a control gate layer, and floating gate layer residues being formed at the floating gate layer; performing an atomic layer deposition oxidation process to form a first oxide layer, the first oxide layer covering the control gate layer and the opening; performing a rapid thermal oxidation process to form a second oxide layer, and the process gas of the rapid thermal oxidation process penetrating the first oxide layer to remove the floating gate layer residues. The problem that the residues of the floating gate cause short circuit and leakage between adjacent floating gates during the control gate etching process is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a NAND flash memory device and a manufacturing method thereof. Background Art

[0002] NAND flash memory is a storage device better than a hard disk drive. With the pursuit of non-volatile storage products with low power consumption, light weight, and good performance by people, it has been widely used in electronic products.

[0003] During the etching process of the control gate of NAND FLASH, since the floating gate (FG) is surrounded by silicon oxide - silicon nitride - silicon oxide (ONO). The material of the floating gate is polysilicon, and the etching rate of silicon oxide - silicon nitride - silicon oxide is different from that of polysilicon, a silicon oxide - silicon nitride - silicon oxide fence will be formed on the side of the floating gate, and residues of the floating gate will be formed on the lower side of the silicon oxide - silicon nitride - silicon oxide. The residues of the floating gate will cause short - circuit and leakage between adjacent floating gates. Summary of the Invention

[0004] The purpose of the present invention is to provide a NAND flash memory device and a manufacturing method thereof to solve the problem that residues of the floating gate cause short - circuit and leakage between adjacent floating gates during the etching process of the control gate.

[0005] To solve the above - mentioned technical problems, the present invention provides a manufacturing method of a NAND flash memory, including:

[0006] Providing a substrate, and forming at least two floating gate layers on the substrate, with openings provided between adjacent floating gate layers, a first sidewall is formed on the floating gate layer, and the first sidewall covers the sidewall and the top of the floating gate layer;

[0007] Forming a control gate material layer, the control gate material layer filling the opening and covering the first sidewall;

[0008] Performing an etching process on the control gate material layer to form a control gate layer, and residues of the floating gate layer are formed at the floating gate layer;

[0009] Performing an atomic layer deposition oxidation process to form a first oxide layer, the first oxide layer covering the control gate layer and the opening;

[0010] Performing a rapid thermal oxidation process to form a second oxide layer, and the process gas of the rapid thermal oxidation process penetrates the first oxide layer to remove the residues of the floating gate layer.

[0011] Optionally, the material of the floating gate layer is polysilicon.

[0012] Optionally, in the rapid thermal oxidation process, the process gas includes oxygen, and the oxygen reacts with the floating gate layer residue to form a silicon oxide layer.

[0013] Optionally, the thickness of the floating gate layer residue removed in the rapid thermal oxidation process does not exceed 1 nanometer.

[0014] Optionally, the process temperature of the rapid thermal oxidation process is 850°C - 950°C.

[0015] Optionally, the thickness of the first oxide layer formed by the atomic layer deposition oxidation process is 10 Å - 40 Å.

[0016] Optionally, before the etching process of the control gate material layer, a hard mask layer is further formed on the control gate material layer.

[0017] Optionally, before the etching process of the control gate material layer, a patterned photoresist is formed on the hard mask layer.

[0018] Optionally, the dry etching process is used for the etching process of the control gate material layer.

[0019] Based on the same inventive concept, the present invention further provides a NAND flash memory device, including:

[0020] A substrate, on which at least two floating gate layers are formed, an opening is provided between adjacent floating gate layers, a first sidewall is formed on the floating gate layer, and the first sidewall covers the top of the floating gate layer;

[0021] A control gate layer, which is located above the first sidewall;

[0022] A first oxide layer, which covers the control gate layer;

[0023] A second oxide layer, which is formed by rapid thermal oxidation of the floating gate layer residue and oxygen, and the second oxide layer covers the first oxide layer.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] In a NAND flash memory device and a manufacturing method of a NAND flash memory provided by the present invention, when an etching process is performed on a control gate material layer to form a control gate layer, a floating gate layer residue is formed at the floating gate layer. An atomic layer deposition oxidation process is used to form a first oxide layer, and the first oxide layer covers the control gate layer and the opening. Through a rapid thermal oxidation process, the process gas of the rapid thermal oxidation process penetrates the first oxide layer to remove the floating gate layer residue, the control gate layer is the control gate, and the floating gate layer is the floating gate; thus, the problem of short circuit and leakage between adjacent floating gates caused by the residue of the floating gate during the control gate etching process can be solved. Description of the Drawings

[0026] Figure 1 is a flowchart of a method for manufacturing a NAND flash memory according to an embodiment of the present invention;

[0027] Figures 2 - 5 is a schematic cross-sectional view of a structure formed in the method for manufacturing a NAND flash memory according to an embodiment of the present invention;

[0028] In the figure,

[0029] 100 - substrate; 101 - gate oxide layer; 102 - floating gate layer; 103 - first sidewall; 104 - control gate material layer, 104a - control gate layer; 105 - second hard mask layer; 106 - second patterned photoresist; 107 - floating gate layer residue; 108 - first oxide layer; 109 - second oxide layer. Detailed implementation manners

[0030] The following further describes in detail a NAND flash memory device and a method for manufacturing a NAND flash memory proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description and the claims, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0031] Specifically, please refer to Figure 1 , Figure 1 is a flowchart of a method for manufacturing a NAND flash memory according to an embodiment of the present invention. As Figure 1 shown, the present embodiment provides a method for manufacturing a NAND flash memory, including:

[0032] Step S10: Provide a substrate, and form at least two floating gate layers on the substrate, with openings provided between adjacent floating gate layers, and form a first sidewall on the floating gate layers, and the first sidewall covers the sidewalls and the top of the floating gate layers.

[0033] Step S20: Form a control gate material layer, and the control gate material layer fills the openings and covers the first sidewall;

[0034] Step S30: Perform an etching process on the control gate material layer to form a control gate layer, and floating gate layer residues are formed at the floating gate layers;

[0035] Step S40: Perform an atomic layer deposition oxidation process to form a first oxide layer, and the first oxide layer covers the control gate layer and the openings;

[0036] Step S50: Perform a rapid thermal oxidation process to form a second oxide layer, and the process gas of the rapid thermal oxidation process penetrates the first oxide layer to remove the floating gate layer residues.

[0037] Figures 2 - 5 It is a schematic cross-sectional view of a structure formed in the manufacturing method of the NAND flash memory according to an embodiment of the present invention; hereinafter, the manufacturing method of the NAND flash memory provided in this embodiment will be described in more detail with reference to the accompanying Figures 2 - 5 drawings.

[0038] First, perform step S10, as Figure 2 shown, provide a substrate 100. The substrate 100 can be single-crystalline silicon or polycrystalline silicon, or can also be a semiconductor material such as silicon, germanium, silicon germanide, gallium arsenide, etc., and can also be a composite structure such as silicon-on-insulator. Those skilled in the art can select the type of the semiconductor substrate 100 according to the semiconductor devices formed on the semiconductor substrate 100. Therefore, the type of the semiconductor substrate 100 should not limit the protection scope of the present invention. At least two floating gate layers 102 are formed on the substrate 100, and an opening (not shown in the figure) is provided between adjacent floating gate layers 102. A first sidewall 103 is formed on the floating gate layer 102, and the first sidewall 103 covers the sidewalls and the top of the floating gate layer 102.

[0039] Before forming the floating gate layer 102, first form a gate oxide layer 101 on the substrate 100, and the gate oxide layer 101 can be formed by a thermal oxidation process. A floating gate layer material layer is formed on the gate oxide layer 101, and a first hard mask layer (not shown in the figure) is deposited on the floating gate layer material layer. The first hard mask layer is, for example, silicon nitride and can be deposited by chemical vapor deposition. A patterned photoresist layer is formed on the first hard mask layer. Using the patterned photoresist layer as a mask, etch the first hard mask layer to form a first patterned hard mask layer; the first patterned hard mask layer and the first patterned photoresist layer form a mask pattern. Using the first patterned hard mask layer and the first patterned photoresist layer together as a mask, etch the floating gate layer material layer to form an opening in the floating gate layer material layer, and etch the floating gate layer material layer into the floating gate layer 102. After the step of forming the floating gate layer, if the first patterned photoresist has not been completely consumed, a photoresist removal process is also required, and usually an ashing process or a stripping method is used to remove the remaining first patterned photoresist. Deposit the first sidewall 103 on the top and sidewalls of the floating gate layer 102, which can be formed by chemical vapor deposition. In this embodiment, the first sidewall 103 is, for example, an ONO stack, that is, a silicon oxide - silicon nitride - silicon oxide layer. The floating gate layer 102 is a floating gate.

[0040] Next, perform step S20, as Figure 2As shown, a control gate material layer 104 is formed. The control gate material layer 104 fills the opening and covers the first sidewall 103. The control gate material layer 104 is, for example, polysilicon, and the control gate material layer 104 can be formed by chemical vapor deposition.

[0041] After step S20 and before step S30, a second hard mask layer 105 and a second patterned photoresist 106 are further formed on the control gate material layer 104. The second hard mask layer 105 is, for example, silicon nitride and can be deposited by chemical vapor deposition. A second patterned photoresist layer 106 is formed on the second hard mask layer 105.

[0042] Next, step S30 is performed. As Figure 3 shown, an etching process is performed on the control gate material layer 104 to form a control gate layer 104a, and a floating gate layer residue 107 is formed at the floating gate layer 102.

[0043] In step S30, using the second patterned photoresist layer 106 as a mask, the second hard mask layer 105 is etched to form a second patterned hard mask layer 105a; the second patterned hard mask layer 105a and the second patterned photoresist layer 106 form a mask pattern. Using the second patterned hard mask layer 105a and the second patterned photoresist layer 106 together as a mask, the control gate material layer 104 is etched to form a control gate layer 104a. After the step of forming the control gate layer 104a, if the second patterned photoresist 106 has not been completely consumed, a photoresist removal process is also required, and usually an ashing process or a stripping method is used to remove the remaining second patterned photoresist 106.

[0044] The etching process is, for example, a dry etching process. During the etching of the control gate material layer 104, since the floating gate layer 102 is surrounded by the first sidewall 103. The material of the first sidewall 103 is, for example, ONO, and the material of the floating gate layer 102 is, for example, polysilicon. The etching rate of ONO is different from that of poly, so a fence of ONO will be formed on the side of the floating gate layer 102, and a floating gate layer residue 107 will be formed under the side of ONO. In this embodiment, the control gate layer 104a is the control gate.

[0045] Next, step S40 is performed. As Figure 4 shown, an atomic layer deposition (ALD) oxidation process is performed to form a first oxide layer 108, and the first oxide layer 108 covers the control gate layer 104a; the thickness of the first oxide layer 108 formed by the atomic layer deposition oxidation process is, for example, 10 angstroms - 40 angstroms.

[0046] Next, step S50 is performed. AsFigure 5 As shown, a rapid thermal oxidation (RTO) process is performed to form a second oxide layer 109. The rapid thermal oxidation process penetrates the first oxide layer 108 to remove the floating gate layer residue 107.

[0047] In this embodiment, the process temperature of the rapid thermal oxidation process is, for example, 850°C - 950°C. The process gas in the rapid thermal oxidation process includes oxygen. The oxygen reacts with the floating gate layer residue 107 to form the second oxide layer 109. The floating gate layer residue 107 is composed of polysilicon. That is to say, the oxygen in the rapid thermal oxidation process passes through the first oxide layer 108 and reacts with the floating gate layer residue 107 to form the second oxide layer 109, so as to remove the floating gate layer residue 107, avoiding the short circuit and leakage phenomena caused by the floating gate layer residue 107 between adjacent floating gate layers. The thickness of the floating gate layer 102 removed in the rapid thermal oxidation process does not exceed 1 nanometer. The first oxide layer 108 can control the reaction amount of the oxygen in the rapid thermal oxidation process with the floating gate layer residue 107, preventing the oxygen from continuing to react with the floating gate layer 102. The second oxide layer 109 formed by the rapid thermal oxidation process is denser, improving the performance of the NAND flash memory device. The first oxide layer 108 and the second oxide layer 109 form the sidewall of the control gate layer 104a.

[0048] Continue to refer to Figure 5 , based on the same inventive concept, this embodiment also provides a NAND flash memory device, including:

[0049] A substrate 100, on which at least two floating gate layers 102 are formed. An opening is provided between adjacent floating gate layers 102. A first sidewall 103 is formed on the floating gate layer 102, and the first sidewall 103 covers the top of the floating gate layer 102;

[0050] A control gate layer 104a, which is located above the first sidewall 103;

[0051] A first oxide layer 108, which covers the control gate layer 104a;

[0052] A second oxide layer 109, which is formed by rapid thermal oxidation of the floating gate layer residue and oxygen, and the second oxide layer 109 covers the first oxide layer 108.

[0053] In this embodiment, the floating gate layer 102 is a floating gate, the control gate layer 104a is a control gate, and the first oxide layer 108 and the second oxide layer 109 form the sidewall of the control gate layer 104a.

[0054] In summary, in the NAND flash memory device and the manufacturing method of the NAND flash memory provided in the embodiments of the present invention, when forming the control gate layer by etching the control gate material layer, floating gate layer residues are formed at the floating gate layer. An atomic layer deposition oxidation process is used to form a first oxide layer, and the first oxide layer covers the control gate layer. Through a rapid thermal oxidation process, the process gas of the rapid thermal oxidation process penetrates the first oxide layer to remove the floating gate layer residues. The control gate layer is the control gate, and the floating gate layer is the floating gate. Therefore, the problem of short circuit and leakage between adjacent floating gates caused by the residues of the floating gate during the control gate etching process can be solved.

[0055] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing a NAND flash memory, characterized in that, Comprising: A substrate is provided, and at least two floating gate layers are formed on the substrate. An opening is provided between adjacent floating gate layers. A first sidewall is formed on the floating gate layer, and the first sidewall covers the sidewalls and the top of the floating gate layer; A control gate material layer is formed, and the control gate material layer fills the opening and covers the first sidewall; An etching process is performed on the control gate material layer to form a control gate layer, and floating gate layer residues are formed at the floating gate layer; An atomic layer deposition oxidation process is performed to form a first oxide layer, and the first oxide layer covers the control gate layer and the opening; A rapid thermal oxidation process is performed to form a second oxide layer, and the process gas of the rapid thermal oxidation process penetrates the first oxide layer to remove the floating gate layer residues.

2. The manufacturing method of the NAND flash memory according to claim 1, wherein The material of the floating gate layer is polysilicon.

3. The manufacturing method of the NAND flash memory according to claim 1, characterized in that, In the rapid thermal oxidation process, the process gas includes oxygen, and the oxygen reacts with the floating gate layer residues to form the second oxide layer.

4. The manufacturing method of the NAND flash memory according to claim 1, characterized in that, The thickness of the floating gate layer residues removed in the rapid thermal oxidation process does not exceed 1 nanometer.

5. The manufacturing method of the NAND flash memory according to claim 1, characterized in that The process temperature of the rapid thermal oxidation process is 850°C - 950°C.

6. The manufacturing method of the NAND flash memory according to claim 1, characterized in that, The thickness of the first oxide layer formed by the atomic layer deposition oxidation process is 10 Å - 40 Å.

7. The manufacturing method of the NAND flash memory according to claim 1, wherein, Before the etching process is performed on the control gate material layer, a hard mask layer is further formed on the control gate material layer.

8. The manufacturing method of the NAND flash memory according to claim 7, characterized in that, Before the etching process is performed on the control gate material layer, a patterned photoresist is formed on the hard mask layer.

9. The manufacturing method of the NAND flash memory according to claim 1, wherein The etching process performed on the control gate material layer uses a dry etching process.

10. A NAND flash memory device, characterized in that, Comprising: A substrate, at least two floating gate layers are formed on the substrate. An opening is provided between adjacent floating gate layers. A first sidewall is formed on the floating gate layer, and the first sidewall covers the top of the floating gate layer; A control gate layer, the control gate layer is located above the first sidewall; A first oxide layer, the first oxide layer covers the control gate layer and the opening; A second oxide layer, formed by rapid thermal oxidation of floating gate layer residues and oxygen, and the second oxide layer covers the first oxide layer.

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