Solar cell unit and method for manufacturing the same

Abstract

A solar cell unit and a method for manufacturing the solar cell unit are provided. The solar cell unit comprises: a silicon substrate; a passivation dielectric layer disposed on the silicon substrate; a first silicon layer, a second silicon layer and a third silicon layer disposed sequentially on the surface of the passivation dielectric layer facing away from the silicon substrate and in contact with each other; and a metal contact electrode passing through the third silicon layer and the second silicon layer and directly contacting the first silicon layer.

Description

Technical Field

[0001] The present disclosure relates to a solar cell unit and a method for manufacturing the solar cell unit. Background Art

[0002] Human survival and development are inseparable from energy. Solar energy is one of the most advantageous renewable, large-volume, and clean energy sources. Crystalline silicon solar cells are semiconductor devices that convert light energy directly into electrical energy. High photoelectric conversion rate and low cost of use are what humans desire for crystalline silicon solar cells. High-efficiency solar cells must have good surface passivation and low surface recombination rate, so as to obtain higher open circuit voltage, short circuit current, and conversion efficiency. At present, surface passivation is mainly achieved through single-layer or multi-layer dielectric film structures. However, after surface passivation, metallization is still required. For example, metallization is achieved by printing metal contact electrodes on dielectric film structures. In this case, the metal contact electrode is inevitably damaged when the dielectric film structure under the printed metal contact electrode is formed, resulting in a relatively large surface recombination rate in the metal contact area, thereby reducing the open circuit voltage of the battery.

[0003] A passivated contact solar cell is proposed, which includes an ultra-thin oxide layer and a doped silicon film layer on the oxide layer. The cell can achieve good passivation while reducing the surface contact recombination caused by metal contact, effectively improving the open circuit voltage and cell conversion efficiency of the cell. However, there is still a need to further improve the open circuit voltage and cell conversion efficiency of the cell. Summary of the invention

[0004] At least some embodiments of the present disclosure provide a solar cell unit, comprising: a silicon substrate; a passivation dielectric layer disposed on the silicon substrate; a first silicon layer, a second silicon layer, and a third silicon layer, which are sequentially disposed on a surface of the passivation dielectric layer facing away from the silicon substrate and in contact with each other; and a metal contact electrode, which passes through the third silicon layer and the second silicon layer and is in direct contact with the first silicon layer.

[0005] For example, in some embodiments, the first silicon layer is a doped polycrystalline silicon layer, the second silicon layer is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, the third silicon layer is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and the first silicon layer and the third silicon layer have the same doping type, which is n-type or p-type.

[0006] For example, in some embodiments, the metal contact electrode is also in direct contact with a surface of the third silicon layer facing away from the second silicon layer.

[0007] For example, in some embodiments, the doping concentration of the first silicon layer is 1*10 20 Up to 1*1021 Number of atoms / cm 3 The doping concentration of the third silicon layer is within the range of 5*10 18 Up to 5*10 20 Number of atoms / cm 3 within the range.

[0008] For example, in some embodiments, the first silicon layer is a crystallized polysilicon layer.

[0009] For example, in some embodiments, the passivation dielectric layer includes a single layer or a stack of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride, and silicon nitride.

[0010] For example, in some embodiments, the thickness of the first silicon layer is in the range of 10-300 nm, the thickness of the second silicon layer is in the range of 1-100 nm, and the thickness of the third silicon layer is in the range of 1-100 nm.

[0011] For example, in some embodiments, the transparent conductive layer includes a metal oxide having a doping element or a metal nitride having a doping element.

[0012] For example, in some embodiments, the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide, and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum, and fluorine.

[0013] At least some embodiments of the present disclosure provide a method for manufacturing a solar cell unit, comprising: providing a silicon substrate; forming a passivation dielectric layer on a surface of the silicon substrate; sequentially forming a first silicon layer, a second silicon layer, and a third silicon layer on a surface of the passivation dielectric layer facing away from the silicon substrate, wherein the first silicon layer, the second silicon layer, and the third silicon layer are in contact with each other; and forming a metal contact electrode, the metal contact electrode passing through the third silicon layer and the second silicon layer and directly contacting the first silicon layer.

[0014] For example, in some embodiments, the first silicon layer is a doped polycrystalline silicon layer. Forming the first silicon layer includes: forming a first pre-layer, the first pre-layer including a single layer or a stack of one or more of a microcrystalline silicon layer, an amorphous silicon layer, and polycrystalline silicon with doped atoms; and performing a high temperature annealing heat treatment to activate the doped atoms and crystallize the first pre-layer to transform it into the first silicon layer.

[0015] For example, in some embodiments, the first pre-layer further includes a single layer or a stacked layer of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and polycrystalline silicon.

[0016] For example, in some embodiments, forming a metal contact electrode includes: patterning the second silicon layer and the third silicon layer to remove a portion of the second silicon layer and the third silicon layer; and forming a metal contact electrode at the area where the second silicon layer and the third silicon layer are removed, so that the metal contact electrode passes through the third silicon layer and the second silicon layer and is in direct contact with the first silicon layer.

[0017] For example, in some embodiments, the second silicon layer is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, the third silicon layer is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and the first silicon layer and the third silicon layer have the same doping type, which is n-type or p-type.

[0018] For example, in some embodiments, the passivation dielectric layer includes a single layer or a stack of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride, and silicon nitride.

[0019] For example, in some embodiments, the transparent conductive layer includes a metal oxide or a metal nitride having a doping element, and the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide, and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum, and fluorine. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A partial structural schematic diagram of a solar cell unit according to an embodiment of the present disclosure is shown;

[0021] Figure 2 Shows Figure 1 A schematic plan view of a solar cell unit is shown;

[0022] Figure 3 A flow chart showing a method for manufacturing a solar cell unit according to an embodiment of the present disclosure is shown;

[0023] Figure 4A-4H They are shown respectively with Figure 3 The schematic diagram of the structure corresponding to each step of the manufacturing method of the solar cell unit shown; and

[0024] Figure 5 A schematic plan view of a solar cell unit according to another embodiment of the present disclosure is shown.

[0025] Wherein, the accompanying drawings are marked as follows:

[0026] 1 Silicon substrate

[0027] 2 Passivation dielectric layer

[0028] 3 First silicon layer

[0029] 4 Second Silicon Layer

[0030] 5 Third Silicon Layer

[0031] 6 Metal contact electrode DETAILED DESCRIPTION

[0032] Hereinafter, a solar cell unit and a method for manufacturing the same according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] According to at least one embodiment of the present disclosure, a solar cell unit is provided, which may include: a silicon substrate; a passivation dielectric layer, which is arranged on the silicon substrate; a first silicon layer, a second silicon layer and a third silicon layer, which are sequentially arranged on the surface of the passivation dielectric layer facing away from the silicon substrate and are in direct contact with each other; and a metal contact electrode, which passes through the third silicon layer and the second silicon layer and is in direct contact with the first silicon layer.

[0034] The structural layers of the solar cell unit not only form a silicon thin film structure with a relatively high bandgap width, but also further improve the surface passivation performance of the solar cell and increase the open circuit voltage of the cell.

[0035] The metal contact electrode passes through the third silicon layer and the second silicon layer and directly contacts the heavily doped first silicon layer, thereby improving the fill factor and thus the conversion efficiency of the battery.

[0036] For example, the metal contact electrode is also in direct contact with the surface of the third silicon layer facing away from the second silicon layer.

[0037] For example, the silicon substrate may be an n-type or p-type silicon substrate. For example, the silicon substrate may be a single crystal silicon substrate or a polycrystalline silicon substrate. For example, the resistivity of the silicon substrate is in the range of 0.1-20Ω·cm, and the thickness thereof is in the range of 40-300μm.

[0038] For example, the first silicon layer is a doped polycrystalline silicon layer, which is subjected to high temperature annealing heat treatment and is therefore a crystallized polycrystalline silicon layer. For example, the second silicon layer is a single layer or stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer. For example, the third silicon layer is a single layer or stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer. The first silicon layer and the third silicon layer have the same doping type, which is n-type or p-type.

[0039] The second silicon layer and the third silicon layer have a wider bandgap than the first silicon layer. As an example, the bandgap of the second silicon layer and the third silicon layer is about 1.74 eV, and the bandgap of the first silicon layer is about 1.38 eV.

[0040] For example, the doping concentration of the first silicon layer is greater than the doping concentration of the third silicon layer. 20 Up to 1*10 21 Number of atoms / cm 3 The doping concentration of the third silicon layer is within the range of 5*10 18 Up to 5*10 20 Number of atoms / cm 3 within the range.

[0041] For example, the thickness of the first silicon layer is in the range of 10-300 nm, the thickness of the second silicon layer is in the range of 1-100 nm, and the thickness of the third silicon layer is in the range of 1-100 nm.

[0042] Herein, the term "polymorphic silicon" refers to silicon existing in a mixed form in a plurality of crystalline states, including, for example, amorphous silicon, nanocrystalline silicon and microcrystalline silicon mixed together, or amorphous silicon and microcrystalline silicon mixed together, or amorphous silicon and nanocrystalline silicon mixed together.

[0043] For example, the passivation dielectric layer includes a single layer or a stack of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride and silicon nitride. For example, the thickness of the passivation dielectric layer is in the range of 0.1-10 nm. For example, the passivation dielectric layer can be arranged on the backlight surface of the silicon substrate in the solar cell unit.

[0044] For example, in some embodiments, the solar cell unit may be a heterojunction cell, such as an n-type heterojunction cell having an n-type silicon substrate. For n-type heterojunction cells, reference may be made to the contents of Chapter 10, Section 10.1 of "Principles of Crystalline Silicon Solar Cell Manufacturing Process" compiled by Chen Zhegen and Zheng Zhidong (China Industry and Information Technology Publishing Group, Electronic Industry Press, 1st edition, March 2017), which is incorporated herein by reference. For example, the passivation dielectric layer may be disposed on the backlight surface of the silicon substrate in the n-type heterojunction cell.

[0045] According to at least one embodiment of the present disclosure, a method for manufacturing a solar cell unit is provided, which may include: providing a silicon substrate; forming a passivation dielectric layer on a surface of the silicon substrate; sequentially forming a first silicon layer, a second silicon layer, and a third silicon layer on a surface of the passivation dielectric layer facing away from the silicon substrate, wherein the first silicon layer, the second silicon layer, and the third silicon layer are in direct contact with each other; and forming a metal contact electrode, which passes through the third silicon layer and the second silicon layer and is in direct contact with the first silicon layer.

[0046] The method can be used to manufacture a solar cell unit as described above.

[0047] Specifically, forming the first silicon layer may include: forming a first prelayer, the first prelayer including a single layer or a stack of one or more of a microcrystalline silicon layer, an amorphous silicon layer and polycrystalline silicon with doped atoms; and performing a high temperature annealing heat treatment to activate the doping atoms and crystallize the first prelayer to transform it into a first silicon layer.

[0048] In addition, for example, the first pre-layer may also include a single layer or a stacked layer of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polycrystalline silicon layer.

[0049] In some embodiments, compared with the first pre-layer having only the doped portion, the first pre-layer having the doped portion and the undoped portion can form a film layer of the same thickness in a shorter time, for example, through a plasma enhanced chemical vapor deposition (PECVD) process, etc. Therefore, the production efficiency is improved. Here, the doped portion and the undoped portion of the first pre-layer will be doped and crystallized after the high temperature annealing heat treatment, so that the first pre-layer is completely transformed into a doped polysilicon layer.

[0050] For example, the method may also include surface treatment of the surface of the silicon substrate where the passivation dielectric layer is to be formed before forming the passivation dielectric layer, including first texturing the surface of the silicon substrate, then rounding the pyramids of the texturized surface, or further wet etching or polishing the surface.

[0051] For example, the passivation dielectric layer can be formed by a low-temperature furnace tube oxidation process, a nitric acid oxidation process, an ozone oxidation process, an atomic layer deposition (ALD) process (for example, including plasma enhanced atomic layer deposition (PEALD), plasma enhanced atomic layer deposition (PEALD), etc.), a chemical vapor deposition (CVD) process (for example, including plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), etc.), a physical vapor deposition (PVD) process (such as sputtering or evaporation), a reactive plasma deposition (RPD) process, etc.

[0052] For example, the first prelayer, the second silicon layer or the third silicon layer may be formed by plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD) processes.

[0053] For example, forming a metal contact electrode may include: patterning the second silicon layer and the third silicon layer to remove a portion of the second silicon layer and the third silicon layer; and forming a metal contact electrode at the area where the second silicon layer and the third silicon layer are removed, so that the metal contact electrode passes through the third silicon layer and the second silicon layer and is in direct contact with the first silicon layer.

[0054] For example, the second silicon layer and the third silicon layer may be chemically etched using a mask layer to pattern the second silicon layer and the third silicon layer, or the second silicon layer and the third silicon layer may be patterned using a laser. For example, a metal contact electrode may be formed at the area where the second silicon layer and the third silicon layer are removed by screen printing, electroplating, or a combination of the two.

[0055] It should be noted that the embodiments of the present disclosure only describe the structure on one surface of the silicon substrate. Such a structure can be arranged on the front side of the solar cell unit that receives light or on the back side opposite to the front side, and the present disclosure is not limited to this. The present disclosure does not limit the structure on the other surface of the silicon substrate. As an example, a doping layer with a doping type opposite to that of the first silicon layer, a passivation layer on the surface of the doping layer facing away from the silicon substrate, and a metal contact electrode that passes through the passivation layer and contacts the doping layer can be formed on the other surface of the silicon substrate. As an example, a heterojunction structure can be formed on the other surface of the silicon substrate.

[0056] Figure 1 FIG. 1 shows a partial structural schematic diagram of a solar cell unit according to an embodiment of the present disclosure. Figure 2 They are shown respectively Figure 1 A schematic plan view of a solar cell unit is shown.

[0057] like Figure 1 As shown, the solar cell unit includes: a silicon substrate 1; a passivation dielectric layer 2 arranged on a surface of the silicon substrate 1; a first silicon layer 3, a second silicon layer 4 and a third silicon layer 5 which are sequentially arranged on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 and in contact with each other; and a metal contact electrode 6, which passes through the third silicon layer 5 and the second silicon layer 4 and directly contacts the first silicon layer 3.

[0058] The solar cell unit has three silicon layers, which constitute a silicon thin film structure with a relatively high bandgap width, which not only further improves the surface passivation performance of the solar cell, but also improves the open circuit voltage of the cell.

[0059] In addition, the metal contact electrode 6 passes through the third silicon layer 5 and the second silicon layer 4 to directly contact the medium-doped first silicon layer 3. Therefore, the filling factor is improved, thereby improving the conversion efficiency of the battery.

[0060] Specifically, the silicon substrate 1 adopts an n-type single crystal silicon wafer with a resistivity of 0.1-20Ω·cm, the passivation dielectric layer 2 is a silicon dioxide layer with a thickness of 1.5nm, the first silicon layer 3 is a polycrystalline silicon layer doped with phosphorus (P) with a thickness of 70nm, the second silicon layer 4 is an intrinsic amorphous silicon layer with a thickness of 10nm, the third silicon layer 5 is a phosphorus-doped amorphous silicon layer with a thickness of 10nm, and the metal contact electrode 6 is, for example, a silver electrode, an aluminum electrode or a silver-aluminum electrode.

[0061] like Figure 2 As shown, the metal contact electrode 6 may include a plurality of first strip electrodes 61 extending in a first direction and a plurality of second strip electrodes 62 extending in a second direction perpendicular to the first direction, wherein the width of the second strip electrodes is greater than the width of the first strip electrodes. For example, the plurality of first strip electrodes 61 may be used as fine grids of a solar cell unit, and the plurality of second strip electrodes 62 may be used as main grids of a solar cell unit.

[0062] Figure 3 A flow chart showing a method for manufacturing a solar cell unit according to an embodiment of the present disclosure is shown; Figure 4A-4H They are shown respectively with Figure 3 The schematic diagram of the structure corresponding to each step of the manufacturing method of the solar cell unit shown in FIG. For example, the manufacturing method can be used to manufacture Figure 1 and Figure 2 The solar cell shown.

[0063] like Figure 3 As shown, the manufacturing method for manufacturing a solar cell unit includes:

[0064] Step S11, surface treatment of the silicon substrate 1: placing the silicon substrate 1 in a texturing tank containing KOH or NaOH solution to perform surface texturing to form a velvet structure, and then using a mixed solution of HNO3 and HF to smooth the pyramids of the velvet surface. Figure 4A shown.

[0065] Step S12, forming a passivation dielectric layer 2: using a plasma enhanced chemical vapor deposition (PECVD) process to form a passivation dielectric layer 2 of silicon dioxide (SiO2) with a thickness of 1.5 nm on one surface of the silicon substrate 1. Figure 4B shown.

[0066] Step S13, forming a first silicon layer 3: In the same equipment used in step S12, a first pre-layer (not shown) of polysilicon in-situ doped with phosphorus with a thickness of 70 nm is formed on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 by a PECVD process.

[0067] Step S14, annealing treatment: placing the silicon substrate 1 on which the first pre-layer is formed in a furnace tube, and performing high temperature annealing heat treatment to activate the phosphorus atoms in situ doped in the first pre-layer and crystallize the first pre-layer to transform into the first silicon layer 3, thereby achieving high concentration doping and further improving the passivation performance, such as Figure 4C shown.

[0068] Step S15, forming a second silicon layer 4: using a PECVD process to form a second silicon layer 4 of undoped intrinsic amorphous silicon with a thickness of 10 nm on the surface of the first silicon layer 3 facing away from the passivation dielectric layer 2, such as Figure 4D shown.

[0069] Step S16, forming a third silicon layer 5: forming a third silicon layer 5 of in-situ phosphorus-doped amorphous silicon with a thickness of 10 nm on the surface of the second silicon layer 4 facing away from the first silicon layer 3 by using a PECVD process, such as Figure 4E shown.

[0070] Step S17, patterning the second silicon layer 4 and the third silicon layer 5: firstly, forming a patterned paraffin mask layer 7 on the surface of the third silicon layer 5 facing away from the second silicon layer 4, such as Figure 4F As shown, the second silicon layer 4 and the third silicon layer 5 not covered by the mask layer 7 are etched with a KOH solution to expose the corresponding portion of the first silicon layer 3, as shown in FIG. Figure 4G As shown, the mask layer 7 is finally removed, so that the second silicon layer 4 and the third silicon layer 5 are patterned, as shown in FIG. Figure 4H Here, the etching depth is controlled by controlling the etching time, so there may be errors in the etching depth. For example, there may be a second silicon layer 4 that is not etched away, or a part of the first silicon layer 3 may be etched away.

[0071] Step S18, forming a metal contact electrode 6: a patterned metal contact layer is formed on the exposed portion of the first silicon layer 3 (i.e., the area where the second silicon layer 4 and the third silicon layer 5 are removed) by a screen printing process to realize a metal contact electrode 6, and the metal contact electrode 6 is also in direct contact with the surrounding third silicon layer 5, such as Figure 1 shown.

[0072] According to another embodiment of the present disclosure, a solar cell unit includes: a silicon substrate 1; a passivation dielectric layer 2 arranged on a surface of the silicon substrate 1; a first silicon layer 3, a second silicon layer 4 and a third silicon layer 5 which are sequentially arranged on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 and in contact with each other; and a metal contact electrode 6, which passes through the third silicon layer 5 and the second silicon layer 4 and is in direct contact with the first silicon layer 3.

[0073] Specifically, the silicon substrate 1 adopts a p-type single crystal silicon wafer with a resistivity of 0.1-20Ω·cm, the passivation dielectric layer 2 is a stack of aluminum oxide (Al2O3) and titanium oxide (TiO2) with a thickness of 1.3nm, the first silicon layer 3 is a polycrystalline silicon layer doped with phosphorus (P) with a thickness of 100nm, the second silicon layer 4 is an intrinsic amorphous silicon layer with a thickness of 12nm, the third silicon layer 5 is a 9nm phosphorus-doped amorphous silicon layer, and the metal contact electrode 6 is, for example, a silver electrode, an aluminum electrode or a silver-aluminum electrode.

[0074] According to another embodiment of the present disclosure, a manufacturing method for manufacturing a solar cell unit includes:

[0075] Step S21, surface treatment of the silicon substrate 1: placing a p-type single crystal silicon wafer with a resistivity of 0.1 to 20 Ω·cm in a texturing tank containing a KOH or NaOH solution for surface texturing to form a velvet structure, then using a mixed solution of HNO3 and HF to round off the pyramids of the velvet surface, and finally polishing one surface of the silicon substrate 1 with a NaOH solution.

[0076] Step S22, forming a passivation dielectric layer 2: using an atomic deposition (ALD) process to form a passivation dielectric layer 2 of aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked layers with a thickness of 1.3 nm on the polished surface of the silicon substrate 1.

[0077] Step S23 , forming a first silicon layer 3 : forming a first pre-layer of in-situ phosphorus-doped amorphous silicon with a thickness of 100 nm on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 by a physical vapor deposition (PVD) process.

[0078] Step S24, annealing treatment: the silicon substrate 1 on which the first pre-layer is formed is placed in a furnace tube, and a high-temperature annealing heat treatment is performed to activate the phosphorus atoms in situ doped in the first pre-layer and to crystallize the first pre-layer to transform from the first pre-layer of amorphous silicon into the first silicon layer 3 of polycrystalline silicon, thereby achieving high-concentration doping and further improving the passivation performance.

[0079] Step S25 , forming a second silicon layer 4 : forming a second silicon layer 4 of undoped intrinsic amorphous silicon with a thickness of 12 nm on the surface of the first silicon layer 3 facing away from the passivation dielectric layer 2 by using a PECVD process.

[0080] Step S26, forming a third silicon layer 5: forming a third silicon layer 5 of phosphorus-doped amorphous silicon with a thickness of 9 nm on the surface of the second silicon layer 4 facing away from the first silicon layer 3 by using a PECVD process.

[0081] Step S27 , patterning the second silicon layer 4 and the third silicon layer 5 : using a picosecond laser to remove portions of the second silicon layer 4 and the third silicon layer 5 in regions corresponding to the metal contact electrodes 6 to be formed.

[0082] Step S28 , forming a metal contact electrode 6 : using a screen printing process to form a patterned metal contact layer on the exposed portion of the first silicon layer 3 to realize the metal contact electrode 6 , and the metal contact electrode 6 is also in direct contact with the surrounding third silicon layer 5 .

[0083] According to another embodiment of the present disclosure, a solar cell unit includes: a silicon substrate 1; a passivation dielectric layer 2 arranged on a surface of the silicon substrate 1; a first silicon layer 3, a second silicon layer 4 and a third silicon layer 5 arranged in sequence on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 and in contact with each other; and a metal contact electrode 6, which passes through the third silicon layer 5 and the second silicon layer 4 and is in direct contact with the first silicon layer 3.

[0084] Specifically, the silicon substrate 1 adopts an n-type single crystal silicon wafer with a resistivity of 0.1-20Ω·cm, the passivation dielectric layer 2 is a silicon dioxide layer with a thickness of 1.0nm, the first silicon layer 3 is an 80nm phosphorus-doped polycrystalline silicon layer, the second silicon layer 4 is an intrinsic amorphous silicon layer with a thickness of 5nm, the third silicon layer 5 is a phosphorus-doped microcrystalline silicon layer with a thickness of 8nm, and the metal contact electrode 6 is, for example, a silver electrode, an aluminum electrode or a silver-aluminum electrode.

[0085] According to yet another embodiment of the present disclosure, a method for manufacturing a solar cell unit includes:

[0086] Step S31, surface treatment of the silicon substrate 1: placing an n-type single crystal silicon wafer with a resistivity of 0.1-20Ω·cm in a texturing tank containing KOH or NaOH solution for surface texturing to form a textured surface structure, and then wet etching the textured surface with a mixed solution of HNO3 and HF.

[0087] Step S32, forming a passivation dielectric layer 2: a passivation dielectric layer 2 of silicon dioxide (SiO2) with a thickness of 1.0 nm is formed on one surface of the silicon substrate 1 by a nitric acid oxidation process, as shown in FIG. 4 .

[0088] Step S33, forming a first silicon layer 3: using a physical vapor deposition (PVD) process, a first pre-layer with a thickness of 80 nm is formed on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1, and the first pre-layer includes an intrinsic non-doped portion with a thickness of 40 nm and an in-situ phosphorus-doped doped portion with a thickness of 40 nm. Here, the non-doped portion is arranged closer to the passivation dielectric layer 2 than the doped portion. In other examples, the doped portion can be arranged closer to the passivation dielectric layer 2 than the non-doped portion.

[0089] Step S34, annealing treatment: the silicon substrate 1 on which the first pre-layer is formed is placed in a furnace tube, and a high-temperature annealing heat treatment is performed to activate the phosphorus atoms in the doped part of the first pre-layer and diffuse them to the non-doped part, and at the same time, the first pre-layer is crystallized to convert it into a first silicon layer 3 of polycrystalline silicon, thereby finally achieving a high concentration of doping and further improving the passivation performance.

[0090] Step S35 , forming a second silicon layer 4 : forming a second silicon layer 4 of undoped intrinsic amorphous silicon with a thickness of 5 nm on the surface of the first silicon layer 3 facing away from the passivation dielectric layer 2 by using a PECVD process.

[0091] Step S36, forming a third silicon layer 5: forming a third silicon layer 5 of phosphorus-doped microcrystalline silicon with a thickness of 8 nm on the surface of the second silicon layer 4 facing away from the first silicon layer 3 by using a PECVD process.

[0092] Step S37, patterning the second silicon layer 4 and the third silicon layer 5: firstly, forming a patterned mask layer 7 on the surface of the third silicon layer 5 facing away from the second silicon layer 4, and then etching the second silicon layer 4 and the third silicon layer 5 not covered by the mask layer 7 using a mixed solution of HNO3 and HF to expose the corresponding portion of the first silicon layer 3, thereby patterning the second silicon layer 4 and the third silicon layer 5. Here, the patterned mask layer 7 is a dry film photoresist.

[0093] Step S38, forming a metal contact electrode 6: using the mask layer 7 to form a patterned metal contact layer on the exposed portion of the first silicon layer 3 using an electroplating process to achieve the metal contact electrode 6, which is also in direct contact with the surrounding third silicon layer 5, and finally removing the mask layer 7.

[0094] According to another embodiment of the present disclosure, a solar cell unit includes: a silicon substrate 1; a passivation dielectric layer 2 arranged on a surface of the silicon substrate 1; a first silicon layer 3, a second silicon layer 4 and a third silicon layer 5 arranged in sequence on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 and in contact with each other; and a metal contact electrode 6, which passes through the third silicon layer 5 and the second silicon layer 4 and is in direct contact with the first silicon layer 3.

[0095] Figure 5FIG. 2 shows a schematic plan view of a solar cell unit according to another embodiment of the present disclosure. Figure 5 As shown, the metal contact electrode 6 only includes a plurality of first strip electrodes 61 extending in a first direction. For example, the plurality of first strip electrodes 61 can be used as fine grids of a solar cell unit.

[0096] Specifically, the silicon substrate 1 adopts a p-type single crystal silicon wafer with a resistivity of 0.1-20Ω·cm, the passivation dielectric layer 2 is a silicon dioxide layer with a thickness of 2.0nm, the first silicon layer 3 is a 120nm boron (B) doped polycrystalline silicon layer, the second silicon layer 4 is an intrinsic microcrystalline silicon layer with a thickness of 9nm, the third silicon layer 5 is a 9nm boron doped polysilicon layer, and the metal contact electrode 6 is, for example, a silver electrode, an aluminum electrode or a silver-aluminum electrode.

[0097] According to yet another embodiment of the present disclosure, a method for manufacturing a solar cell unit includes:

[0098] Step S41, surface treatment of the silicon substrate 1: surface texturing of a p-type single crystal silicon wafer with a resistivity of 0.1-20Ω·cm in a texturing tank containing KOH or NaOH solution to form a textured surface structure, and then wet etching of the textured surface with a mixed solution of HNO3 and HF.

[0099] Step S42 , forming a passivation dielectric layer 2 of silicon dioxide (SiO 2 ) with a thickness of 2.0 nm on a surface of the silicon substrate 1 by using a low pressure chemical vapor deposition (LPCVD) process.

[0100] Step S43, forming a first silicon layer 3: In the same equipment used in step S42, a first pre-layer of amorphous silicon in-situ doped with boron (B) with a thickness of 120 nm is formed on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 by an LPCVD process.

[0101] Step S44, annealing treatment: the silicon substrate 1 on which the first pre-layer is formed is placed in a furnace tube, and a high-temperature annealing heat treatment is performed to activate the boron atoms in situ doped in the first pre-layer and to crystallize the first pre-layer to transform from the first pre-layer of amorphous silicon into the first silicon layer 3 of polycrystalline silicon, thereby achieving high-concentration doping and further improving the passivation performance.

[0102] Step S45 , forming a second silicon layer 4 : forming a second silicon layer 4 of undoped intrinsic microcrystalline silicon with a thickness of 9 nm on the surface of the first silicon layer 3 facing away from the passivation dielectric layer 2 by using a PECVD process.

[0103] Step S46, forming a third silicon layer 5: forming a third silicon layer 5 of boron-doped polysilicon with a thickness of 9 nm on the surface of the second silicon layer 4 facing away from the first silicon layer 3 by using a PECVD process.

[0104] Step S47 , patterning the second silicon layer 4 and the third silicon layer 5 : using a picosecond laser to remove portions of the second silicon layer 4 and the third silicon layer 5 in regions corresponding to the metal contact electrodes 6 to be formed.

[0105] Step S48 , forming a metal contact electrode 6 : using a screen printing process to form a patterned metal contact layer on the exposed portion of the first silicon layer 3 to realize the metal contact electrode 6 , and the metal contact electrode 6 is also in direct contact with the surrounding third silicon layer 5 .

[0106] The manufacturing method is not limited to the order of the steps described herein. Optionally, in alternative embodiments, steps may be omitted, or other steps may be added. Optionally, in alternative embodiments, the order of the steps may be rearranged. Optionally, one or more of the steps may be performed simultaneously.

[0107] This disclosure at least describes the following technical solutions:

[0108] Solution 1: A solar cell unit, comprising:

[0109] Silicon substrate (1);

[0110] A passivation dielectric layer (2) disposed on the silicon substrate (1);

[0111] A first silicon layer (3), a second silicon layer (4) and a third silicon layer (5), which are sequentially arranged on a surface of the passivation dielectric layer (2) facing away from the silicon substrate (1) and are in contact with each other; and

[0112] A metal contact electrode (6) passes through the third silicon layer (5) and the second silicon layer (4) to directly contact the first silicon layer (3).

[0113] Solution 2: The solar cell unit according to Solution 1, wherein:

[0114] The first silicon layer (3) is a doped polysilicon layer,

[0115] The second silicon layer (4) is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer.

[0116] The third silicon layer (5) is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and

[0117] The first silicon layer (3) and the third silicon layer (5) have the same doping type, which is n-type or p-type.

[0118] Solution 3: The solar cell unit according to Solution 1 or 2, wherein:

[0119] The metal contact electrode (6) is also in direct contact with the surface of the third silicon layer (5) facing away from the second silicon layer (4).

[0120] Solution 4: The solar cell unit according to Solution 3, wherein:

[0121] The doping concentration of the first silicon layer (3) is in the range of 1*1020 to 1*1021 atoms / cm3, and

[0122] The doping concentration of the third silicon layer (5) is in the range of 5*1018 to 5*1020 atoms / cm3.

[0123] Solution 5. The solar cell unit according to Solution 1 or 2, wherein:

[0124] The first silicon layer (3) is a crystallized polysilicon layer.

[0125] Solution 6. The solar cell unit according to Solution 1 or 2, wherein:

[0126] The passivation dielectric layer (2) comprises a single layer or a stacked layer of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride and silicon nitride.

[0127] Solution 7: The solar cell unit according to solution 1 or 2, wherein:

[0128] The thickness of the first silicon layer (3) is in the range of 10-300 nm,

[0129] The thickness of the second silicon layer (4) is in the range of 1-100 nm, and

[0130] The thickness of the third silicon layer (5) is in the range of 1-100 nm.

[0131] Solution 8. The solar cell unit according to solution 1 or 2, wherein:

[0132] The transparent conductive layer includes a metal oxide with a doping element or a metal nitride with a doping element.

[0133] Solution 9. The solar cell unit according to Solution 8, wherein:

[0134] The metal oxide includes at least one of indium oxide, tin oxide, zinc oxide and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum and fluorine.

[0135] Solution 10. A method for manufacturing a solar cell unit, comprising:

[0136] Providing a silicon substrate (1);

[0137] forming a passivation dielectric layer (2) on a surface of the silicon substrate (1);

[0138] A first silicon layer (3), a second silicon layer (4) and a third silicon layer (5) are sequentially formed on a surface of the passivation dielectric layer (2) facing away from the silicon substrate (1), wherein the first silicon layer (3), the second silicon layer (4) and the third silicon layer (5) are in contact with each other; and

[0139] A metal contact electrode (6) is formed, wherein the metal contact electrode (6) passes through the third silicon layer (5) and the second silicon layer (4) and is in direct contact with the first silicon layer (3).

[0140] Scheme 11. The manufacturing method according to Scheme 10, wherein:

[0141] The first silicon layer (3) is a doped polysilicon layer,

[0142] Forming the first silicon layer (3) includes:

[0143] forming a first front layer, the first front layer comprising a single layer or a stacked layer of one or more of a microcrystalline silicon layer, an amorphous silicon layer and polycrystalline silicon having doped atoms; and

[0144] A high temperature annealing heat treatment is performed to activate the doping atoms and crystallize the first pre-layer to transform it into a first silicon layer (3).

[0145] Scheme 12. The manufacturing method according to Scheme 11, wherein:

[0146] The first front layer further includes a single layer or a stacked layer of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer and a polycrystalline silicon layer.

[0147] Scheme 13. A manufacturing method according to any one of schemes 10-12, wherein:

[0148] Forming the metal contact electrode (6) comprises:

[0149] patterning the second silicon layer (4) and the third silicon layer (5) to remove a portion of the second silicon layer (4) and the third silicon layer (5); and

[0150] The metal contact electrode (6) is formed at the region where the second silicon layer (4) and the third silicon layer (5) are removed, so that the metal contact electrode (6) passes through the third silicon layer (5) and the second silicon layer (4) and is in direct contact with the first silicon layer (3).

[0151] Scheme 14. A manufacturing method according to any one of schemes 10-12, wherein:

[0152] The second silicon layer (4) is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer.

[0153] The third silicon layer (5) is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and

[0154] The first silicon layer (3) and the third silicon layer (5) have the same doping type, which is n-type or p-type.

[0155] Scheme 15. A manufacturing method according to any one of schemes 10-12, wherein:

[0156] The passivation dielectric layer (2) comprises a single layer or a stacked layer of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride and silicon nitride.

[0157] Scheme 16. A manufacturing method according to any one of schemes 10-12, wherein:

[0158] The transparent conductive layer includes a metal oxide or a metal nitride having a doping element, and

[0159] The metal oxide includes at least one of indium oxide, tin oxide, zinc oxide and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum and fluorine.

[0160] The scope of the present disclosure is not limited by the above-described embodiments but by the appended claims and their equivalents.

Claims

1. A solar cell unit, comprising: Silicon substrate (1); A passivation dielectric layer (2) disposed on the silicon substrate (1); A first silicon layer (3), a second silicon layer (4) and a third silicon layer (5), which are sequentially arranged on a surface of the passivation dielectric layer (2) facing away from the silicon substrate (1) and are in contact with each other; and a metal contact electrode (6) which passes through the third silicon layer (5) and the second silicon layer (4) and is in direct contact with the first silicon layer (3), The first silicon layer (3) is a doped polysilicon layer, The second silicon layer (4) is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer. The third silicon layer (5) is a single layer or a stacked layer of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer.

2. The solar cell unit according to claim 1, wherein: The first silicon layer (3) and the third silicon layer (5) have the same doping type, which is n-type or p-type.

3. The solar cell unit according to claim 1 or 2, wherein: The doping concentration of the first silicon layer is greater than the doping concentration of the third silicon layer.

4. The solar cell unit according to claim 1 or 2, wherein: The metal contact electrode (6) is also in direct contact with the surface of the third silicon layer (5) facing away from the second silicon layer (4).

5. The solar cell unit according to claim 3, wherein: The doping concentration of the first silicon layer (3) is 1*10 20 Up to 1*10 21 Number of atoms / cm 3 within the range of The doping concentration of the third silicon layer (5) is 5*10 18 Up to 5*10 20 Number of atoms / cm 3 within the range.

6. The solar cell unit according to claim 1 or 2, wherein: The first silicon layer (3) is a crystallized polysilicon layer.

7. The solar cell unit according to claim 1 or 2, wherein: The passivation dielectric layer (2) comprises a single layer or a stacked layer of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride and silicon nitride.

8. The solar cell unit according to claim 1 or 2, wherein: The thickness of the first silicon layer (3) is in the range of 10-300 nm, The thickness of the second silicon layer (4) is in the range of 1-100 nm, and The thickness of the third silicon layer (5) is in the range of 1-100 nm.

9. A method for manufacturing a solar cell unit, comprising: Providing a silicon substrate (1); forming a passivation dielectric layer (2) on a surface of the silicon substrate (1); A first silicon layer (3), a second silicon layer (4) and a third silicon layer (5) are sequentially formed on a surface of the passivation dielectric layer (2) facing away from the silicon substrate (1), wherein the first silicon layer (3), the second silicon layer (4) and the third silicon layer (5) are in contact with each other; as well as forming a metal contact electrode (6), wherein the metal contact electrode (6) passes through the third silicon layer (5) and the second silicon layer (4) and directly contacts the first silicon layer (3), The first silicon layer (3) is a doped polysilicon layer, The second silicon layer (4) is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer. The third silicon layer (5) is a single layer or a stacked layer of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer.

10. The manufacturing method according to claim 9, wherein: The doping concentration of the first silicon layer is greater than the doping concentration of the third silicon layer.

11. The manufacturing method according to claim 9, wherein: Forming the first silicon layer (3) includes: forming a first front layer, the first front layer comprising a single layer or a stacked layer of one or more of a microcrystalline silicon layer, an amorphous silicon layer and polycrystalline silicon having doped atoms; and A high temperature annealing heat treatment is performed to activate the doping atoms and crystallize the first pre-layer to transform it into a first silicon layer (3).

12. The manufacturing method according to claim 11, wherein: The first front layer further includes a single layer or a stacked layer of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer and a polycrystalline silicon layer.

13. The manufacturing method according to any one of claims 9 to 12, wherein: Forming the metal contact electrode (6) comprises: patterning the second silicon layer (4) and the third silicon layer (5) to remove a portion of the second silicon layer (4) and the third silicon layer (5); and The metal contact electrode (6) is formed at the region where the second silicon layer (4) and the third silicon layer (5) are removed, so that the metal contact electrode (6) passes through the third silicon layer (5) and the second silicon layer (4) and is in direct contact with the first silicon layer (3).

14. The manufacturing method according to any one of claims 9 to 12, wherein: The first silicon layer (3) and the third silicon layer (5) have the same doping type, which is n-type or p-type.

15. The manufacturing method according to any one of claims 9 to 12, wherein: The passivation dielectric layer (2) comprises a single layer or a stacked layer of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride and silicon nitride.

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