A surge suppression circuit for a high-power adapter and the high-power adapter

Abstract

The application discloses a surge suppression circuit for a high-power adapter, the high-power adapter comprising a rectifier circuit, two ends of an alternating current end of the rectifier circuit being connected with an alternating current, the surge suppression circuit comprising an electrolytic capacitor, a suppression resistor, a first MOS tube and a first MOS tube control unit, wherein the electrolytic capacitor and the suppression resistor are connected in series between two ends of a direct current end of the rectifier circuit, the first MOS tube is connected in parallel between two ends of the suppression resistor, and the first MOS tube control unit is connected and used for turning on the first MOS tube after the electrolytic capacitor is connected with electricity. The application further discloses a high-power adapter comprising a rectifier circuit and the above surge suppression circuit. The surge suppression circuit for the high-power adapter and the high-power adapter disclosed by the application can meet low power consumption and effectively suppress surge current.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a surge suppression circuit for a high-power adapter and the high-power adapter. BACKGROUND

[0002] In recent years, with the increasing demand for laser projectors and audio products, the power of the applied adapter is also required to be larger and smaller. In addition to meeting the basic requirements of temperature rise of the regulatory requirements, some even have further more stringent requirements on the surface temperature of the power supply for better customer experience. To meet these requirements, first of all, the power supply must use high-efficiency topology to design (currently typical is to use PFC+LLC to meet the energy efficiency 6 level requirements), and secondly, the internal optimization of the power supply reduces the loss of all devices as much as possible. Only by reducing the loss as much as possible can the temperature requirements be met.

[0003] However, when the existing adapter is designed to meet the above requirements as much as possible, the inrush current at the moment of connecting the power supply is often too large, thereby greatly increasing the probability of current breakdown of the rectifier bridge, BYPASS diode and MOS tube.

[0004] The disclosure of the above background art content is only used to assist in understanding the concept and technical solutions of the present application, and it does not necessarily belong to the prior art of the present patent application. In the absence of explicit evidence that the above content has been disclosed on the filing date of the present patent application, the above background art should not be used to evaluate the novelty and inventiveness of the present application. SUMMARY

[0005] To solve the above technical problems of the present application, the present application discloses a surge suppression circuit for a high-power adapter and the high-power adapter, which meets low power consumption and effectively suppresses inrush current.

[0006] In order to achieve the above purpose, the present application adopts the following technical solutions:

[0007] The present application discloses a surge suppression circuit for a high-power adapter, the high-power adapter comprising a rectifier circuit, the two ends of the alternating current end of the rectifier circuit being connected to alternating current, the surge suppression circuit comprising an electrolytic capacitor, a suppression resistor, a first MOS tube and a first MOS tube control unit, wherein the electrolytic capacitor and the suppression resistor are connected in series between the two ends of the direct current end of the rectifier circuit, the first MOS tube is connected in parallel across the two ends of the suppression resistor, and the first MOS tube control unit is connected and used to turn on the first MOS tube after the electrolytic capacitor is connected to the power supply.

[0008] In a further aspect, the surge suppression circuit further comprises a voltage-dependent resistor, two ends of the voltage-dependent resistor being connected across the DC end of the rectifier circuit.

[0009] In a further aspect, the surge suppression circuit further comprises a first capacitor, two ends of the first capacitor being connected across the DC end of the rectifier circuit.

[0010] In a further aspect, the surge suppression circuit further comprises a power factor correction circuit, the power factor correction circuit being connected across the DC end of the rectifier circuit, and the power factor correction circuit being connected between the rectifier circuit and the series circuit of the electrolytic capacitor and the suppression resistor.

[0011] In a further aspect, the surge suppression circuit further comprises a voltage-dependent resistor, the voltage-dependent resistor being connected between the rectifier circuit and the power factor correction circuit.

[0012] In a further aspect, the surge suppression circuit further comprises a first capacitor, the first capacitor being connected between the power factor correction circuit and the series circuit of the electrolytic capacitor and the suppression resistor.

[0013] In a further aspect, the first capacitor is a CBB capacitor or an SMD ceramic capacitor.

[0014] In a further aspect, the first capacitor is less than 5 mu F.

[0015] In a further aspect, the first MOS tube control unit is a control chip timing circuit module, a time delay module or a logic circuit module.

[0016] The application further discloses a high-power adapter comprising a rectifier circuit and the surge suppression circuit.

[0017] Compared with the prior art, the application has the following advantages: the surge suppression circuit for the high-power adapter and the high-power adapter disclosed by the application connect a suppression resistor in series at the positive end or the negative end of an electrolytic capacitor, and connect a first MOS tube across the suppression resistor, which can reduce the loss of the suppression resistor, meet the low-power consumption, such as the energy efficiency six standard, and effectively suppress the surge current, thereby ensuring the self-controllable, safe and non-additional-loss suppression of the surge current, and having obvious advantages in improving the efficiency and temperature rise.

[0018] In a further aspect, the application has the following advantages:

[0019] Connecting the voltage-dependent resistor across the DC end of the rectifier circuit can suppress the damage of the ringing of the lightning test to the MOS tube.

[0020] The first capacitor is connected in parallel with the series circuit of the suppression resistor and the electrolytic capacitor, so that the interference of the internal resistance (ESR) of the main power circuit on the circuit can be improved.

[0021] The first MOS control unit adopts a control chip timing circuit module, a time delay module or a logic circuit module, so that the switch tube connected in parallel with the surge resistor can be closed after a surge impact, and the switch tube can be automatically reset when restarted, and the surge current can be inhibited according to the timing opening and closing action. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a schematic diagram of a surge suppression circuit for a high-power adapter according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of a surge suppression circuit for a high-power adapter according to an embodiment of the present application;

[0024] Figure 3 is a schematic diagram of a surge suppression circuit for a high-power adapter according to an embodiment of the present application;

[0025] Figure 4 is a timing diagram of the VREG pin of the chip HR1211;

[0026] Figure 5 is a schematic diagram of a surge current of a surge suppression circuit of a comparative example;

[0027] Figure 6 is a schematic diagram of a surge current of a surge suppression circuit of a comparative example; DETAILED DESCRIPTION

[0028] In order to make the technical problems to be solved by the embodiments of the present application, the technical solutions and the beneficial effects more clearly understood, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0029] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element. In addition, the connection can be for fixing or for circuit communication.

[0030] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate directions or positions based on the directions or positions shown in the drawings and are used for purposes of convenience and brevity in describing the embodiments of the present application and the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the application.

[0031] In addition, the terms "first", "second", "third", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined as "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0032] For increasingly stringent design requirements, in addition to meeting the basic requirements, the power adapter also has requirements for output instantaneous peak power, generally requiring at least 2.5 times the output current load capacity. To meet this requirement, optimizing the DC / DC loop parameters can improve but not completely solve the problem, because the PFC (Power Factor Correction) control loop is very slow (10-20 Hz), at this time the voltage of the PFC output capacitor is easily pulled to a very low value, triggering various protections, and cannot completely solve the problem. The best solution is to increase the PFC output capacitor capacity and optimize the control loop, only in this way can the instantaneous several times output power be controlled to prevent the LLC (Logical Link Control) input voltage from being too low to enter the capacitive mode or capacitive protection mode.

[0033] As the power of the power adapter itself becomes larger and larger, and the peak power needs to be met, the PFC output capacitor capacity must be very large. The defect brought by the large-capacity high-voltage capacitor is that the surge current of the power adapter is very large at the moment of connecting to the mains, which greatly increases the probability of current breakdown of the rectifier bridge, BYPASS diode and MOS tube. Except for special applications such as projection audio, power adapters with power exceeding several hundred watts, NTC resistors are generally connected in series at the input end to suppress the surge current, so as to ensure that the power supply is not damaged under the impact current. However, the disadvantage of adding NTC resistors is that the overall efficiency is reduced, and the continuous heating of NTC (about 1-2W of power consumption for a 350W power adapter using a 5 ohm NTC) causes serious internal temperature rise problems.

[0034] The preferred embodiment of the present application uses a control circuit to solve the above problem of input surge current of high-power adapters, ensuring that the surge current is self-controllable, safe and does not increase additional loss, and has obvious advantages in improving efficiency and temperature rise.

[0035] As Figure 1 shown in the surge suppression circuit for high-power adapter of the embodiment of the present application, the high-power adapter comprises a rectifier circuit 10, the two ends of the AC end of the rectifier circuit 10 are connected with AC, the surge suppression circuit comprises an electrolytic capacitor 20, a suppression resistor 30, a first MOS tube 40, and a first MOS tube control unit 50, wherein the electrolytic capacitor 20 and the suppression resistor 30 are connected in series between the two ends of the DC end of the rectifier circuit 10, specifically, the positive end of the electrolytic capacitor 20 is connected with the positive end of the DC end of the rectifier circuit 10, one end of the suppression resistor 30 is connected with the negative end of the electrolytic capacitor 20, and the other end is connected with the negative end of the DC end of the rectifier circuit 10; the first MOS tube 40 is connected in parallel between the two ends of the suppression resistor 30, and the first MOS tube control unit 50 is connected and used for controlling the first MOS tube 40; specifically, the source of the first MOS tube 40 is connected with the negative end of the DC end of the rectifier circuit 10, the drain is connected with the negative end of the electrolytic capacitor 20, and the gate is connected with the first MOS tube control unit 50.

[0036] The surge suppression circuit of the embodiment of the present application can realize the suppression of the input surge current according to the power supply sequence and the logic control when the first MOS tube 40 connected in parallel between the two ends of the suppression resistor 30 is opened by the control chip timing circuit module, the time delay module or the logic circuit module when the power supply of the switching power supply control chip meets the starting requirement, and can realize the smooth starting when the control chip timing circuit module, the time delay module or the logic circuit module is automatically reset when the power is off or the machine is shut down, so as to ensure the effective function of the circuit. The use of the logic control voltage to drive a MOS tube will not cause additional loss, so the surge suppression circuit can meet the requirements of energy efficiency in no-load or light-load state.

[0037] Furthermore, the surge suppression circuit in this embodiment also includes a varistor 60, a first capacitor 70, and a power factor correction circuit 80. The power factor correction circuit 80 is connected across the DC terminals of the rectifier circuit 10 and is also connected between the rectifier circuit 10 and the circuit in series with the electrolytic capacitor 20 and the suppression resistor 30. In this embodiment, the power factor correction circuit 80 includes an inductor 81, a first diode 82, a BYPASS diode 83, a second MOSFET 84, and a power factor correction control unit 85. One end of the inductor 81 is connected to the positive terminal of the DC terminal of the rectifier circuit 10. The positive terminal of the first diode 82 is connected to the inductor 81, and the negative terminal of the first diode 82 is connected to the positive terminal of the electrolytic capacitor 20. The positive terminal of the BYPASS diode 83 is connected to the positive terminal of the DC terminal of the rectifier circuit 10, and the negative terminal of the BYPASS diode 83 is connected to the electrolytic capacitor 20. The positive terminal of the first MOSFET 84 is connected, with its drain connected between the inductor 81 and the first diode 82. Its source is connected to the negative terminal of the DC power supply of the rectifier circuit 10, and its gate is connected to the power factor correction control unit 85. A varistor 60 is connected between the rectifier circuit 10 and the power factor correction circuit 80, meaning it is directly connected in parallel between the two ends of the DC power supply of the rectifier circuit 10. By connecting a varistor in parallel after the rectifier circuit 10, the overcurrent damage to the surge MOSFET caused by ringing during lightning strike testing can be significantly reduced, improving reliability and ensuring effective practical application. The first capacitor 70 is connected between the power factor correction circuit 80 and the series circuit of the electrolytic capacitor 20 and the suppression resistor 30. That is, the first capacitor 70 is directly connected in parallel between the two ends of the series circuit of the electrolytic capacitor 20 and the suppression resistor 30. This first capacitor 70 can be a CBB capacitor or an SMD ceramic capacitor, with a relatively small capacitance, typically less than 5μF. By connecting the first capacitor in parallel before the suppression resistor 30, the influence of the internal resistance (ESR) in the main power circuit on the preceding and following stages can be improved. In some cases, the power factor correction control unit 85 and the first MOSFET control unit 50 can be controlled by the same chip.

[0038] like Figure 2 As shown, the surge suppression circuit for a high-power adapter in Embodiment 2 of the present invention differs from Embodiment 1 only in that one end of the suppression resistor 30 is connected to the positive terminal of the electrolytic capacitor 20, and the other end is connected to the positive terminal of the DC terminal of the rectifier circuit 10. The source of the first MOSFET 40 is connected to the positive terminal of the electrolytic capacitor 20, the drain is connected to the positive terminal of the DC terminal of the rectifier circuit 10, and the gate is connected to the first MOSFET control unit 50. All other structures are the same and will not be described further. The effect of this embodiment is the same as that of Embodiment 1 and will not be described further.

[0039] Another embodiment of the present invention discloses a surge suppression circuit, including a rectifier circuit and the surge suppression circuit of the above embodiment one or embodiment two.

[0040] The following examples, in conjunction with specific application examples, further illustrate the effectiveness of the surge suppression circuit in the embodiments of the present invention.

[0041] like Figure 3 As shown in this specific application example, the high-power adapter includes a rectifier bridge BD1. The two ends of the AC section of the rectifier bridge BD1 are connected to AC power. The surge suppression circuit includes an electrolytic capacitor EC1, a suppression resistor TH1, a MOSFET Q2, a varistor MOV1, a capacitor C1, a power factor correction circuit, and a chip HR1211. The power factor correction circuit includes a MOSFET Q1, an inductor L1, a diode D1, and a diode D2. Both the MOSFET Q2 and the MOSFET Q1 in the power factor correction circuit are controlled by the chip HR1211. Specifically, the GATE pin of the chip HR1211 controls the MOSFET Q1, and the VREG pin controls the MOSFET Q2. The series circuit of the varistor MOV1, the power factor correction circuit, and the electrolytic capacitor EC1 and the suppression resistor TH1 are connected in parallel across the DC end of the rectifier bridge BD1. The MOSFET Q2 is connected in parallel across the suppression resistor TH1.

[0042] In this design, a varistor MOV1 is connected in parallel at the output of the rectifier bridge BD1. A MOSFET Q2 and an NTC resistor TH1 are connected in series between the negative terminal of the electrolytic capacitor EC1 and the source of the MOSFET Q1 (MOSFET Q2 and NTC resistor TH1 are connected in parallel). The gate of the MOSFET Q2 is connected to the VREG pin of the HR1211 via a drive resistor R2. A CBB capacitor C1 is connected in parallel between the positive terminal of the electrolytic capacitor EC1 and the source of the MOSFET Q1. This design is very simple. Because the surge suppression circuit's MOSFET is driven directly using the VREG pin of the HR1211 chip as the output, reliability is very high.

[0043] In this specific application example, controlling MOSFET Q2 via the VREG pin of the HR1211 chip can suppress inrush current while ensuring very low loss in the surge suppression circuit. Specifically, in the control timing, the VREG pin (PIN6) of the HR1211 chip remains at a low level when the power is first applied. After VCC is charged to the turn-on voltage of the HR1211 chip through the high-voltage pin HV and the chip is operating normally, the VREG pin remains at 12V (equivalent to a reliable PG signal, which can be directly used to drive the MOSFET Q2 in the surge suppression circuit). If there is an external fault, the voltage will drop to 0V. The timing of the VREG pin of the HR1211 chip during normal power-on and fault encounter is as follows: Figure 4 As shown.

[0044] The main purpose of this novel surge suppression circuit is to control the power-on inrush current below the required level and reduce the losses of the NTC resistor TH1 by turning on the MOSFET Q2. In traditional surge suppression circuits without the NTC resistor TH1, the inrush current is very large, exceeding the inrush current limits of the rectifier bridge BD1 and diode D1. Specifically... Figure 5 As shown, the surge current reached 286A. The novel surge suppression circuit in this example connects an NTC resistor TH1 in series with either the positive or negative terminal of the electrolytic capacitor EC1, and connects a low-resistance MOSFET Q2 in parallel with the NTC resistor TH1 to reduce the current flowing through the NTC resistor TH1 during normal operation. The working principle of this novel surge suppression circuit is that at the moment of AC power-on, pin 6 VREG of the integrated circuit HR1211 is at a low level. At this time, the surge current path is first through fuse F1—rectifier bridge BD1—diode D1—electrolytic capacitor EC1—NTC resistor TH1 and then back to the power grid. After the surge current impacts, the integrated circuit HR1211 charges to the turn-on voltage. At this time, pin 6 VREG of HR1211 outputs a high level, and the MOSFET Q2 is turned on. The internal resistance of the MOSFET Q2 is only 0.19Ω, and the NTC... The resistance of resistor TH1 is approximately 0.7Ω at 100 degrees Celsius. According to the current shunt principle, most of the current during normal operation flows through MOSFET Q2, with only a small portion flowing through NTC resistor TH1. Actual measurements show that the overall efficiency is about 0.3% higher than the traditional method. The measured surge current magnitude of the new surge current suppression circuit is as follows... Figure 6 As shown, the surge current is only 68A. A 350W projector adapter designed based on this novel surge suppression circuit has its surge current controlled below 80A and the circuit operates reliably.

[0045] The background section of this invention may include background information about the problems or circumstances surrounding the invention, rather than a description of prior art by others. Therefore, the content included in the background section is not an admission of prior art by the applicant.

[0046] The above description is further to the present application in conjunction with specific / preferred embodiments, and cannot be deemed as limiting the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, they can make several substitutions or variations to the described embodiments, and these substitutions or variations shall be deemed as falling within the protection scope of the present application. In the description of the present application, the description of the terms "an embodiment", "some embodiments", "a preferred embodiment", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are contained in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Furthermore, the skilled in the art can combine and combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction. Although the embodiments of the present application and their advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the scope defined by the appended claims.

Claims

1. A surge suppression circuit for a high power adapter including a rectifier circuit, both ends of an AC terminal of the rectifier circuit being connected with an AC power, characterized by, The surge suppression circuit comprises an electrolytic capacitor, a suppression resistor, a power factor correction circuit, a first MOS tube and a first MOS tube control unit, wherein the electrolytic capacitor and the suppression resistor are connected in series across the DC terminals of the rectifier circuit, the power factor correction circuit is connected across the DC terminals of the rectifier circuit, and the power factor correction circuit is connected between the rectifier circuit and the series circuit of the electrolytic capacitor and the suppression resistor; the first MOS tube is connected in parallel across the suppression resistor, and the first MOS tube control unit is connected and configured to turn on the first MOS tube after the electrolytic capacitor is connected to power, and the first MOS tube control unit employs a control chip timing circuit module, a time delay module or a logic circuit module. The series circuit of the power factor correction circuit, the electrolytic capacitor and the suppression resistor is connected in parallel across the DC terminals of the rectifier circuit, so that the control ground of the power factor correction circuit and the series circuit of the electrolytic capacitor and the suppression resistor is the same reference ground. When AC is connected at any phase angle, the initial state of the surge suppression circuit is that the electrolytic capacitor and the suppression resistor are connected in series, and when the power supply of the switching power supply control chip meets the start-up requirement, the first MOS tube control unit uses the control chip timing circuit module, the time delay module or the logic circuit module to open the first MOS tube connected in parallel across the suppression resistor, and automatically realizes suppression of the input surge current according to the power supply timing and logic control to realize smooth start-up, and when power failure or shutdown occurs, the control chip timing circuit module, the time delay module or the logic circuit module is automatically reset to close the first MOS tube, at which time the suppression resistor and the electrolytic capacitor are still connected in series to ensure the effective function of the circuit.

2. The surge suppression circuit of claim 1, wherein, A pressure-sensitive resistor is further included, and the two ends of the pressure-sensitive resistor are connected across the DC terminals of the rectifier circuit.

3. The surge suppression circuit of claim 1, wherein, A first capacitor is further included, and the two ends of the first capacitor are connected across the DC terminals of the rectifier circuit.

4. The surge suppression circuit of claim 1, wherein, A pressure-sensitive resistor is further included, and the two ends of the pressure-sensitive resistor are connected between the rectifier circuit and the power factor correction circuit.

5. The surge suppression circuit of claim 1, wherein, A first capacitor is further included, and the first capacitor is connected between the power factor correction circuit and the series circuit of the electrolytic capacitor and the suppression resistor.

6. The surge suppression circuit of claim 3 or 5, wherein The first capacitor employs a CBB capacitor or an SMD ceramic capacitor.

7. The surge suppression circuit of claim 3 or 5, wherein The first capacitor is less than 5 μF.

8. A high power adapter, characterized by, The surge suppression circuit of any one of claims 1 to 7 is included in a rectifier circuit.

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