A data processing method, apparatus, and storage medium

Abstract

This application discloses a data processing method, comprising: obtaining a first read interference count value of a flash memory block; if the first read interference count value is not greater than a first threshold and falls within an adjustment range, obtaining statistical information, the statistical information being obtained based on a first set, including multiple original error bit counts corresponding to multiple target data units in the flash memory block, each target data unit corresponding to one original error bit count; determining whether the first read interference count value meets the adjustment conditions based on the statistical information; if it does, determining a second read interference count value of the flash memory block based on the statistical information; if the second read interference count value is greater than the first threshold, performing data migration on the flash memory block. This application also provides corresponding apparatus and storage media. The technical solution of this application can improve the accuracy of evaluating the degree of read interference affecting a flash memory block using the read interference count value, and can also avoid unnecessary GC operations while ensuring data reliability, thereby extending the lifespan of the memory.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to a data processing method, apparatus, and storage medium. Background Technology

[0002] Flash memory storage systems, due to their excellent random access performance, high density, and low power consumption, have become important storage media and are widely used in embedded systems, portable laptops, data centers, and other fields requiring storage. NAND flash memory is a type of flash memory. During the application of NAND, various factors can cause changes in the voltage distribution carrying information, resulting in erroneous bits in the read data. In recent years, with the evolution of NAND manufacturing processes, read disturbance (RD) has gradually become a major factor affecting the number of erroneous bits in read data that urgently needs to be addressed.

[0003] NAND flash memory represents data by storing a certain amount of charge in memory cells. To improve storage density, NAND uses a series structure between memory cells, with multiple memory cells forming word lines horizontally. When reading data on a word line, a read voltage of a specific amplitude is applied to that word line. Memory cells in different word lines are connected by bit lines. To detect whether a memory cell being read is turned on, other memory cells in the series path need to be turned on beforehand. Therefore, other unread word lines will be given a turn-on voltage, the amplitude of which is greater than the read voltage. During this process, the turn-on voltage causes the unread word lines to be slightly programmed, resulting in a change in the voltage distribution carrying the information. Based on the physical structure of NAND, the basic storage unit in the logical structure of NAND is a page, and erase operations are performed in blocks. A block consists of multiple word lines, and a word line can be divided into one or more pages. Therefore, reading a page within a block affects the voltage of adjacent pages on the same word line, and other word lines adjacent to that word line are also affected. Although the voltage change from a single read operation is relatively small and has little impact on the voltage state, this impact accumulates with the number of reads. Continuous read operations cause voltage shifts, eventually leading to a voltage change in a different range. This voltage state change results in errors in the data stored in that page cell, ultimately causing flash memory read interference errors. Therefore, when performing read operations on NAND flash memory, repeatedly reading a block cell increases the error rate of the read data.

[0004] The common method for handling read disturbances in existing technologies is as follows: a read disturb count (RDC) is used to count the number of times each block is read, and the count is compared with a pre-defined threshold. Blocks whose read count exceeds the threshold will be erased and the data in the corresponding block unit will be rewritten through garbage collection (GC) and other means. The valid data is moved to a new block unit, and the read disturb count value is cleared to zero.

[0005] However, due to varying tolerances to read interference among different blocks in NAND flash memory, and the different levels of interference caused by different input / output (IO) models, the number of read operations that can be performed on different blocks varies significantly under different workloads. Therefore, the aforementioned read interference handling methods, which rely solely on the number of times each block in the NAND flash memory is read, cannot accurately measure the impact of read interference on each block. Furthermore, setting a uniform threshold to trigger GC operations to meet the reliability requirements of the data stored in NAND flash memory may not only lead to the failure or missed detection of early warnings for read interference in certain scenarios, but may also result in unnecessary GC operations, increasing the read / write coefficient of NAND flash memory and reducing its lifespan. Summary of the Invention

[0006] This application provides a data processing method that can not only improve the accuracy of the read interference count value in evaluating the degree of read interference affecting the flash memory block, but also avoid unnecessary GC operations and extend the lifespan of the memory while ensuring data reliability.

[0007] The first aspect of this application provides a data processing method, comprising: acquiring a first read interference count value of a flash memory block, wherein the read interference count value of the flash memory block is a changing value, and the first read interference count value is the read interference count value of the flash memory block at a specific moment; if the first read interference count value is not greater than a first threshold and the first read interference count value belongs to an adjustment interval, then acquiring statistical information, wherein the statistical information is obtained based on a first set, the first set including multiple original error bit counts corresponding to multiple target data units in the flash memory block, wherein each target data unit corresponds to one original error bit count, the first threshold and the adjustment interval are preset, a flash memory block whose read interference count value exceeds the first threshold can be considered to be affected by a greater degree of read interference, the first threshold can be set according to the average number of erase and write cycles of all flash memory blocks, the adjustment interval is an interval less than the first threshold, a target data unit refers to a target page in the flash memory block, or 1 / 2 page, 1 / 4 page or 1 / 8 page of a target page, etc.; and determining the first read interference count value based on the statistical information. Whether the adjustment conditions are met refers to whether the multiple original error bits of the flash memory block meet the expected distribution pattern and certain conditions. The expected distribution pattern means that the noise and abnormal conditions of the flash memory block are controllable. The statistical information is obtained based on multiple original error bits, which may include the largest error bit, the second largest error bit, the sum of the error bits of multiple original error bits, the square of the error bits of multiple original error bits, or the degree of difference of multiple original error bits, etc. If the conditions are met, the second read interference count value of the flash memory block is determined based on the statistical information. The second read interference count value is a count value that is corrected and adjusted based on the statistical information of the first read interference count value. If the second read interference count value is greater than the first threshold, the flash memory block is migrated. Specifically, this can be done by executing a GC read command to read the data in the flash memory block, and then executing a GC write command to write the data read by the GC read command to other flash memory blocks, thereby moving the data in the flash memory block to other flash memory blocks.

[0008] As can be seen from the first aspect above, by first setting a unified threshold and adjustment range for the read interference count value of the flash memory block, when the obtained first read interference count value of the flash memory block is less than the threshold and falls within the adjustment range, the first read interference count value is corrected using statistical information based on multiple original error bits of the flash memory block. Since the original error bits are a relatively direct measure of data reliability, the second read interference count value obtained by correcting the first read interference count value based on the statistical information of multiple original error bits has a higher accuracy in evaluating the degree of read interference affecting the flash memory block. Finally, based on this more accurate second read interference count value, it is determined whether data migration of the flash memory block is necessary. This not only improves the accuracy of the read interference count value in evaluating the degree of read interference affecting the flash memory block, but also avoids unnecessary GC operations and extends the lifespan of the memory while ensuring data reliability.

[0009] In conjunction with the first aspect of the embodiments of this application, in a first implementation of the first aspect of the embodiments of this application, the statistical information includes the difference degree of multiple original error bit counts and a first error bit count. The first error bit count is the original error bit count ranked Nth in descending order of value in the first set, where N is an integer greater than 0. For example, when N equals 1, the first error bit count is the largest original error bit count among multiple original error bit counts; when N equals 3, the first error bit count is the third original error bit count among multiple original error bit counts. The difference degree of multiple original error bit counts refers to the degree of dispersion among multiple original error bit counts, or in other words, it is used to represent the multiple original error bits. The degree of difference between the number of bits can be used to characterize the distribution of multiple original error bits. The method for characterizing the degree of difference among multiple original error bits can be to calculate the variance or standard deviation among multiple original error bits. The degree of difference among multiple original error bits can be used to indicate the similarity of multiple original error bits. When the degree of difference among multiple original error bits is smaller, it means that the similarity among multiple original error bits is greater, and vice versa. Based on statistical information, it is determined whether the first read interference count value meets the adjustment conditions, including: judging whether the first read interference count value meets the adjustment conditions based on the degree of difference among multiple original error bits and the first error bit.

[0010] As can be seen from the first implementation of the first aspect above, since the original number of error bits is a relatively direct measure of data reliability, judging whether the first read interference count needs to be adjusted based on the difference between multiple original error bits and the first error bit can better determine whether the first read interference count needs to be adjusted, improve the accuracy of the judgment and the reliability of the data, and improve the accuracy of the read interference count in evaluating the degree of read interference affecting the flash memory block.

[0011] In conjunction with the first implementation of the first aspect of this application, in the second implementation of the first aspect of this application, determining whether the first read interference count value meets the adjustment condition based on the difference degree and the first number of error bits includes: when the difference degree is less than or equal to a second threshold, determining whether the first number of error bits is greater than a third threshold; when the difference degree is less than or equal to the second threshold, it can be considered that the similarity of the multiple original error bit counts is relatively good and meets the expected distribution pattern; when the difference degree of the multiple original error bit counts is greater than the second threshold, it is considered that the similarity of the multiple original error bit counts is poor and does not meet the distribution pattern. If the value of the first number of error bits is large, the second read interference count value obtained after adjusting the first read interference count value based on the first number of error bits may have certain problems, for example, adjustment... Even after adjustment, the second read interference count is still relatively large, and the overall difference before and after adjustment is small. This fails to improve the accuracy of the read interference count in evaluating the degree of read interference experienced by the flash memory block. Therefore, in addition to determining that the number of original error bits meets the expected distribution pattern, it is also necessary to determine whether the number of the first error bits is greater than the third threshold. If the number of the first error bits is less than or equal to the third threshold, the first read interference count is determined to meet the adjustment conditions. When the difference is greater than the second threshold, it is determined whether the abnormal data in the first set can be processed. Abnormal data is one or more original error bits in the first set that are greater than the average number of original error bits of multiple target data units and cause the difference to be greater than the second threshold. If it is determined that the abnormal data in the first set can be processed, the first read interference count is determined to meet the adjustment conditions.

[0012] As can be seen from the second implementation method of the first aspect above, the original error bit count is a relatively direct measure of data reliability. By judging whether the first count value meets the adjustment conditions based on the differences of multiple original error bit counts and the first error bit count, the accuracy of the judgment can be improved, unnecessary GC operations of flash memory blocks can be avoided to a certain extent, and the service life of the memory can be extended.

[0013] In conjunction with the first implementation of the first aspect of this application, in the third implementation of the first aspect of this application, determining whether the first read interference count value meets the adjustment condition based on the difference degree and the first number of error bits includes: when the difference degree is less than or equal to a second threshold, determining whether the first number of error bits is greater than a third threshold; if the first number of error bits is less than or equal to the third threshold, determining that the first read interference count value meets the adjustment condition; when the difference degree is greater than the second threshold, determining whether the first number of error bits is greater than the third threshold; if the first number of error bits is less than or equal to the third threshold, determining that the first read interference count value meets the adjustment condition; if the first number of error bits is greater than the third threshold, determining whether abnormal data in the first set can be processed, wherein the abnormal data is the number of original error bits in the first set that is greater than the average of multiple target data units and causes the difference degree to be greater than the second threshold, or one or more original error bits; if it is determined that the abnormal data can be processed, determining that the first read interference count value meets the adjustment condition.

[0014] As can be seen from the third implementation of the first aspect above, in the process of judging whether the first count value meets the adjustment condition by the difference of multiple original error bits and the first error bit, when the distribution pattern of multiple original error bits does not meet the expected distribution pattern, it is also possible to first judge whether the first error bit in the statistical information is greater than the third threshold, and then further judge whether the first error bit meets the adjustment condition based on the size of the first error bit, which increases the diversity of judging whether the read interference count value of the flash memory block meets the adjustment condition.

[0015] In conjunction with the second or third implementation of the first aspect of this application, in the fourth implementation of the first aspect of this application, when the difference is less than or equal to the second threshold and the first number of error bits is less than or equal to the third threshold, if the conditions are met, then the second read interference count value of the flash memory block is determined according to statistical information, including: determining the second read interference count value according to the second number of error bits, there is a corresponding relationship between the second number of error bits and the second read interference count value, the second number of error bits is the original number of error bits with the largest value in the first set, the relationship between the second number of error bits and the second count value can change with the change of media characteristics or application strategy, and there can be multiple representation forms, such as tables, functions, etc. Specifically, multiple different intervals can be preset, the size of each interval can be the same or different, each interval corresponds to a second read interference count value, and the corresponding second read interference count value can be determined based on the interval to which the second number of error bits belongs.

[0016] As can be seen from the fourth implementation method of the first aspect above, when the difference is less than or equal to the second threshold, and the first number of error bits is less than or equal to the third threshold, and the first count value meets the adjustment conditions, the second count value can be determined based on the second number of error bits according to the pre-set correspondence, thereby correcting the measurement error of the read interference count by means of the second number of error bits, improving the reliability of the data and avoiding unnecessary GC operations. In addition, the correspondence has flexible configurability, which makes the implementation of the scheme diverse.

[0017] In conjunction with the fourth implementation of the first aspect of the present application, in the fifth implementation of the first aspect of the present application, determining the second read interference count value based on the second number of error bits, wherein there is a correspondence between the second number of error bits and the second read interference count value, includes: determining the target interval to which the second number of error bits belongs, wherein the target interval is one of multiple intervals, and each of the multiple intervals corresponds to a count value; and determining the second read interference count value based on the target interval.

[0018] As can be seen from the fifth implementation method of the first aspect above, by using interval partitioning to represent the correspondence between the second error bit number and the second read interference count value, not only can the reliability of the data be guaranteed, but also the flexibility and configurability of the correspondence can be guaranteed.

[0019] In conjunction with the second or third implementation of the first aspect of the present application, in the sixth implementation of the first aspect of the present application, when it is determined that abnormal data can be processed, if the conditions are met, the second read interference count value of the flash memory block is determined based on statistical information, including: determining the second read interference count value based on the third error bit count, wherein there is a corresponding relationship between the third error bit count and the second read interference count value, the third error bit count is the largest original error bit count in the second set, and the second set is a set of one or more original error bit counts obtained after processing the abnormal data.

[0020] As can be seen from the sixth implementation method of the first aspect above, when it is determined that abnormal data can be processed and the first read interference count value meets the adjustment conditions, the measurement error of the read interference count can be corrected based on the pre-set correspondence and the third error bit number, thereby improving the reliability of the data and avoiding unnecessary GC operations. In addition, the correspondence has flexible configurability, making the implementation of the solution diverse.

[0021] In conjunction with the sixth implementation of the first aspect of the present application, in the seventh implementation of the first aspect of the present application, determining the second read interference count value based on the third error bit count, wherein there is a correspondence between the third error bit count and the second read interference count value, includes: determining the target interval to which the third error bit count belongs, wherein the target interval is one of multiple intervals, and each of the multiple intervals corresponds to a count value; and determining the second read interference count value based on the target interval.

[0022] In conjunction with any of the second to seventh implementations of the first aspect of the present application, in the eighth implementation of the first aspect of the present application, when the abnormal data includes abnormal large data, the abnormal large data is one or more original error bits ranked in descending order of value in the first set, where M is an integer greater than 0. For example, when M=1, the abnormal large data is the largest original error bit among the multiple original error bits; when M=3, the abnormal large data is the three original error bits ranked in descending order of value. The implementation also includes: data migration of the target data unit corresponding to the abnormal large data.

[0023] In conjunction with the first aspect of the embodiments of this application and any one of the first to eighth implementations of the first aspect, in the ninth implementation of the first aspect of the embodiments of this application, obtaining statistical information includes: reading a codeword of a target data unit, wherein the codeword is any codeword in the data stored in the target data unit; decoding the codeword to obtain a decoding result; if decoding fails, determining the original number of error bits of the target data unit as a second preset value, wherein the second preset value can be a pre-set infinite value represented within a finite range; if decoding succeeds, determining the original number of error bits of the target data unit based on the Hamming distance between the codeword and the decoding result; and determining statistical information based on the original number of error bits of multiple target data units.

[0024] In conjunction with the ninth implementation of the first aspect of the present application, in the tenth implementation of the first aspect of the present application, before reading a codeword of a target data unit, the method further includes: setting the reading voltage of multiple target data units to a preset voltage. The setting of the preset voltage may be determined according to the characteristics of the NAND flash memory. The characteristics of the NAND flash memory may refer to whether the original number of error bits of the target page corresponding to the target data unit is sensitive to influencing factors other than read interference. Correspondingly, reading a codeword of a target data unit includes: reading a codeword of the target data unit under the preset voltage.

[0025] In conjunction with the tenth implementation of the first aspect of the embodiments of this application, in the eleventh implementation of the first aspect of the embodiments of this application, the preset voltage is either the default read voltage or the optimal read voltage updated online. Based on the characteristics of NAND flash memory, if the original number of error bits of the target page corresponding to the target data unit is sensitive to multiple factors, the optimal read voltage updated online by the system can be selected as the preset voltage; otherwise, the default read voltage can be selected as the preset voltage to reduce complexity.

[0026] As can be seen from the eleventh implementation of the first aspect above, the correlation between the impact of read interference on the flash memory block and the original number of erroneous bits read can be improved by selecting an appropriate preset voltage, thereby improving the accuracy of the data.

[0027] In conjunction with any of the second to eleventh implementations of the first aspect of the embodiments of this application, in the twelfth implementation of the first aspect of the embodiments of this application, the flash memory block contains pages of different types, and the different types of pages correspond to different count value increments. The different count value increments corresponding to the different types of pages can be preset. The first read interference count value of the flash memory block is determined based on the number of times the different types of pages are read and the count value increments corresponding to the different types of pages.

[0028] In conjunction with the twelfth implementation of the first aspect of the present application, the thirteenth implementation of the first aspect of the present application, after obtaining the statistical information, further includes: correcting the different count value increments based on the statistical information.

[0029] In conjunction with the thirteenth implementation of the first aspect of this application, in the fourteenth implementation of the first aspect of this application, the correction of different count increments based on statistical information includes: correcting different count increments based on the second error bit number to obtain different update count increments corresponding to different types of pages. The second error bit number is the largest original error bit number among multiple original error bit numbers. The update count increment and the second error bit number are positively correlated. The positive correlation between the update count increment and the second error bit number for different types of pages can be the same or different.

[0030] In conjunction with any of the first to fourteenth implementations of the first aspect of the embodiments of this application, in the fifteenth implementation of the first aspect of the embodiments of this application, after determining whether the first read interference count value meets the adjustment conditions based on statistical information, the method further includes: if it does not meet the conditions, then performing data migration on the flash memory block.

[0031] In conjunction with the first aspect of the embodiments of this application and any one of the first to fifteenth implementations of the first aspect, in the sixteenth implementation of the first aspect of the embodiments of this application, after data migration of the flash memory block, the method further includes: setting the read interference count value of the flash memory block to a first preset value. The first preset value can be 0, that is, clearing the read interference count value of the flash memory block to zero, or it can be non-zero, set according to certain rules, thereby avoiding congestion problems caused by GC operations and other processing behavior problems in the memory to a certain extent.

[0032] In conjunction with the first aspect and any one of the first to sixteenth implementations of the first aspect of this application, in the seventeenth implementation of the first aspect of this application, the multiple target data units correspond to all pages in the flash memory block, pages of the same type in the flash memory block, or pages in the flash memory block whose read voltage includes the erase state decision voltage. As can be seen from the seventeenth implementation of the first aspect, the multiple target data units can be certain specific pages in the flash memory block. Due to the negative externality of read interference, using a general sampling method to collect the original error bit count carries the risk of missed detections and cannot guarantee data reliability. Furthermore, collecting the original error bit count for all pages in the flash memory block while only considering data reliability incurs significant overhead. Therefore, when the multiple target data units correspond to certain specific pages in the flash memory block, not only can data reliability be guaranteed, but the overhead of data collection can also be reduced, improving system performance.

[0033] A second aspect of this application provides a data processing apparatus, comprising: an acquisition module, configured to acquire a first read interference count value of a flash memory block; the acquisition module is further configured to acquire statistical information when the first read interference count value is not greater than a first threshold and the first read interference count value belongs to an adjustment range, the statistical information being obtained based on a first set, the first set including multiple original error bit counts corresponding to multiple target data units in the flash memory block, wherein each target data unit corresponds to one original error bit count; a judgment module, configured to determine whether the first read interference count value meets the adjustment conditions based on the statistical information acquired by the acquisition module; a determination module, configured to determine a second read interference count value of the flash memory block based on the statistical information when the judgment module determines that the first read interference count value meets the adjustment conditions; and a data migration module, configured to perform data migration on the flash memory block when the second read interference count value determined by the determination module is greater than the first threshold.

[0034] In conjunction with the second aspect of the embodiments of this application, in the first implementation of the second aspect of the embodiments of this application, the statistical information includes the difference degree of multiple original error bit numbers and the first error bit number, the first error bit number is the original error bit number ranked N in descending order of value in the first set, N is an integer greater than 0, and the judgment module is used to determine whether the first read interference count value meets the adjustment condition based on the difference degree and the first error bit number.

[0035] In conjunction with the first implementation of the second aspect of the embodiments of this application, in the second implementation of the second aspect of the embodiments of this application, the judgment module is used to determine whether the first number of error bits is greater than a third threshold when the difference is less than or equal to a second threshold; when the difference is greater than the second threshold, it is used to determine whether the abnormal data in the first set can be processed, wherein the abnormal data is the number of original error bits in the first set that is greater than the average of the number of original error bits of multiple target data units, and causes the difference to be greater than the second threshold of one or more original error bits; the determination module is further used to determine that the first read interference count value meets the adjustment condition when the judgment module determines that the first number of error bits is less than or equal to the third threshold; and when the difference is greater than the second threshold and the abnormal data in the first set can be processed, it is determined that the first read interference count value meets the adjustment condition.

[0036] In conjunction with the first implementation of the second aspect of this application, in the third implementation of the second aspect of this application, the judgment module is used to determine whether the first number of error bits is greater than a third threshold when the difference is less than or equal to a second threshold; when the difference is greater than the second threshold, determine whether the first number of error bits is greater than the third threshold; when the difference is greater than the second threshold and the first number of error bits is greater than the third threshold, determine whether the abnormal data in the first set can be processed, wherein the abnormal data is the average number of original error bits of multiple target data units in the first set that is greater than the difference. The system determines the first read interference count value if the difference is less than or equal to the second threshold and the first read interference count value is less than or equal to the third threshold. It also determines if the difference is greater than the second threshold and the first read interference count value is less than or equal to the third threshold. Furthermore, it determines if the difference is greater than the second threshold and the first read interference count value is greater than the third threshold, and if the system determines that abnormal data can be processed, it determines that the first read interference count value meets the adjustment conditions.

[0037] In conjunction with the second or third implementation of the second aspect of the present application, in the fourth implementation of the second aspect of the present application, the determining module is used to determine the second read interference count value based on the second error bit number when the difference is less than or equal to the second threshold and the first error bit number is less than or equal to the third threshold. There is a corresponding relationship between the second error bit number and the second read interference count value. The second error bit number is the original error bit number with the largest value in the first set.

[0038] In conjunction with the fourth implementation of the second aspect of the present application, in the fifth implementation of the second aspect of the present application, the determining module is used to determine the target interval to which the second error bit count belongs, the target interval being one of multiple intervals, each of the multiple intervals corresponding to a count value; and to determine the second read interference count value based on the target interval.

[0039] In conjunction with the second or third implementation of the second aspect of the embodiments of this application, in the sixth implementation of the second aspect of the embodiments of this application, the determining module is used to determine the second read interference count value based on the third error bit number when it is determined that abnormal data can be processed. There is a corresponding relationship between the third error bit number and the second read interference count value. The third error bit number is the original error bit number with the largest value in the second set. The second set is a set of one or more original error bit numbers obtained after processing the abnormal data.

[0040] In conjunction with the sixth implementation of the second aspect of the present application, in the seventh implementation of the second aspect of the present application, a determining module is used to determine the target interval to which the third error bit count belongs, the target interval being one of multiple intervals, each of the multiple intervals corresponding to a count value; and to determine the second read interference count value based on the target interval.

[0041] In conjunction with any of the second to seventh implementations of the second aspect of the present application, in the eighth implementation of the second aspect of the present application, the data migration module is further configured to perform data migration on the target data unit corresponding to the abnormal big data when the abnormal big data includes abnormal big data, wherein the abnormal big data is one or more original error bits ranked in descending order of value in the first set, and M is an integer greater than 0.

[0042] In conjunction with the second aspect of the embodiments of this application, and any one of the first to eighth implementations of the second aspect, in the ninth implementation of the second aspect of the embodiments of this application, the acquisition module is used to read a codeword of the target data unit, wherein the codeword is any codeword in the data stored in the target data unit; decode the codeword to obtain a decoding result; if the decoding fails, determine the original number of error bits of the target data unit as a second preset value; if the decoding succeeds, determine the original number of error bits of the target data unit according to the Hamming distance between the codeword and the decoding result; and determine statistical information based on the original number of error bits of multiple target data units.

[0043] In conjunction with the ninth implementation of the second aspect of the present application, the tenth implementation of the second aspect of the present application further includes a setting module, which is used to set the reading voltage of multiple target data units to a preset voltage before the acquisition module reads a codeword of the target data unit; correspondingly, the acquisition module is used to read a codeword of the target data unit under the preset voltage set by the setting module.

[0044] In conjunction with the tenth implementation of the second aspect of the embodiments of this application, in the eleventh implementation of the second aspect of the embodiments of this application, the preset voltage is either the default reading voltage or the optimal reading voltage updated online.

[0045] In conjunction with any of the second to eleventh implementations of the second aspect of the present application, in the twelfth implementation of the second aspect of the present application, the flash memory block contains pages of different types, and the different types of pages correspond to different count value increments. The first read interference count value of the flash memory block is determined based on the number of times the different types of pages are read and the count value increments corresponding to the different types of pages.

[0046] In conjunction with the twelfth implementation of the second aspect of the embodiments of this application, the thirteenth implementation of the second aspect of the embodiments of this application further includes: a correction module, used to correct the different count value increments based on the statistical information obtained by the acquisition module.

[0047] In conjunction with the thirteenth implementation of the second aspect of the present application, in the fourteenth implementation of the second aspect of the present application, the correction module is used to correct different count value increments according to the second error bit number to obtain different update count value increments corresponding to different types of pages. The second error bit number is the original error bit number with the largest value in the first set, and the update count value increment is positively correlated with the second error bit number.

[0048] In conjunction with any one of the first to fourteenth implementations of the second aspect of the present application, in the fifteenth implementation of the second aspect of the present application, the data migration module is further configured to perform data migration on the flash memory block after the judgment module determines that the first read interference count value does not meet the adjustment conditions.

[0049] In conjunction with any one of the first to fifteenth implementations of the second aspect of the present application, in the sixteenth implementation of the second aspect of the present application, the data migration apparatus is further configured to set the read interference count value of the flash memory block to a first preset value after data migration of the flash memory block.

[0050] In conjunction with any one of the first to sixteenth implementations of the second aspect of the present application, in the seventeenth implementation of the second aspect of the present application, the plurality of target data units correspond to all pages in the flash memory block, pages of the same type in the flash memory block, or pages in the flash memory block whose read voltage includes the erase state decision voltage.

[0051] A third aspect of this application provides a storage device including a processor and a computer-readable storage medium storing a computer program; the processor is coupled to the computer-readable storage medium, and the computer program, when executed by the processor, implements the data processing method provided in the first aspect and any possible implementation thereof.

[0052] A fourth aspect of this application provides a computer-readable storage medium storing instructions that, when executed on a storage device, enable the storage device to perform the data processing method described in the first aspect or any possible implementation thereof.

[0053] The fifth aspect of this application provides a computer program product containing instructions that, when run on a storage device, enables the storage device to execute the image processing method described in the first aspect or any possible implementation thereof.

[0054] In the technical solution provided in this application embodiment, a unified threshold and adjustment range are first set for the read interference count value of the flash memory block. When the first read interference count value of the obtained flash memory block is less than the threshold and belongs to the adjustment range, the first read interference count value is corrected using statistical information based on multiple original error bits of the flash memory block. Since the original error bits are a relatively direct measure of data reliability, the second read interference count value obtained by correcting the first read interference count value based on the statistical information of multiple original error bits has a higher accuracy in evaluating the degree of impact of read interference on the flash memory block. Finally, based on the more accurate second read interference count value, it is determined whether data migration of the flash memory block is required. This not only improves the accuracy of the read interference count value in evaluating the degree of impact of read interference on the flash memory block, but also avoids unnecessary GC operations and improves the lifespan of the memory while meeting data reliability requirements. Attached Figure Description

[0055] Figure 1 A schematic diagram of a network architecture provided for an embodiment of this application;

[0056] Figure 2 A schematic diagram of an embodiment of the data processing method provided in this application;

[0057] Figure 3 A schematic diagram illustrating an embodiment of obtaining statistical information provided in this application;

[0058] Figure 4(1) is a schematic diagram of an embodiment of the present application that provides a method for determining whether the first reading interference count value meets the adjustment conditions based on statistical information;

[0059] Figure 4(2) is a schematic diagram of another embodiment of the present application, which provides a method for determining whether the first reading interference count value meets the adjustment conditions based on statistical information.

[0060] Figure 5 A schematic diagram of another embodiment of the data processing method provided in this application;

[0061] Figure 6 This is a schematic diagram of a data processing apparatus provided in an embodiment of this application. Detailed Implementation

[0062] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Those skilled in the art will recognize that, with the evolution of memory manufacturing processes and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems, such as similar technical problems based on different types of storage media.

[0063] This application provides a data processing method that sets a uniform threshold and adjustment range for the read interference count value of a flash memory block. When the first read interference count value of the acquired flash memory block is less than the threshold and falls within the adjustment range, since the original error bit count is a relatively direct measure of data reliability, the statistical information of multiple original error bit counts of the flash memory block is used to correct the first read interference count value, thereby obtaining a second read interference count value with higher accuracy in evaluating the degree of read interference affecting the flash memory block. Based on the second read interference count value, it is determined whether data migration of the flash memory block is necessary, thereby improving the accuracy of the read interference count value in assessing the degree of read interference affecting the flash memory block. While ensuring data reliability, unnecessary GC operations are avoided, and the lifespan of the memory is extended. This invention also provides corresponding devices and storage media, which will be described in detail below.

[0064] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0065] Figure 1 This is a schematic diagram of a network architecture provided for an embodiment of this application.

[0066] like Figure 1 As shown, the network architecture in this embodiment includes a host 11 and a storage device 12, which are connected to each other. The storage device 12 can be an embedded storage device such as a solid-state drive (SSD), universal flash storage (UFS), or an embedded multimedia card (eMMC), and is used to execute operation commands issued by the host 11.

[0067] Storage device 12 includes a controller 121, a flash array 122, and a communication interface 124. The communication interface 124 is used to communicate with devices such as the host 11, for example, to receive operation commands issued by the host 11. The communication interface 124 can be a non-volatile memory express (NVMe), a serial attached small computer system interface (SAS), a peripheral component interconnect express (PCIe), or an interface such as UFS or eMMC.

[0068] Storage device 12 may further include memory 123. Controller 121 is connected to memory 123. Memory 123 may exist independently and be connected to controller 121 via bus 125. Memory 123 may also be integrated with controller 121. Memory 123 can be used to store software programs and application modules. Controller 121 executes various operation instructions and responds to data processing by running the software programs and application modules stored in memory 123. It is understood that memory 123 in this embodiment may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory 123 described herein is intended to include, but is not limited to, these and any other suitable types of memory. The memory 123 primarily includes a program storage area. This program storage area may store the operating system, applications required for at least one function, such as applications required to execute various operating instructions, etc.

[0069] like Figure 1As shown, the controller 121, flash memory array 122, memory 123, and communication interface 124 are all interconnected via bus 125. The storage device 12 is managed using address space virtualization. All flash memory arrays 122 contain multiple flash memory modules, each consisting of thousands of identical physical blocks. The size of each physical block typically ranges from hundreds of KB to several MB. Each physical block is further divided into several identical pages. It should be noted that in this document, physical blocks are sometimes referred to as flash memory blocks, and the terms "physical block" and "flash memory block" are used interchangeably in this embodiment.

[0070] The controller 121 can execute I / O write commands issued by the host. When writing data, the controller 121 writes data to the flash array 122 in page-by-page increments. After writing data, when the host 11 needs to read data, the controller 121 executes the I / O read command issued by the host 11 to read the data previously written to the flash array 122.

[0071] If garbage data exists in a physical block, the controller 121 will erase the garbage data in the physical block through GC operations, so that when there is a need to write data later, the data to be written can be written to the clean physical block at the page level. GC operations are implemented through read commands for data reading (referred to as "GC read commands" in this application) and write commands for data writing (referred to as "GC write commands" in this application). When erasing garbage data in a physical block, the controller 121 will read the valid data in the physical block by executing GC read commands, and then write the valid data read by executing GC write commands to other physical blocks, thereby moving the valid data in the physical block to other physical blocks, and thus erasing the physical block into a clean physical block. Therefore, the operation commands that the controller 121 can execute include I / O read commands, I / O write commands, GC write commands, and GC read commands. After receiving an operation command, the controller 121 identifies the physical block accessed when the operation command is to be executed. It then saves the operation command to the waiting queue corresponding to the flash memory of the physical block accessed when the operation command is to be executed. The controller 121 can process the operation commands in the waiting queue corresponding to the flash memory in the order they were stored. The controller 121 can be implemented by reading and executing program instructions stored in the memory 123, or by hardware processing circuits without program instruction processing capabilities. For example, it can be an Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or a processor. It can also be implemented through a combination of hardware and software; this embodiment does not limit this approach.

[0072] Since the physical block accessed by the controller 121 when executing an I / O read command is determined by the host 11, the controller 121 can confirm the physical block accessed by the I / O read command based on the information in the I / O read command. However, for I / O write commands, GC write commands, and GC read commands, the controller 121 can confirm the physical block accessed when executing the operation command based on the physical blocks in the flash array 122 and the amount and type of data storage in the flash memory. Therefore, the physical block accessed by the controller 121 when executing an I / O read command is passively determined, while the controller 121 can actively determine the physical block accessed when executing I / O write commands, GC write commands, and GC read commands.

[0073] This application provides a data processing method that can be applied to... Figure 1 The storage device 12 can be specifically executed by the controller 121 within the storage device 12, such as... Figure 2 The diagram shown is a schematic representation of an embodiment of the data processing method provided in this application.

[0074] See Figure 2 One embodiment of the data processing method provided in this application may include:

[0075] 21. The controller obtains the first read interference count value of the flash memory block.

[0076] In this embodiment, the read interference count of the flash memory block is a variable value, which can be implemented by a counting program. When any page in the flash memory block is actually read once, the read interference count of the flash memory block increases. For example, when any page in the flash memory block is actually read once, the count increases by 1. It should be noted that the increase in the count value when any page in the flash memory block is actually read once can also be other values, and this embodiment does not limit this.

[0077] The first read interference count value is the read interference count value of the flash memory block at a specific moment, such as the current moment. The controller can directly read the count value of the counting unit executing the counting program at a specific moment to obtain the first read interference count value of the flash memory block at that specific moment.

[0078] Optionally, in this embodiment, the flash memory block may contain different types of pages, and different types of pages may correspond to different count increments. The first count value of the read interference count of the flash memory block may be determined based on the number of times each type of page is read and the count increment corresponding to each type of page. For example, if the flash memory block contains three types of pages, A, B, and C, the controller may set the count increment corresponding to type A pages to 'a', the count increment corresponding to type B pages to 'b', and the count increment corresponding to type C pages to 'c'. When any page of a certain type in the flash memory block is read once, the count value of the read interference count increases accordingly by the corresponding count increment. Therefore, the first count value obtained by the flash memory block may be determined based on the number of times each type of page in the flash memory block is read and the corresponding count increment. For example, if the number of times types A, B, and C pages are read are 2, 3, and 0 respectively, then the first count value may be 2a + 3b + 0.

[0079] 22. If the first read interference count value is not greater than the first threshold and the first read interference count value is within the adjustment range, the controller obtains statistical information. The statistical information is obtained based on the first set, which includes multiple original error bit counts corresponding to multiple target data units in the flash memory block. Each target data unit corresponds to one original error bit count.

[0080] In this embodiment, the first threshold and the adjustment range are preset. The first threshold can be set based on the average program / erase cycling (PE) count of all flash memory blocks. Specifically, the controller can set multiple ranges, each corresponding to a threshold. The controller can determine the first threshold based on the range to which the average PE count of all flash memory blocks belongs. Flash memory blocks whose read interference count exceeds the first threshold are considered to be significantly affected by read interference. In this case, the controller can directly perform data migration on the flash memory block. In this embodiment, the adjustment range is a range smaller than the first threshold. For example, when the first threshold is x, the adjustment range can be set to 70% to 90% of the first threshold, i.e., the adjustment range is (0.7x, 0.9x).

[0081] After obtaining the first read interference count value of the flash memory block, the controller first compares the first read interference count value with the first threshold. If the first read interference count value is less than or equal to the first threshold and the first read interference count value is within the preset adjustment range, the controller obtains the statistical information of the flash memory block. This statistical information is obtained based on the first set of multiple original error bit counts corresponding to multiple target data units in the flash memory block. One target data unit corresponds to one original error bit count.

[0082] In this embodiment, the controller can use pages as the sampling unit, meaning one target data unit refers to a target page in a flash memory block. The controller samples the raw error bit count for each target page, with each target page corresponding to one raw error bit count. Alternatively, the sampling unit in this embodiment can be 1 / 2 page, 1 / 4 page, or 1 / 8 page, etc. In this case, the controller samples the raw error bit count for the target page using 1 / 2 page, 1 / 4 page, or 1 / 8 page as a sampling unit. In this case, one target data unit refers to 1 / 2 page, 1 / 4 page, or 1 / 8 page within the target page. Each target page corresponds to 2, 4, or 8 target data units, and each target data unit corresponds to one raw error bit count. It should be noted that the sampling unit in this embodiment can also have other division methods, which are not limited in this embodiment.

[0083] The statistical information in this application embodiment is obtained based on multiple original error bit counts, which may include various types of information obtained by statistical analysis of multiple original error bit counts.

[0084] Optionally, the statistical information in this application embodiment may include a first error bit count, which is the Nth original error bit count ranked in descending order among multiple original error bit counts, where N is an integer greater than 0. N can be equal to 1. When N is equal to 1, the first error bit count is the largest original error bit count among multiple original error bit counts, i.e., the second error bit count. When N is equal to 2, the first error bit count is the second largest error bit count among multiple original error bit counts. It is understood that N can also be other values, and this application embodiment does not limit this.

[0085] Optionally, the statistical information may also include the sum of the number of faulty bits of multiple original faulty bits, the average of multiple original faulty bits, or the sum of squares of multiple original faulty bits, quantiles, medians, the frequency proportion of the mode, etc. In addition, the statistical information in the embodiments of this application may also include other information, and the embodiments of this application do not specifically limit this information.

[0086] Optionally, in this embodiment, the flash memory block may contain different types of pages, and different types of pages may correspond to different count increments. These different count increments for different types of pages may be pre-set. In this embodiment, after acquiring statistical information, the controller may also correct the different count increments corresponding to different types of pages based on the acquired statistical information.

[0087] Specifically, the controller can correct the different count increments corresponding to different types of pages based on the second error bit count contained in the statistical information to obtain different update count increments corresponding to those different types of pages. The different update count increments corresponding to those different types of pages can be positively correlated with the second error bit count. For example, if a flash memory block contains three types of pages, A, B, and C, the controller pre-sets the count increments corresponding to the three types of pages as a, b, and c, respectively. After obtaining the statistical information, which contains the second error bit count, the controller can correct the original count increments a, b, and c based on the second error bit count. The larger the second error bit count, the greater the correction percentage. For example, when the second error bit count is x, a, b, and c are corrected to (1+10%)a, (1+12%)b, and (1+18%)c, respectively; when the second error bit count is 2x, a, b, and c are corrected to (1+19%)a, (1+23%)b, and (1+25%)c, respectively. The controller may also correct the different count increments corresponding to different types of pages based on the average of multiple original error bit counts contained in the statistical information, so as to obtain different update count increments corresponding to the different types of pages. In addition, the controller may also correct the different count increments corresponding to different types of pages based on other information contained in the statistical information, which is not limited in this embodiment.

[0088] Optionally, in this embodiment, the target page can refer to all pages in the flash memory block, and multiple target data units correspond to all pages in the flash memory block. That is, the controller 121 uses 1 page, 1 / 2 page, 1 / 4 page, or 1 / 8 page as sampling units to sample the original error bit count of all pages in the flash memory block. The target page can also refer to all pages of the same type in the flash memory block, in which case multiple target data units correspond to all pages of the same type in the flash memory block. For example, the page where all least significant bits (LSBs) in the flash memory block are located. The target page can also be a page in the flash memory block whose read voltage includes the erase state judgment voltage, in which case multiple target data units correspond to all pages in the flash memory block whose read voltage includes the erase state judgment voltage. This embodiment does not limit this.

[0089] 23. The controller determines whether the first reading interference count value meets the adjustment conditions based on the statistical information.

[0090] In this embodiment of the application, after obtaining statistical information, the controller can determine whether the first read interference count value of the flash memory block meets the adjustment conditions based on the statistical information.

[0091] In this embodiment, since the original error bit count is a relatively direct measure of data reliability, when the first read interference count is not greater than the first threshold and falls within the adjustment range, the distribution of multiple original error bits in the flash memory block can reflect the reliability of the first read interference count to a certain extent. Therefore, the distribution of multiple original error bits in the flash memory block can be used to determine whether the first read interference count needs to be corrected, thereby adjusting to obtain a more accurate read interference count, reducing the error of the flash memory block's read interference count to a certain extent, and avoiding unnecessary GC operations. Therefore, in this embodiment, the controller determines whether the first read interference count meets the adjustment conditions based on statistical information, specifically, the controller determines whether the multiple original error bits in the flash memory block meet the expected distribution pattern and certain conditions based on statistical information. In this embodiment, the expected distribution pattern means that the noise and abnormal conditions of the flash memory block are controllable. Therefore, if the distribution of multiple original error bits meets the expected distribution pattern, it means that the noise and abnormal conditions of the multiple original error bits are controllable. When the multiple original error bits meet the expected distribution pattern and certain conditions, the flash memory block can determine that the first read interference count value meets the adjustment conditions, and thus the first read interference count value can be adjusted. Otherwise, it means that the first read interference count value does not meet the adjustment conditions.

[0092] It should be noted that different flash memory media have different tolerances to read interference. Therefore, the expected distribution pattern of multiple original error bits may also be different for different flash memory media. Therefore, the embodiments of this application do not make specific limitations on the expected distribution pattern corresponding to the flash memory block.

[0093] In this embodiment of the application, the statistical information is obtained from multiple original error bit counts, and the controller determines whether the multiple original error bit counts meet the expected distribution pattern and certain conditions based on the statistical information.

[0094] Based on step 22 above, it can be seen that the statistical information in this application embodiment can include various types of information, such as the first number of error bits, the sum of the error bits of multiple original error bits, the average of multiple original error bits, or the sum of squares of multiple original error bits, quantiles, medians, the frequency proportion of the mode, etc. Therefore, based on different statistical information, the controller's method for judging whether multiple original error bits meet the expected distribution pattern is also different, that is, the adjustment conditions for the controller to judge whether the first read interference count value needs to be adjusted are also different.

[0095] Optionally, the distribution of multiple original error bits can be characterized by the degree of difference between the multiple original error bits, or by the absolute value between the median and the average of the multiple original error bits. Alternatively, it can be characterized by the proportion of the mode among the multiple original error bits. Based on any of the above characterization methods, the characterization results are used to determine whether the distribution of multiple original error bits meets the expected distribution pattern.

[0096] Specifically, this application embodiment will take the difference in the number of original error bits as an example to characterize the distribution of the number of original error bits, and will specifically introduce whether the controller in this application embodiment judges whether the first read interference count value meets the adjustment conditions based on statistical information. Please refer to the specific description in Figure 4(1) and Figure 4(2) below.

[0097] 24. If satisfied, the controller determines the second read interference count value of the flash memory block based on the statistical information.

[0098] In this embodiment, after the controller determines that the first read interference count value of the flash memory block meets the adjustment conditions, the controller adjusts the first read interference count value to a second read interference count value. In this embodiment, the second read interference count value is the count value that the controller uses to correct and adjust the first read interference count value, and the second read interference count value is determined by the controller based on statistical information.

[0099] Specifically, the statistical information in this embodiment may include a first error bit count. The controller determines a second read interference count value for the flash memory block based on the statistical information, specifically, the second read interference count value may be determined based on the first error bit count. There is a pre-set correspondence between the first error bit count and the second read interference count value. The controller determines the second read interference count value based on the first error bit count and the pre-set correspondence. The first error bit count may be the maximum error bit count or the second largest error bit count. It should be noted that in practical applications, the first error bit count can be selected according to actual needs. For example, the first error bit count may be any one of the first 20% of the original error bit counts in descending order of value; this embodiment does not limit this.

[0100] Optionally, in this embodiment, the correspondence between the first number of error bits and the second read interference count value can be presented in tabular form, as shown in Table 1, which is a table showing the correspondence between the first number of error bits and the target read interference count value in this embodiment.

[0101] Table 1. Correspondence between the number of first error bits and the target read interference count.

[0102] Table Header Return value E0 RDC0 E1 RDC1 … … En RDCn

[0103] In Table 1, the headers E0, E1, ..., En are multiple different intervals of pre-set count values. The size of each interval can be the same or different. This application does not limit this. The return values ​​RDC0, RDC1, ..., RDCn are the target read interference count values ​​corresponding to each interval.

[0104] Optionally, in this embodiment of the application, the target read interference count value is the second read interference count value corresponding to the first number of error bits. Based on the correspondence shown in Table 1, the controller can determine the second read interference count value according to the first number of error bits in the following specific method: The controller first determines the target interval to which the first number of error bits belongs. For example, if the first number of error bits is x, the interval to which x belongs is Ex, where Ex is an interval from E0 to En. Then, based on the target interval Ex to which the first number of error bits x belongs, the controller determines the corresponding target read interference count value as the return value RDCx, which is the second read interference count value.

[0105] Optionally, the target read interference count value in this embodiment can also be an intermediate adjustment value between the first error bit count and the second read interference count value during the adjustment process. That is, after the controller determines the corresponding target read interference count value as the return value RDCx based on the target interval to which the first error bit count belongs, the target read interference count value is an intermediate adjustment value between the first error bit count and the second read interference count value. The controller also needs to further modify this intermediate adjustment value to obtain the second read interference count value. For example, if the target read interference count value is the return value RDCx, then the second read interference count value is RDCx + (x % Mask), where Mask is a preset value, "%" is the modulo operation, and "x % Mask" means taking the modulo of x according to Mask.

[0106] In this embodiment of the application, the correspondence between the first number of error bits and the second read interference count can be presented in the form of a table, or the correspondence in Table 1 can be represented by a piecewise function, a polynomial function, etc. This embodiment of the application does not limit this.

[0107] 25. If the second read interference count value is greater than the first threshold, the controller performs data migration on the flash memory block.

[0108] In this embodiment of the application, after the controller determines the second read interference count value of the flash memory block, it will determine whether the second read interference count value is greater than the first threshold. If the second read interference count value is greater than the first threshold, the controller will perform data migration on the flash memory block.

[0109] Specifically, the controller can read data from the flash memory block by executing a GC read command, and then write the data read by executing a GC write command to other flash memory blocks, thereby moving the data in the flash memory block to other flash memory blocks.

[0110] In this embodiment, a unified threshold and adjustment range are first set for the read interference count value of the flash memory block. When the first read interference count value of the acquired flash memory block is less than the threshold and falls within the adjustment range, the first read interference count value is corrected using statistical information based on multiple original error bit counts of the flash memory block. Since the original error bit count is a relatively direct measure of data reliability, the second read interference count value obtained by correcting the first read interference count value based on the statistical information of multiple original error bit counts has higher accuracy in evaluating the degree of read interference affecting the flash memory block. Finally, based on the more accurate second read interference count value, it is determined whether data migration of the flash memory block is required. This not only improves the accuracy of the read interference count value in evaluating the degree of read interference affecting the flash memory block, but also avoids unnecessary GC operations and extends the lifespan of the memory while ensuring data reliability.

[0111] based on Figure 2 In the embodiments described above, the statistical information is obtained based on multiple original error bit counts. This application will first provide a detailed description of the method for obtaining the statistical information in step 22, such as... Figure 3 The diagram shown is a schematic representation of an embodiment of the controller acquiring statistical information provided in this application.

[0112] See Figure 3 One embodiment of obtaining statistical information provided in this application may include:

[0113] 221. Set the reading voltage of the plurality of target data units to a preset voltage.

[0114] In this embodiment of the application, when the controller acquires the number of original error bits corresponding to multiple target data units, it first sets the reading voltage of the multiple target data units to a preset voltage.

[0115] In this embodiment, the preset voltage can be determined based on the characteristics of the NAND flash memory. These characteristics refer to whether the original number of error bits in the target page corresponding to the target data unit is sensitive to factors other than read interference. Based on the NAND flash memory characteristics, if the original number of error bits in the target page corresponding to the target data unit is sensitive to multiple factors, the optimal read voltage updated online by the system can be selected as the preset voltage; otherwise, the default read voltage can be selected as the preset voltage to reduce complexity. Alternatively, the preset voltage can also be a read voltage set for other reasons, and this embodiment does not limit this.

[0116] It should be noted that step 221 in the embodiments of this application is an optional step.

[0117] 222. Read a codeword from the target data unit. The codeword is any codeword in the data stored in the target data unit.

[0118] In this embodiment of the application, the controller reads a codeword from each of the multiple target data units. For example, the codeword is codeword A, and codeword A can be any codeword in each target data unit.

[0119] 223. Decode the codeword to obtain the decoding result.

[0120] In this embodiment of the application, after the controller reads a codeword from each of the multiple target data units, it decodes the codeword.

[0121] 224. If decoding fails, the original number of error bits in the target data unit is determined to be the second preset value.

[0122] In this embodiment of the application, the controller decodes the codeword. If the decoding fails, the controller sets the original number of error bits of the target data unit corresponding to the codeword to a second preset value. The second preset value can be a pre-set infinite value represented within a finite range.

[0123] 225. If decoding is successful, determine the original number of error bits of the target data unit based on the Hamming distance between the codeword and the decoding result.

[0124] In this embodiment, the controller decodes the codeword. If decoding is successful, the controller obtains the original number of error bits of the target data unit corresponding to the codeword by comparing the successfully decoded result with the codeword. Specifically, the comparison method can be to calculate the Hamming distance between the two vectors of the successfully decoded result and the codeword. Other comparison methods are also possible, and this application does not limit them.

[0125] 226. Determine statistical information based on the original number of error bits of multiple target data units.

[0126] In this embodiment of the application, after reading multiple original error bit counts corresponding to multiple target data units, the controller determines statistical information based on the multiple original error bit counts. This statistical information is obtained by the controller through statistics and analysis of the multiple original error bit counts.

[0127] Taking the inclusion of a first error bit count in the statistical information as an example, the controller can determine the first error bit count based on the original error bit counts of multiple target data units using the following method: the controller ranks the multiple original error bit counts in descending order of their values, and then determines the original error bit count ranked N as the first error bit count, where N is an integer greater than 0. The statistical information may also include a second error bit count, which is the largest original error bit count among the multiple original error bit counts. When N equals 1, the first error bit count is the second error bit count.

[0128] The above Figure 3 Implementation examples Figure 2 A specific implementation of step 22, "the controller obtains statistical information," in the embodiment has been described. The following embodiments of this application will further elaborate on this. Figure 2 The specific implementation method of "the controller determines whether the first reading interference count value meets the adjustment conditions based on statistical information" in step 23 of the embodiment will be introduced.

[0129] based on Figure 2 In step 23 of the embodiment, the controller determines whether the first read interference count value meets the adjustment conditions based on statistical information. Specifically, the controller determines whether the first read interference count value meets the adjustment conditions by judging whether the multiple original error bits of the flash memory block meet the expected distribution pattern and certain conditions. The statistical information obtained by the controller may include the difference between the first error bit number and the multiple original error bits. The difference between the multiple original error bits can characterize the distribution of the multiple original error bits. Therefore, this embodiment will specifically describe how the controller determines whether the first read interference count value meets the adjustment conditions based on the difference between the multiple original error bits and the first error bit number. Please refer to Figures 4(1) and 4(2).

[0130] It should be noted that, in this embodiment, the degree of difference among multiple original error bits refers to the dispersion among multiple original error bits, or in other words, it is used to represent the degree of difference among multiple original error bits. For example, if the values ​​of multiple original error bits are concentrated in a small range, then the degree of difference among the multiple original error bits can be considered small. Taking the value range of the original error bits as [0, 200] as an example, if, during a certain sampling process, the values ​​of multiple original error bits corresponding to multiple target data units acquired by the controller are concentrated around 100, such as [90, 110], then the degree of difference among the multiple original error bits can be considered small; conversely, if, during a certain sampling process, some of the values ​​of multiple original error bits corresponding to multiple target data units acquired by the controller are concentrated around 10, while others are concentrated around 180, then the degree of difference among the multiple original error bits can be considered large.

[0131] The method for characterizing the difference among multiple original error bits in this application embodiment can be to calculate the variance or standard deviation among the multiple original error bits. The difference among the multiple original error bits is characterized by the value of the variance or standard deviation. The larger the value of the variance or standard deviation, the greater the difference. It should be noted that in addition to using variance or standard deviation, other characterization methods can also be used in this application embodiment. It should also be noted that the method for measuring the difference can be determined according to the actual situation. This is only a simple example to introduce the difference and should not be construed as a limitation of this application.

[0132] In this embodiment, the smaller the difference between multiple original error bits, the higher the similarity between the multiple original error bits; conversely, the greater the difference, the lower the similarity between the multiple original error bits. In this embodiment, a high similarity between multiple original error bits, i.e., a difference between the multiple original error bits less than a second threshold, is used as the expected distribution pattern.

[0133] Optionally, the method by which the controller determines whether the first read interference count value meets the adjustment conditions based on the difference between multiple original error bits can be the method shown in Figure 4(1).

[0134] Referring to Figure 4(1), an embodiment of this application provides a method for determining whether the first read interference count value meets the adjustment conditions based on statistical information, which may include:

[0135] 2311. Determine whether the difference is greater than the second threshold.

[0136] In this embodiment of the application, the controller first determines whether the difference between the number of original error bits is greater than a second threshold.

[0137] 2312. When the difference is less than or equal to the second threshold, determine whether the number of first erroneous bits is greater than the third threshold.

[0138] In this embodiment, when the difference between multiple original error bit counts is less than or equal to a second threshold, it indicates that the similarity of the multiple original error bit counts is good and meets the expected distribution pattern. At this time, the controller will further determine whether the first error bit count in the statistical information is greater than a third threshold. Since the controller in this embodiment adjusts the first read interference count based on the first error bit count, if the value of the first error bit count is large, the second read interference count obtained after the controller adjusts the first read interference count based on the first error bit count may have certain problems. For example, the adjusted second read interference count may still be relatively large, and the overall difference before and after the adjustment may be small, which cannot improve the accuracy of the read interference count in evaluating the degree of read interference on the flash memory block. Therefore, after determining that multiple original error bit counts meet the expected distribution pattern, the controller also needs to determine whether the first error bit count is greater than the third threshold. If the first error bit count is greater than the third threshold, the first read interference count does not meet the adjustment condition and does not need to be adjusted.

[0139] 2313. If the difference is less than or equal to the second threshold, and the number of first error bits is less than or equal to the third threshold, then the first read interference count value is determined to meet the adjustment condition.

[0140] In this embodiment of the application, when it is determined that the difference between multiple original error bit counts is less than or equal to a second threshold, and the first error bit count is less than or equal to a third threshold, the controller determines that the first read interference count value meets the adjustment conditions.

[0141] Optionally, in this embodiment, after the controller determines that the first read interference count value meets the adjustment condition, it can determine the second read interference count value based on the second error bit count. The method by which the controller determines the second read interference count value based on the second error bit count in this embodiment can be found in [reference needed]. Figure 2 The method by which the controller determines the second read interference count value based on the first number of error bits in step 24 is understood and will not be elaborated here.

[0142] In this embodiment, the second error bit count is the largest original error bit count among multiple original error bit counts. When the value of the first error bit count is large and exceeds the third threshold, the second error bit count must also be greater than the third threshold. Therefore, in this embodiment, when it is determined that the difference between multiple original error bit counts is less than or equal to the second threshold, it is also necessary to ensure that the first error bit count is less than or equal to the third threshold. Only then can it be determined that the first read interference count value meets the adjustment condition, and the second read interference count value is determined based on the second error bit count.

[0143] 2314. When the difference is greater than the second threshold, the controller determines whether abnormal data processing can be performed on the first set and obtains the third error bit count.

[0144] In this embodiment, if the difference between multiple original error bit counts is greater than a second threshold, it indicates that the multiple original error bit counts do not meet the expected distribution pattern and have poor similarity. In this case, the controller can process the first set of abnormal data to make the second set obtained through abnormal data processing conform to the expected distribution pattern. Therefore, the controller will first determine whether the abnormal data in the multiple original error bit counts in the first set can be processed. If abnormal data processing cannot be performed, the adjustment is abandoned, that is, the flash memory block determines that the first read interference count value does not meet the adjustment conditions.

[0145] In this embodiment, the abnormal data refers to one or more original error bits in the first set that are greater than the average number of original error bits of multiple target data units, and that cause the difference between multiple target data units to exceed a second threshold. In this embodiment, the controller's determination of whether it can process the abnormal data in the first set can refer to the controller's determination of whether it can migrate the data of the page corresponding to the abnormal data in the first set. Specifically, the controller determines whether it can execute a GC read command to read the data of the page corresponding to the abnormal data, and then executes a GC write command to rewrite the data read by the GC read command to other flash memory blocks. If the GC read and GC write commands can complete the above data migration process, it indicates that the controller can process the abnormal data in the first set.

[0146] Optionally, in this embodiment, after successfully processing the abnormal data in the first set, the controller obtains a third error bit count. This third error bit count is the largest original error bit count in the second set obtained after the controller processes the abnormal data in the first set. The controller may obtain the third error bit count by resampling and re-counting the pages containing valid data in the flash memory block after processing the abnormal data. At this point, the data in the pages containing the abnormal data has been migrated, effectively removing the abnormal data from the multiple original error bit counts in the first set and transferring it to the second set. The third error bit count is then obtained through re-counting and analysis.

[0147] Optionally, in this embodiment of the application, when the abnormal data contains abnormally large data, the abnormally large data is one or more original error bits ranked in descending order of the original error bits in the first set, where M is an integer greater than 0. For example, when M=1, the abnormally large data is the largest original error bit among the original error bits; when M=3, the abnormally large data is the three original error bits ranked in descending order of the original error bits. When the abnormal data contains such abnormally large data, the controller can also perform data migration on one or more target data units corresponding to the abnormally large data. For example, it can perform page-based garbage collection on the pages corresponding to the one or more target data units.

[0148] 2315. If it is determined that abnormal data processing can be performed and the third error bit count can be obtained, the controller determines whether the third error bit count is greater than the third threshold.

[0149] In this embodiment, after processing abnormal data and counting the third error bits, the controller determines whether the third error bits are greater than a third threshold. The reason the controller determines whether the third error bits are greater than the third threshold in this embodiment is the same as the reason for determining whether the first error bits are greater than the third threshold in step 2312, and will not be repeated here.

[0150] 2316. If the number of the third error bits is less than or equal to the third threshold, then the first read interference count value is determined to meet the adjustment condition.

[0151] In this embodiment of the application, if the number of third error bits is less than or equal to the third threshold, the flash memory block determines that the first read interference count value meets the adjustment condition.

[0152] In this embodiment, the specific method by which the controller determines the second read interference count value based on the third error bit count can be found in [reference needed]. Figure 2 The method by which the controller determines the second read interference count value based on the first number of error bits in step 24 is understood and will not be elaborated here.

[0153] In this embodiment of the application, the controller can determine whether the first read interference count value meets the adjustment condition based on the difference between multiple original error bit counts and the first error bit count, or it can be the method shown in Figure 4(2).

[0154] Referring to Figure 4(2), another embodiment of the present application, which provides a method for determining whether the first reading interference count value meets the adjustment conditions based on statistical information, may include:

[0155] 2321. Determine whether the difference is greater than the second threshold.

[0156] The embodiments of this application can be understood by referring to step 2311 in Figure 4(1), and will not be repeated here.

[0157] 2322. When the difference is less than or equal to the second threshold, determine whether the number of first erroneous bits is greater than the third threshold.

[0158] The embodiments of this application can be understood by referring to step 2312 in Figure 4(1), and will not be repeated here.

[0159] 2323. If the difference is less than or equal to the second threshold, and the number of first error bits is less than or equal to the third threshold, then the first read interference count value is determined to meet the adjustment condition.

[0160] The embodiments of this application can be understood by referring to step 2313 in Figure 4(1), and will not be repeated here.

[0161] 2324. When the difference is greater than the second threshold, determine whether the number of first erroneous bits is greater than the third threshold.

[0162] In this embodiment of the application, if it is determined that the difference between multiple original error bits is greater than the second threshold, it indicates that the distribution pattern of multiple original error bits does not meet the expected distribution pattern. At this time, the controller can first determine whether the first error bit in the statistical information is greater than the third threshold.

[0163] 2325. If the difference is greater than the second threshold and the number of first erroneous bits is less than or equal to the third threshold, the first read interference count value is determined to meet the adjustment condition.

[0164] In this embodiment of the application, if the distribution pattern of multiple original error bits does not meet the expected distribution pattern, the controller can also determine that the first read interference count value meets the adjustment condition if the first error bit count is less than or equal to the third threshold.

[0165] 2326. If the difference is greater than the second threshold and the first error bit count is greater than the third threshold, the controller determines whether abnormal data processing can be performed on the first set and obtains the third error bit count.

[0166] In this embodiment, when the difference between multiple original error bit counts is greater than the second threshold and the first error bit count is greater than the third threshold, adjusting the first read interference count value with a larger first error bit count may cause some problems. Therefore, the controller will first determine whether the abnormal data in the multiple original error bit counts in the first set can be processed and the third error bit count can be obtained. The specific method of the controller determining whether the first set can be processed for abnormal data and obtaining the third error bit count in this embodiment can be understood by referring to step 2314 in Figure 4(1), and will not be repeated here.

[0167] 2327. If it is possible to process abnormal data in the first set and obtain the third error bit count, control whether the third error bit count is greater than the third threshold.

[0168] The embodiments of this application can be understood by referring to step 2315 in Figure 4(1), and will not be repeated here.

[0169] 2328. If the number of the third error bits is less than or equal to the third threshold, then the first read interference count value is determined to meet the adjustment condition.

[0170] The embodiments of this application can be understood by referring to step 2316 in Figure 4(1), and will not be repeated here.

[0171] It should be noted that the embodiments of this application provide two methods, Figure 4(1) and Figure 4(2), for determining whether the first read interference count value meets the adjustment conditions based on the difference of multiple original error bits. In practical applications, other methods may also be used to determine whether the first read interference count value meets the adjustment conditions based on the difference of multiple original error bits. The two methods, Figure 4(1) and Figure 4(2), provided in the embodiments of this application should not be construed as limitations on the embodiments of this application.

[0172] See Figure 5 Based on the above embodiments, this application also provides another embodiment of a data processing method, which may include:

[0173] 501. Obtain the first read interference count value of the flash memory block.

[0174] The embodiments of this application can be referred to. Figure 2 Step 21 in the previous section will be understood and will not be repeated here.

[0175] 502. If the first read interference count value is not greater than the first threshold and the first read interference count value belongs to the adjustment range, then obtain statistical information. The statistical information is obtained based on the first set, which includes multiple original error bit counts corresponding to multiple target data units in the flash memory block. Each target data unit corresponds to one original error bit count.

[0176] The embodiments of this application can be referred to. Figure 2 Step 22 and Figure 3 The examples are explained in detail here and will not be repeated.

[0177] 503. Based on the statistical information, determine whether the first reading interference count value meets the adjustment conditions.

[0178] The embodiments of this application can be referred to. Figure 2 The embodiments corresponding to steps 23, Figure 4(1), and Figure 4(2) will be understood in the following text, and will not be repeated here.

[0179] 504. If satisfied, determine the second read interference count value of the flash memory block based on the statistical information.

[0180] The embodiments of this application can be referred to. Figure 2 Step 24 in the previous section will be understood and will not be repeated here.

[0181] 505. If the second read interference count value is greater than the first threshold, then perform data migration on the flash memory block.

[0182] The embodiments of this application can be referred to. Figure 2 Step 25 in the previous section will be understood and will not be repeated here.

[0183] 506. If the conditions are not met, then perform data migration on the flash memory block.

[0184] In this embodiment, if it is determined that the first read interference count value does not meet the adjustment conditions, the controller can directly migrate the data in the flash memory block. Specifically, the controller can read the data in the flash memory block by executing a GC read command, and then write the data read by executing the GC write command to other flash memory blocks, thereby moving the data in the flash memory block to other flash memory blocks.

[0185] 507. Set the read interference count value of the flash memory block to the first preset value.

[0186] In this embodiment, after data migration of the flash memory block, the controller can set the read interference count value of the flash memory block to a first preset value. This first preset value can be 0, meaning the read interference count value of the flash memory block is cleared. The first preset value can also be non-zero. For example, based on the example given in step 24 above, if the second read interference count value is x, the first preset value can be set to (x%Mask), or the first preset value can be set to a random number between 0 and Mask. Alternatively, it can be set according to other rules, which this embodiment does not limit.

[0187] In this embodiment, a unified threshold and adjustment range are first set for the read interference count value of the flash memory block. When the first read interference count value of the acquired flash memory block is less than the threshold and falls within the adjustment range, the first read interference count value is corrected using statistical information based on multiple original error bit counts of the flash memory block. Since the original error bit count is a relatively direct measure of data reliability, the second read interference count value obtained by correcting the first read interference count value based on the statistical information of multiple original error bit counts has higher accuracy in evaluating the degree of read interference affecting the flash memory block. Finally, based on the more accurate second read interference count value, it is determined whether data migration of the flash memory block is required. This not only improves the accuracy of the read interference count value in evaluating the degree of read interference affecting the flash memory block, but also avoids unnecessary GC operations and extends the lifespan of the memory while ensuring data reliability.

[0188] The data processing method provided in the embodiments of this application has been described above. The embodiments of this application also provide a data processing device 60. Please refer to [link to relevant documentation]. Figure 6 .

[0189] Figure 6 This is a schematic diagram of the structure of the data processing apparatus 60 provided in an embodiment of this application.

[0190] See Figure 6 The data processing apparatus 60 provided in this application embodiment may include:

[0191] The acquisition module 601 is used to acquire the first read interference count value of the flash memory block;

[0192] The acquisition module 601 is further configured to acquire statistical information when the first read interference count value is not greater than the first threshold and the first read interference count value belongs to the adjustment range. The statistical information is obtained based on a first set, which includes multiple original error bit counts corresponding to multiple target data units in the flash memory block, wherein each target data unit corresponds to one original error bit count.

[0193] The judgment module 602 is used to determine whether the first reading interference count value meets the adjustment conditions based on the statistical information obtained by the acquisition module 601.

[0194] The determining module 603 is used to determine the second read interference count value of the flash memory block based on the statistical information when the judging module 602 determines that the first read interference count value meets the adjustment condition;

[0195] The data migration module 604 is used to migrate data to the flash memory block when the second read interference count value determined by the determining module 603 is greater than the first threshold.

[0196] In this embodiment, the data processing device first sets a unified threshold and adjustment range for the read interference count value of the flash memory block. When the first read interference count value of the acquired flash memory block is less than the threshold and falls within the adjustment range, the first read interference count value is corrected using statistical information based on multiple original error bit counts of the flash memory block. Since the original error bit count is a relatively direct measure of data reliability, the second read interference count value obtained by correcting the first read interference count value based on the statistical information of multiple original error bit counts has higher accuracy in evaluating the degree of read interference affecting the flash memory block. Finally, based on the more accurate second read interference count value, it is determined whether data migration of the flash memory block is required. This not only improves the accuracy of the read interference count value in evaluating the degree of read interference affecting the flash memory block, but also avoids unnecessary GC operations and improves the lifespan of the memory while meeting data reliability requirements.

[0197] Optionally, in this embodiment of the application, the statistical information includes the difference degree of the plurality of original error bit counts and the first error bit count, wherein the first error bit count is the original error bit count ranked N in descending order of value in the first set, and N is an integer greater than 0. The judgment module 602 is used to determine whether the first read interference count value meets the adjustment condition based on the difference degree and the first error bit count.

[0198] Optionally, as an embodiment, the judgment module 602 is used to determine whether the first number of error bits is greater than a third threshold when the difference is less than or equal to a second threshold; and to determine whether abnormal data in the first set can be processed when the difference is greater than the second threshold, wherein the abnormal data is the average number of original error bits in the first set that is greater than the multiple target data units, and one or more original error bits that cause the difference to be greater than the second threshold; the determination module 603 is further used to determine that the first read interference count value satisfies the adjustment condition when the judgment module 602 determines that the first number of error bits is less than or equal to the third threshold; and to determine that the first read interference count value satisfies the adjustment condition when the difference is greater than the second threshold and the abnormal data in the first set can be processed.

[0199] Optionally, as an embodiment, the determination module 602 is configured to: determine whether the first number of error bits is greater than a third threshold when the difference is less than or equal to a second threshold; determine whether the first number of error bits is greater than the third threshold when the difference is greater than the second threshold; and determine whether the abnormal data in the first set can be processed when the difference is greater than the second threshold and the first number of error bits is greater than the third threshold, wherein the abnormal data is the average number of original error bits in the first set that is greater than the multiple target data units, and one or more original error bits that cause the difference to be greater than the second threshold; and determine... Module 603 is configured to: when the difference is less than or equal to the second threshold, if the judgment module 602 determines that the first number of error bits is less than or equal to the third threshold, determine that the first read interference count value meets the adjustment condition; when the difference is greater than the second threshold, if the judgment module 602 determines that the first number of error bits is less than or equal to the third threshold, determine that the first read interference count value meets the adjustment condition; when the difference is greater than the second threshold and the first number of error bits is greater than the third threshold, if the judgment module 602 determines that the abnormal data can be processed, determine that the first read interference count value meets the adjustment condition.

[0200] Optionally, as an embodiment, the determining module 603 is used to determine the second read interference count value based on the second error bit number when the difference is less than or equal to the second threshold and the first error bit number is less than or equal to the third threshold. There is a corresponding relationship between the second error bit number and the second read interference count value. The second error bit number is the original error bit number with the largest value in the first set.

[0201] Optionally, as an embodiment, a determining module is used to determine the target interval to which the second number of erroneous bits belongs, the target interval being one of a plurality of intervals, each of the plurality of intervals corresponding to a count value; and to determine the second read interference count value based on the target interval.

[0202] Optionally, as an embodiment, the determining module 603 is used to determine the second read interference count value based on the third error bit number when it is determined that the abnormal data can be processed. There is a correspondence between the third error bit number and the second read interference count value. The third error bit number is the original error bit number with the largest value in the second set. The second set is a set of one or more original error bit numbers obtained after processing the abnormal data.

[0203] Optionally, as an embodiment, the determining module 603 is used to determine the target interval to which the third error bit count belongs, the target interval being one of a plurality of intervals, each of the plurality of intervals corresponding to a count value; and to determine the second read interference count value based on the target interval.

[0204] Optionally, as an embodiment, the data migration module 604 is further configured to perform data migration on the target data unit corresponding to the abnormal big data when the abnormal big data includes abnormal big data, wherein the abnormal big data is one or more original error bits ranked in descending order of value in the first set, where M is an integer greater than 0.

[0205] Optionally, as an embodiment, the acquisition module 601 is used to read a codeword of a target data unit, wherein the codeword is any codeword in the data stored in the target data unit; decode the codeword to obtain a decoding result; if decoding fails, determine the original number of error bits of the target data unit as a second preset value; if decoding succeeds, determine the original number of error bits of the target data unit based on the Hamming distance between the codeword and the decoding result; and determine the statistical information based on the original number of error bits of the plurality of target data units.

[0206] Optionally, as an embodiment, the data processing device 60 further includes: a setting module 605, configured to set the reading voltage of the plurality of target data units to a preset voltage before the acquisition module 601 reads a codeword of the target data unit; correspondingly, the acquisition module 601 is configured to read a codeword of the target data unit under the preset voltage set by the setting module 605.

[0207] Optionally, as an example, the preset voltage is either the default read voltage or the optimal read voltage updated online.

[0208] Optionally, as an embodiment, the flash memory block contains different types of pages, each type of page corresponding to a different count increment. The first read interference count value of the flash memory block is determined based on the number of times each type of page is read and the count increment corresponding to each type of page.

[0209] Optionally, as an embodiment, the data processing device 60 further includes a correction module 606, used to correct the different count value increments based on the statistical information acquired by the acquisition module 601.

[0210] Optionally, as an embodiment, the correction module 606 is used to correct the different count increments according to the second number of error bits to obtain different update count increments corresponding to the different types of pages, wherein the second number of error bits is the original number of error bits with the largest value in the first set, and the update count increment is positively correlated with the second number of error bits.

[0211] Optionally, as an embodiment, the data migration module 604 is further configured to perform data migration on the flash memory block after the judgment module 602 determines that the first read interference count value does not meet the adjustment condition.

[0212] Optionally, as an embodiment, the data migration module 604 is further configured to set the read interference count value of the flash memory block to a first preset value after data migration of the flash memory block.

[0213] Optionally, as an embodiment, the plurality of target data units correspond to all pages in the flash memory block, pages of the same type in the flash memory block, or pages in the flash memory block whose read voltage includes an erase state decision voltage.

[0214] When using integrated modules, the acquisition module 601, judgment module 602, determination module 603, data migration module 604, setting module 605, and correction module 606 in the embodiments of this application can be... Figure 1 Controller 121 in the middle. When the controller runs, it performs the following... Figure 2 and Figure 5 The illustrated embodiment describes the execution method of the data processing method. In other implementations, the acquisition module 601, judgment module 602, determination module 603, data migration module 604, setting module 605, and correction module 606 can be integrated together or arbitrarily combined, and the specific implementation is not limited to the embodiments of this application.

[0215] It should be noted that each of the above modules or units can be implemented through software, hardware, or a combination of both.

[0216] In this application, "implemented via software" means that the controller reads and executes program instructions stored in memory to implement the functions corresponding to the aforementioned modules or units. The controller refers to a processing circuit capable of executing program instructions, including but not limited to at least one of the following: a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a microcontroller unit (MCU), or an artificial intelligence processor, etc., all processing circuits capable of running program instructions. These processing circuits may include one or more cores for executing program instructions to perform data operations or processing. In this application, the controller can be a separately packaged semiconductor chip; it can also be integrated with other circuits and packaged into a separate semiconductor chip. For example, one or more controllers can be integrated with other circuits (such as encoding / decoding circuits, hardware acceleration circuits, or various bus and interface circuits) to form a SoC (system on a chip), which is packaged as a separate chip.

[0217] In this application, "implemented in hardware" means that the functions of the above-mentioned modules or units are implemented through hardware processing circuits that do not have program instruction processing capabilities. These hardware processing circuits can be composed of discrete hardware components or integrated circuits. To reduce power consumption and size, integrated circuits are typically used. The hardware processing circuits can include ASICs (application-specific integrated circuits) or PLDs (programmable logic devices); PLDs can further include FPGAs (field-programmable gate arrays), CPLDs (complex programmable logic devices), and so on. These hardware processing circuits can be a separately packaged semiconductor chip, or they can be integrated with other circuits (such as CPUs or DSPs) and packaged into a single semiconductor chip. For example, an ASIC and a CPU can be integrated to form a SoC and packaged separately as a chip, or an FPGA and a CPU can be integrated to form a SoPC (system on a programmable chip).

[0218] It should be noted that when this application is implemented through software, hardware, or a combination of both, different software or hardware can be used, and it is not limited to using only one type of software or hardware. For example, one module or unit can be implemented using a CPU, while another module or unit can be implemented using a DSP. Similarly, when implemented using hardware, one module or unit can be implemented using an ASIC, while another module or unit can be implemented using an FPGA. Of course, it is not limited to using the same software (e.g., all through a CPU) or the same hardware (e.g., all through an ASIC) to implement some or all modules or units. Furthermore, those skilled in the art will understand that software is generally more flexible but less performant than hardware, while hardware is the opposite. Therefore, those skilled in the art can choose software, hardware, or a combination of both based on actual needs.

[0219] This application embodiment also provides a computer-readable storage medium storing instructions that, when executed on a data processing device 60, cause the data processing device 60 to perform actions such as... Figure 2 or Figure 5 The data processing method shown.

[0220] This application embodiment also provides a computer program product, which includes computer-executable instructions stored in a computer-readable storage medium; the data processing device 60 may read the computer-executable instructions from the computer-readable storage medium, and the controller may execute the computer-executable instructions to cause the data processing device to perform as follows. Figure 2 or Figure 5 The data processing method shown.

[0221] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0222] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0223] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include ROM, RAM, disk, or optical disk, etc.

[0224] The data processing method, apparatus, and storage medium provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A data processing method, characterized in that, include: Obtain the first read interference count value of the flash memory block; If the first read interference count value is not greater than the first threshold and the first read interference count value belongs to the adjustment range, then statistical information is obtained. The statistical information is obtained based on the first set, which includes multiple original error bit counts corresponding to multiple target data units in the flash memory block. Each target data unit corresponds to one original error bit count. The first threshold is used as the judgment threshold for data migration of the flash memory block. If the first read interference count value is greater than the first threshold, then data migration is performed on the flash memory block. The adjustment range is defined as a preset range that is less than the first threshold. Based on the statistical information, determine whether the first read interference count value meets the adjustment conditions; If the condition is met, then the second read interference count value of the flash memory block is determined based on the statistical information; If the second read interference count value is greater than the first threshold, then data migration is performed on the flash memory block.

2. The method according to claim 1, characterized in that, The statistical information includes the difference between the multiple original error bit counts and a first error bit count, where the first error bit count is the Nth original error bit count ranked in descending order of value in the first set, and N is an integer greater than 0. The step of determining whether the first read interference count value meets the adjustment conditions based on the statistical information includes: Based on the difference and the first number of erroneous bits, determine whether the first read interference count value meets the adjustment condition.

3. The method according to claim 2, characterized in that, The step of determining whether the first read interference count value meets the adjustment condition based on the difference degree and the first number of error bits includes: When the difference is less than or equal to the second threshold, it is determined whether the first number of erroneous bits is greater than the third threshold; If the first number of erroneous bits is less than or equal to the third threshold, then the first read interference count value is determined to meet the adjustment condition; When the difference is greater than the second threshold, it is determined whether the abnormal data in the first set can be processed. The abnormal data is the average number of original error bits in the first set that is greater than the average number of original error bits of the plurality of target data units, and causes the difference to be greater than the second threshold. If it is determined that the abnormal data in the first set can be processed, then the first read interference count value is determined to meet the adjustment condition.

4. The method according to claim 2, characterized in that, The step of determining whether the first read interference count value meets the adjustment condition based on the difference degree and the first number of error bits includes: When the difference is less than or equal to the second threshold, it is determined whether the first number of erroneous bits is greater than the third threshold; If the first number of error bits is less than or equal to the third threshold, it is determined that the first read interference count value meets the adjustment condition; When the difference is greater than the second threshold, it is determined whether the first number of erroneous bits is greater than the third threshold; If the first number of erroneous bits is less than or equal to the third threshold, then the first read interference count value is determined to meet the adjustment condition; If the first number of error bits is greater than the third threshold, it is determined whether the abnormal data in the first set can be processed. The abnormal data is the average number of original error bits in the first set that is greater than the average number of original error bits of the plurality of target data units, and causes the difference to be greater than the second threshold. If it is determined that the abnormal data can be processed, then the first read interference count value is determined to meet the adjustment condition.

5. The method according to claim 3 or 4, characterized in that, When the difference is less than or equal to the second threshold, and the first number of error bits is less than or equal to the third threshold, the step of determining the second read interference count value of the flash memory block based on the statistical information includes: The second read interference count value is determined based on the second number of error bits. There is a corresponding relationship between the second number of error bits and the second read interference count value. The second number of error bits is the original number of error bits with the largest value in the first set.

6. The method according to claim 5, characterized in that, The step of determining the second read interference count value based on the second number of error bits, wherein there is a corresponding relationship between the second number of error bits and the second read interference count value, includes: Determine the target interval to which the second number of error bits belongs, wherein the target interval is one of multiple intervals, and each of the multiple intervals corresponds to a count value; The second read interference count value is determined based on the target interval.

7. The method according to claim 3 or 4, characterized in that, When it is determined that the abnormal data can be processed, the step of determining the second read interference count value of the flash memory block based on the statistical information, if satisfied, includes: The second read interference count value is determined based on the third error bit count. There is a corresponding relationship between the third error bit count and the second read interference count value. The third error bit count is the largest original error bit count in the second set. The second set is a set of one or more original error bit counts obtained after processing the abnormal data.

8. The method according to claim 7, characterized in that, The step of determining the second read interference count value based on the third error bit count, wherein there is a corresponding relationship between the third error bit count and the second read interference count value, includes: Determine the target interval to which the third error bit count belongs. The target interval is one of multiple intervals, and each of the multiple intervals corresponds to a count value. The second read interference count value is determined based on the target interval.

9. The method according to claim 3 or 4, characterized in that, When the abnormal data includes abnormally large data, the abnormally large data is one or more original error bits ranked in descending order of value in the first set, where M is an integer greater than 0. The method further includes: Data migration is performed on the target data units corresponding to the abnormal big data.

10. The method according to claim 1, characterized in that, The acquisition of statistical information includes: Read a codeword from the target data unit, where the codeword is any one of the codewords stored in the target data unit; The codeword is decoded to obtain the decoding result; If decoding fails, the original number of error bits of the target data unit is determined to be the second preset value; If decoding is successful, the original number of error bits of the target data unit is determined based on the Hamming distance between the codeword and the decoding result; The statistical information is determined based on the original number of error bits in the plurality of target data units.

11. The method according to claim 10, characterized in that, Before reading a codeword from the target data unit, the method further includes: Set the read voltage of the plurality of target data units to a preset voltage; Correspondingly, reading a codeword of the target data unit includes: Under the preset voltage, a codeword of the target data unit is read.

12. The method according to claim 11, characterized in that, The preset voltage is either the default reading voltage or the optimal reading voltage updated online.

13. The method according to claim 2, characterized in that, The flash memory block contains different types of pages, each corresponding to a different count increment. The first read interference count value of the flash memory block is determined based on the number of times each type of page is read and the count increment corresponding to each type of page.

14. The method according to claim 13, characterized in that, After obtaining the statistical information, the process also includes: The different count increments are corrected based on the statistical information.

15. The method according to claim 14, characterized in that, The step of correcting the different count value increments based on the statistical information includes: The different count increments are corrected based on the second error bit number to obtain different update count increments corresponding to the different types of pages. The second error bit number is the original error bit number with the largest value in the first set. The update count increment is positively correlated with the second error bit number.

16. The method according to claim 1, characterized in that, After determining whether the first read interference count value meets the adjustment conditions based on the statistical information, the method further includes: If the conditions are not met, data migration will be performed on the flash memory block.

17. The method according to claim 1, characterized in that, After migrating the data to the flash memory block, the process further includes: Set the read interference count value of the flash memory block to a first preset value.

18. The method according to claim 1, characterized in that, The plurality of target data units correspond to all pages in the flash memory block, pages of the same type in the flash memory block, or pages in the flash memory block whose read voltage includes an erase state decision voltage.

19. A data processing apparatus, characterized in that, The device includes: The acquisition module is used to acquire the first read interference count value of the flash memory block; The acquisition module is further configured to acquire statistical information when the first read interference count value is not greater than a first threshold and the first read interference count value belongs to an adjustment range. The statistical information is obtained based on a first set, which includes multiple original error bit counts corresponding to multiple target data units in the flash memory block. Each target data unit corresponds to one original error bit count. The first threshold is used as a judgment threshold for data migration of the flash memory block. If the first read interference count value is greater than the first threshold, data migration is performed on the flash memory block. The adjustment range is defined as a preset range that is less than the first threshold. The judgment module is used to determine whether the first read interference count value meets the adjustment conditions based on the statistical information obtained by the acquisition module. The determining module is configured to determine the second read interference count value of the flash memory block based on the statistical information when the judging module determines that the first read interference count value meets the adjustment condition; The data migration module is used to migrate data to the flash memory block when the second read interference count value determined by the determining module is greater than the first threshold.

20. The apparatus according to claim 19, characterized in that, The statistical information includes the difference between the multiple original error bit counts and a first error bit count, where the first error bit count is the Nth original error bit count in the first set, ranked in descending order of value, and N is an integer greater than 0. The judgment module is used to determine whether the first read interference count value meets the adjustment condition based on the difference degree and the first number of error bits.

21. The apparatus according to claim 20, characterized in that, The judgment module is used to determine whether the first number of error bits is greater than a third threshold when the difference is less than or equal to a second threshold; and to determine whether the abnormal data in the first set can be processed when the difference is greater than the second threshold. The abnormal data is the average number of original error bits in the first set that is greater than the average number of original error bits of the plurality of target data units, and one or more original error bits that cause the difference to be greater than the second threshold. The determining module is further configured to determine that the first read interference count value satisfies the adjustment condition when the judging module determines that the first number of erroneous bits is less than or equal to the third threshold; When the difference is greater than the second threshold and the abnormal data in the first set can be processed, it is determined that the first read interference count value meets the adjustment condition.

22. The apparatus according to claim 20, characterized in that, The judgment module is used to determine whether the first number of error bits is greater than a third threshold when the difference degree is less than or equal to a second threshold; to determine whether the first number of error bits is greater than the third threshold when the difference degree is greater than the second threshold; and to determine whether the abnormal data in the first set can be processed when the difference degree is greater than the second threshold and the first number of error bits is greater than the third threshold. The abnormal data is the average number of original error bits in the first set that is greater than the average number of original error bits of the plurality of target data units, and one or more original error bits that cause the difference degree to be greater than the second threshold. The determining module is used to determine that the first read interference count value satisfies the adjustment condition when the difference degree is less than or equal to the second threshold and the judging module determines that the first error bit count is less than or equal to the third threshold. When the difference is greater than the second threshold, if the judgment module determines that the first number of erroneous bits is less than or equal to the third threshold, it determines that the first read interference count value meets the adjustment condition. When the difference is greater than the second threshold and the first number of error bits is greater than the third threshold, if the judgment module determines that the abnormal data can be processed, it determines that the first read interference count value meets the adjustment condition.

23. The apparatus according to claim 21 or 22, characterized in that, The determining module is used to determine the second read interference count value based on the second error bit number when the difference is less than or equal to the second threshold and the first error bit number is less than or equal to the third threshold. There is a corresponding relationship between the second error bit number and the second read interference count value. The second error bit number is the original error bit number with the largest value in the first set.

24. The apparatus according to claim 23, characterized in that, The determining module is used to determine the target interval to which the second number of erroneous bits belongs, wherein the target interval is one of multiple intervals, and each of the multiple intervals corresponds to a count value; and to determine the second read interference count value based on the target interval.

25. The apparatus according to claim 21 or 22, characterized in that, The determining module is used to determine the second read interference count value based on the third error bit count when it is determined that the abnormal data can be processed. There is a corresponding relationship between the third error bit count and the second read interference count value. The third error bit count is the original error bit count with the largest value in the second set. The second set is a set of one or more original error bit counts obtained after processing the abnormal data.

26. The apparatus according to claim 25, characterized in that, The determining module is used to determine the target interval to which the third error bit count belongs, wherein the target interval is one of multiple intervals, and each of the multiple intervals corresponds to a count value; and to determine the second read interference count value based on the target interval.

27. The apparatus according to claim 21 or 22, characterized in that, The data migration module is further configured to perform data migration on the target data unit corresponding to the abnormal big data when the abnormal big data includes abnormal big data, wherein the abnormal big data is one or more original error bits ranked in descending order of value in the first set, and M is an integer greater than 0.

28. The apparatus according to claim 19, characterized in that, The acquisition module is used to read a codeword from the target data unit, wherein the codeword is any codeword in the data stored in the target data unit; and to decode the codeword to obtain a decoding result. If decoding fails, the original number of error bits of the target data unit is determined to be the second preset value; If decoding is successful, the original number of error bits of the target data unit is determined based on the Hamming distance between the codeword and the decoding result; The statistical information is determined based on the original number of error bits in the plurality of target data units.

29. The apparatus according to claim 28, characterized in that, The device further includes: The setting module is used to set the reading voltage of the plurality of target data units to a preset voltage before the acquisition module reads a codeword of the target data unit; Correspondingly, the acquisition module is used to read a codeword of the target data unit under the preset voltage set by the setting module.

30. The apparatus according to claim 29, characterized in that, The preset voltage is either the default reading voltage or the optimal reading voltage updated online.

31. The apparatus according to claim 20, characterized in that, The flash memory block contains different types of pages, each corresponding to a different count increment. The first read interference count value of the flash memory block is determined based on the number of times each type of page is read and the count increment corresponding to each type of page.

32. The apparatus according to claim 31, characterized in that, The device further includes: The correction module is used to correct the different count value increments based on the statistical information obtained by the acquisition module.

33. The apparatus according to claim 32, characterized in that, The correction module is used to correct the different count increments according to the second error bit number to obtain different update count increments corresponding to the different types of pages. The second error bit number is the original error bit number with the largest value in the first set. The update count increment is positively correlated with the second error bit number.

34. The apparatus according to claim 19, characterized in that, The data migration module is further configured to perform data migration on the flash memory block after the judgment module determines that the first read interference count value does not meet the adjustment conditions.

35. The apparatus according to claim 19, characterized in that, The data migration module is further configured to set the read interference count value of the flash memory block to a first preset value after performing data migration on the flash memory block.

36. The apparatus according to claim 19, characterized in that, The plurality of target data units correspond to all pages in the flash memory block, pages of the same type in the flash memory block, or pages in the flash memory block whose read voltage includes an erase state decision voltage.

37. A computer device, characterized in that, The computer device includes: an input / output (I / O) interface, a processor, and a memory, wherein the memory stores program instructions; The processor is used to execute program instructions stored in the memory to perform the method as described in any one of claims 1-18.

38. A computer-readable storage medium comprising instructions, characterized in that, When the instructions are executed on a computer device, the computer device causes the computer device to perform the method as described in any one of claims 1-18.

39. A computer program product containing instructions, characterized in that, When the computer program product is run on a computer device, it causes the computer device to execute the execution method of the computer operation command according to any one of claims 1-18.

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