Method for manufacturing an opto-semiconductor device

Abstract

Including: a step of forming a semiconductor layer on the surface of an n-type InP substrate (10); an etching step of etching a part of the semiconductor layer to form an active layer ridge (20); a cleaning step of removing Si attached to the surface of the etched semiconductor layer while supplying a raw material gas for crystal growth and an etching gas; and a crystal growth step of forming buried layers (40) on both sides of the active layer ridge (20) at a processing temperature higher than the temperature in the cleaning step, and performing cleaning in a state where the ridge shape is maintained.

Description

Technical Field

[0001] The present application relates to a method for manufacturing an opto-semiconductor device. Background Art

[0002] In a method for manufacturing an opto-semiconductor device having an embedded structure used in a laser diode or an optical modulator, when dry etching a semiconductor, Si-based reaction products are generated as etching residues. Further, even when removing the Si residues with a chemical solution, when the wafer is then moved to a chamber for crystal growth, Si in the atmosphere adheres thereto, and a sufficiently normal surface cannot be obtained. In order not to significantly reduce the maximum optical output of the laser diode, it is important to set the Si concentration on the ridge side to 1.0E17 / cm 3 as follows.

[0003] In response to this, Patent Document 1 discloses a method of supplying a halogen-based reactive gas while annealing a substrate inside a chamber of a crystal growth apparatus as in-situ etching. Since Si cannot be completely removed by simply supplying a halogen-based gas, an annealing method is employed. On the other hand, Patent Document 2 discloses a method of more efficiently removing Si by supplying both an etching gas and a crystal growth raw material instead of using an annealing method.

[0004] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2013-222804 (paragraph 0023)

[0005] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2003-282455 (paragraph 0079, Table 1)

[0006] However, in the method of Patent Document 1, since annealing is performed while maintaining at a high temperature, the shape of the ridge collapses, and thus there are problems of deterioration of element characteristics and reduction of manufacturing stability.

[0007] Further, even in the method of Patent Document 2, when applied to a wafer after ridge formation instead of a flat wafer surface, since the ridge side is preferentially etched during cleaning, there is a problem that the longer the cleaning time is performed to improve the cleaning effect, the more the ridge shape collapses and the more significantly the element characteristics deteriorate. And, based on the principle that the cleaning effect is highest when the value obtained by subtracting the etching rate from the growth rate, that is, the film thickness change rate, becomes near 0, when the film thickness change rate at the bottom of the ridge is set to 0, the film thickness change rate at the ridge side becomes a value much smaller than 0, and thus there is a problem that the cleaning effect at the ridge side cannot be fully exerted. Summary of the Invention

[0008] The present application discloses a technology for solving the above problems, and an object thereof is to provide a manufacturing method of an optical semiconductor device that can introduce clean light while maintaining the ridge shape even when ridges are formed on a wafer.

[0009] The manufacturing method of the optical semiconductor device disclosed in the present application is characterized by including: a step of forming a semiconductor layer on the surface of a substrate; an etching step of etching a part of the semiconductor layer to form a ridge; a cleaning step of removing an attachment on the surface of the etched semiconductor layer while supplying a raw material gas for crystal growth and an etching gas; and a crystal growth step of forming current blocking layers on both sides of the ridge at a processing temperature higher than the temperature in the cleaning step.

[0010] According to the present application, by including a cleaning step of removing an attachment on the surface of the etched semiconductor layer while supplying a raw material gas for crystal growth and an etching gas at a processing temperature lower than the temperature in the crystal growth step, cleaning can be performed while maintaining the ridge shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a cross-sectional view showing the structure of an optical semiconductor device manufactured by the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0012] Figure 2 It is a flowchart showing the manufacturing process of the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0013] Figure 3 It is a cross-sectional view showing the manufacturing process of the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0014] Figure 4 It is a cross-sectional view showing the manufacturing process of the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0015] Figure 5 It is a cross-sectional view showing the manufacturing process of the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0016] Figure 6 It is a cross-sectional view showing the manufacturing process of the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0017] Figure 7 It is a diagram showing the relationship between the temperature curve and the supplied gas in the manufacturing process of the manufacturing method of the optical semiconductor device according to Embodiment 1. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Embodiment 1

[0019] Figure 1 is a cross-sectional view showing the structure of the optoelectronic semiconductor device 101 according to Embodiment 1 of the present application. As Figure 1 shown, the optoelectronic semiconductor device 101 has a structure in which an active layer ridge 20 serving as a ridge is provided. The active layer ridge 20 is formed by laminating an n-type InP cladding layer 12 having a convex portion 12a provided in the center on an n-type InP substrate 10, and an AlGaInAs active layer 14 and a p-type InP cladding layer 16 are sequentially laminated on the convex portion 12a of the n-type InP cladding layer 12. Both side surfaces of the active layer ridge 20 are buried by a buried layer 40 serving as a current blocking layer that covers the n-type InP current blocking layer 42 with a p-type InP current blocking layer 41 and a p-type InP current blocking layer 44. A p-type InP cladding layer 46 is laminated on the surface of the buried layer 40 and the active layer ridge 20, and a p-type InGaAs contact layer 48 is laminated on the surface of the p-type InP cladding layer 46.

[0020] Next, a method for manufacturing the optoelectronic semiconductor device 101 according to Embodiment 1 of the present application will be described. Figure 2 is a flowchart showing the manufacturing process of the optoelectronic semiconductor device 101, which is the basic structure of an optoelectronic semiconductor device, i.e., a semiconductor laser element. Figures 3 to 6 is related to Figure 2 corresponding cross-sectional views showing each manufacturing process of the optoelectronic semiconductor device 101. Figure 3 shows the formation process of the semiconductor layer on the substrate. Figure 4 shows the mask formation process on the semiconductor layer. Figure 5 shows the etching process of the semiconductor layer. Figure 6 shows the formation process of the buried layer.

[0021] First, in Figure 2 step S201 (refer to Figure 3 ), as the formation process of the semiconductor layer on the substrate, an n-type InP cladding layer 12 is formed on the n-type InP substrate 10 by using the MOCVD method (Metal Organic Chemical Vapor Deposition). Then, an AlGaInAs active layer 14 is formed on the n-type InP cladding layer 12. Next, a p-type InP cladding layer 16 is formed on the AlGaInAs active layer 14.

[0022] Next, in Figure 2 step S202 (refer to Figure 4 ), as the mask formation process on the semiconductor layer, an SiO Figure 3 layer is formed on the p-type InP cladding layer 16 on the surface of the semiconductor element shown in 2 . Then, lithography using a resist pattern is performed on the SiO 2The layer is formed into a prescribed pattern, and SiO is formed. 2 Mask 18.

[0023] Next, in Figure 2 step S203 (refer to Figure 5 ), as an etching process of the semiconductor layer, the wafer is transferred into the chamber of an RIE (Reactive Ion Etching) apparatus, and a part of the semiconductor layer is etched using SiO 2 mask 18 as a mask to form the active layer ridge 20 that becomes a vertical stepped surface portion. In the etching, a gas containing Si and Cl in its molecular structure and Ar gas are used. As the gas containing Si and Cl in its molecular structure, for example, SiCl 4 can be used.

[0024] Conventionally, due to this etching, Si residues are generated, and there has been a problem that Si in the atmosphere adheres when the wafer is moved to the chamber for crystal growth. Therefore, the present application is characterized in that after the etching process and before the formation process of the buried layer, cleaning is performed while maintaining the shape of the active layer ridge 20.

[0025] Next, in Figure 2 step S204 (refer to Figure 5 ), as a cleaning process, the etched wafer is transferred to the chamber of an MOCVD apparatus to clean the semiconductor surface, that is, to remove Si attached to the side surface of the active layer ridge 20 and the surface of the n-type InP cladding layer 12 (the bottom surface of the mesa groove).

[0026] The cleaning process is performed, for example, at a wafer temperature of 560°C. For the temperature of the cleaning process, a temperature is selected at which the growth rate of the bottom surface of the mesa groove and the growth rate of the ridge side surface become substantially equal during crystal growth. Although it will be described later, in the subsequent formation process of the buried layer, as the optimum temperature for crystal growth, for example, 620°C is used. The cleaning process needs to be set at a temperature lower than this temperature. This is because if the temperature is not lower than the optimum temperature for crystal growth, the growth rate of the bottom surface of the mesa groove and the growth rate of the ridge side surface will not become equal.

[0027] The temperature range of the cleaning process is preferably 400°C or higher and 600°C or lower. If it is higher than 600°C, the growth rate of the bottom surface of the ridge during crystal growth becomes higher than the growth rate of the ridge side surface. If it is lower than 400°C, it is a temperature at which crystal growth cannot be performed, and only etching is performed, and a cleaning effect cannot be obtained.

[0028] When the temperature of the cleaning process is set to be equal to the temperature of the formation process of the buried layer, etching of the side surface starts from the upper part of the ridge, resulting in the collapse of the ridge shape. The inventors of the present application found the principle of the ridge shape collapse as follows.

[0029] At the optimum temperature for crystal growth, the growth rate of the bottom surface of the mesa trench is faster than that of the side surface of the ridge. This is because the atoms of the gas supplied to the side surface of the ridge diffuse to the bottom surface of the mesa trench.

[0030] On the other hand, the etching rate using the etching gas is equal between the bottom surface of the mesa trench and the side surface of the ridge. When the raw material gas and the etching gas are supplied simultaneously, the film thickness change rate is obtained by subtracting the etching rate from the growth rate. Therefore, in this case, the film thickness change rate of the side surface of the ridge becomes larger in the negative direction compared to the bottom surface of the mesa trench.

[0031] The inventor of the present application considered the reasons for the above-mentioned problems discovered by himself and found the solution. That is, it was found that by performing the cleaning process at a temperature lower than the optimum temperature for crystal growth (the temperature of the buried layer formation process), the film thickness changes of the side surface of the ridge and the bottom surface of the mesa trench can be made equal. This principle can be explained as follows.

[0032] When growing at a temperature lower than the optimum temperature for crystal growth, the diffusion distance of atoms becomes shorter, the diffusion to the bottom surface of the mesa trench is suppressed, and the growth rates of the bottom surface of the mesa trench and the side surface of the ridge become equal. On the other hand, the etching rate of the etching gas is equal between the bottom surface of the mesa trench and the side surface of the ridge even at low temperatures. As a result, the film thickness changes of the side surface of the ridge and the bottom surface of the mesa trench become equal. If the cleaning is performed near the film thickness change rate of 0, Si on the semiconductor surface can be removed while maintaining the ridge shape unchanged, and the Si concentration at the interface between the side surface of the ridge and the buried layer is set to 1.0E17 / cm 3 The following.

[0033] Figure 7 It is a diagram showing the relationship between the temperature curve from the cleaning process (step S204) to the buried layer formation process (step S205) and the supplied gas.

[0034] From the cleaning process to the buried layer formation process described later, a group V raw material gas (for example, phosphine (PH 3 )) is always supplied. This is a general measure for preventing group V atoms from detaching from the surface and is always supplied when heating the wafer in the MOCVD apparatus.

[0035] In the cleaning process, a group III raw material gas (for example, trimethylindium ((CH 3 )) 3 In: TMI)), which is a raw material for crystal growth, and a halogen-based etching gas (for example, tert-butyl chloride ((CH 3 )) 3CCl: TBCl)). By simultaneously supplying group III source gases and etching gases, reattachment of the detached Si to the semiconductor surface can be suppressed, improving the cleaning effect. Here, the supply amounts of the source gases and the etching gases are adjusted such that the film thickness variations at the ridge side surfaces and the bottom surfaces of the mesa grooves become near 0. In addition, the gases to be supplied are not limited to those described in the figure. For example, HCl or the like can also be used in the etching gas.

[0036] Next, in Figure 2 step S205 (refer to Figure 6 ), as the formation process of the buried layer, in the MOCVD apparatus, the temperature of the wafer in the cleaning process is increased to, for example, 620 °C (step S205-1), and crystal growth is performed on both sides of the active layer ridge 20 (step S205-2), thereby forming the buried layer 40.

[0037] In the temperature increasing process (step S205-1), group III source gases and etching gases are not supplied, and crystal growth and etching are not performed either. The temperature to be increased is set to the optimal temperature for the semiconductor material on which crystal growth is to be performed next. For the optimal temperature for crystal growth, for example, for InP it is 600 to 650 °C, and for GaAs it is 650 to 750 °C. The optimal temperature can be appropriately selected for other semiconductor materials as well.

[0038] In the crystal growth process (step S205-2), by using the MOCVD method, a p-type InP current blocking layer 41, an n-type InP current blocking layer 42, and a p-type InP current blocking layer 44 are sequentially grown on both sides of the active layer ridge 20, thereby forming the buried layer 40.

[0039] Next, in Figure 2 step S206 (refer to Figure 1 ), as the formation process of the contact layer, after removing the SiO 2 mask 18, a p-type InP cladding layer 46 is formed on the surfaces of the buried layer 40 and the active layer ridge 20 by using the MOCVD method. Finally, a p-type InGaAs contact layer 48 is formed on the surface of the p-type InP cladding layer 46, completing the Figure 1 photonic semiconductor device 101 shown.

[0040] In addition, although the substrate 10 is set to n-type InP, the effects of the present application can also be obtained even if it is p-type InP. In this case, the conductivity types of the respective layers of the cladding layer, the blocking layer, and the contact layer are opposite to those described above. Alternatively, the substrate can be set to semi-insulating InP. In this case, the conductivity type structure of the cladding layer on the substrate is determined, and appropriate conductivity types are appropriately used for the conductivity types of the respective layers.

[0041] In addition, a layer with high resistance can also be used in the blocking layer. For example, it is InP doped with Fe. Additionally, the substrate is not limited to InP. For example, substrates such as GaAs or GaN can also be used. In this case, GaAs-based or GaN-based epitaxial layers are appropriately used. In addition, the etching process can also be a method other than RIE, and can also be wet etching.

[0042] In addition, between the etching process and the cleaning process, surface cleaning using a chemical solution treatment or the like can also be performed. However, since Si also adheres in the air even in this case, the cleaning process of the present application is indispensable. In addition, for parts other than the important structural elements of the present application, the structure can also be different from that of the embodiment according to the desired characteristics.

[0043] As described above, according to the manufacturing method of the optoelectronic semiconductor device 101 according to the first embodiment, it includes: a step of forming a semiconductor layer on the surface of the n-type InP substrate 10; an etching step of etching a part of the semiconductor layer to form the active layer ridge 20; a cleaning step of removing Si attached to the surface of the etched semiconductor layer while supplying a raw material gas for crystal growth and an etching gas; and a crystal growth step of forming the buried layer 40 on both sides of the active layer ridge 20 at a processing temperature higher than the temperature in the cleaning step. Therefore, cleaning can be performed while maintaining the ridge shape.

[0044] Embodiment 2

[0045] In Embodiment 1, the film thickness change rate is set to be near 0, but in Embodiment 2, the case where the film thickness change rate is adjusted to be greater than 0 will be described.

[0046] In the optoelectronic semiconductor device according to the second embodiment of the present application, the film thickness change rate is made greater than 0 in the cleaning step. For example, it is adjusted to 0.05 nm / sec. In this case, even when the cleaning time is implemented for 20 minutes in order to fully exert the cleaning effect, the film thickness only increases by 60 nm. If this value is used, no reduction in crystallinity occurs. Regarding other manufacturing methods of the optoelectronic semiconductor device based on Embodiment 2, they are the same as those of the optoelectronic semiconductor device in Embodiment 1, and their descriptions are omitted.

[0047] It is not preferable to make the film thickness change rate less than 0. This is because if so, the ridge side surface and the bottom surface of the mesa groove decrease, and in particular, the decrease in the film thickness of the ridge side surface involves deterioration of the device characteristics. That is, it is preferably adjusted so that the film thickness change rate is set to 0, or is slightly greater than 0 considering the deviation.

[0048] The increase in film thickness during the cleaning process is preferably 0 nm or more and less than 100 nm. If the film thickness increases by 100 nm or more during the cleaning process, the crystallinity decreases due to growth at low temperature.

[0049] Therefore, by selecting the raw material gas supply amount, the etching gas supply amount, and the cleaning time, the film thickness change rate is adjusted so that the increase in film thickness during the cleaning process is in the range of 0 nm or more and less than 100 nm.

[0050] In this way, if the film thickness change rate is greater than 0, for example, 0.05 nm / sec, not only can the cleaning effect be sufficiently obtained, but also the reduction in film thickness on the ridge side can be reliably suppressed.

[0051] As described above, according to the manufacturing method of the optoelectronic semiconductor device according to the second embodiment, the cleaning process is set such that the film thickness change rate of the crystal is greater than 0 and the increase in film thickness is in the range of 0 or more and less than 100 nm. Therefore, the Si concentration at the interface between the ridge side and the buried layer can be set to 1.0E17 / cm 3 Hereinafter, and reliably suppressing the reduction in film thickness on the ridge side, stable production can be performed more stably.

[0052] In addition, in the first and second embodiments, a process of performing crystal growth at a low temperature may be provided between the cleaning process and the temperature increase process. By growing at a low temperature, the crystal can be reliably attached to the ridge side, so that the barrier layer can be stably formed. In addition, for this purpose, crystal growth may be performed in the temperature increase process. However, these are growths at low temperatures. If the growth is thick, the crystallinity decreases. Therefore, the film thickness of the crystal growth at low temperature and the crystal growth in the temperature increase process is preferably set to 100 nm or less.

[0053] Embodiment 3

[0054] In Embodiment 3, a case where a dopant having a conductivity type different from that of the substrate is supplied while performing a cleaning process will be described.

[0055] In the optoelectronic semiconductor device according to the third embodiment of the present application, in the cleaning process, a gas having a dopant having a conductivity type different from that of the substrate is added to the supply gas. In the case of applying to the cleaning process in the first and second embodiments, by supplying the same dopant as the p-type InP current blocking layer 41 during cleaning, the ridge side and the bottom surface of the mesa groove have the same conductivity type as the p-type InP current blocking layer 41. When the buried layer 40 is formed, the desired blocking layer effect can be obtained. As a gas having a dopant having a conductivity type different from that of the substrate, hydrogen sulfide (H can be cited in the case of using a p-type substrate 2S), in the case of using an n-type substrate, diethylzinc ((C 2 H 5 ) 2 Zn: DEZn) can be cited. However, it is not limited thereto, and other gases may also be used. Regarding other manufacturing methods of the optoelectronic semiconductor device according to Embodiment 3, they are the same as those of the optoelectronic semiconductor devices of Embodiments 1 and 2, and the description thereof is omitted.

[0056] If an undoped layer is formed in the cleaning process, the blocking effect is weakened and the characteristics deteriorate. In this regard, in Embodiment 3, an undoped layer is not formed in the cleaning process. In particular, in the case of applying the cleaning process of Embodiment 2, that is, when the film thickness change rate is set to positive, a part of the p-type InP current blocking layer 41 and the p-type InP current blocking layer 44 is formed in the cleaning process.

[0057] As described above, according to the manufacturing method of the optoelectronic semiconductor device according to the present Embodiment 3, the cleaning process is set to include a gas containing a dopant having a conductivity type different from that of the substrate in the supplied gas. Therefore, an undoped layer is not formed in the cleaning process, and the desired blocking layer effect can be obtained.

[0058] Embodiment 4

[0059] In Embodiment 4, the case where a cleaning process is performed while supplying a dopant that becomes a high resistance is described.

[0060] In the optoelectronic semiconductor device according to Embodiment 4 of the present application, in the cleaning process, a gas containing a dopant having a semi-insulating property that becomes a high resistance is added to the supplied gas. By supplying a semi-insulating dopant that becomes a high resistance during cleaning, the ridge side surface and the bottom surface of the mesa groove become high resistance. When a buried layer is formed, the desired blocking layer effect can be obtained. As a gas containing a dopant having a semi-insulating property that becomes a high resistance, ferrocene (Fe(C 5 H 5 ) 2 : Cp 2 Fe) can be cited. When it is used, Fe is doped to become a high resistance. Regarding other manufacturing methods of the optoelectronic semiconductor device according to Embodiment 4, they are the same as those of the optoelectronic semiconductor devices of Embodiments 1 and 2, and the description thereof is omitted.

[0061] In Embodiment 4, the present application can be most effectively applied by using a high-resistance layer in the buried layer. In addition, in this case, appropriate design is performed so that the blocking layer also becomes a high-resistance layer and other desired characteristics are obtained.

[0062] As described above, according to the manufacturing method of the optoelectronic semiconductor device according to the fourth embodiment, the cleaning process is set to include a gas containing a semi-insulating dopant in the supplied gas. Therefore, the layer formed in the cleaning process becomes a high resistance, and the desired barrier layer effect can be obtained.

[0063] This application describes various exemplary embodiments and examples. However, the various features, modes, and functions described in one or more embodiments are not limited to the application of a specific embodiment, and can be applied individually or in various combinations to the embodiments. Therefore, within the technical scope disclosed in this application specification, countless unillustrated variations can be conceived. For example, it includes cases where at least one structural element is deformed, cases where at least one structural element is added, or cases where at least one structural element is omitted. Furthermore, cases where at least one structural element is extracted and combined with the structural elements of other embodiments.

[0064] Description of Reference Numerals

[0065] 10... n-type InP substrate; 12... n-type InP cladding layer; 12a... convex portion; 14... AlGaInAs active layer; 16... p-type InP cladding layer; 20... active layer ridge; 40... buried layer; 41... p-type InP current blocking layer; 42... n-type InP current blocking layer; 44... p-type InP current blocking layer; 101... optoelectronic semiconductor device.

Claims

1. A method for manufacturing an opto-semiconductor device, characterized in that, comprising: a step of forming a semiconductor layer on the surface of a substrate; an etching step of etching a part of the semiconductor layer to form a ridge; a cleaning step of removing an attachment on the surface of the etched semiconductor layer while supplying a raw material gas for crystal growth and an etching gas; and a crystal growth step of forming current blocking layers on both sides of the ridge at a processing temperature higher than the temperature in the cleaning step.

2. The method for manufacturing an opto-semiconductor device according to claim 1, characterized in that, the heating temperature range in the cleaning step is 400 °C or higher and 600 °C or lower.

3. The method for manufacturing an opto-semiconductor device according to claim 1 or 2, characterized in that, the raw material gas includes a first raw material gas and a second raw material gas.

4. The method for manufacturing an opto-semiconductor device according to claim 3, characterized in that, in a temperature rising step between the cleaning step and the crystal growth step, the first raw material gas is supplied.

5. The method for manufacturing an opto-semiconductor device according to claim 3, characterized in that, the first raw material gas is a group V gas and the second raw material gas is a group III gas.

6. The method for manufacturing an opto-semiconductor device according to claim 5, characterized in that, the etching gas is a halogen gas.

7. The method for manufacturing an opto-semiconductor device according to any one of claims 1, 2, 4 to 6, characterized in that, in the cleaning step, the variation speed obtained by subtracting the etching rate from the growth rate of the crystal film thickness is greater than 0 and the increase amount of the film thickness is in a range greater than 0 and less than 100 nm.

8. The method for manufacturing an opto-semiconductor device according to any one of claims 1, 2, 4 to 6, characterized in that, in the cleaning step, the supplied gas contains a gas having a dopant that becomes a conductivity type different from that of the substrate.

9. The method for manufacturing an opto-semiconductor device according to any one of claims 1, 2, 4 to 6, characterized in that, in the cleaning step, the supplied gas contains a gas having a semi-insulating dopant.

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