Semiconductor memory device

Abstract

At the bottom of the cell, transistors (N1-N12) are formed, corresponding to the drive transistors (PD1, PD2), access transistors (PG1, PG2), read drive transistor (RPD1), and read access transistor (RPG1). At the top of the cell, transistors (P1, P2) are formed, corresponding to the load transistors (PU1, PU2). Transistors (P1, P2) overlap with transistors (N3, N8) when viewed from above.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device including a three-dimensional structured transistor, and more particularly to a layout structure of a dual-port SRAM (Static Random Access Memory) cell using the three-dimensional structured transistor. Background Art

[0002] SRAM is widely used in semiconductor integrated circuits. Among SRAMs, there is a dual-port SRAM including one write port and one read port (eg, Patent Document 1).

[0003] Transistors, the fundamental components of LSI, have achieved increased integration density, lower operating voltage, and higher operating speeds by reducing gate length (scaling). However, recent issues have arisen, such as excessive scaling leading to increased off-state current, which in turn significantly increases power consumption. To address this issue, research has been actively underway on three-dimensional transistors, shifting from the conventional planar structure to a three-dimensional one.

[0004] In non-patent documents 1 and 2, a three-dimensional structure device and an SRAM unit (hereinafter referred to as a unit) using the same are disclosed as a new device. The three-dimensional structure device is obtained by stacking three-dimensional structured P-type FET and N-type FET on a substrate in a direction perpendicular to the substrate.

[0005] Patent Document 1: U.S. Patent No. 9362292 ( Figure 1 )

[0006] Non-Patent Literature 1: Ryckaert J. et al., “The Complementary FET (CFET) for CMOS scaling beyond N3,” 2018 Symposium on VLSI Technology Digest of Technical Papers

[0007] Non-patent literature 2: A.Mocuta et al., "Enabling CMOS Scaling Towards 3nm andBeyond", 2018 Symposium on VLSI Technology Digest of Technical Papers Summary of the Invention

[0008] -Technical problem to be solved by the invention-

[0009] In this specification, a three-dimensional structure device formed by stacking a P-type FET and an N-type FET perpendicularly to a substrate is referred to as a CFET (Complementary Field Effect Transistor) with reference to the description in Non-Patent Document 1. Furthermore, the direction perpendicular to the substrate is referred to as the depth direction.

[0010] However, so far, no one has done detailed research on the layout of a dual-port SRAM cell using CFETs.

[0011] The purpose of the present disclosure is to provide a layout structure of a dual-port SRAM cell using CFET.

[0012] -Technical solutions to technical problems-

[0013] The first aspect discloses a semiconductor memory device including a dual-port SRAM cell, wherein the dual-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. In the first transistor, one node is connected to a first power supply supplying a first voltage, another node is connected to the first node, and a gate is connected to a second node. In the second transistor, one node is connected to the first power supply, another node is connected to the second node, and a gate is connected to the first node. In the third transistor, one node is connected to the first node, another node is connected to a second power supply supplying a second voltage, the second voltage being different from the first voltage, and the gate is connected to the second node. In the fourth transistor, one node is connected to the second node, another node is connected to the second power supply, and the gate is connected to the first node. In the fifth transistor, one node is connected to the first write bit line, another node is connected to the first node, and the gate is connected to the write word line. In the sixth transistor, one node is connected to the second write bit line, which forms a complementary bit line pair with the first write bit line, another node is connected to the second node, and the gate is connected to the write word line. In the seventh transistor, one node is connected to the second power supply, and the gate is connected to the second node. In the eighth transistor, one node is connected to another node in the seventh transistor, another node is connected to a read bit line, and the gate is connected to a read word line. The third to sixth transistors are each formed of a first conductivity type transistor formed in a first layer and having a three-dimensional structure. The first and second transistors are each formed of a second conductivity type transistor formed in a second layer, the second layer being different from the first layer, and the second conductivity type being different from the first conductivity type. At least a portion of the first and second transistors overlaps with the third and fourth transistors, respectively, when viewed from above. The seventh transistor and the eighth transistor include the first conductivity type three-dimensional structure transistor formed in the first layer, and are arranged in a first direction, which is a direction in which the channel portions from the first transistor to the eighth transistor extend.

[0014] According to the present disclosure, a dual-port SRAM circuit is formed by the first to eighth transistors. In addition, the third to sixth transistors are respectively formed by a first-conductivity-type three-dimensional structure transistor formed on the first layer. The first and second transistors are respectively formed by a second-conductivity-type three-dimensional structure transistor formed on the second layer. The seventh transistor and the eighth transistor are respectively composed of a first-conductivity-type three-dimensional structure transistor formed on the first layer. In other words, the first to eighth transistors constituting the dual-port SRAM circuit are respectively formed by three-dimensional structure transistors. In this way, a dual-port SRAM cell using CFETs can be realized.

[0015] Furthermore, at least a portion of the first and second transistors overlap with the third and fourth transistors, respectively, when viewed from above. That is, the first and second transistors are stacked with the third and fourth transistors, respectively. Furthermore, the seventh and eighth transistors are arranged along the first direction. This reduces the area of the dual-port SRAM cell.

[0016] Therefore, a dual-port SRAM cell using CFET can be realized while reducing the area of the dual-port SRAM cell.

[0017] The second aspect discloses a semiconductor memory device including a dual-port SRAM cell, wherein the dual-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. In the first transistor, one node is connected to a first power supply supplying a first voltage, another node is connected to the first node, and a gate is connected to a second node. In the second transistor, one node is connected to the first power supply, another node is connected to the second node, and a gate is connected to the first node. In the third transistor, one node is connected to the first node, another node is connected to a second power supply supplying a second voltage, the second voltage being different from the first voltage, and the gate is connected to the second node. In the fourth transistor, one node is connected to the second node, another node is connected to the second power supply, and the gate is connected to the first node. In the fifth transistor, one node is connected to the first write bit line, another node is connected to the first node, and the gate is connected to the write word line. In the sixth transistor, one node is connected to the second write bit line, which forms a complementary bit line pair with the first write bit line, another node is connected to the second node, and the gate is connected to the write word line. In the seventh transistor, one node is connected to the first power supply, and the gate is connected to the second node. In the eighth transistor, one node is connected to another node in the seventh transistor, another node is connected to a read bit line, and the gate is connected to a read word line. The third to sixth transistors are each formed of a first conductivity type transistor formed in a first layer and having a three-dimensional structure. The first and second transistors are each formed of a second conductivity type transistor formed in a second layer, the second layer being different from the first layer, and the second conductivity type being different from the first conductivity type. At least a portion of the first and second transistors overlaps with the third and fourth transistors, respectively, when viewed from above. The seventh transistor and the eighth transistor include three-dimensional transistors of the second conductivity type formed in the second layer, and are arranged in a first direction, which is a direction in which the channel portions from the first transistor to the eighth transistor extend.

[0018] According to the present disclosure, a dual-port SRAM circuit is formed by the first to eighth transistors. In addition, the third to sixth transistors are respectively formed by a first-conductivity-type three-dimensional structure transistor formed on the first layer. The first and second transistors are respectively formed by a second-conductivity-type three-dimensional structure transistor formed on the second layer. The seventh and eighth transistors include a second-conductivity-type three-dimensional structure transistor formed on the second layer. In other words, the first to eighth transistors that constitute the dual-port SRAM circuit are respectively formed by a three-dimensional structure transistor. In this way, a dual-port SRAM cell using CFETs can be realized.

[0019] Furthermore, at least a portion of the first and second transistors overlap with the third and fourth transistors, respectively, when viewed from above. That is, the first and second transistors are stacked with the third and fourth transistors, respectively. Furthermore, the seventh and eighth transistors are arranged along the first direction. This reduces the area of the dual-port SRAM cell.

[0020] Therefore, a dual-port SRAM cell using CFET can be realized while reducing the area of the dual-port SRAM cell.

[0021] The third aspect discloses a semiconductor memory device including a dual-port SRAM cell, wherein the dual-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. In the first transistor, one node is connected to a first power supply supplying a first voltage, another node is connected to the first node, and a gate is connected to a second node. In the second transistor, one node is connected to the first power supply, another node is connected to the second node, and a gate is connected to the first node. In the third transistor, one node is connected to the first node, another node is connected to a second power supply supplying a second voltage different from the first voltage, and a gate is connected to the second node. The fourth transistor has one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node. The fifth transistor has one node connected to the first write bit line, another node connected to the first node, and a gate connected to the write word line. The sixth transistor has one node connected to the second write bit line, which forms a complementary bit line pair with the first write bit line, another node connected to the second node, and a gate connected to the write word line. The seventh transistor has one node connected to the first power supply or the second power supply, and a gate connected to the second node. The eighth transistor has one node connected to the other node in the seventh transistor, another node connected to a read bit line, and a gate connected to a read word line. The third to sixth transistors respectively include a first and a second stereoscopic transistor. The first stereoscopic transistor is a first conductivity type stereoscopic transistor formed in a first layer, and the second stereoscopic transistor is a first conductivity type stereoscopic transistor formed in a second layer different from the first layer so that at least a portion overlaps with the first stereoscopic transistor in a plan view. The first and second transistors each include a second conductivity type stereoscopic transistor formed in the second layer, which is different from the first conductivity type. The seventh and eighth transistors respectively include a third three-dimensional structure transistor and a fourth three-dimensional structure transistor, the third three-dimensional structure transistor is a three-dimensional structure transistor of the first conductive type or the second conductive type formed on the first layer, and the fourth three-dimensional structure transistor is a three-dimensional structure transistor of the same conductive type as the third three-dimensional structure transistor formed on the second layer in a manner that at least a portion overlaps with the third three-dimensional structure transistor when viewed from above.

[0022] According to the present disclosure, a dual-port SRAM circuit is formed by the first to eighth transistors. In addition, the third to sixth transistors respectively include a first stereo structure transistor and a second stereo structure transistor, the first stereo structure transistor is a stereo structure transistor of the first conductivity type formed on the first layer, and the second stereo structure transistor is a stereo structure transistor of the first conductivity type formed on the second layer. The first and second transistors respectively include a stereo structure transistor of the second conductivity type formed on the second layer. The seventh and eighth transistors respectively include a third stereo structure transistor and a fourth stereo structure transistor, the third stereo structure transistor is a stereo structure transistor of the first conductivity type or the second conductivity type formed on the first layer, and the fourth stereo structure transistor is a stereo structure transistor of the same conductivity type as the third stereo structure transistor formed on the second layer. In other words, the first to eighth transistors constituting the dual-port SRAM circuit are respectively composed of stereo structure transistors. In this way, a dual-port SRAM cell using CFETs can be realized.

[0023] Furthermore, at least a portion of the first three-dimensional structure transistor overlaps with the second three-dimensional structure transistor when viewed from above. At least a portion of the third three-dimensional structure transistor overlaps with the fourth three-dimensional structure transistor when viewed from above. In other words, the first and second three-dimensional structure transistors constituting the third through sixth transistors are stacked separately. The third and fourth three-dimensional structure transistors constituting the seventh and eighth transistors are stacked separately. This reduces the area of the dual-port SRAM cell.

[0024] Therefore, a dual-port SRAM cell using CFET can be realized while reducing the area of the dual-port SRAM cell.

[0025] The fourth aspect discloses a semiconductor memory device, including a dual-port SRAM cell, wherein the dual-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. In the first transistor, one node is connected to a first power supply supplying a first voltage, another node is connected to the first node, and a gate is connected to a second node. In the second transistor, one node is connected to the first power supply, another node is connected to the second node, and a gate is connected to the first node. In the third transistor, one node is connected to the first node, another node is connected to a second power supply supplying a second voltage, the second voltage being different from the first voltage, and the gate is connected to the second node. In the fourth transistor, one node is connected to the second node, another node is connected to the second power supply, and the gate is connected to the first node. In the fifth transistor, one node is connected to the first write bit line, another node is connected to the first node, and the gate is connected to the write word line. In the sixth transistor, one node is connected to the second write bit line, which forms a complementary bit line pair with the first write bit line, another node is connected to the second node, and the gate is connected to the write word line. In the seventh transistor, one node is connected to the first power supply, and the gate is connected to the second node. In the eighth transistor, one node is connected to another node in the seventh transistor, another node is connected to a read bit line, and the gate is connected to a read word line. The third to sixth transistors are each formed of a first conductivity type stereoscopic transistor formed in the first layer. The first and second transistors each include a second conductivity type stereoscopic transistor formed in the second layer, the second layer being different from the first layer, and the second conductivity type being different from the first conductivity type. The seventh transistor includes a second conductivity type stereoscopic transistor formed in the second layer, and at least a portion thereof overlaps with the third transistor in a plan view. The eighth transistor includes a three-dimensional structure transistor of the second conductivity type formed in the second layer, and is arranged along the second direction with the seventh transistor, and the second direction is a direction perpendicular to the first direction in which the channel portion from the first transistor to the eighth transistor extends.

[0026] According to the present disclosure, a dual-port SRAM circuit is formed by the first to eighth transistors. In addition, the third to sixth transistors are each formed by a first-conductivity-type stereoscopic transistor formed on the first layer. The first and second transistors each include a second-conductivity-type stereoscopic transistor formed on the second layer. The seventh and eighth transistors each include a second-conductivity-type stereoscopic transistor formed on the second layer. In this way, a dual-port SRAM cell using CFETs can be realized.

[0027] Furthermore, at least a portion of the seventh transistor overlaps with the third transistor when viewed from above. That is, the seventh transistor and the third transistor are stacked separately. Furthermore, the eighth transistor and the seventh transistor are arranged along the second direction. This reduces the area of the dual-port SRAM cell.

[0028] Therefore, a dual-port SRAM cell using CFET can be realized while reducing the area of the dual-port SRAM cell.

[0029] -Effects of the Invention-

[0030] According to the present disclosure, a dual-port SRAM cell using CFET can be realized while reducing the area of the dual-port SRAM cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 1 is a plan view showing an example of the layout structure of a dual-port SRAM cell according to the first embodiment;

[0032] Figure 2 is a cross-sectional view showing an example of the layout structure of a dual-port SRAM cell according to the first embodiment;

[0033] Figure 3 1 is a circuit diagram showing the configuration of a dual-port SRAM cell according to the first embodiment;

[0034] Figure 4 is a plan view showing another example of the layout structure of the dual-port SRAM cell according to the first embodiment;

[0035] Figure 5 is a plan view showing another example of the layout structure of the dual-port SRAM cell according to the first embodiment;

[0036] Figure 6 is a plan view showing another example of the layout structure of the dual-port SRAM cell according to the first embodiment;

[0037] Figure 7 1 is a circuit diagram showing the configuration of a dual-port SRAM cell according to a second embodiment;

[0038] Figure 8 1 is a plan view showing an example of the layout structure of a dual-port SRAM cell according to the second embodiment;

[0039] Figure 9 is a plan view showing another example of the layout structure of the dual-port SRAM cell according to the second embodiment;

[0040] Figure 10is a plan view showing another example of the layout structure of the dual-port SRAM cell according to the second embodiment;

[0041] Figure 11 is a plan view showing another example of the layout structure of the dual-port SRAM cell according to the second embodiment;

[0042] Figure 12 is a plan view showing another example of the layout structure of the dual-port SRAM cell according to the second embodiment;

[0043] Figure 13 is a cross-sectional view showing the configuration of a semiconductor device including a CFET;

[0044] Figure 14 is a cross-sectional view showing the configuration of a semiconductor device including a CFET;

[0045] Figure 15 is a cross-sectional view showing the configuration of a semiconductor device including a CFET;

[0046] Figure 16 is a cross-sectional view showing the configuration of a semiconductor device including a CFET. DETAILED DESCRIPTION

[0047] The following embodiments are described with reference to the accompanying drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells (referred to as "cells" in this specification as appropriate), at least some of which include CFETs, i.e., devices comprising a three-dimensional structure in which P-type FETs and N-type FETs are stacked on a substrate in a direction perpendicular to the substrate.

[0048] First, the basic structure of CFET is described. Figures 13 to 16 is a diagram showing the configuration of a semiconductor device including a CFET, Figure 13 is a cross-sectional view in the X direction, Figure 14 It is a cross-sectional view of the gate portion in the Y direction. Figure 15 It is a cross-sectional view of the source / drain portion in the Y direction. Figure 16 It is a top view. It should be noted that the X direction is the direction in which the nanowire extends, the Y direction is the direction in which the gate extends, and the Z direction is the direction perpendicular to the substrate surface. Figures 13 to 15 This is a simplified diagram; the sizes and positions of the various parts may not be consistent.

[0049] In this semiconductor device, an element isolation region 302 is formed on the surface of a semiconductor substrate 301 such as a silicon (Si) substrate, and an element active region 30a is defined by the element isolation region 302. In the element active region 30a, an N-type FET is formed on a P-type FET.

[0050] In the device active region 30a, a stacked transistor structure 390a is formed on a semiconductor substrate 301. The stacked transistor structure 390a includes a gate structure 391 formed on the semiconductor substrate 301. The gate structure 391 includes a gate electrode 356, a plurality of nanowires 358, a gate insulating film 355, and an insulating film 357. The gate electrode 356 extends in the Y direction and rises in the Z direction. The nanowires 358 penetrate the gate electrode 356 in the X direction and are arranged in the Y and Z directions. The gate insulating film 355 is formed between the gate electrode 356 and the nanowires 358. Both the gate electrode 356 and the gate insulating film 355 are formed in the X direction at positions set back from both ends of the nanowires 358, and the insulating film 357 is formed on these setback portions. On the semiconductor substrate 301, insulating films 316 are formed on both sides of the insulating film 357. 321 and 322 denote interlayer insulating films.

[0051] like Figure 14 As shown, the gate electrode 356 is connected to the upper layer wiring via a contact 385 provided in the opening 375 .

[0052] For example, the gate electrode 356 can be made of titanium, titanium nitride, or polysilicon. For example, the gate insulating film 355 can be made of a high-dielectric-constant material such as hafnium oxide, aluminum oxide, or hafnium aluminum oxide. For example, the nanowires 358 can be made of silicon. For example, the insulating films 316 and 357 can be made of silicon oxide or silicon nitride.

[0053] In this semiconductor device, there are four nanowires 358 arranged along the Z direction. In the device active region 30a, a P-type semiconductor layer 331p is formed at each end of two nanowires 358 on the side closer to the semiconductor substrate 301. Two local wirings 386 in contact with the P-type semiconductor layer 331p are formed so as to sandwich a gate structure 391 along the X direction. Furthermore, an N-type semiconductor layer 341n is formed at each end of the two nanowires 358 on the side farther from the semiconductor substrate 101. Two local wirings 388 in contact with the N-type semiconductor layer 341n are formed so as to sandwich the gate structure 391 along the X direction. An insulating film 332 is formed between the local wirings 386 and 388. An insulating film 389 is formed over the local wirings 388. For example, the P-type semiconductor layer 331p is a P-type SiGe layer, and the N-type semiconductor layer 341n is an N-type Si layer. For example, the insulating film 332 can be made of silicon oxide or silicon nitride.

[0054] like Figure 15 As shown, the local wiring 388 is connected to the embedded wiring 3101 via the contact 3071. The local wiring 386 is connected to the embedded wiring 3102 via the contact 3072.

[0055] As described above, stacked transistor structure 390a includes a P-type FET, which includes a gate electrode 356, a nanowire 358, a gate insulating film 355, and a P-type semiconductor layer 331p. In this P-type FET, one P-type semiconductor layer 331p functions as a source region, the other P-type semiconductor layer 331p functions as a drain region, and the nanowire 358 functions as a channel. Stacked transistor structure 390a also includes an N-type FET, which includes a gate electrode 356, a nanowire 358, a gate insulating film 355, and an N-type semiconductor layer 341n. In this N-type FET, one N-type semiconductor layer 341n functions as a source region, the other N-type semiconductor layer 341n functions as a drain region, and the nanowire 358 functions as a channel.

[0056] It should be noted that the upper layer of the stacked transistor structure uses contacts and metal wiring to perform wiring between transistors, but these can be achieved using known wiring processes.

[0057] It should be noted that here, the total number of nanowires in the P-type FET and the N-type FET is eight, four in the Y direction and two in the Z direction, but the number of nanowires is not limited to this. The number of nanowires in the P-type FET and the N-type FET can also be different.

[0058] In this specification, the semiconductor layer portions formed at both ends of the nanowire and constituting the source or drain terminals of the transistor are referred to as “pads.” In the above-described basic structure example of the CFET, the P-type semiconductor layer 331p and the N-type semiconductor layer 341n correspond to the pads.

[0059] In the top views and cross-sectional views of the following embodiments, illustrations of various insulating films, etc., may be omitted. In the top views and cross-sectional views of the following embodiments, the nanowires and the pads on both sides may be simplified linear shapes. In this specification, expressions such as "same size" refer to identical dimensions, etc., including variations in manufacturing.

[0060] In this specification, the source and drain of a transistor are referred to as "nodes" of the transistor, depending on the situation. That is, a node of a transistor refers to the source or drain of the transistor, and two nodes of a transistor refer to the source and drain of the transistor.

[0061] In this specification, P-type FETs and N-type FETs are basically stacked, but in some cases, P-type FETs or N-type FETs are formed only in the upper (or lower) layer. This formation method is as follows: After forming the upper (or lower) layer elements, the upper (or lower) layer elements are partially removed (for example, by removing the pad portion or removing the gate wiring and pad portion), thereby forming the P-type FET or N-type FET only in the upper (or lower) layer. Furthermore, when forming the upper (or lower) layer elements by epitaxial growth of the pad portion, the upper (or lower) layer is partially removed, thereby forming the P-type FET or N-type FET only in the upper (or lower) layer.

[0062] In this specification, P-type FETs and N-type FETs are basically stacked together. However, in some cases, FETs of the same conductivity type (P-type FETs or N-type FETs) are stacked in the upper and lower layers. In other words, FETs of different conductivity types may be formed in at least one of the upper and lower layers. The formation method is as follows: For example, when forming an N-type FET (or P-type FET) in a portion of the upper layer (or lower layer), the portion where the N-type FET (or P-type FET) is formed is masked, and the remaining portion is doped to P conductivity type (or N conductivity type). Then, the portion other than the portion where the N-type FET is formed is masked and doped to N conductivity type (or P conductivity type). In this way, FETs of different conductivity types can be formed in at least one of the upper and lower layers, thereby reliably stacking FETs of the same conductivity type.

[0063] In the following embodiments, “VDD” and “VSS” are used to represent voltage or power supply itself.

[0064] In the following embodiments and their modifications, the same components and the like are denoted by the same reference numerals and their description may be omitted.

[0065] (First embodiment)

[0066] Figure 1 and Figure 2 1 is a diagram showing an example of the layout structure of a dual-port SRAM cell according to the first embodiment. Figure 1 (a)~ Figure 1 (c) is a top view, Figure 2 (a)~ Figure 2 (c) is a horizontal cross-sectional view from above. Specifically, Figure 1 (a) shows the lower part, i.e., the part including the three-dimensional structure transistor (here, N-type nanowire FET) formed on the side close to the substrate. Figure 1 (b) shows the upper portion, i.e., the portion including the three-dimensional transistor (here, a P-type nanowire FET) formed on the side away from the substrate. Figure 1(c) shows the M1 and M2 wiring layers, that is, the metal wiring layers above the portion where the three-dimensional structure transistors are formed. Figure 2 (a) is the cross section taken along line X1-X1', Figure 2 (b) is the cross section taken along line X2-X2', Figure 2 (c) is a cross section taken along line X3-X3'.

[0067] Figure 3 1 is a circuit diagram showing the configuration of a dual-port SRAM cell according to the first embodiment. Figure 3 As shown, in a dual-port SRAM cell, a dual-port SRAM circuit is formed by load transistors PU1 and PU2, drive transistors PD1 and PD2, access transistors PG1 and PG2, read drive transistor RPD1, and read access transistor RPG1. Load transistors PU1 and PU2 are P-type FETs, while drive transistors PD1 and PD2, access transistors PG1 and PG2, read drive transistor RPD1, and read access transistor RPG1 are N-type FETs.

[0068] Load transistor PU1 is provided between power supply VDD and a first node NA, and drive transistor PD1 is provided between the first node NA and power supply VSS. The gates of load transistor PU1 and drive transistor PD1 are connected to a second node NB, forming an inverter INV1. Load transistor PU2 is provided between power supply VDD and a second node NB, and drive transistor PD2 is provided between the second node NB and power supply VSS. The gates of load transistor PU2 and drive transistor PD2 are connected to a first node NA, forming an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, forming a latch.

[0069] Access transistor PG1 is provided between write bit line WBL and a first node NA, with its gate connected to write word line WWL. Access transistor PG2 is provided between write bit line WBLB and a second node NB, with its gate connected to write word line WWL. It should be noted that write bit lines WBL and WBLB form a complementary write bit line pair.

[0070] The source of read driver transistor RPD1 is connected to power supply VSS, the gate is connected to second node NB, and the drain is connected to the source of read access transistor RPG1. The gate of read access transistor RPG1 is connected to read word line RWL, and the drain is connected to read bit line RBL.

[0071] In a dual-port SRAM circuit, when the write bit lines WBL and WBLB, which constitute the complementary write bit line pair, are driven high and low, respectively, and the write word line WWL reaches a high level, the high level is written to the first node NA, and the low level is written to the second node NR. Conversely, when the write bit lines WBL and WBLB are driven low and high, respectively, and the write word line WWL is driven high, the low level is written to the first node NA, and the high level is written to the second node NB. Furthermore, when the write word line WWL is driven low after data has been written to the first node NA and the second node NB, the latch state is locked, maintaining the data already written to the first node NA and the second node NB.

[0072] After precharging read bit line RBL to a high level and driving read word line RWL to a high level, the state of read bit line RBL is determined according to the data written to second node NB, allowing data to be read from the SRAM cell. Specifically, if second node NB is high, read bit line RBL is discharged to a low level. On the other hand, if second node NB is low, read bit line RBL remains high.

[0073] As described above, the dual-port SRAM cell has the functions of writing data to the SRAM cell, retaining data, and reading data from the SRAM cell by controlling the write bit lines WBL, WBLB, the read bit line RBL, the write word line WWL, and the read word line RWL.

[0074] It should be noted that in the following description, Figure 1 In the top view, the horizontal direction of the drawing is set as the X direction, the vertical direction of the drawing is set as the Y direction, and the direction perpendicular to the substrate surface is set as the Z direction. Figure 1 The solid lines extending vertically and horizontally in the top view and Figure 2 The solid lines extending longitudinally in the isosectional views represent the grid used to arrange components during design. The grid is arranged with equal spacing in the X direction and in the Y direction. It should be noted that the grid spacing can be the same or different in the X and Y directions. The grid spacing can also vary for each layer. Furthermore, components do not necessarily need to be arranged on a grid. However, to minimize manufacturing variations, it is preferred that components be arranged on a grid.

[0075] exist Figure 1 In the top view, the dotted line surrounding the cell shows the cell frame of the dual-port SRAM cell (the outer edge of the dual-port SRAM cell). The cell frame of the dual-port SRAM cell is arranged to contact the cell frame of the adjacent cell in the X direction or the Y direction.

[0076] like Figure 1As shown in (a), power supply lines 11 and 12 extending in the Y direction are provided at the bottom of the cell. Both power supply lines 11 and 12 are buried power rails (BPR) formed in a buried wiring layer. Power supply lines 11 and 12 supply voltage VSS.

[0077] Nanowires 21a to 211 extending in the Y direction are formed in the lower portion of the cell, and nanowires 21m, 21n, and 26a to 26h extending in the Y direction are formed in the upper portion of the cell.

[0078] Nanowires 21a to 21f are formed to be aligned in the X direction. Nanowires 21g to 21l are formed to be aligned in the X direction. Nanowires 21m and 26a to 26d are formed to be aligned in the X direction. Nanowires 21n and 26e to 26h are formed to be aligned in the X direction.

[0079] The nanowires 21a to 21f are formed so as to be aligned with the nanowires 21g to 211 in the Y direction, respectively. The nanowires 26a to 26d are formed so as to be aligned with the nanowires 26e to 26h in the Y direction, respectively.

[0080] The nanowires 21c and 21h overlap with the nanowires 21m and 21n, respectively, in a plan view. The nanowires 21a, 21d to 21g, and 21j to 21l overlap with the nanowires 26a to 26h, respectively, in a plan view.

[0081] Gate wirings 31-35 extend from the lower portion of the cell toward the upper portion in the Z direction and also in the X direction. Gate wirings 31 and 32 are arranged in the X direction, while gate wirings 33-35 are arranged in the X direction. Gate wiring 31 serves as the gate of transistors N1 and N2 and dummy transistor P21. Gate wiring 32 serves as the gate of transistors N3-N6 and P1 and dummy transistors P22-P24. Gate wiring 33 serves as the gate of transistors N7, N8, P2 and dummy transistor P25. Gate wiring 34 serves as the gate of transistors N9 and N10 and dummy transistor P26. Gate wiring 35 serves as the gate of transistors N11 and N12 and dummy transistors P27 and P28.

[0082] Pads 22a to 22r formed of a doped N-type semiconductor are formed at the upper end of nanowire 21a in the drawing, between nanowires 21a and 21g, at the lower end of nanowire 21g in the drawing, at the upper end of nanowire 21b in the drawing, between nanowires 21b and 21h, at the lower end of nanowire 21h in the drawing, at the upper end of nanowire 21c in the drawing, between nanowires 21c and 21i, at the lower end of nanowire 21i in the drawing, at the upper end of nanowire 21d in the drawing, between nanowires 21d and 21j, at the lower end of nanowire 21j in the drawing, at the upper end of nanowire 21e in the drawing, between nanowires 21e and 21k, at the lower end of nanowire 21k in the drawing, at the upper end of nanowire 21f in the drawing, between nanowires 21f and 21l, and at the lower end of nanowire 21l in the drawing. Nanowires 21a to 21l constitute the channel portions of transistors N1 to N12, respectively. Pads 22a and 22b form a node of transistor N1. Pads 22d and 22e form a node of transistor N2. Pads 22g and 22h form a node of transistor N3. Pads 22j and 22k form a node of transistor N4. Pads 22m and 22n form a node of transistor N5. Pads 22p and 22q form a node of transistor N6. Pads 22b and 22c form a node of transistor N7. Pads 22e and 22f form a node of transistor N8. Pads 22h and 22i form a node of transistor N9. Pads 22k and 22l form a node of transistor N10. Pads 22n and 22o form a node of transistor N11. Pads 22q and 22r form a node of transistor N12.

[0083] That is, nanowire 21a, gate wiring 31, and pads 22a and 22b constitute transistor N1. Nanowire 21b, gate wiring 31, and pads 22d and 22e constitute transistor N2. Nanowire 21c, gate wiring 32, and pads 22g and 22h constitute transistor N3. Nanowire 21d, gate wiring 32, and pads 22j and 22k constitute transistor N4. Nanowire 21e, gate wiring 32, and pads 22m and 22n constitute transistor N5. Nanowire 21f, gate wiring 32, and pads 22p and 22q constitute transistor N6. Nanowire 21g, gate wiring 33, and pads 22b and 22c constitute transistor N7. Nanowire 21h, gate wiring 33, and pads 22e and 22f constitute transistor N8. Nanowire 21i, gate wiring 34, and pads 22h and 22i constitute transistor N9. Nanowire 21j, gate wiring 34, and pads 22k and 22l form transistor N10. Nanowire 21k, gate wiring 35, and pads 22n and 22o form transistor N11. Nanowire 21l, gate wiring 35, and pads 22q and 22r form transistor N12.

[0084] Pads 22s to 22v, made of a doped P-type semiconductor, are formed at the upper and lower ends of nanowire 21m, 21m, 21n, and 21n, respectively. Nanowires 21m and 21n form the channels of transistors P1 and P2, respectively. Pads 22s and 22t form nodes of transistor P1. Pads 22u and 22v form nodes of transistor P2.

[0085] That is, nanowire 21m, gate wiring 32, and pads 22s and 22t constitute transistor P1. Nanowire 21n, gate wiring 33, and pads 22u and 22v constitute transistor P2. It should be noted that transistors P1 and P2 correspond to load transistors PU1 and PU2, respectively.

[0086] Dummy pads 27a to 271, formed of a doped P-type semiconductor, are formed at the upper end of nanowire 26a, between nanowires 26a and 26e, at the lower end of nanowire 26e, at the upper end of nanowire 26b, between nanowires 26b and 26f, at the lower end of nanowire 26f, at the upper end of nanowire 26c, between nanowires 26c and 26g, at the lower end of nanowire 26g, at the upper end of nanowire 26d, between nanowires 26d and 26h, and at the lower end of nanowire 26h. Dummy pads 27a and 27b form nodes for dummy transistor P21. Dummy pads 27d and 27e form nodes for dummy transistor P22. Dummy pads 27g and 27h form nodes for dummy transistor P23. Dummy pads 27j and 27k form nodes for dummy transistor P24. Dummy pads 27b and 27c form a node for dummy transistor P25. Dummy pads 27e and 27f form a node for dummy transistor P26. Dummy pads 27h and 27i form a node for dummy transistor P27. Dummy pads 27k and 271 form a node for dummy transistor P28.

[0087] That is, nanowire 26a, gate wiring 31, and dummy pads 27a and 27b form dummy transistor P21. Nanowire 26b, gate wiring 32, and dummy pads 27d and 27e form dummy transistor P22. Nanowire 26c, gate wiring 32, and dummy pads 27g and 27h form dummy transistor P23. Nanowire 26d, gate wiring 32, and dummy pads 27j and 27k form dummy transistor P24. Nanowire 26e, gate wiring 33, and dummy pads 27b and 27c form dummy transistor P25. Nanowire 26f, gate wiring 34, and dummy pads 27e and 27f form dummy transistor P26. Nanowire 26g, gate wiring 35, and dummy pads 27h and 27i form dummy transistor P27. Nanowire 26h, gate wiring 35, and dummy pads 27k and 27l constitute dummy transistor P28. Nanowires 26a to 26h correspond to the channel portions of dummy transistors P21 to P28, respectively. It should be noted that dummy transistors P21 to P28 are transistors without logic functions. Figure 3 In the circuit diagram, dummy transistors P21 to P28 are omitted. It should be noted that some of the dual-port SRAM cells described below in the embodiments and their variations include dummy transistors. However, since these dummy transistors do not affect the logic function of the dual-port SRAM cell, they are omitted from the circuit diagram.

[0088] Therefore, the transistors N1 , N3 to N8 , and N10 to N12 overlap with the dummy transistor P21 , the transistor P1 , the dummy transistors P22 to P25 , the transistor P2 , and the dummy transistors P26 to P28 , respectively, in a plan view.

[0089] Transistors N1 to N6 are arranged in the X direction. Transistors N7 to N12 are arranged in the X direction. Transistor P1 and dummy transistors P21 to P24 are arranged in the X direction. Transistor P2 and dummy transistors P25 to P28 are arranged in the X direction.

[0090] The transistors N1 to N6 are formed in parallel with the transistors N7 to N12 in the Y direction. The dummy transistors P21 to P24 are formed in parallel with the dummy transistors P25 to P28 in the Y direction.

[0091] like Figure 1As shown in (a), local interconnects (LI) 41a to 41h are formed in the lower portion of the cell, extending in the X direction. Local interconnect 41a connects to pads 22a and 22d. Local interconnect 41b connects to pads 22b and 22e. Local interconnect 41c connects to pads 22c and 22f. Local interconnect 41d connects to pads 22g, 22j, 22m, and 22p. Local interconnect 41e connects to pads 22h and 22k. Local interconnect 41f connects to pads 22i and 22l. Local interconnect 41g connects to pads 22n and 22q. Local interconnect 41h connects to pads 22o and 22r.

[0092] That is, the pads of transistors N1 and N2 are connected by local wiring, and transistors N1 and N2 share a gate wiring. The pads of transistors N3 and N4 are connected by local wiring, and transistors N3 and N4 share a gate wiring. The pads of transistors N5 and N6 are connected by local wiring, and transistors N5 and N6 share a gate wiring. The pads of transistors N7 and N8 are connected by local wiring, and transistors N7 and N8 share a gate wiring. The pads of transistors N9 and N10 are connected by local wiring, and transistors N9 and N10 share a gate wiring. The pads of transistors N11 and N12 are connected by local wiring, and transistors N11 and N12 share a gate wiring. It should be noted that transistors N1 and N2 correspond to access transistor PG2, transistors N3 and N4 correspond to driver transistor PD1, transistors N5 and N6 correspond to read driver transistor RPD1, transistors N7 and N8 correspond to driver transistor PD2, transistors N9 and N10 correspond to access transistor PG1, and transistors N11 and N12 correspond to read access transistor RPG1. Therefore, in the dual-port SRAM cell of this embodiment, the driver transistors PD1 and PD2, the access transistors PG1 and PG2, the read driver transistor RPD1, and the read access transistor RPG1 are each composed of two N-type FETs connected in parallel.

[0093] like Figure 1 As shown in (b), local wirings 41i to 41l extending in the X direction are formed on the upper portion of the cell. Local wiring 41i is connected to pad 22s. Local wiring 41j is connected to pad 22t. Local wiring 41k is connected to pad 22u. Local wiring 41l is connected to pad 22v.

[0094] Local wiring 41b is connected to local wiring 41k via contact 51a. Local wiring 41c is connected to power supply wiring 11 via contact 51b. Local wiring 41d is connected to power supply wiring 12 via contact 51c. Local wiring 41e is connected to local wiring 41j via contact 51d.

[0095] The local wiring 41j is connected to the gate wiring 33 via a shared contact 61a. The local wiring 41k is connected to the gate wiring 32 via a shared contact 61b. It should be noted that the local wirings 41e and 41j, the contact 51d, the shared contact 61a, and the gate wiring 33 correspond to the first node NA, and the local wirings 41b and 41k, the contact 51a, the shared contact 61b, and the gate wiring 32 correspond to the second node NB.

[0096] like Figure 1 As shown in (c), the metal wiring layer, or M1 wiring layer, has wirings 71-74 extending in the Y direction to the top and bottom ends of the cell. Wirings 75-77 are also formed. Wiring 71 supplies voltage VDD. Wirings 72-74 correspond to write bit lines WBL and WBLB, and read bit line RBL, respectively.

[0097] In the M2 wiring layer, which is above the M1 wiring layer, wirings 81 and 82 are formed, extending in the X direction to the left and right ends of the cell. Wirings 81 and 82 are arranged in the Y direction. Wiring 81 corresponds to the write word line WWL, and wiring 82 corresponds to the read word line RWL.

[0098] Wiring 71 is connected to local wiring 41i via contact 91a and to local wiring 41l via contact 91b. Wiring 72 is connected to local wiring 41f via contact 91c. Wiring 73 is connected to local wiring 41a via contact 91d. Wiring 74 is connected to local wiring 41h via contact 91e. Wiring 75 is connected to gate wiring 31 via contact (gate wiring contact) 61c and to wiring 81 via contact 91f. Wiring 76 is connected to gate wiring 34 via contact 61d and to wiring 81 via contact 91g. Wiring 77 is connected to gate wiring 35 via contact 61e and to wiring 82 via contact 91h. In other words, wiring 81 is connected to gate wiring 31 via contact 91f, wiring 75, and contact 61c, and to gate wiring 34 via contact 91g, wiring 76, and contact 61d. The wiring 82 is connected to the gate wiring 35 via the contact 91h, the wiring 77, and the contact 61e.

[0099] According to the above configuration, in transistor P1 (load transistor PU1), pad 22s is connected to wiring 71 supplied with voltage VDD, pad 22t is connected to local wiring 41j (first node NA), and gate wiring 32 is connected to common contact 61b (second node NB). In transistor P2 (load transistor PU2), pad 22v is connected to wiring 71 supplied with voltage VDD, pad 22u is connected to local wiring 41k (second node NB), and gate wiring 33 is connected to common contact 61a (first node NA). In transistors N3 and N4 (drive transistors PD1), pads 22h and 22k are connected to local wiring 41e (first node NA), pads 22g and 22j are connected to power supply wiring 12 supplied with voltage VSS, and gate wiring 32 is connected to common contact 61b (second node NB). In transistors N7 and N8 (driver transistors PD2), pads 22b and 22e are connected to local wiring 41b (second node NB), pads 22c and 22f are connected to power supply wiring 11 supplying voltage VSS, and gate wiring 33 is connected to common contact 61a (first node NA). In transistors N9 and N10 (access transistors PG1), pads 22i and 22l are connected to wiring 72 (write bit line WBL), pads 22h and 22k are connected to local wiring 41e (first node NA), and gate wiring 34 is connected to wiring 81 (write word line WWL). In transistors N1 and N2 (access transistors PG2), pads 22a and 22d are connected to wiring 73 (write bit line WBLB), pads 22b and 22e are connected to local wiring 41b (second node NB), and gate wiring 31 is connected to wiring 81 (write word line WWL). In transistors N5 and N6 (read drive transistors RPD1), pads 22m and 22p are connected to power supply wiring 12, which supplies voltage VSS, and gate wiring 32 is connected to common contact 61b (second node NB). In transistors N11 and N12 (read access transistors RPG1), pads 22n and 22q are shared with transistors N5 and N6, respectively. Pads 22o and 22r are connected to wiring 74 (read bit line RBL), and gate wiring 35 is connected to wiring 82 (read word line RWL). In other words, transistors N1 to N12, P1, and P2 form a dual-port SRAM circuit. Transistors N1 to N12 are formed in the lower portion of the cell, while transistors P1 and P2 are formed in the upper portion of the cell. Transistors N1 to N12, P1, and P2 are each three-dimensional transistors. This makes it possible to implement a dual-port SRAM cell formed using CFETs.

[0100] Transistors P1 and P2 overlap with transistors N3 and N8, respectively, when viewed from above. In other words, transistors P1 and P2 are stacked with transistors N3 and N8, respectively. Transistors N5 and N6 are arranged along the Y direction with transistors N11 and N12, respectively. This reduces the area of the dual-port SRAM cell.

[0101] Therefore, a dual-port SRAM cell formed using CFET can be realized while reducing the area of the dual-port SRAM cell.

[0102] Transistors N1 to N12 are formed in the lower portion of the cell; transistors P1 and P2 and dummy transistors P21 to P26 are formed in the upper portion of the cell. In other words, only N-type FETs are formed in the lower portion of the cell, while only P-type FETs, including the dummy transistors, are formed in the upper portion of the cell. This prevents complication in the manufacturing process.

[0103] It should be noted that when arranging the dual-port SRAM cells adjacent to each other along the X direction, the dual-port SRAM cells need to be reversed along the X direction. When arranging the dual-port SRAM cells adjacent to each other along the Y direction, the dual-port SRAM cells need to be reversed along the Y direction.

[0104] None of the nodes of the dummy transistors P21-P28 are connected to any local wiring. Therefore, the dummy transistors P21-P28 do not affect the logic function of the dual-port SRAM cell. Furthermore, the dummy transistors P21-P28 may not be formed in the dual-port SRAM cell of this embodiment. However, forming the dummy transistors P21-P28 can suppress manufacturing variations in the semiconductor memory device, improve yield, and enhance reliability.

[0105] In addition, the common contact 61a connecting the local wiring 41j and the gate wiring 33 and the common contact 61b connecting the local wiring 41k and the gate wiring 32 can be formed in the same process step as the contacts 61c~61e connecting the wiring arranged in the M1 wiring layer and the gate wiring, or can be formed in other process steps.

[0106] Furthermore, although wiring 71 for supplying voltage VDD is provided in the M1 wiring layer, wiring 71 may also be provided in a buried wiring layer. Alternatively, wiring 71 may be provided in both the M1 wiring layer and the buried wiring layer. In this case, the power supply for supplying voltage VDD is enhanced, thereby stabilizing the power supply.

[0107] (Variation 1)

[0108] Figure 4 1 is a top view showing another example of the layout structure of the dual-port SRAM cell according to the first embodiment. Figure 4 (a) shows the lower part of the unit, Figure 4(b) shows the upper part of the unit, Figure 4 (c) shows the M1 and M2 wiring layers. Figure 4 In this modification, an N-type FET is formed in the upper portion of the cell, and a P-type FET is formed in the lower portion of the cell. That is, in this modification, the conductivity types of the transistors formed in the upper and lower portions of the cell are opposite to those of the dual-port SRAM according to the first embodiment.

[0109] Specifically, transistors N1 to N12 and local wirings 41 a to 41 h are formed in the upper portion of the cell, and transistors P1 and P2 , dummy transistors P21 to P28 , and local wirings 41 i to 41 l are formed in the lower portion of the cell.

[0110] The buried wiring layer includes a power supply wiring 13. The power supply wiring 13 supplies a voltage VDD.

[0111] The local wiring 41i is connected to the power supply wiring 13 via a contact 51e, and the local wiring 411 is connected to the power supply wiring 13 via a contact 51f.

[0112] The local wiring 41k is connected to the gate wiring 32 via the contact 51a, the local wiring 41b, and the common contact 61b. The local wiring 41j is connected to the gate wiring 33 via the contact 51d, the local wiring 41e, and the common contact 61a.

[0113] According to this modification, the same effects as those of the dual-port SRAM cell according to the first embodiment can be obtained.

[0114] (Variation 2)

[0115] Figure 5 1 is a top view showing another example of the layout structure of the dual-port SRAM cell according to the first embodiment. Figure 5 (a) shows the lower part of the unit, Figure 5 (b) shows the upper part of the unit, Figure 5 (c) shows the M1 and M2 wiring layers. Figure 5 In FIG. 4 , transistors N6 and N12 are formed at the upper portion of the cell. Also, dummy transistors P23, P24, P27, and P28 are not formed.

[0116] Specifically, nanowires 21f and 211 are formed on the upper portion of the cell.

[0117] Nanowire 21f is aligned with nanowires 21m, 26a, and 26b in the X direction, and nanowire 21l is aligned with nanowires 21n, 26e, and 26f in the X direction. That is, transistor N6 is aligned with transistor P1 and dummy transistors P21 and P22 in the X direction, and transistor N12 is aligned with transistor P2 and dummy transistors P25 and P26 in the X direction.

[0118] The nanowires 21f and 211 overlap with the nanowires 21e and 21k, respectively, when viewed from above. That is, the transistors N6 and N12 overlap with the transistors N5 and N11, respectively, when viewed from above.

[0119] Local wirings 42a to 42c extending in the X direction are formed on the cell upper portion. Local wiring 42a is connected to pad 22p. Local wiring 42b is connected to pad 22q. Local wiring 42c is connected to pad 22r.

[0120] In the lower portion of the cell, local wiring 41d is connected to pads 22g, 22j, and 22m. Local wiring 41g is connected to pad 22n. Local wiring 41h is connected to pad 22o.

[0121] Local wiring 42a is connected to local wiring 41d via contact 52a. Local wiring 42b is connected to local wiring 41g via contact 52b. Local wiring 42c is connected to local wiring 41h via contact 52c and to wiring 74 via contact 91e.

[0122] In this modification, a transistor corresponding to the read driver transistor RPD1 and a transistor corresponding to the read access transistor RPG1 are stacked separately. Furthermore, this modification can achieve the same effects as the dual-port SRAM cell according to the first embodiment.

[0123] Transistors N6 and N12 overlap with transistors N5 and N11, respectively, when viewed from above. That is, transistors N6 and N12 are stacked with transistors N5 and N11, respectively. This reduces the area of the dual-port SRAM cell.

[0124] Transistors N1 to N5, N7 to N11 are formed in the lower portion of the cell; transistors N6, N12, P1, P2, and dummy transistors P21, P22, P25, and P26 are formed in the upper portion of the cell. In other words, only N-type FETs are formed in the lower portion of the cell. The above configuration is achieved by replacing some of the transistors formed in the upper portion of the cell with N-type FETs. This reduces the complexity of the manufacturing process.

[0125] (Variation 3)

[0126] Figure 6 1 is a top view showing another example of the layout structure of the dual-port SRAM cell according to the first embodiment. Figure 6 (a) shows the lower part of the unit, Figure 6 (b) shows the upper part of the unit, Figure 6 (c) shows the M1 and M2 wiring layers. Figure 6In FIG. 1 , transistors N2 , N4 , N6 , N8 , N10 , and N12 are formed on the upper portion of the cell. Dummy transistors P21 to P28 are not formed.

[0127] Specifically, nanowires 21b, 21d, 21f, 21h, 21j, and 21l are formed on the upper portion of the cell.

[0128] Nanowires 21b, 21d, and 21f are aligned with nanowire 21m along the X direction. Nanowires 21h, 21j, and 21l are aligned with nanowire 21n along the X direction. In other words, transistors N2, N4, and N6 are aligned with transistor P1 along the X direction. Transistors N8, N10, and N12 are aligned with transistor P2 along the X direction.

[0129] Nanowires 21b, 21d, 21f, 21h, 21j, and 21l overlap with nanowires 21a, 21c, 21e, 21g, 21i, and 21k, respectively, when viewed from above. That is, transistors N2, N4, N6, N8, N10, and N12 overlap with transistors N1, N3, N5, N7, N9, and N11, respectively, when viewed from above.

[0130] Nanowires 26i and 26j are formed at the bottom of the cell, extending in the Y direction. Gate wiring 32 forms the gate of dummy transistor N21, and gate wiring 33 forms the gate of dummy transistor N22. Dummy pads 27m to 27p, formed by doping N-type semiconductor, are formed at the upper end of nanowire 26i (see figure), the lower end of nanowire 26i (see figure), the upper end of nanowire 26j (see figure), and the lower end of nanowire 26j (see figure). Nanowires 26i and 26j form the channel portions of dummy transistors N21 and N22, respectively. Dummy pads 27m and 27n form the nodes of dummy transistor N21, and dummy pads 27o and 27p form the nodes of dummy transistor N22. In other words, nanowire 26i, gate wiring 32, and dummy pads 27m and 27n constitute dummy transistor N21. Nanowire 26j, gate wiring 33, and dummy pads 27o and 27p constitute dummy transistor N22. It should be noted that dummy transistors N21 and N22 are transistors that do not have a logic function.

[0131] Here, the nanowires 21m and 21n overlap with the nanowires 26i and 26j, respectively, in a plan view. In other words, the transistors P1 and P2 overlap with the dummy transistors N21 and N22, respectively, in a plan view.

[0132] like Figure 6As shown in (b), local wiring 43a to 43f extending in the X direction are formed in the upper portion of the cell. Local wiring 43a is connected to pad 22d. Local wiring 43b is connected to pads 22j and 22p. Local wiring 43c is connected to pad 22q. Local wiring 43d is connected to pad 22f. Local wiring 43e is connected to pad 22l. Local wiring 43f is connected to pad 22r. In the upper portion of the cell, local wiring 41j is connected to pads 22k and 22t. Local wiring 41k is connected to pads 22e and 22u.

[0133] like Figure 6 As shown in (a), in the lower portion of the cell, local wiring 41a is connected to pad 22a. Local wiring 41b is connected to pad 22b. Local wiring 41c is connected to pad 22c. Local wiring 41d is connected to pads 22g and 22m. Local wiring 41e is connected to pad 22h. Local wiring 41f is connected to pad 22i. Local wiring 41g is connected to pad 22n. Local wiring 41h is connected to pad 22o.

[0134] Local wiring 43a is connected to local wiring 41a via contact 53a and to wiring 73 via contact 91d. Local wiring 43b is connected to local wiring 41d via contact 53b. Local wiring 43c is connected to local wiring 41g via contact 53c. Local wiring 43d is connected to local wiring 41c via contact 53d. Local wiring 43e is connected to local wiring 41f via contact 53e and to wiring 72 via contact 91c. Local wiring 43f is connected to local wiring 41h via contact 53f and to wiring 74 via contact 91e.

[0135] In this variation, a transistor corresponding to the driver transistor PD1, a transistor corresponding to the driver transistor PD2, a transistor corresponding to the access transistor PG1, a transistor corresponding to the access transistor PG2, a transistor corresponding to the read driver transistor RPD1, and a transistor corresponding to the read access transistor RPG1 are stacked separately. Furthermore, this variation achieves the same effects as the dual-port SRAM cell according to the first embodiment.

[0136] Transistors N2, N4, N6, N8, N10, and N12 overlap with transistors N1, N3, N5, N7, N9, and N11, respectively, when viewed from above. In other words, transistors N2, N4, N6, N8, N10, and N12 are stacked with transistors N1, N3, N5, N7, N9, and N11, respectively. This reduces the area of the dual-port SRAM cell. Because each transistor is stacked with other transistors, it is not necessary to remove some transistors. This reduces the complexity of the manufacturing process.

[0137] Transistors N1, N3, N5, N7, N9, and N11, along with dummy transistors N21 and N22, are formed in the lower portion of the cell. Transistors N2, N4, N6, N8, N10, N12, P1, and P2 are formed in the upper portion of the cell. In other words, only N-type FETs are formed in the lower portion of the cell. This configuration is achieved by replacing some of the transistors formed in the upper portion of the cell with N-type FETs. This reduces the complexity of the manufacturing process.

[0138] (Second embodiment)

[0139] Figure 7 1 is a circuit diagram showing the configuration of a dual-port SRAM cell according to the second embodiment. Figure 7 As shown, the dual-port SRAM cell according to the second embodiment includes a dual-port SRAM circuit comprising load transistors PU1 and PU2, driver transistors PD1 and PD2, access transistors PG1 and PG2, a read driver transistor RPD2, and a read access transistor RPG2. The read driver transistor RPD2 and the read access transistor RPG2 are P-type FETs.

[0140] The source of read driver transistor RPD2 is connected to power supply VDD, the gate is connected to second node NB, and the drain is connected to the source of read access transistor RPG2. The gate of read access transistor RPG2 is connected to read word line NRWL, and the drain is connected to read bit line RBL.

[0141] In a dual-port SRAM circuit, after the read bit line RBL is discharged to a low level and the read word line NRWL is driven low, the state of the read bit line RBL is determined according to the data written to the second node NB, allowing data to be read from the SRAM cell. Specifically, if the second node NB is at a low level, the read bit line RBL is charged to a high level. On the other hand, if the second node NB is at a high level, the read bit line RBL remains at a low level.

[0142] Figure 8 1 is a top view showing an example of the layout structure of a dual-port SRAM cell according to the second embodiment. Figure 8 (a) shows the lower part of the unit, Figure 8 (b) shows the upper part of the unit, Figure 8 (c) shows the M1 and M2 wiring layers. In the dual-port SRAM cell according to the second embodiment, transistors P1 to P6 and dummy transistors P21, P22, P25, and P26 are formed on the upper portion of the cell; transistors N1 to N4, N7 to N10 and dummy transistors N23 to N26 are formed on the lower portion of the cell. It should be noted that Figure 8 In FIG, wiring 82 corresponds to read word line NRWL.

[0143] like Figure 8 As shown in (a) and (b), nanowires 23a to 23d extending in the Y direction are formed in the upper portion of the unit; and nanowires 28a to 28d extending in the Y direction are formed in the lower portion of the unit.

[0144] Nanowires 23a and 23b are aligned with nanowires 21m, 26a, and 26b in the X direction. Nanowires 23c and 23d are aligned with nanowires 21n, 26e, and 26f in the X direction. Nanowires 28a and 28b are aligned with nanowires 21a to 21d in the X direction. Nanowires 28c and 28d are aligned with nanowires 21g to 21j in the X direction.

[0145] The nanowires 23a and 23b are arranged along the Y direction with the nanowires 23c and 23d, respectively. The nanowires 28a and 28b are arranged along the Y direction with the nanowires 28c and 28d, respectively.

[0146] The gate wiring 32 serves as the gates of the transistors P3 and P4 and the dummy transistors N23 and N24 , and the gate wiring 35 serves as the gates of the transistors P5 and P6 and the dummy transistors N25 and N26 .

[0147] Pads 24a to 24f, made of a doped P-type semiconductor, are formed at the upper end of nanowire 23a in the drawing, between nanowires 23a and 23c, at the lower end of nanowire 23c in the drawing, at the upper end of nanowire 23b in the drawing, between nanowires 23b and 23d, and at the lower end of nanowire 23d in the drawing. Nanowires 23a to 23d form the channel portions of transistors P3 to P6, respectively. Pads 24a and 24b form a node for transistor P3. Pads 24d and 24e form a node for transistor P4. Pads 24b and 24c form a node for transistor P5. Pads 24e and 24f form a node for transistor P6.

[0148] That is, nanowire 23a, gate wiring 32, and pads 24a and 24b form transistor P3. Nanowire 23b, gate wiring 32, and pads 24d and 24e form transistor P4. Nanowire 23c, gate wiring 35, and pads 24b and 24c form transistor P5. Nanowire 23d, gate wiring 35, and pads 24e and 24f form transistor P6.

[0149] Dummy pads 29a to 29f, made of doped N-type semiconductor, are formed at the upper end of nanowire 28a in the drawing, between nanowires 28a and 28c, at the lower end of nanowire 28c in the drawing, at the upper end of nanowire 28b in the drawing, between nanowires 28b and 28d, and at the lower end of nanowire 28d in the drawing. Nanowires 28a to 28d constitute the channel portions of dummy transistors N23 to N26, respectively. Dummy pads 29a and 29b constitute the node of dummy transistor N23. Dummy pads 29d and 29e constitute the node of dummy transistor N24. Dummy pads 29b and 29c constitute the node of dummy transistor N25. Dummy pads 29e and 29f constitute the node of dummy transistor N26.

[0150] That is, nanowire 28a, gate wiring 32, and dummy pads 29a and 29b form dummy transistor N23. Nanowire 28b, gate wiring 32, and dummy pads 29d and 29e form dummy transistor N24. Nanowire 28c, gate wiring 35, and dummy pads 29b and 29c form dummy transistor N25. Nanowire 28d, gate wiring 35, and dummy pads 29e and 29f form dummy transistor N26. It should be noted that dummy transistors N23 to N26 do not have logic functions.

[0151] Therefore, in the dual-port SRAM cell according to this embodiment, the transistors P3 to P6 overlap with the dummy transistors N23 to N26 , respectively, in a plan view.

[0152] Local wiring 44a and 44b extending along the X direction are formed at the top of the cell. Local wiring 44a is connected to pads 24b and 24e. Local wiring 44b is connected to pads 24c and 24f. Local wiring 41i is connected to pads 22s, 24a, 24d, and dummy pad 27d. At the bottom of the cell, local wiring 41d is connected to pads 22g and 22j. In other words, the pads of transistors P3 and P4 are connected via local wiring, and transistors P3 and P4 share a gate wiring. The pads of transistors P5 and P6 are connected via local wiring, and transistors P5 and P6 share a gate wiring. It should be noted that transistors P3 and P4 correspond to readout driver transistors RPD2, and transistors P5 and P6 correspond to readout access transistors RPG2. Therefore, in the dual-port SRAM cell of this embodiment, readout driver transistor RPD2 and readout access transistor RPG2 are each composed of two P-type FETs connected in parallel.

[0153] The local wiring 41i is connected to the wiring 71 via the contact 91a, and the local wiring 44b is connected to the wiring 74 via the contact 91e. The wiring 82 is connected to the gate wiring 35 via the contact 91h, the wiring 77, and the contact 61e.

[0154] According to the above configuration, in transistors P3 and P4 (read drive transistors RPD2), pads 24a and 24d are connected to wiring 71 supplying voltage VDD, and gate wiring 32 is connected to second node NB via common contact 61b. Transistors P5 and P6 (read access transistors RPG2) share pads 24b and 24e with transistors P3 and P4, respectively. Pads 24c and 24f are connected to wiring 74 (read bit line RBL), and gate wiring 35 is connected to wiring 82 (read word line NRWL). In other words, transistors N1 to N4, N7 to N10, and P1 to P6 form a dual-port SRAM circuit. Transistors N1 to N4 and N7 to N10 are formed in the lower portion of the cell, while transistors P1 to P6 are formed in the upper portion of the cell. Transistors N1 to N4, N7 to N10, and P1 to P6 are each three-dimensional transistors. This makes it possible to implement a dual-port SRAM cell using CFETs.

[0155] Transistors P1 and P2 overlap with transistors N3 and N8, respectively, when viewed from above. In other words, transistors P1 and P2 are stacked with transistors N3 and N8, respectively. Transistors P3 and P4 are arranged along the Y direction with transistors P5 and P6, respectively. This reduces the area of the dual-port SRAM cell.

[0156] Therefore, a dual-port SRAM cell using CFET can be realized while reducing the area of the dual-port SRAM cell.

[0157] Transistors N1-N4, N7-N10, and dummy transistors N23-N26 are formed in the lower portion of the cell; transistors P1-P6 and dummy transistors P21, P22, P25, and P26 are formed in the upper portion of the cell. In other words, only N-type FETs, including dummy transistors, are formed in the lower portion of the cell; only P-type FETs, including dummy transistors, are formed in the upper portion of the cell. This prevents complication in the manufacturing process.

[0158] It should be noted that when the dual-port SRAM cells are arranged adjacent to each other in the X direction, they are arranged inversely in the Y direction. When the dual-port SRAM cells are arranged adjacent to each other in the Y direction, they are arranged inversely in the X direction.

[0159] None of the nodes of the dummy transistors N23 to N26, P21, P22, P25, and P26 are connected to any local wiring. Therefore, the dummy transistors N23 to N26, P21, P22, P25, and P26 do not affect the logic function of the dual-port SRAM cell. It should be noted that the dummy transistors N23 to N26, P21, P22, P25, and P26 may not be formed in the dual-port SRAM cell of this embodiment. However, forming the dummy transistors N23 to N26, P21, P22, P25, and P26 can suppress manufacturing variations in the semiconductor memory device, improve yield, and enhance reliability.

[0160] Furthermore, although wiring 71 for supplying voltage VDD is provided in the M1 wiring layer, wiring 71 may also be provided in a buried wiring layer. Alternatively, wiring 71 may be provided in both the M1 wiring layer and the buried wiring layer. In this case, the power supply for supplying voltage VDD is enhanced, thereby stabilizing the power supply.

[0161] (Variation 1)

[0162] Figure 9 1 is a top view showing another example of the layout structure of the dual-port SRAM cell according to the second embodiment. Figure 9 (a) shows the lower part of the unit, Figure 9 (b) shows the upper part of the unit, Figure 9 (c) shows the M1 and M2 wiring layers. Figure 9 In the embodiment, an N-type FET is formed in the upper portion of the cell, and a P-type FET is formed in the lower portion of the cell. That is, the conductivity types of the transistors formed in the upper and lower portions of the cell are opposite to those of the dual-port SRAM according to the second embodiment.

[0163] Specifically, if Figure 9 As shown in (a), the buried wiring layer has power supply wirings 13 and 14 extending in the Y direction. The power supply wirings 13 and 14 supply a voltage VDD.

[0164] Transistors P1 to P6, dummy transistors P21, P22, P25, P26, and local wirings 41i to 411, 44a, and 44b are formed in the lower portion of the cell; transistors N1 to N4, N7 to N10, dummy transistors N23 to N26, and local wirings 41a to 41f are formed in the upper portion of the cell.

[0165] A local wiring 45a extending in the X direction is formed in the lower portion of the cell. The local wiring 45a is connected to the pads 24a and 24d. The local wiring 41i is connected to the pad 22s.

[0166] The local wiring 45a is connected to the power supply wiring 14 via the contact 55a. The local wiring 41i is connected to the power supply wiring 13 via the contact 51e. The local wiring 411 is connected to the power supply wiring 13 via the contact 51f.

[0167] The local wiring 41k is connected to the gate wiring 32 via the contact 51b, the local wiring 41b, and the common contact 61b. The local wiring 41j is connected to the gate wiring 33 via the contact 51d, the local wiring 41e, and the common contact 61a.

[0168] According to this modification, the same effects as those of the dual-port SRAM cell according to the second embodiment can be obtained.

[0169] (Variation 2)

[0170] Figure 10 1 is a top view showing another example of the layout structure of the dual-port SRAM cell according to the second embodiment. Figure 10 (a) shows the lower part of the unit, Figure 10 (b) shows the upper part of the unit, Figure 10 (c) shows the M1 and M2 wiring layers. Figure 10 In FIG. 4 , transistors P4 and P6 are formed at the lower portion of the cell. Also, dummy transistors N23 to N26 are not formed.

[0171] Specifically, nanowires 23b and 23d are formed in the lower portion of the cell.

[0172] Nanowire 23b is aligned with nanowires 21a to 21d in the X direction. Nanowire 23d is aligned with nanowires 21g to 21j in the X direction. In other words, transistor P4 is aligned with transistors N1 to N4 in the X direction. Transistor P6 is aligned with transistors N7 to N10 in the X direction.

[0173] The nanowires 23b and 23d overlap with the nanowires 23a and 23c, respectively, in a plan view. That is, the transistors P4 and P6 overlap with the transistors P3 and P5, respectively, in a plan view.

[0174] Local wirings 46a to 46c extending in the X direction are formed in the lower portion of the cell. Local wiring 46a is connected to pad 24d. Local wiring 46b is connected to pad 24e. Local wiring 46c is connected to pad 24f.

[0175] In the upper portion of the cell, local wiring 41i is connected to pads 22s and 24a and dummy pad 27d. Local wiring 44a is connected to pad 24b. Local wiring 44b is connected to pad 24c.

[0176] The local wiring 46a is connected to the local wiring 41i via the contact 56a. The local wiring 46b is connected to the local wiring 44a via the contact 56b. The local wiring 46c is connected to the local wiring 44b via the contact 56c.

[0177] In this modification, a transistor corresponding to the read driver transistor RPD2 and a transistor corresponding to the read access transistor RPG2 are stacked separately. Furthermore, this modification can achieve the same effects as the dual-port SRAM cell according to the second embodiment.

[0178] Transistors P4 and P6 overlap with transistors P3 and P5, respectively, when viewed from above. That is, transistors P4 and P6 are stacked with transistors P3 and P5, respectively. This reduces the area of the dual-port SRAM cell.

[0179] Transistors N1 to N4, N7 to N10, P4, and P6 are formed in the lower portion of the cell; transistors P1 to P3, P5 and dummy transistors P21, P22, P25, and P26 are formed in the upper portion of the cell. In other words, because only P-type FETs are formed in the upper portion of the cell, the above configuration can be achieved by replacing some of the transistors formed in the lower portion of the cell with P-type FETs. This reduces the complexity of the manufacturing process.

[0180] (Variation 3)

[0181] Figure 11 1 is a top view showing another example of the layout structure of the dual-port SRAM cell according to the second embodiment. Figure 11 (a) shows the lower part of the unit, Figure 11 (b) shows the upper part of the unit, Figure 11 (c) shows the M1 and M2 wiring layers. Figure 11 In the example, transistors N2, N4, N8, and N10 are formed in the upper portion of the cell, and transistors P4 and P6 are formed in the lower portion of the cell. Furthermore, dummy transistors N23 to N26, P21, P22, P25, and P26 are not formed.

[0182] Specifically, if Figure 11 As shown in (a), a wiring 14 for supplying a voltage VDD is formed in the buried wiring layer.

[0183] Nanowires 21b, 21d, 21h, and 21j are formed on the upper portion of the cell, and nanowires 23b, 23d, 26i, and 26j are formed on the lower portion of the cell.

[0184] Nanowires 21b and 21d are aligned with nanowires 21m and 23a along the X direction. Nanowires 21h and 21j are aligned with nanowires 21n and 23c along the X direction. Nanowires 23b and 26i are aligned with nanowires 21a and 21c along the X direction. Nanowires 23d and 26j are aligned with nanowires 21g and 21i along the X direction. In other words, transistors N2 and N4 are aligned with transistors P1 and P3 along the X direction. Transistors N8 and N10 are aligned with transistors P2 and P5 along the X direction. Transistor P4 and dummy transistor N21 are aligned with transistors N1 and N3 along the X direction. Transistor P6 and dummy transistor N22 are aligned with transistors N7 and N9 along the X direction.

[0185] Nanowires 21b, 21d, 21h, 21j, 23a, and 23c overlap with nanowires 21a, 21c, 21g, 21i, 23b, and 23d, respectively, when viewed from above. Nanowires 21m and 21n overlap with nanowires 26i and 26j, respectively, when viewed from above. That is, transistors N2, N4, N8, N10, P3, and P5 overlap with transistors N1, N3, N7, N9, P4, and P6, respectively, when viewed from above. Transistors P1 and P2 overlap with dummy transistors N21 and N22, respectively, when viewed from above.

[0186] In the lower portion of the cell, local wiring 47a to 47c are formed, extending in the X direction. Local wiring 47a is connected to pad 24d. Local wiring 47b is connected to pad 24e. Local wiring 47c is connected to pad 24f. In the lower portion of the cell, local wiring 41a is connected to pad 22a. Local wiring 41b is connected to pad 22b. Local wiring 41c is connected to pad 22c. Local wiring 41d is connected to pad 22g. Local wiring 41e is connected to pad 22h. Local wiring 41f is connected to pad 22i.

[0187] Local wiring 47d to 47h are formed in the upper portion of the cell, extending in the X direction. Local wiring 47d is connected to pad 22d. Local wiring 47e is connected to pad 22f. Local wiring 47f is connected to pad 22j. Local wiring 47g is connected to pad 22l. Local wiring 47h is connected to pad 24a. In the upper portion of the cell, local wiring 41i is connected to pad 22s. Local wiring 41j is connected to pads 22i and 22t. Local wiring 41k is connected to pads 22e and 22u. Local wiring 44a is connected to pad 24b. Local wiring 44b is connected to pad 24c.

[0188] Local wiring 47a is connected to wiring 14 via contact 57a and to local wiring 47h via contact 57b. Local wiring 47b is connected to local wiring 44a via contact 57c. Local wiring 47c is connected to local wiring 44b via contact 57d. Local wiring 47d is connected to local wiring 41a via contact 57e and to wiring 73 via contact 91d. Local wiring 47e is connected to local wiring 41c via contact 57f. Local wiring 47f is connected to local wiring 41d via contact 57g. Local wiring 47g is connected to local wiring 41f via contact 57h and to wiring 72 via contact 91c.

[0189] In this variation, a transistor corresponding to the driver transistor PD1, a transistor corresponding to the driver transistor PD2, a transistor corresponding to the access transistor PG1, a transistor corresponding to the access transistor PG2, a transistor corresponding to the read driver transistor RPD2, and a transistor corresponding to the read access transistor RPG2 are stacked separately. Furthermore, this variation achieves the same effects as the dual-port SRAM cell according to the second embodiment.

[0190] Transistors N2, N4, N8, N10, P3, and P5 overlap with transistors N1, N3, N7, N9, P4, and P6, respectively, when viewed from above. In other words, transistors N2, N4, N8, N10, P3, and P5 are stacked with transistors N1, N3, N7, N9, P4, and P6, respectively. This reduces the area of the dual-port SRAM cell. Because each transistor is stacked with other transistors, some transistors do not need to be removed. This reduces the complexity of the manufacturing process.

[0191] Transistors N1, N3, N7, N9, P4, and P6, as well as dummy transistors N21 and N22, are formed in the lower portion of the cell. Transistors N2, N4, N6, N8, P1, P2, P3, and P5 are formed in the upper portion of the cell. This configuration is achieved by replacing some of the N-type FETs formed in the lower portion of the cell with P-type FETs, and some of the P-type FETs formed in the upper portion of the cell with N-type FETs. This reduces the complexity of the manufacturing process.

[0192] (Variation 4)

[0193] Figure 12 1 is a top view showing another example of the layout structure of the dual-port SRAM cell according to the second embodiment. Figure 12 (a) shows the lower part of the unit, Figure 12 (b) shows the upper part of the unit, Figure 12 (c) shows the M1 and M2 wiring layers. Figure 12In the upper portion of the cell, transistors P3, P4, P5, and P6 are arranged in the X direction. Also, dummy transistors N25 and N26 are not formed.

[0194] like Figure 12 As shown in (b), nanowires 23a to 23d are formed on the upper portion of the cell. Nanowires 23a to 23d are arranged along the X direction with nanowires 21m, 26a, and 26b. Nanowires 23a, 23b, 23c, and 23d overlap with nanowires 21c, 21d, 28a, and 28c, respectively, when viewed from above.

[0195] Nanowires 26i and 26j are formed in the lower portion of the cell and overlap with nanowires 21m and 21n in a plan view. In other words, transistors P1 and P2 overlap with dummy transistors N21 and N22 in a plan view.

[0196] The gate wiring 35 is formed to be aligned with the gate wirings 31 and 32 in the X direction.

[0197] like Figure 12 As shown in FIG. (b), at the lower ends of the nanowires 23a to 23d, pads 24g to 24j are formed, each of which is formed by doping a P-type semiconductor. Figure 12 In the example, nanowire 23a, gate wiring 32, and pads 24a and 24g form transistor P3. Nanowire 23b, gate wiring 32, and pads 24d and 24h form transistor P4. Nanowire 23c, gate wiring 35, and pads 24c and 24i form transistor P5. Nanowire 23d, gate wiring 35, and pads 24f and 24j form transistor P6.

[0198] That is, the transistors P3 to P6 overlap with the transistors N3 and N4 and the dummy transistors N23 and N24 in a plan view. The transistors P3 to P6 are arranged in the X direction along with the transistor P1 and the dummy transistors P21 and P22.

[0199] Local wiring 41d is connected to pads 22g and 22j and dummy pads 29a and 29d. Local wiring 41i is connected to pads 22s, 24a, and 24d. Local wiring 44a is connected to pads 24g to 24j.

[0200] In this variation, the transistor corresponding to the read driver transistor RPD2 is stacked with the transistor corresponding to the driver transistor PD1. Furthermore, the transistor corresponding to the read driver transistor RPD2 and the transistor corresponding to the read access transistor RPG2 are arranged in the X direction. Furthermore, this variation achieves the same effects as the dual-port SRAM cell according to the second embodiment.

[0201] Transistors P3 and P4 overlap with transistors N3 and N4 when viewed from above. That is, transistors P3 and P4 are stacked on top of transistors N3 and N4. Transistors P3 to P6 are arranged in the X direction. This reduces the area of the dual-port SRAM cell.

[0202] It should be noted that in the above embodiments and variations, each transistor includes a single nanowire, but a portion or all of the transistors may include multiple nanowires. In this case, multiple nanowires may be arranged along the X direction or along the Z direction when viewed from above. Multiple nanowires may also be arranged in both the X and Z directions. Furthermore, the number of nanowires included in the transistors may be different at the top and bottom of the cell.

[0203] In the above embodiments, the cross-sectional shape of the nanowire is approximately square, but is not limited thereto and may be, for example, circular or rectangular.

[0204] In the above embodiments, nanowire FETs are described as examples of three-dimensional transistors, but the present invention is not limited thereto. For example, the transistor formed at the bottom of each cell may be a fin transistor.

[0205] -Industrial Applicability-

[0206] In the present disclosure, a dual-port SRAM cell using a CFE can be realized while reducing the area of the dual-port SRAM cell.

[0207] -Explanation of symbols-

[0208] 11, 12, 13, 14 Power supply wiring

[0209] 21a~21u, 23a~23d nanowires

[0210] 22a~22v, 24a~24j solder pads

[0211] 72~77, 81, 82 wiring

[0212] N1~N12, P1~P6 transistors

[0213] PU1, PU2 load transistors

[0214] PD1, PD2 drive transistors

[0215] PG1, PG2 access transistors

[0216] RPD1, RPD2 readout driver transistors

[0217] RPG1, RPG2 read access transistors

[0218] WBL, WBLB write bit line

[0219] RBL Read bit line

[0220] WWL Write Word Line

[0221] RWL, NRWL read word line

Claims

1. A semiconductor memory device comprising a dual-port SRAM cell, characterized in that: The dual-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. In the first transistor, one node is connected to a first power supply supplying a first voltage, another node is connected to the first node, and a gate is connected to the second node. In the second transistor, one node is connected to the first power supply, another node is connected to the second node, and a gate is connected to the first node. In the third transistor, one node is connected to the first node, the other node is connected to a second power supply that supplies a second voltage that is different from the first voltage, and the gate is connected to the second node. In the fourth transistor, one node is connected to the second node, another node is connected to the second power supply, and a gate is connected to the first node. In the fifth transistor, one node is connected to the first write bit line, another node is connected to the first node, and the gate is connected to the write word line. In the sixth transistor, one node is connected to the second write bit line, the second write bit line and the first write bit line form a complementary bit line pair, another node is connected to the second node, and the gate is connected to the write word line. In the seventh transistor, a node is connected to the second power supply, and a gate is connected to the second node. In the eighth transistor, one node is connected to the other node in the seventh transistor, the other node is connected to the read bit line, and the gate is connected to the read word line. The third transistor to the sixth transistor are each composed of a first conductivity type three-dimensional structure transistor formed in the first layer, The first transistor and the second transistor are each composed of a three-dimensional structure transistor of a second conductivity type formed in a second layer, the second layer is different from the first layer, and the second conductivity type is different from the first conductivity type, and at least a portion of the first transistor and the second transistor overlaps with the third transistor and the fourth transistor, respectively, in a plan view. The seventh transistor and the eighth transistor each include a three-dimensional transistor of the first conductivity type formed in the first layer, and are arranged along a first direction in which the channel portion from the first transistor to the eighth transistor extends. The seventh transistor and the eighth transistor include a first three-dimensional structure transistor and a second three-dimensional structure transistor, respectively. The first three-dimensional transistor is formed in the first layer. The second three-dimensional structure transistor is formed in the second layer so that at least a portion thereof overlaps with the first three-dimensional structure transistor in a plan view.

2. The semiconductor memory device according to claim 1, wherein: The third transistor to the eighth transistor are formed by a plurality of three-dimensional transistors connected in parallel.

3. The semiconductor memory device according to claim 1, wherein: The third transistor and the fifth transistor are arranged along the first direction. The fourth transistor and the sixth transistor are arranged along the first direction.

4. The semiconductor memory device according to claim 1, wherein: The third transistor, the sixth transistor, and the seventh transistor are arranged along a second direction perpendicular to the first direction. The fourth transistor, the fifth transistor, and the eighth transistor are arranged along the second direction.

5. The semiconductor memory device according to claim 1, wherein: The second layer is located higher than the first layer in the depth direction.

6. The semiconductor memory device according to claim 1, wherein: The first transistor and the third transistor each have a first gate wiring directly connected to the same gate wiring at their gates. The second transistor and the fourth transistor each have a second gate wiring directly connected to the gate.

7. The semiconductor memory device according to claim 1, wherein: The third transistor and the seventh transistor each have a first gate wiring directly connected to the same gate wiring at their gates.

8. A semiconductor memory device comprising a dual-port SRAM cell, characterized in that: The dual-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. In the first transistor, one node is connected to a first power supply supplying a first voltage, another node is connected to the first node, and a gate is connected to the second node. In the second transistor, one node is connected to the first power supply, another node is connected to the second node, and a gate is connected to the first node. In the third transistor, one node is connected to the first node, the other node is connected to a second power supply that supplies a second voltage that is different from the first voltage, and the gate is connected to the second node. In the fourth transistor, one node is connected to the second node, another node is connected to the second power supply, and a gate is connected to the first node. In the fifth transistor, one node is connected to the first write bit line, another node is connected to the first node, and the gate is connected to the write word line. In the sixth transistor, one node is connected to the second write bit line, the second write bit line and the first write bit line form a complementary bit line pair, another node is connected to the second node, and the gate is connected to the write word line. In the seventh transistor, a node is connected to the first power supply, and a gate is connected to the second node. In the eighth transistor, one node is connected to the other node in the seventh transistor, the other node is connected to the read bit line, and the gate is connected to the read word line. The third transistor to the sixth transistor are each composed of a first conductivity type three-dimensional structure transistor formed in the first layer, The first transistor and the second transistor are each composed of a three-dimensional structure transistor of a second conductivity type formed in a second layer, the second layer is different from the first layer, and the second conductivity type is different from the first conductivity type, and at least a portion of the first transistor and the second transistor overlaps with the third transistor and the fourth transistor, respectively, in a plan view. The seventh transistor and the eighth transistor each include a three-dimensional transistor of the second conductivity type formed in the second layer, and are arranged along a first direction in which the channel portion from the first transistor to the eighth transistor extends. The seventh transistor and the eighth transistor include a first three-dimensional structure transistor and a second three-dimensional structure transistor, respectively. The first three-dimensional transistor is formed in the first layer. The second three-dimensional structure transistor is formed in the second layer so that at least a portion thereof overlaps with the first three-dimensional structure transistor in a plan view.

9. The semiconductor memory device according to claim 8, wherein: The third transistor to the eighth transistor are formed by a plurality of three-dimensional transistors connected in parallel.

10. The semiconductor memory device according to claim 8, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are respectively arranged with the seventh transistor, the eighth transistor, the sixth transistor, and the fifth transistor along a second direction perpendicular to the first direction.

11. The semiconductor memory device according to claim 8, wherein: The third transistor and the fifth transistor are arranged along the first direction. The fourth transistor and the sixth transistor are arranged along the first direction.

12. The semiconductor memory device according to claim 8, wherein: The second layer is located higher than the first layer in the depth direction.

13. The semiconductor memory device according to claim 8, wherein: The first transistor and the third transistor each have a first gate wiring directly connected to the same gate wiring at their gates. The second transistor and the fourth transistor each have a second gate wiring directly connected to the gate.

14. The semiconductor memory device according to claim 8, wherein: The third transistor and the seventh transistor each have a first gate wiring directly connected to the same gate wiring at their gates.

15. A semiconductor memory device comprising a dual-port SRAM cell, characterized in that: The dual-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. In the first transistor, one node is connected to a first power supply supplying a first voltage, another node is connected to the first node, and a gate is connected to the second node. In the second transistor, one node is connected to the first power supply, another node is connected to the second node, and a gate is connected to the first node. In the third transistor, one node is connected to the first node, the other node is connected to a second power supply that supplies a second voltage that is different from the first voltage, and the gate is connected to the second node. In the fourth transistor, one node is connected to the second node, another node is connected to the second power supply, and a gate is connected to the first node. In the fifth transistor, one node is connected to the first write bit line, another node is connected to the first node, and the gate is connected to the write word line. In the sixth transistor, one node is connected to the second write bit line, the second write bit line and the first write bit line form a complementary bit line pair, another node is connected to the second node, and the gate is connected to the write word line. In the seventh transistor, a node is connected to the first power supply or the second power supply, and a gate is connected to the second node. In the eighth transistor, one node is connected to the other node in the seventh transistor, the other node is connected to the read bit line, and the gate is connected to the read word line. The third transistor to the sixth transistor include a first stereoscopic transistor and a second stereoscopic transistor, respectively. The first three-dimensional structure transistor is a first conductivity type three-dimensional structure transistor formed in the first layer. The second three-dimensional structure transistor is a three-dimensional structure transistor of the first conductivity type formed in a second layer different from the first layer so as to at least partially overlap with the first three-dimensional structure transistor in a plan view. The first transistor and the second transistor each include a three-dimensional structure transistor of a second conductivity type different from the first conductivity type formed in the second layer. The seventh transistor and the eighth transistor include a third stereoscopic transistor and a fourth stereoscopic transistor, respectively. The third three-dimensional structure transistor is a three-dimensional structure transistor of the first conductivity type or a three-dimensional structure transistor of the second conductivity type formed in the first layer. The fourth three-dimensional structure transistor is a three-dimensional structure transistor formed in the second layer so that at least a portion overlaps with the third three-dimensional structure transistor in a plan view and has the same conductivity type as the third three-dimensional structure transistor.

16. The semiconductor memory device according to claim 15, wherein: The third transistor and the fifth transistor are arranged along a first direction in which the channel portions of the first transistor to the eighth transistor extend. The fourth transistor and the sixth transistor are arranged along the first direction. The seventh transistor and the eighth transistor are arranged along the first direction.

17. The semiconductor memory device according to claim 15, wherein: The first transistor, the third transistor, the sixth transistor, and the seventh transistor are arranged along a second direction, and the second direction is perpendicular to the first direction in which the channel portions of the first transistor to the eighth transistor extend. The second transistor, the fourth transistor, the fifth transistor, and the eighth transistor are arranged along the second direction.

Images