Semiconductor device and manufacturing method thereof, three-dimensional memory, and electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, a three-dimensional memory, and an electronic device, which relate to the field of semiconductor chip technology and aim to solve the problem of gate line short circuit in different gate layers caused by excessive etching. The semiconductor device includes a stacked structure, a conductive pad, a coupling portion, and a first gate line contact extending along a first direction. The stacked structure has a step area, including a plurality of gate lines and a plurality of insulating layers alternately stacked along a first direction, the plurality of gate lines including a first gate line; the plurality of insulating layers including a first insulating layer, the first insulating layer being located on one side of the first gate line along the first direction and in contact with the first gate line. In the step area, the conductive pad is located on one side of the first gate line along the first direction and is separated from the first gate line by the first insulating layer. The coupling portion is configured to couple the conductive portion and the first gate line. The first gate line contact and the conductive pad are located on the same side of the first gate line and are connected to the conductive pad.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a manufacturing method thereof, a three-dimensional memory, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process lower limit, manufacturing technologies such as planar processes become challenging and costly. This causes the storage density of planar memories such as 2D NAND flash memory to approach the upper limit, posing severe challenges to the semiconductor memory industry.

[0003] Three-dimensional memory (such as 3D NAND flash memory) overcomes these limitations. Specifically, by stacking memory cells three-dimensionally to form a multi-layer structure, the storage density is increased, and its storage capacity is several times higher than that of similar planar memory. Currently, three-dimensional memory has evolved from 32 layers to 64 layers, and even higher. As the number of layers in three-dimensional memory increases, the depth of the contact holes continues to deepen, making the process of forming contact holes more difficult. Over-etching can easily lead to short circuits between gate lines in different gate layers. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a three-dimensional memory, and an electronic device, aiming to solve the problem of over-etching that easily causes short circuits in gate lines in different gate layers.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a semiconductor device is provided, comprising a stacked structure, a conductive portion, a coupling portion, and a first gate line contact extending along a first direction. The stacked structure has a step region, the stacked structure comprising a plurality of gate lines and a plurality of insulating layers alternately stacked along a first direction, the plurality of gate lines comprising a first gate line; the plurality of insulating layers comprising a first insulating layer, the first insulating layer being located on one side of the first gate line along the first direction and in contact with the first gate line. In the step region, the conductive portion is located on one side of the first gate line along the first direction and is separated from the first gate line by the first insulating layer. The coupling portion is configured to couple the conductive portion to the first gate line. The first gate line contact is located on the same side of the first gate line as the conductive portion and is connected to the conductive portion.

[0007] In some embodiments, along an extension direction of the first gate line, the coupling portion is located on one side of the first insulating layer, and the coupling portion contacts a side surface of the first insulating layer.

[0008] In some embodiments, the coupling portion is away from a side surface of the first insulating layer and is flush with an end surface of the first gate line.

[0009] In some embodiments, an end surface of the first gate line is flush with a side surface of the conductive portion.

[0010] In some embodiments, the conductive portion contacts a surface of the first insulating layer away from the first gate line.

[0011] In some embodiments, a thickness of the conductive portion is no greater than a thickness of the gate conductive layer.

[0012] In some embodiments, the gate line contact does not contact the first gate line.

[0013] In some embodiments, an orthographic projection of the gate line contact on the first gate line is included in an orthographic projection of the conductive portion on the first gate line.

[0014] In some embodiments, the multiple gate lines include multiple first gate lines arranged along the first direction, two adjacent first gate lines among the multiple first gate lines are respectively a lower gate line and an upper gate line, the length of the lower gate line is greater than the length of the upper gate line; and there is a gap between the conductive part coupled to the lower gate line and the end surface of the upper gate line.

[0015] In some embodiments, the first gate line, the conductive portion, and the coupling portion are made of the same material.

[0016] In some embodiments, the multiple gate lines also include a second gate line located on one side of the first gate line along the first direction, and the length of the first gate line is greater than the length of the second gate line; the semiconductor device also includes: a second gate line contact extending along the first direction, connected to the second gate line.

[0017] In some embodiments, the multiple insulating layers also include a second insulating layer, which is located on a side of the second gate line away from the first gate line and is in contact with the second gate line; the semiconductor device also includes a retention portion, which is located on one side of the second insulating layer along the extension direction of the second gate line, and the retention portion is in contact with the side surface of the second insulating layer; the retention portion is connected to the second gate line.

[0018] In some embodiments, along the first direction, a first gate line adjacent to the second gate line is coupled to a conductive portion, and a gap exists between the conductive portion and the reserved portion.

[0019] In some embodiments, the reserved portion and the second gate line contact are respectively located at two ends of the second gate line; and the reserved portion is located on a side of the second gate line close to the conductive portion.

[0020] In some embodiments, a through hole is provided on the first insulating layer, and the coupling portion is provided in the through hole.

[0021] In some embodiments, the cross-section of the whole formed by the coupling portion and the conductive portion is T-shaped or L-shaped; the cross-section is parallel to the first direction and a second direction, and the second direction is the extension direction of the first gate line.

[0022] Other embodiments of the present disclosure provide a three-dimensional memory, comprising the semiconductor device as described in any of the aforementioned embodiments, and further comprising: a peripheral circuit coupled to the semiconductor device.

[0023] Other embodiments of the present disclosure provide an electronic device including the three-dimensional memory as described in any of the aforementioned embodiments.

[0024] Still other embodiments of the present disclosure provide a method for preparing a semiconductor device, for preparing a semiconductor device as described in any of the aforementioned embodiments. The preparation method includes: forming an intermediate semiconductor structure on a substrate, the intermediate semiconductor structure including: a first stacked structure and a protective layer covering the first stacked structure; wherein the first stacked structure includes a plurality of gate line sacrificial portions and a plurality of insulating layers alternately stacked along a first direction, the plurality of gate line sacrificial portions including a first gate line sacrificial portion; the plurality of insulating layers including a first insulating layer located above the first gate line sacrificial portion; the first stacked structure also includes: a conductive portion sacrificial portion and a coupling sacrificial portion located in a step region, the conductive portion sacrificial portion being located above the first gate line sacrificial portion and separated from the first gate line sacrificial portion by the first insulating layer, the coupling sacrificial portion being connected between the conductive portion sacrificial portion and the first gate line sacrificial portion. The plurality of gate line sacrificial portions, the conductive portion sacrificial portion, and the coupling sacrificial portion are replaced with gate material to obtain a plurality of gate lines, a conductive portion, and a coupling portion, the plurality of gate lines including a first gate line obtained by replacing the first gate line sacrificial portion. A first gate line contact extending along the first direction is formed, wherein the first gate line contact and the conductive portion are located on the same side of the first gate line and are connected to the conductive portion.

[0025] In some embodiments, forming an intermediate semiconductor structure on a substrate includes: forming a second stacked structure on the substrate, the second stacked structure including: a plurality of gate sacrificial layers and a plurality of insulating layers alternately stacked along a first direction, the plurality of gate sacrificial layers and the plurality of insulating layers forming a stepped morphology in the step region; the plurality of insulating layers including: at least one first insulating layer; forming a conductive sacrificial layer located on the upper surface of each first insulating layer and extending along an end surface of the first insulating layer, and a coupling sacrificial layer covering the end surface of the first insulating layer in the step region to obtain a third stacked structure, wherein the conductive sacrificial layer and the coupling sacrificial layer are in contact; forming a protective layer covering the third stacked structure; and dividing the third stacked structure covered with the protective layer to obtain the intermediate semiconductor structure, wherein the gate sacrificial layer, the conductive sacrificial layer, and the coupling sacrificial layer located below and in contact with the first insulating layer are respectively divided into a plurality of first gate line sacrificial portions, a plurality of conductive sacrificial portions, and a plurality of coupling sacrificial portions.

[0026] In some embodiments, in the step region, forming a coupling portion sacrificial layer covering an end surface of the first insulating layer includes: performing surface treatment on the end surface of the first insulating layer.

[0027] In some embodiments, forming the intermediate semiconductor structure on the substrate further includes: before dividing the third stacked structure covered with the protective layer, planarizing the upper surface of the third stacked structure covered with the protective layer to remove the uppermost conductive sacrificial layer.

[0028] In the semiconductor device provided by the embodiment of the present disclosure, the first gate line contact contacts the conductive portion, and the conductive portion contacts the first gate line through the coupling portion, thereby realizing coupling between the first gate line contact and the corresponding first gate line. Since the conductive portion is located above the first gate line, the contact hole etched in the protective layer only needs to expose the surface of the conductive portion without exposing the first gate line, and then the contact hole is filled with conductive material to form the first gate line contact, that is, if a gate line needs to be connected, the scheme in this embodiment can move the bottom end of the first gate line contact up to the position of the conductive portion, and then connect the gate line, thereby reducing the depth of the contact hole and reducing the difficulty of the corresponding contact hole formation process. In the embodiment of the present disclosure, since the first gate line and the conductive portion are separated by the first insulating layer, the thickness of each of the first gate line and the conductive portion is relatively small. In the process of back etching to form the first gate line and the conductive portion, it is not easy for conductive material to remain, thereby helping to reduce the risk of short circuit between different gate lines.

[0029] It can be understood that the beneficial effects achieved by the semiconductor device manufacturing method, three-dimensional memory and electronic device provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the semiconductor device above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0031] Figure 1 is a partial structural diagram of a three-dimensional memory according to some embodiments;

[0032] Figure 2 is a partial structural diagram of a three-dimensional memory according to some other embodiments;

[0033] Figure 3 is a process flow chart for forming gate lines in some embodiments;

[0034] Figure 4 is a three-dimensional block diagram of a three-dimensional memory according to some embodiments;

[0035] Figure 5 for Figure 3 Equivalent circuit diagram of the storage string array layer in the middle;

[0036] Figure 6 is a schematic diagram of a three-dimensional structure of a semiconductor device according to some embodiments;

[0037] Figure 7 for Figure 6 Cross-sectional view along the A-A' direction;

[0038] Figure 8 for Figure 6 Cross-sectional view along the BB' direction;

[0039] Figure 9 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments;

[0040] Figures 10A to 10S is a flow chart of a process for preparing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0042] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0043] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0045] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0046] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0047] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0048] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0049] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0050] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0051] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0052] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0053] As used herein, the term "substrate" refers to a material onto which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate material may include at least one semiconductor material such as silicon, germanium, gallium arsenide, indium phosphide, or the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0054] The term “three-dimensional memory” refers to a memory formed by regularly arranging (eg, array-arranging) substantially parallel memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings).

[0055] In some embodiments, see Figure 1 The three-dimensional memory includes a stacked structure formed by stacking a gate conductive layer and an insulating layer, and the gate conductive layer includes a plurality of gate lines. The stacked structure can be divided into a core storage area and a step area. In the step area, a plurality of gate lines located in different gate conductive layers have a step morphology and are electrically connected to the peripheral circuit through contact parts. In the actual preparation process of the three-dimensional memory, in order to achieve electrical connection between the contact parts and the gate lines in the stacked structure, it is necessary to etch a plurality of contact holes in the dielectric layer covering the stacked structure in the step area to expose parts of each gate line, and then fill the contact holes with conductive material to form contact parts. However, with the improvement of the integration level of the three-dimensional memory and the increase in the number of stacked layers, the depth of the contact holes corresponding to the gate lines at the lower position is getting deeper and deeper. Due to the difficulty of deep hole etching, over-etching is prone to occur, making the contact holes formed too deep and damaging the corresponding gate lines, resulting in an increased risk of short-circuiting between different gate lines.

[0056] In some embodiments, see Figure 2 In order to avoid short circuits between different gate lines caused by excessive etching, the portion of the gate line located below the contact hole will be thickened so that the formed contact hole will not penetrate the gate line, thereby solving the problem of the contact hole being too deep and damaging the corresponding gate line.

[0057] In some embodiments, a conductive material is generally used to replace the gate sacrificial layer to form a gate conductive layer, for example, see Figure 3 In (a), the isolation trench can be used as a channel for the etchant, and the gate sacrificial layer can be removed by wet etching to form multiple gaps. Figure 3 (b) in the figure, and then using any of the thin film deposition processes such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), atomic layer deposition (ALD), etc., to deposit a gate conductive layer in the gap. While depositing the gate conductive layer, a conductive material is also deposited on the sidewalls of the isolation trench. Figure 3 In (c), after the gate conductive layer is deposited, the conductive material deposited on the sidewall of the isolation trench can be removed by etchback, so that the conductive materials in different gaps are isolated from each other, thereby forming gate lines that are not coupled to each other.

[0058] In some embodiments, to form partially thickened gate lines, portions of the gate sacrificial layer are also thickened, thereby forming larger voids. When filling the voids with conductive material through deposition, the resulting larger voids require a longer deposition time, and accordingly, the thickness of the conductive material deposited on the sidewalls of the isolation trenches is also greater. Subsequent etching back to remove the conductive material deposited on the sidewalls of the isolation trenches can result in incomplete removal, leaving residual conductive material. This can cause short circuits between gate lines located in different gate conductive layers, leading to memory failure.

[0059] In order to at least partially solve the above problems, some embodiments of the present disclosure provide a three-dimensional memory 1, see Figure 4 The three-dimensional memory 1 includes a semiconductor device 10 and a peripheral circuit 20 . The semiconductor device 10 can be coupled to the peripheral circuit 20 by bonding or other methods.

[0060] The peripheral circuit 20 is configured to control and sense the semiconductor device 10. The peripheral circuit 20 may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for supporting the operation of the three-dimensional memory 1, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit 20 may also include any other circuitry compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)) or memory circuits (e.g., static random access memories (SRAMs)).

[0061] See also Figure 4 and Figure 5 The semiconductor device 10 includes a memory string array layer 110, which includes, for example, a plurality of memory cell strings 111 arranged in an array. The peripheral circuit 20 is coupled to the plurality of memory cell strings 111 to support data read, write, and erase operations on the memory cell strings 111.

[0062] A memory cell string 111 (e.g., each memory cell string 111) may include multiple transistors T (e.g., including: T1-Tm, a total of m transistors, m ≥ 2). The multiple transistors T in each memory cell string 111 are arranged along a first direction (i.e., the Z direction). One transistor T may be configured as a memory cell. These transistors T are connected together to form the memory cell string 111. A transistor T (e.g., each transistor T) is coupled to a gate line GL, which is configured to control the conduction state of the transistor T.

[0063] Furthermore, among the multiple gate lines GL, the gate line located at the bottom along the first direction (i.e., the Z direction) is constructed as a source select gate SGS, which is configured to control the conduction state of the transistor Tm in the memory cell string 111, that is, to control the on-off between the source channel of the memory cell string 111 and the source terminal SL; the gate line located at the top along the Z direction is constructed as a drain select gate SGD, which is configured to control the conduction state of the transistor T1 in the memory cell string 111, that is, to control the on-off of the drain channel of the memory cell string 111; the gate line located in the middle is constructed as multiple word lines WL, for example, including word line WL0, word line WL1, ..., word line WLn. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 111 can be completed.

[0064] In some embodiments, see Figure 4 and Figure 5 The semiconductor device 10 may further include an array interconnect layer 120, coupled to the memory string array layer 110 and the peripheral circuit 20, respectively, and configured to transmit electrical signals between the memory cell strings 111 and the peripheral circuit 20. In this embodiment, the relative positions of the array interconnect layer 120, the memory string array layer 110, and the peripheral circuit 20 are not limited. For example, the array interconnect layer 120 may be located between the memory string array layer 110 and the peripheral circuit 20, or may be located on a side of the memory string array layer 110 away from the peripheral circuit 20.

[0065] For example, the peripheral circuit 20 and the semiconductor device 10 can be fabricated sequentially on a single silicon substrate. Furthermore, for example, the peripheral circuit 20 and the semiconductor device 10 can be fabricated separately and then coupled (i.e., stacked) together to form the three-dimensional memory 1. The following describes in detail the structure and fabrication method of the three-dimensional memory 1 provided in embodiments of the present disclosure, using the latter as an example.

[0066] Some embodiments of the present disclosure provide a semiconductor device that can be applied to the above-mentioned three-dimensional memory. Figures 6 to 8 , Figure 6 A schematic diagram of the three-dimensional structure of a semiconductor device 10 provided in some embodiments of the present disclosure is shown. Figure 7 for Figure 6 A cross-sectional view of the semiconductor device 10 along the section line AA', Figure 8 for Figure 6 FIG. 1 is a cross-sectional view of one memory cell string 111 of the semiconductor device 10 along the section line BB′.

[0067] like Figures 6 to 8 As shown, the semiconductor device 10 includes a memory string array layer 110 and may further include an array interconnect layer 120. The memory string array layer 110 includes: a plurality of memory cell strings 111. To form the plurality of memory cell strings 111, the memory string array layer 110 includes: a stacked structure 130 and a channel structure 112 extending through the stacked structure 130 and extending through the plurality of memory cell strings 111. The stacked structure includes a plurality of gate conductive layers 131 and a plurality of insulating layers 132 alternately stacked along a first direction (i.e., the Z direction). The embodiments of the present disclosure do not limit the number of layers of the stacked structure 130. For example, the number of layers of the stacked structure 130 may be 8, 32, 64, 128, etc. The more layers of the stacked structure 130, the higher the integration density of the three-dimensional memory. Along the extension direction of the gate conductive layer 131 (i.e., the X direction, also the second direction), the stacked structure 130 can be divided into a core storage region CT and a step region ST. The plurality of channel structures 112 are located in the region defined by the core storage region CT, and the portion of the stacked structure 130 corresponding to the step region ST has a stepped morphology. Corresponding to the region division of the stacked structure 130, the semiconductor device 10 can also be divided into the core storage region CT and the step region ST.

[0068] The material of the insulating layer 132 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and a combination of one or more of an organic insulating material. In some embodiments, the material of the insulating layer can be silicon oxide. The materials of the various insulating layers can be the same or different. In some embodiments, the materials of the various insulating layers are the same, for example, silicon oxide.

[0069] A gate conductive layer 131 (e.g., each gate conductive layer 131) includes a plurality of gate lines GL, each of which extends in the second direction (i.e., the X direction). In the same gate conductive layer 131, the plurality of gate lines are arranged along the third direction (i.e., the Y direction). The X direction and the Y direction are within the plane of the gate conductive layer 131 and intersect with each other. For example, any two of the Z direction, the X direction, and the Y direction are perpendicular to each other.

[0070] In some embodiments, see Figure 6 and Figure 7Along the Z direction, among the multiple gate conductive layers 131, the gate line GL in the uppermost gate conductive layer 131 is constructed as a drain select gate SGD, coupled to the string select line CL1 in the array interconnect layer 120; the gate line in the lowermost gate conductive layer 131 is constructed as a source select gate SGS, coupled to the ground select line CL2 in the array interconnect layer 120; the gate conductive layer 131 in the middle layer includes multiple gate lines GL, which are used as word lines WL, for example Figure 6 W1 to W4 shown in FIG.

[0071] Among them, see Figure 7 The gate conductive layer 131 may include a conductor layer 132a. The conductor layer 132a is formed of a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. In some embodiments, the conductor layer may be made of tungsten. The materials of the various conductor layers may be the same or different. In some embodiments, the conductor layers 132a in each gate conductive layer 131 may be made of the same material, such as tungsten.

[0072] In some embodiments, see Figure 7 The gate conductive layer 131 further includes an interface layer 132b, and the conductive layer 132a is separated from both the insulating layer 132 and the channel structure by the interface layer 132b. The interface layer 132b is configured as a barrier material layer, which can serve as a barrier layer to reduce the diffusion of impurity atoms or gases into the insulating layer and the channel structure; the interface layer 132b can also be configured as an adhesion layer, which can enhance the adhesion between the conductive layer and the insulating layer. The material of the interface layer 132b may include a metal compound, such as a combination of one or more of titanium nitride, tantalum nitride, and tungsten carbide.

[0073] In some embodiments, see Figure 6 To implement block storage in the core memory area CT, the semiconductor device 10 further includes isolation trenches Sp for dividing the stacked structure 130 into multiple memory blocks. In some embodiments, the isolation trenches Sp penetrate the stacked structure 130 along the Z direction and extend along the X direction. Multiple gate lines GL in the same gate conductive layer 131 can be divided by the isolation trenches Sp.

[0074] Continue to see Figure 6 and Figure 7 , multiple contact portions (also referred to as contacts) are provided in the step region ST, and the multiple contact portions are configured to couple the memory string array layer and the array interconnect layer. One (e.g., each) gate line contact G-CNT extends along the Z direction and is coupled to a gate line GL, whereby the gate line contact G-CNT can address each memory cell string 111 separately. The gate line contact G-CNT is made of a conductive material, including but not limited to one or more combinations of tungsten, cobalt, copper, aluminum, silicide, etc.

[0075] The semiconductor device may further include at least one (e.g., multiple) source select gate contacts SGS-CNT extending along the Z direction and coupled to the source select gate SGS, and a source terminal SL located below the source select gate SGS, wherein the source terminal SL is coupled to the bottom ends of the channel structures 112 in the plurality of memory cell strings 111, so that these memory cell strings 111 can share the source terminal SL. The semiconductor device may further include at least one (e.g., multiple) source contacts SL-CNT extending along the Z direction and coupled to the source terminal SL. Exemplarily, the source select gate SGS and the source contact SL-CNT are made of a conductive material, and the materials of the two may be the same or different; wherein the conductive material includes but is not limited to tungsten, cobalt, copper, aluminum, and / or silicide.

[0076] Continue to see Figure 6 At least one (e.g., multiple) channel structures 112 are located in the core storage region CT and extend through multiple gate lines GL along the Z direction. The channel structure 112 and the gate lines GL surrounding the channel structure 112 form a memory cell string 111. The semiconductor device 10 includes multiple memory cell strings 111 arranged in an array on the XY plane.

[0077] In some embodiments, the array interconnect layer 120 in the semiconductor device 10 may further include at least one (e.g., multiple) bit lines BL and at least one (e.g., multiple) bit line contacts BL-CNT. Each bit line contact BL-CNT couples the top of a memory cell string 111 to a bit line BL, thereby enabling each memory cell string 111 to be addressed separately through these bit lines BL and bit line contacts BL-CNT. The bit lines BL and the bit line contacts BL-CNT are made of conductive materials, which may be the same or different. The conductive materials include, but are not limited to, one or more combinations of tungsten, cobalt, copper, aluminum, silicide, and the like.

[0078] In some embodiments, see Figure 8 , the channel structure 112 includes a dielectric layer structure 112a and a channel 112b. The channel 112b is in the shape of a column, and the dielectric layer structure 112a is a tubular structure covering the sidewalls of the channel 112b. The dielectric layer structure 112a may include a tunnel insulating layer, a charge storage layer, and a blocking layer stacked sequentially from the sidewalls of the channel 112b. The tunnel insulating layer may include an oxide, such as silicon oxide. The charge storage layer may include a nitride, such as silicon nitride or a metal oxide. The blocking layer may include silicon oxide or a metal oxide, such as hafnium oxide or aluminum oxide. Specifically, the dielectric layer structure 112a may have an oxide-nitride-oxide (ONO) layered structure. The material of the channel 112b may be a semiconductor, such as polycrystalline silicon or single crystal silicon, and may include, for example, p-type impurities such as boron (B) in a portion thereof.

[0079] In some embodiments, see Figure 7 The semiconductor device further includes a protection layer 140 covering the stacked structure 130. The protection layer 140 is made of an insulating material, including but not limited to silicon oxides such as tetraethyl orthosilicate (TEOS), siloxane, and silsesquioxane.

[0080] The connection structure between the gate line GL and the gate line contact G-CNT will be described in detail below.

[0081] Continue to see Figure 6 and Figure 7 , the semiconductor device 10 in the embodiment of the present disclosure further includes at least one (for example, multiple) conductive parts 150 located in the step region ST, and each conductive part 150 couples the gate line and the contact part. The conductive part 150 is made of a conductive material, and the conductive material includes but is not limited to a combination of one or more of tungsten, cobalt, copper, aluminum, silicide, etc. There are no excessive restrictions on the specific shape of the conductive part 150. For example, the shape of the conductive part 150 can be columnar, planar, or any other shape that can be formed by relevant preparation processes. In the present disclosure, an example is given in which the conductive part 150 is a planar conductive pad (also referred to as a conductive pad, EMI pad, etc.).

[0082] For simplicity, the gate lines in the semiconductor device 10 that are coupled to the gate line contacts G-CNT via the conductive portion 150 are referred to as first gate lines GL1; and the gate lines that are not coupled to the gate line contacts G-CNT via the conductive portion 150 are referred to as second gate lines GL2. In some examples, some (at least one, for example, multiple) of the gate lines in the semiconductor device 10 may be first gate lines GL1, and some may be second gate lines GL2. In other examples, all gate lines in the semiconductor device 10 are first gate lines GL1.

[0083] In some embodiments, see Figure 7 Along the stacking direction (ie, the Y direction) of the stacking structure 130, the gate line GL included in the gate conductive layer 131 at the top is the second gate line GL2, and except for the gate conductive layer 131 at the top, the gate line GL included in other gate conductive layers 131 is the first gate line GL1.

[0084] In addition, hereinafter, among the multiple insulating layers 132 of the semiconductor device 10, an insulating layer 132 located on one side of the first gate line GL1 along the Z direction and in contact with the first gate line GL1 is referred to as the first insulating layer L1. Each conductive portion 150 and the first gate line GL1 coupled thereto are separated by the first insulating layer L1. In some examples, the first insulating layer L1 is in contact with the upper surface of the corresponding first gate line GL1, and the gate line contact coupled to the first gate line GL1 is referred to as the first gate line contact G-CNT1. In this case, the first gate line contact G-CNT1 is located on the same side of the first gate line GL1 as the conductive portion 150 and is connected to (e.g., in contact with) the conductive portion 150.

[0085] In order to couple the conductive portion 150 to the first gate line GL1, see Figure 7 , the semiconductor device further includes at least one (for example, multiple) coupling portions 160 located in the step region ST. The conductive portion 150 and the coupling portion 160 are similar to the gate line GL, both including a conductor layer, and further including an interface layer. The corresponding materials can refer to the above description of the gate conductive layer 131. Specifically, along the Z direction, the conductive portion 150, the coupling portion 160 and the first gate line contact G-CNT1 coupled to the same first gate line GL1 are all located on the same side of the first gate line GL1, and the conductive portion 150 and the first gate line GL1 coupled thereto are separated by a first insulating layer L1. The first gate line GL1 and the conductive portion 150 are connected by the coupling portion 160 provided therebetween. There are no excessive restrictions on the specific manner in which the first gate line contact G-CNT1 is coupled to the first gate line GL1.

[0086] In one example, a first gate line contact G-CNT1 can penetrate the conductive portion 150 and contact the first gate line GL1. In this case, the first gate line contact G-CNT1 is connected to both the conductive portion 150 and the first gate line GL1. In another example, a first gate line contact G-CNT1 is in contact with the conductive portion 150 and is electrically connected to the first gate line GL1 through the conductive portion 150 and the coupling portion 160. For example, Figure 7 In the figure, each conductive portion 160 coupled to the two first gate lines GL1 located at the top and bottom along the Y direction is penetrated by the first gate line contact G-CNT1 but does not reach the first gate line GL1, and each conductive portion 160 coupled to other first gate lines GL1 is in contact with the first gate line contact G-CNT1 but is not penetrated by the first gate line contact G-CNT1. There is no excessive restriction on the position of the coupling portion 160. For example, the orthographic projection of the coupling portion 160 on the first gate line GL1 has an overlapping area with the first gate line GL1 and also has an overlapping area with the orthographic projection of the conductive portion 150 on the first gate line GL1.

[0087] For example, the conductive portion 150 and the first gate line GL1 coupled thereto may be provided with only the first insulating layer, or with other film layers in addition to the first insulating layer, without further limitation. For example, the conductive portion 150 and the first gate line GL1 coupled thereto may be provided with only the first insulating layer L1. In this case, the conductive portion 150 contacts the surface of the first insulating layer L1 away from the first gate line GL1.

[0088] In the semiconductor device 10 described above, the first gate line contact G-CNT1 contacts the conductive portion 150, which contacts the first gate line GL via the coupling portion, thereby achieving coupling between the first gate line contact G-CNT1 and the corresponding first gate line GL1. Since the conductive portion 150 is located above the first gate line GL1, the contact hole H etched in the protective layer 140 only needs to expose the surface of the conductive portion 150 without exposing the first gate line GL1. The contact hole H is then filled with a conductive material to form the first gate line contact G-CNT1. That is, if a gate line needs to be connected, the solution in this embodiment can move the bottom end of the first gate line contact G-CNT1 to the position of the conductive portion 150 to connect the gate line, thereby reducing the depth of the contact hole H and reducing the difficulty of the corresponding contact hole H formation process. In addition, compared to some embodiments 1, the solution provided by the present disclosure adds the conductive portion 150 on the basis of the first gate line GL1. Even if the contact hole H is over-etched, the conductive portion 150 can well protect the first gate line GL1 from damage. In addition, compared to some embodiments 2, when the overall thickness d of the required contact portion remains unchanged, since in the embodiments of the present disclosure, there is a first insulating layer L1 between the first gate line GL and the conductive part 150, the thickness d' of each of the first gate line GL and the conductive part 150 is less than the overall thickness d, that is, both are relatively thin. During the process of etching back to form the first gate line GL and the conductive part 150, it is less likely that conductive material will remain, which helps to reduce the risk of short circuit between different gate lines.

[0089] For example, see Figure 6 and Figure 7Along the extending direction of the first gate line GL1 (ie, the X direction), the coupling portion 160 is located on one side of the first insulating layer L1 and contacts the side surface of the first insulating layer L1. In other words, the coupling portion 160 is directly disposed on the side surface of the first insulating layer L1. When forming the coupling portion 160, a stacking structure (hereinafter referred to as an initial stacking structure) in which the first insulating layer L1 and the gate sacrificial layer are alternately stacked along the Z direction and have a step morphology can be first formed. Then, ion implantation (IMP) or plasma surface treatment (Plasma) can be performed on the right side surface of the first insulating layer L1 in the step area ST to cause material denaturation of the treated portion of the first insulating layer L1. The denatured portion of the first insulating layer L1 has a greater etching rate than the untreated portion of the first insulating layer L1. Then, a protective layer 140 covering the stacking structure is formed, and then the first insulating layer L1 is etched through an etching process. The treated portion of the first insulating layer L1 will be etched away due to its greater etching rate, so that a gap is generated between the etched first insulating layer L1 and the protective layer 140. Subsequently, a conductive material is filled into the gap to form the coupling portion 160. Since the coupling portion 160 is disposed on the side surface of the first insulating layer L1 , the side surface of the first insulating layer L1 is exposed in the initial stacking structure, and thus surface treatment thereof is relatively easy, which is conducive to simplifying the manufacturing process.

[0090] In other examples, at least one (e.g., one) through-hole may be provided on the first insulating layer L1, and the coupling portion 160 may be provided in the through-hole, thereby achieving coupling between the first gate line GL1 and the conductive portion 150. In this case, the through-hole may be completed by a patterning process such as photolithography, the through-hole passes through the first insulating layer L1, and the hole wall of the through-hole is formed by the first insulating layer L1. The orthographic projection of the coupling portion 160 provided in the through-hole on the first gate line GL1 is completely contained in the orthographic projection of the first insulating layer L1 on the first gate line GL1, and is also contained in the orthographic projection of the conductive portion 150 on the first gate line GL1. Specifically, the inclusion mentioned here refers to complete inclusion or basic inclusion. When the edge of the orthographic projection of the coupling portion 160 on the first gate line GL1 is completely included in the edge of the orthographic projection of the conductive portion 150 on the first gate line GL1 (there may be at least partial overlap, or there may be a gap between each other), it is complete inclusion; when the part of the orthographic projection of the coupling portion 160 on the first gate line GL1 (hereinafter referred to as the first projection part) is located outside the area defined by the orthographic projection of the conductive portion 150 on the first gate line GL1, and the area of ​​the first projection part is less than or equal to 5% of the orthographic projection area of ​​the coupling portion 160 on the first gate line GL1, and less than or equal to 5% of the orthographic projection area of ​​the conductive portion 150 on the first gate line GL1, it is basic inclusion.

[0091] When the first gate line GL1 and the conductive portion 150 are coupled via the coupling portion 160 located in the through-hole, there is no excessive restriction on the number of through-holes and coupling portions. For example, only one through-hole may be provided between a conductive portion 150 and a first gate line GL1, and coupling is achieved via a coupling portion 160 located in the through-hole. For another example, a plurality of through-holes may be provided between a conductive portion 150 and a first gate line GL1, each of which is provided with a coupling portion 160, and the conductive portion 150 and the first gate line GL1 are coupled via the plurality of coupling portions 160. When there are a plurality of coupling portions 160, even if a coupling portion 160 fails, coupling can still be achieved via other coupling portions 160, thereby improving device reliability.

[0092] For example, see Figure 7 , the plurality of gate lines include a plurality of first gate lines GL1 arranged along the Z direction, two adjacent first gate lines GL1 among the plurality of first gate lines GL1 are respectively a lower gate line and an upper gate line, and the length of the lower gate line is greater than the length of the upper gate line. Wherein, the end face of the first gate line GL1 here is the surface closer to the conductive portion 150 among the two surfaces of the first gate lines GL1 arranged along the X direction. Along the extension direction of the plurality of first gate lines GL1 (that is, the third direction, the Y direction), the size of the first gate line GL1 is the length of the first gate line GL1. Specifically, among the two adjacent first gate lines GL1 along the Z direction, the first gate line GL1 closer to the substrate is the lower gate line, and the other first gate line GL1 is the upper gate line, and the length of the upper gate line is shorter than that of the lower gate line, thereby forming a step morphology.

[0093] See also Figure 7 The coupling portion 160 is away from the side of the first insulating layer L1 and is flush with the end surface of the first gate line GL1. Specifically, the flush mentioned here includes completely flush and substantially flush. Figure 7 , the side of the first insulating layer L1 in contact with the coupling portion 160 is called the first side P1, the distance between the side P2 of the coupling portion 160 away from the first insulating layer L1 and the first side P1 is the first distance, and the distance between the end surface P3 of the first gate line GL1 and the first side P1 is the second distance. When the first distance and the second distance are approximately equal, they are basically flush. Among them, when the absolute value of the difference between the first distance and the second distance is less than or equal to 5% of either one, the first distance and the second distance are said to be approximately equal. For the upper gate line and the lower gate line adjacent to each other along the Z direction, this setting can ensure that there is a gap between the conductive portion 150 coupled to the lower gate line and the coupling portion 160 coupled to the upper gate line in the X direction while simplifying the preparation process of the coupling portion 160, ensuring that the conductive portion 150 and the coupling portion 160 coupled to different first gate lines GL1 are not connected, further reducing the risk of short circuit between different gate lines GL.

[0094] For example, see Figure 7 , there is a gap between the conductive portion 150 coupled to the lower gate line and the end face of the upper gate line. Specifically, the conductive portion 150 coupled to the lower gate line and the upper gate line are both arranged on the first insulating layer L1 and in contact with the surface of the first insulating layer L1 away from the lower gate line, that is, the conductive portion 150 coupled to the lower gate line and the upper gate line are arranged in the same layer. The setting of the gap between the side surface closer to the upper gate line and the end face of the upper gate line of the two surfaces of the conductive portion 150 coupled to the lower gate line arranged along the X direction can ensure that the conductive portion 150 and the upper gate line respectively coupled to the lower gate line are not connected, thereby avoiding short circuits between different gate lines GL.

[0095] For example, see Figure 7 , the end surface of the first gate line GL1 is flush with the side surface of the conductive portion 150. Here, the side surface of the conductive portion 150 is the surface closer to the end surface of the first gate line GL1 among the two surfaces of the conductive portion 150 arranged along the X direction. Specifically, the flush mentioned here also includes completely flush and substantially flush. Figure 7 , the side surface where the first insulating layer L1 contacts the coupling portion 160 is still referred to as the first side surface P1, the distance between the end surface of the first gate line GL1 and the first side surface is still referred to as the second distance, and the distance between the side surface P4 of the conductive portion 150 and the first side surface P1 is referred to as the third distance. When the second distance and the third distance are approximately equal, they are considered to be substantially flush. Specifically, when the absolute value of the difference between the second distance and the third distance is less than or equal to 5% of either, the second distance and the third distance are said to be approximately equal. For the upper gate line and the lower gate line adjacent to each other along the Z direction, along the X direction, when there is a gap between the surface of the conductive portion 150 coupled to the lower gate line that is closer to the upper gate line and the end surface of the upper gate line, the setting range of the conductive portion 150 is determined by the side surface of the conductive portion 150. When the side surface of the conductive part 150 is flush with the end surface of the first gate line GL1, the setting range of the conductive part 150 is the largest compared to the case where the side surface of the conductive part 150 is not flush with the end surface of the first gate line GL1. From the foregoing content, it can be seen that as long as the contact hole H is in contact with at least part of the conductive part 150, the corresponding coupling of the first gate line contact G-CNT1 set in the contact hole H and the first gate line GL1 can be achieved. When the setting range of the conductive part 150 is larger, the corresponding setting range of the contact hole H in which the first gate line contact G-CNT1 can be coupled with the first gate line GL1 is also increased, and the alignment requirements for the contact hole H during setting are lower. At the same time, it can reduce or even eliminate the adverse effects caused by the position deviation of the contact hole H to a certain extent.

[0096] Exemplarily, the orthographic projection of the first gate line contact G-CNT1 on the first gate line GL1 is included in the orthographic projection of the conductive portion 150 on the first gate line GL1. Specifically, the inclusion mentioned here also refers to complete inclusion or substantial inclusion. When the edge of the orthographic projection of the first gate line contact G-CNT1 on the first gate line GL1 is completely included within the edge of the orthographic projection of the conductive portion 150 on the first gate line GL1 (there may be at least partial overlap, or there may be a gap between them everywhere), it is considered to be complete inclusion; when the portion of the orthographic projection of the first gate line contact G-CNT1 on the first gate line GL1 (hereinafter referred to as the second projection portion) is located outside the area defined by the orthographic projection of the conductive portion 150 on the first gate line GL1, and the area of ​​the first projection portion is less than or equal to 5% of the area of ​​the orthographic projection of the first gate line contact G-CNT1 on the first gate line GL1, and less than or equal to 5% of the area of ​​the orthographic projection of the conductive portion 150 on the first gate line GL1, it is considered to be substantially included. The above-mentioned setting mode limits the contact hole H to only expose the surface of the conductive portion 150 away from the first gate line GL1, thereby further reducing the risk of short circuit between different first gate lines GL1 caused by excessive etching on the basis of the above-mentioned beneficial effects. For another example, the first gate line contact G-CNT1 can also be set not to contact the first gate line GL1, that is, the first gate line contact G-CNT1 and the first gate line GL1 are separated by the first insulating layer L1, and the contact hole H can only expose the conductive portion 150 or the contact hole H can expose the conductive portion 150 and the first insulating layer L1 at the same time, but the bottom of the contact hole H and the surface of the first gate line GL1 close to the conductive portion 150 are always separated by the first insulating layer L1, which not only enables the first gate line contact G-CNT1 to be coupled to the first gate line GL1, but also minimizes the risk of short circuit between different first gate lines GL1 caused by excessive etching.

[0097] For example, see Figure 7 , the thickness of the conductive portion 150 is no greater than the thickness of the gate conductive layer 131. For example, the thickness of the conductive portion 150 may be equal to the thickness of the gate conductive layer 131. This configuration does not require thickening of a portion of the gate conductive layer 131, and can form a gate conductive layer 131 with a uniform thickness. Accordingly, the thickness of the conductive material deposited on the sidewalls of the isolation trench Sp is relatively small. When the conductive material on the sidewalls of the isolation trench Sp is subsequently etched back to remove the conductive material, thereby forming mutually uncoupled gate lines GL, residual conductive material can be avoided, thereby reducing the risk of short-circuiting between different first gate lines GL1 and improving device reliability.

[0098] Exemplarily, the first gate line GL1, the conductive portion 150, and the first gate line contact G-CNT1 are made of the same material. Specifically, the first gate line GL1, the conductive portion 150, and the first gate line contact G-CNT1 can all be made of a conductive material, for example, tungsten. In this case, the conductive material can be filled into corresponding positions of the first gate line GL1, the conductive portion 150, and the first gate line contact G-CNT1 through the same process steps, which can simplify the preparation process and help control production costs.

[0099] For example, see Figure 6 and Figure 7 , the gate conductive layer 131 located at the top among the multiple gate conductive layers 131 is constructed as a drain selection gate SGD, and the gate conductive layer 131 includes at least one (for example, one) second gate line GL2, and the second gate line GL2 is used as the string selection line CL1. Specifically, along the Z direction, the second gate line GL2 is located on one side of the first gate line GL1, and the length of any first gate line GL1 is greater than the length of the second gate line GL2. The second gate line GL2 is made of a conductive material, including but not limited to a combination of one or more of tungsten, cobalt, copper, aluminum, silicide, etc. Along the extension direction of the multiple first gate lines GL1 (that is, the third direction, the Y direction), the size of the first gate line GL1 is the length of the first gate line GL1. Similarly, along the extension direction of the second gate line GL2 (that is, the third direction, the Y direction), the size of the second gate line GL2 is the length of the second gate line GL2.

[0100] For example, in a semiconductor device configured in the aforementioned manner, the cross-sectional shape of the entire structure formed by a coupling portion 160 and a conductive portion 150 is T-shaped or L-shaped, with the cross-sectional shape being parallel to the first direction (i.e., the Z direction) and the second direction (i.e., the X direction). Specifically, when the coupling portion 160 is disposed in a through hole penetrating the first insulating layer L1, the cross-sectional shape is T-shaped; when the coupling portion 160 contacts the side surface of the first insulating layer L1, the cross-sectional shape is L-shaped.

[0101] For example, see Figure 6 The semiconductor device further includes at least one (e.g., multiple) second gate line contacts G-CNT2 extending along the Z direction, each second gate line contact G-CNT2 being coupled to a second gate line GL2. The second gate line contacts G-CNT2 are made of a conductive material, including but not limited to one or more of tungsten, cobalt, copper, aluminum, silicide, and the like.

[0102] For example, see Figure 7The semiconductor device further includes at least one (e.g., one) second insulating layer L2. The second insulating layer L2 is located on a side of the second gate line GL2 away from the first gate line GL1 and contacts the second gate line GL2. The second insulating layer L2 is made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, or a combination of one or more of the above materials.

[0103] For example, see Figure 7 , the semiconductor device also includes at least one (e.g., multiple) retention portions 170, each of which is connected to a second gate line GL2. Along the X direction, the retention portion 170 is located on one side of the second insulating layer L2, and the retention portion 170 contacts the side of the second insulating layer L2. The retention portion 170 and the second gate line contact G-CNT2 are respectively located at both ends of the second gate line GL2. Specifically, the retention portion 170 is located at one end of the second gate line GL2 close to the conductive portion 150. That is, the first gate line contact G-CNT1 and the second gate line contact G-CNT2 are respectively arranged on both sides of the stacked structure 130. This arrangement can make the spatial structure of the semiconductor device more concise and reasonable. And along the Z direction, the first gate line GL1 adjacent to the second gate line GL2 is coupled to the conductive portion 150, and there is a gap between the retention portion 170 connected to the second gate line GL2 and the conductive portion 150. Similar to the above, this configuration can ensure that the reserved portion 170 connected to the second gate line GL2 and the conductive portion 150 coupled to the first gate line GL1 are not connected to each other, thereby avoiding short circuits between different gate lines.

[0104] For example, the three-dimensional memory provided by some embodiments of the present disclosure may also be provided with data interfaces such as SATA, M.2, PCI-E, and mSATA to facilitate communication with external electronic devices. Because the three-dimensional memory includes the semiconductor device provided by some embodiments of the present disclosure, it has the same beneficial effects as the semiconductor device.

[0105] In another aspect, some embodiments of the present disclosure provide an electronic device, which can be any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, etc. The electronic device includes the aforementioned three-dimensional memory configured for data storage. Similar to the aforementioned device, the electronic device also exhibits the beneficial effects of semiconductor devices.

[0106] On the other hand, some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, for manufacturing the semiconductor device as described above. Figure 9 , the preparation method comprises:

[0107] S101 , forming an intermediate semiconductor structure on a substrate.

[0108] For example, refer to Figure 10L In (a) and (b), the intermediate semiconductor structure includes: a first stacked structure (ie Figure 10L The molded structure 40 in the figure and the protective layer 460 covering the first stacked structure; wherein, along the X direction, the first stacked structure 40 can be divided into a core storage area (not shown in the figure) and a step area ST, and the first stacked structure 40 includes a plurality of gate line sacrificial portions and a plurality of insulating layers 420 alternately stacked along the first direction, the plurality of gate line sacrificial portions including a first gate line sacrificial portion 430a; the plurality of insulating layers include a first insulating layer L1 located above the first gate line sacrificial portion 430a; in the step area ST, the first stacked structure 40 has a step morphology. The first stacked structure 40 also includes: a conductive portion sacrificial portion 441a and a coupling sacrificial portion 450a located in the step area, the conductive portion sacrificial portion 441a is located above the first gate line sacrificial portion 430a and is separated from the first gate line sacrificial portion 430a by the first insulating layer L1, and the coupling sacrificial portion 450a is connected between the conductive portion sacrificial portion 441a and the first gate line sacrificial portion 430a.

[0109] In some embodiments, this step S101 may include:

[0110] S101a, forming a second stacked structure on the substrate.

[0111] For example, refer to Figure 10D , the second stacked structure (for example Figure 10D The molded structure 40 shown includes multiple gate sacrificial layers 430 and multiple insulating layers 420 alternately stacked along the Z direction. These multiple gate sacrificial layers 430 and multiple insulating layers 420 form a stepped topography in the step region ST. The multiple insulating layers 420 include at least one first insulating layer L1. Similar to the first stacked structure 40, the second stacked structure can be divided into a core storage region (not shown) and a step region ST along the X direction.

[0112] S101b, forming a third stacked structure.

[0113] For example, refer to Figure 10G , a conductive portion sacrificial layer 441 is formed on the upper surface of each first insulating layer L1 and extends along the end surface of the first insulating layer L1 in the step region ST, and a coupling portion sacrificial layer 450 is formed covering the end surface of the first insulating layer L1, so as to obtain a third stacked structure (i.e. Figure 10GModule structure 40 shown). Along the X direction, the third stacked structure can be divided into a core storage area (not shown in the figure) and a step area ST. The coupling portion sacrificial layer 450 is in contact with both the conductive portion sacrificial layer 441 and the gate sacrificial layer 430. Specifically, the coupling portion sacrificial layer 450 may only cover a portion of the end surface of the first insulating layer L1, or may completely cover the end surface of the first insulating layer L1. This disclosure does not impose too many restrictions on this. It is only necessary to limit the coupling portion sacrificial layer 450 to contact with both the conductive portion sacrificial layer 441 and the gate sacrificial layer 430.

[0114] In some embodiments, the preparation process can refer to the following Figures 10E to 10G Description.

[0115] In other embodiments, the photolithography process can be used to form a corresponding mask. Figure 10G The structure shown.

[0116] S101c, forming a protective layer covering the third stacked structure.

[0117] For example, the preparation process can refer to the following Figure 10H Description.

[0118] S101d, dividing the third stacked structure covered with the protective layer to obtain an intermediate semiconductor structure.

[0119] Among them, reference Figure 10L The gate sacrificial layer 430, the conductive part sacrificial layer 441 and the coupling part sacrificial layer 450 located below and in contact with the first insulating layer L1 are respectively divided into multiple first gate line sacrificial parts 430a, multiple conductive part sacrificial parts and multiple coupling sacrificial parts 450a.

[0120] In other embodiments, this step S101 may refer to the following description. Figures 10A to 10L Description.

[0121] In yet other embodiments, as described above, the structure of the semiconductor device may have various variations. For example, in the semiconductor device to be manufactured, the coupling portion may pass through the first insulating layer and connect to the gate line. It is understood that as the structure changes, the manufacturing process may also change accordingly. For example, a patterning process such as photolithography may be used to form a corresponding coupling sacrificial portion of the coupling portion.

[0122] S102 , replacing a plurality of gate line sacrificial portions, conductive portion sacrificial portions, and coupling sacrificial portions with gate material to obtain a plurality of gate lines, conductive portions, and coupling portions.

[0123] The plurality of gate lines include a first gate line obtained by replacing the first gate line sacrificial portion 430 a .

[0124] For example, we can get Figure 10P The specific preparation process can be referred to below Figure 10M to Figure 10P Description.

[0125] It should be noted that one material can be used to fill the gap to obtain multiple gate lines, conductive parts and coupling parts. Alternatively, one material, such as a metal compound, can be first spread on the sidewalls of the gap, and then another material, such as a metal material, can be used to fill the remaining gap.

[0126] S103 , forming a first gate line contact extending along a first direction.

[0127] The first gate line contact and the conductive portion are located on the same side of the first gate line and are connected to the conductive portion. Figure 10R The structure shown.

[0128] Below, to form Figure 6 Taking the semiconductor device shown in FIG. 1 as an example, a method for preparing a semiconductor device is described in detail, wherein, referring to FIG. Figures 10A to 10S The method for forming a semiconductor device may include the following steps S201 to S213.

[0129] S201: forming a molded structure.

[0130] For example, see Figure 10A A plurality of insulating layers 420 and a plurality of gate sacrificial layers 430 may be alternately stacked on a substrate 410 along a first direction (ie, Z direction) to form a mold structure 40 , and the mold structure 40 is distributed in both the core storage region and the step region ST of the semiconductor device.

[0131] Specifically, the insulating layer 420 can be formed of silicon oxide, and the gate sacrificial layer 430 can be formed of a material having an etching selectivity relative to the insulating layer and can be easily removed by a wet etching process. For example, the material of the gate sacrificial layer 430 can be silicon nitride. Multiple gate sacrificial layers and multiple insulating layers 420 can be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, an atomic layer deposition (ALD) process or a sputtering process. The gate sacrificial layer can be removed by a subsequent process to provide space for forming multiple first gate lines and second gate lines. Therefore, the number of gate sacrificial layers 430 and insulating layers 420 can be determined according to the number of first gate lines and second gate lines, and can also be increased as the integration of semiconductor devices increases.

[0132] S202 , etching the portion of the mold structure 40 located in the step region ST to form a step morphology.

[0133] For example, see Figures 10B to 10C , the portion of the mold structure 40 located in the step region ST may be etched by a photolithography process to form a step morphology.

[0134] Specifically, a photoresist pattern LP is formed on the top surface of the mold structure 40 (i.e., the surface of the insulating layer 420 in the mold structure 40 with the largest distance from the substrate 410 along the Z direction). The length of the photoresist pattern LP in the X direction can be reduced to 100 nm by a first photolithography process using a first photomask. Figure 10B w1 indicated in .

[0135] Portions of the gate sacrificial layer 430 and the insulating layer 420 that are closest to the photoresist pattern LP in the Z direction and exposed by the reduced photoresist pattern LP may be removed using the reduced photoresist pattern LP etching mask. Figure 10C The photoresist pattern LP can be further reduced, for example, by w2, through a second photolithography process using a second photomask. Portions of the gate sacrificial layer 430 and the insulating layer 420 exposed by the reduced photoresist pattern LP can also be removed using the reduced photoresist pattern LP etching mask. For example, w1 can be greater than w2, for example, equal to or greater than twice w2.

[0136] See also Figure 10D , can be repeated with reference to Figures 10B to 10C The etching process shown is substantially the same as or similar to the etching process to etch the portion of the mold structure 40 located in the step region ST to form Figure 10D The step morphology shown, after which the photoresist pattern LP may be removed by an ashing process and / or a stripping process.

[0137] For example, see Figure 10D , the insulating layer 420 closest to the substrate 410 along the Z direction may not be etched but retained. Specifically, the insulating layer 420 located on the side of the gate sacrificial layer 430 closest to the substrate 410 along the Z direction, away from the substrate 410, and in contact with the gate sacrificial layer 430 may not be etched but retained.

[0138] S203 , forming an auxiliary sacrificial layer covering the mold structure 40 .

[0139] The auxiliary sacrificial layer 440 may be disposed only on the portion of the mold structure 40 located in the step region ST, or may be disposed on the entire mold structure 40 located in the step region ST and the core storage region, without further limitation. Figure 10E The auxiliary sacrificial layer 440 contacts the mold structure 40 everywhere. Along the Z direction, the thickness of the auxiliary sacrificial layer 440 , which is arranged on the surface of the insulating layer 420 away from the gate sacrificial layer 430 , is not greater than the thickness of the gate sacrificial layer 430 .

[0140] For example, the auxiliary sacrificial layer 440 may be formed of a material having an etching selectivity relative to the insulating layer 420 and easily removed by a wet etching process. For example, the material of the auxiliary sacrificial layer 440 may be silicon nitride. The auxiliary sacrificial layer 440 may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, an atomic layer deposition (ALD) process, or a sputtering process.

[0141] S204 , patterning the auxiliary sacrificial layer 440 to form a conductive sacrificial layer on the mold structure 40 .

[0142] Specifically, the auxiliary sacrificial layer 440 may be patterned to form the conductive portion sacrificial layer 441 by etching, for example, dry etching such as deep reactive ion etching (RIDE) or wet etching (such as using phosphoric acid as an etchant).

[0143] See also Figure 10F Among the multiple conductive sacrificial layers 441 formed after the auxiliary sacrificial layer 440 is patterned, any conductive sacrificial layer 441 only contacts the surface of the insulating layer 420 away from the gate sacrificial layer 430, and a gap exists between two adjacent conductive sacrificial layers 441 along the X direction.

[0144] S205 , performing surface treatment on the end surface of the first insulating layer L1 to form a coupling portion sacrificial layer.

[0145] For example, see Figure 10G After forming the conductive sacrificial layer 441 on the mold structure 40, the surface of the insulating layer 420 near the conductive sacrificial layer 441 (i.e., the surface of the insulating layer 420 exposed after the auxiliary sacrificial layer 440 is patterned) can be treated by ion implantation or plasma surface treatment to form at least one (e.g., multiple) coupling sacrificial layers 450. The coupling sacrificial layers 450 cover at least a portion (e.g., completely cover) of the cross section of the first insulating layer L1. The coupling sacrificial layers 450 are in contact with both the conductive sacrificial layer 441 and the gate sacrificial layer 430. The formed coupling sacrificial layers 450 have a higher etching selectivity than other untreated portions of the insulating layer 420 and are more easily removed by a wet etching process.

[0146] S206 , forming a protection layer covering the mold structure 40 .

[0147] For details, see Figure 10HThe protection layer 460 is in contact with the mold structure 40 everywhere. The protection layer 460 can be formed by using silicon oxide such as TEOS, PEOX, siloxane, silsesquioxane, etc. through a CVD process, a spin coating process, etc.

[0148] After forming the protective layer 460, optionally, the third stacked structure ( Figure 10G The upper surface of the molded structure 40 is planarized to remove the uppermost conductive sacrificial layer 441. For example, a process such as chemical mechanical polishing (CMP) can be used to planarize the protective layer 460. This helps ensure the consistency of the contact holes formed by etching during the subsequent formation of contact holes, and avoids large variations in the depth of the contact holes.

[0149] For example, see Figure 10I , the conductive sacrificial layer 441 farthest from the substrate 410 along the Z direction can be removed first, and then the protective layer 460 can be planarized, so that the protective layer 460 is far away from the surface of the molded structure 40 and is flush with the surface of the insulating layer 420 farthest from the substrate 410 along the Z direction and away from the gate sacrificial layer 430.

[0150] S207 , forming a channel structure in the core storage area.

[0151] For example, see Figure 10J First, at least one (e.g., multiple) channel holes CH extending along the Z direction and penetrating the mold structure 40 and the protective layer 460 are formed in the core storage region CT. Specifically, a hard mask (not shown) can be formed on the side of the mold structure 40 away from the substrate 410. A dry etching process, for example, is performed through the hard mask to form the multiple channel holes CH. The hard mask can be formed of a silicon-based or carbon-based spin-on hard mask (SOH) material and / or a photoresist material. After the channel holes CH are formed, the hard mask can be removed by an ashing process and / or a stripping process. The multiple channel holes CH are arranged in an array in the core storage region CT.

[0152] For example, after forming the channel hole CH, see Figure 10K , a channel structure 470 extending along the Z direction may be formed in each channel hole CH.

[0153] Specifically, the channel structure 470 includes a dielectric layer structure 471 and a channel 472. For example, the dielectric layer can be formed on the sidewalls of the channel hole CH and the surface of the protective layer 460 away from the substrate 410. The portion of the dielectric layer formed on the surface of the protective layer 460 away from the substrate 410 can be removed by an etch-back process to form a dielectric layer structure 471 on the sidewalls of the channel hole CH. The shape of the dielectric layer structure 471 can be tubular. The dielectric layer can be formed by sequentially forming a blocking layer, a charge storage layer, and a tunnel insulating layer. For example, the dielectric layer can be formed as a layered structure of oxide-nitride-oxide (ONO).

[0154] The channel layer may be filled within the dielectric layer structure 471. The channel layer may be formed of a semiconductor such as polysilicon or amorphous silicon and may be selectively doped with impurities. The filling layer may be formed of silicon oxide or silicon nitride. The channel layer and the filling layer may be formed by a CVD process, a PECVD process, an ALD process, a PVD process, a sputtering process, or the like.

[0155] For example, after the channel layer is formed, the surface of the channel layer away from the substrate 410 may be planarized until the protection layer 460 is exposed away from the surface of the substrate 410 , so as to form a channel 472 in the channel hole CH.

[0156] For details, see Figure 10K The shape of the channel 472 is a column, and the sidewall of the channel 472 is covered with a dielectric layer structure 471.

[0157] S208 , forming an isolation trench.

[0158] For details, see Figure 10L At least one (e.g., multiple) isolation trenches Sp are formed on the mold structure 40 having the channel structure 470 and the protective layer 460. Each isolation trench Sp extends along the X direction and penetrates the protective layer 460 and the mold structure 40. The number of isolation trenches Sp can be adaptively adjusted according to the circuit design or integration of the semiconductor device. Similar to the aforementioned formation of the channel hole CH, when forming the isolation trench Sp, a hard mask (not shown in the figure) can be first formed on the mold structure 40 having the channel structure 470 and the protective layer 460. A dry etching process, for example, is performed through the hard mask to form multiple isolation trenches Sp. The hard mask can be formed of a silicon-based or carbon-based spin-on hard mask (SOH) material and / or a photoresist material. After the isolation trench Sp is formed, the hard mask can be removed by an ashing process and / or a stripping process.

[0159] For example, after forming the isolation trench Sp, see Figure 10LThe gate sacrificial layer 430 is divided into a plurality of gate line sacrificial portions by the isolation trench Sp, and the plurality of gate line sacrificial portions include at least one (e.g., a plurality) first gate sacrificial portion 430a. The conductive portion sacrificial layer 441 is divided into a plurality of conductive portion sacrificial portions 441a by the isolation trench Sp, and the coupling portion sacrificial layer 450 is divided into a plurality of coupling portion sacrificial portions 450a by the isolation trench Sp. In the subsequent preparation process, the gate sacrificial portion 430a can be replaced with a first gate line, the conductive portion sacrificial portion 441a can be replaced with a conductive portion, and the coupling portion sacrificial portion 450a can be replaced with a coupling portion. Specifically including:

[0160] S209 , removing the first gate line sacrificial portion 430 a , the conductive portion sacrificial portion 441 a , and the coupling portion sacrificial portion 450 a , to form a gate sacrificial gap, a conductive portion sacrificial gap, and a coupling portion sacrificial gap.

[0161] For example, a wet etching process may be used to remove the first gate line sacrificial portion 430a, the conductive portion sacrificial portion 441a, and the coupling sacrificial portion 450a. Furthermore, since the first gate line sacrificial portion 430a and the conductive portion sacrificial portion 441a are both made of silicon nitride, and the coupling sacrificial portion 450a is made of silicon oxide, when wet etching is performed to remove the sacrificial layers, the etchant used to etch the first gate line sacrificial portion 430a and the conductive portion sacrificial portion 441a is different from the etchant used to etch the coupling sacrificial portion 450a. For example, see Figure 10M , the coupling sacrificial portion 450a may be removed by using hydrofluoric acid to form a coupling sacrificial gap 450s, and then Figure 10N Phosphoric acid is used to remove the first gate line sacrificial portion 430 a and the conductive portion sacrificial portion 441 a to form a gate sacrificial gap 430 s and a conductive portion sacrificial gap 441 s.

[0162] S210 , forming an interface layer in the gate sacrificial gap 430s , the conductive portion sacrificial gap 441s , and the coupling portion sacrificial gap 450s .

[0163] For details, see Figure 10O An ALD process or a sputtering process can be used to form an interface layer 480 on the surface of the insulating layer 420 and the surface of the protective layer 460 exposed through the gate sacrificial gap 430s, the conductive portion sacrificial gap 441s, and the coupling portion sacrificial gap 450s. The material of the interface layer 480 may include a metal compound, such as a combination of one or more of titanium nitride, tantalum nitride, and tungsten carbide.

[0164] S211 , forming a first gate line, a conductive portion, and a coupling portion.

[0165] Exemplarily, the first gate line, the conductive portion and the coupling portion are all formed of a conductive material, and the first gate line, the conductive portion and the coupling portion are made of the same material. Optional materials include but are not limited to tungsten, aluminum, copper, titanium, tantalum, etc. or their metal nitrides. For example, see Figure 10P , a conductive material can be filled in the isolation trench Sp and the gate sacrificial gap 430s, the conductive portion sacrificial gap 441s and the coupling portion sacrificial gap 450s where the interface layer 480 is formed by a CVD process, a PECVD process, an ALD process, a PVD process, a sputtering process, etc. After the conductive material is filled, the conductive material set in the isolation trench Sp is removed by back etching to form a plurality of mutually insulated gate lines GL, the plurality of gate lines including at least one (for example, multiple) first gate lines GL1 and at least one (for example, one) second gate line GL2. At this time, the plurality of insulating layers 420 include at least one (for example, multiple) first insulating layer L1 and at least one (for example, one) second insulating layer L2. Each first insulating layer L1 is arranged on a side of a first gate line GL1 away from the substrate 410 and is in contact with the first gate line GL1, and each second insulating layer L2 is arranged on a side of a second gate line GL2 away from the substrate 410 and is in contact with the second gate line GL2. See. Figure 10P , while forming the first gate line GL1 and the second gate line GL2, a conductive portion 442 and a coupling portion 451 coupled to each first gate line GL1, and a reserved portion 452 connected to each second gate line GL2 are also formed. Along the X direction, the reserved portion 452 is located on one side of the second insulating layer L2, and the reserved portion 452 is in contact with the side of the second insulating layer L2. Specifically, the reserved portion 452 is located at one end of the second gate line GL2 close to the conductive portion 442. Along the Z direction, the first gate line GL1 adjacent to the second gate line GL2 is coupled to the conductive portion 442, and there is a gap between the reserved portion 452 connected to the second gate line GL2 and the conductive portion 442. It is possible to make the semiconductor device have a more reasonable spatial structure setting under the premise of avoiding the second gate line GL2 and the first gate line GL1 short-circuiting.

[0166] Specifically, the conductive portion 442 is located on the side of the first gate line GL1 away from the substrate 410, and is separated from the first gate line GL1 by the first insulating layer L1. The coupling portion 451 that contacts the side of the first insulating layer L1 close to the conductive portion 442 and the conductive portion 442 and the first gate line GL1 are all connected.

[0167] S212 , forming a first gate line contact.

[0168] For example, see Figure 10QFirst, at least one (e.g., multiple) contact holes H extending along the Z direction are formed in the step region ST. The contact holes H penetrate the protective layer 460 and expose at least a portion of the conductive portion 442. Specifically, the multiple contact holes H can be formed using an etching process such as wet etching.

[0169] After forming a plurality of contact holes H, see Figure 10R , a conductive material can be filled in each contact hole H through a sputtering process or an ALD process to form at least one (for example, multiple) first gate line contacts G-CNT1 extending along the Z direction, and each first gate line contact G-CNT1 is coupled to a first gate line GL1. At the same time, the mutually coupled first gate line contacts G-CNT1 and the first gate line GL1 do not contact each other, and a first insulating layer L1 is separated therebetween, thereby minimizing the risk of short-circuiting between different first gate lines GL1 caused by excessive etching.

[0170] When a semiconductor device with this setting is coupled with a peripheral circuit, it is only necessary to set the first gate line contact G-CNT1 to be connected to the conductive part 442. The corresponding contact hole used to form the first gate line contact G-CNT1 only needs to expose the surface of the conductive part 442 without exposing the first gate line GL1, so as to form the first gate line contact G-CNT1 that can couple the coupled semiconductor device with the peripheral circuit. The depth of etching required for the contact hole is reduced, the difficulty of the etching process is reduced, and the uniformity of etching is improved, thereby avoiding the problem of short circuit of different gate lines caused by excessive etching.

[0171] As previously mentioned, since the thickness of the portion of the auxiliary sacrificial layer 440 disposed on the surface of the insulating layer 420 away from the gate sacrificial layer 430 along the Z direction is not greater than the thickness of the gate sacrificial layer 430, for the conductive portion 442 and the first gate line GL1 coupled to each other formed by subsequent processes, the thickness of the conductive portion 442 along the Z direction is not greater than the thickness of the first gate line GL1. This arrangement can reduce the risk of short circuits between different first gate lines GL1 without requiring local thickening of the first gate line GL1. At the same time, it can avoid the problem that when the gate line is locally thickened, the thickened gate line portion cannot be completely etched back during etching to form the isolation trench Sp, thereby leaving a sharp corner, and further, due to the existence of the sharp corner, the two adjacent gate conductive layers along the Z direction are short-circuited to each other.

[0172] Exemplarily, the aforementioned method for preparing the semiconductor device further includes forming at least one (e.g., a plurality) second gate line contacts coupled along the Z direction, each second gate line contact being coupled to a second gate line GL2. The method for preparing the second gate line contact is the same as that for the first gate line contact G-CNT and will not be described in detail herein. The second gate line contact is disposed on a side of the second gate line GL2 away from the conductive portion 442, and this arrangement can also optimize the spatial structure of the semiconductor device.

[0173] S213, removing the substrate.

[0174] For example, see Figure 10S The substrate 410 may be removed by chemical mechanical planarization and etching processes to ultimately obtain the semiconductor device 400. Specifically, most of the substrate 410 may be removed by rough grinding, and then the remaining substrate 410 may be removed by chemical mechanical fine grinding.

[0175] The materials and shapes of the layers prepared by the above-mentioned preparation method, as well as the positional relationships therebetween, can all refer to the above-mentioned embodiments of the semiconductor device, and can produce the same technical effects, which will not be described in detail here.

[0176] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A stacked structure having a step region, the stacked structure comprising a plurality of gate lines and a plurality of insulating layers alternately stacked along a first direction, the plurality of gate lines including a first gate line; the plurality of insulating layers including a first insulating layer, the first insulating layer being located on one side of the first gate line along the first direction and in contact with the first gate line; a conductive portion, located on one side of the first gate line along the first direction in the step region and separated from the first gate line by the first insulating layer; a coupling portion configured to couple the conductive portion and the first gate line; A first gate line contact extending along the first direction is located on the same side of the first gate line as the conductive portion and is connected to the conductive portion.

2. The semiconductor device according to claim 1, wherein Along an extending direction of the first gate line, the coupling portion is located on one side of the first insulating layer, and the coupling portion contacts a side surface of the first insulating layer.

3. The semiconductor device according to claim 1, wherein The coupling portion is away from the side surface of the first insulating layer and is flush with the end surface of the first gate line.

4. The semiconductor device according to any one of claims 1 to 3, wherein The end surface of the first gate line is flush with the side surface of the conductive portion.

5. The semiconductor device according to claim 1, wherein The conductive portion contacts a surface of the first insulating layer away from the first gate line. The semiconductor device according to claim 1 , wherein: The thickness of the conductive portion is no greater than the thickness of the gate conductive layer.

7. The semiconductor device according to claim 1, wherein The gate line contact does not contact the first gate line.

8. The semiconductor device according to claim 1, wherein The orthographic projection of the gate line contact on the first gate line is included in the orthographic projection of the conductive portion on the first gate line.

9. The semiconductor device according to claim 1, wherein The plurality of gate lines include a plurality of first gate lines arranged along the first direction, two adjacent first gate lines in the plurality of first gate lines are a lower gate line and an upper gate line, and the length of the lower gate line is greater than the length of the upper gate line; There is a gap between the conductive portion coupled to the lower gate line and the end surface of the upper gate line.

10. The semiconductor device according to claim 1, wherein The first gate line, the conductive portion, and the coupling portion are made of the same material.

11. The semiconductor device according to claim 1, wherein The plurality of gate lines further include a second gate line located on one side of the first gate line along the first direction, and the length of the first gate line is greater than the length of the second gate line; The semiconductor device further includes: A second gate line contact extending along the first direction is connected to the second gate line.

12. The semiconductor device according to claim 11, wherein The plurality of insulating layers further includes a second insulating layer, the second insulating layer being located on a side of the second gate line away from the first gate line and in contact with the second gate line; The semiconductor device further includes a reserved portion, which is located on one side of the second insulating layer along the extension direction of the second gate line and contacts a side surface of the second insulating layer; and the reserved portion is connected to the second gate line.

13. The semiconductor device according to claim 12, wherein: Along the first direction, a first gate line adjacent to the second gate line is coupled to a conductive portion, and a gap exists between the conductive portion and the reserved portion.

14. The semiconductor device according to claim 12, wherein: The reserved portion and the second gate line contact are respectively located at two ends of the second gate line; The reserved portion is located on a side of the second gate line close to the conductive portion.

15. The semiconductor device according to claim 1, wherein A through hole is provided on the first insulating layer, and the coupling portion is provided in the through hole.

16. The semiconductor device according to claim 1, wherein The cross-section of the whole formed by the coupling portion and the conductive portion is T-shaped or L-shaped; The cross section is parallel to the first direction and a second direction, and the second direction is an extending direction of the first gate line.

17. A three-dimensional memory, characterized in that: The semiconductor device according to any one of claims 1 to 16, further comprising: A peripheral circuit coupled to the semiconductor device.

18. An electronic device, characterized in that: include: The three-dimensional memory according to claim 17.

19. A method for preparing a semiconductor device, for preparing the semiconductor device according to any one of claims 1 to 16, characterized in that: The preparation method comprises: An intermediate semiconductor structure is formed on a substrate, the intermediate semiconductor structure comprising: a first stacked structure having a step region and a protective layer covering the first stacked structure; wherein the first stacked structure comprises a plurality of gate line sacrificial portions and a plurality of insulating layers alternately stacked along a first direction, the plurality of gate line sacrificial portions including a first gate line sacrificial portion; the plurality of insulating layers including a first insulating layer located above the first gate line sacrificial portion; the first stacked structure further comprises: a conductive portion sacrificial portion and a coupling sacrificial portion located in the step region, the conductive portion sacrificial portion being located above the first gate line sacrificial portion and separated from the first gate line sacrificial portion by the first insulating layer, and the coupling sacrificial portion being connected between the conductive portion sacrificial portion and the first gate line sacrificial portion; Replacing the plurality of gate line sacrificial portions, the conductive portion sacrificial portions, and the coupling sacrificial portions with gate material to obtain a plurality of gate lines, conductive portions, and coupling portions, wherein the plurality of gate lines includes a first gate line obtained by replacing the first gate line sacrificial portions; A first gate line contact extending along the first direction is formed, wherein the first gate line contact and the conductive portion are located on the same side of the first gate line and are connected to the conductive portion.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The forming of the intermediate semiconductor structure on the substrate comprises: forming a second stacked structure on the substrate, the second stacked structure comprising: a plurality of gate sacrificial layers and a plurality of insulating layers alternately stacked along a first direction, the plurality of gate sacrificial layers and the plurality of insulating layers forming a stepped morphology in the step region; the plurality of insulating layers comprising: at least one first insulating layer; forming, in the step region, a conductive portion sacrificial layer located on the upper surface of each first insulating layer and extending along an end surface of the first insulating layer, and a coupling portion sacrificial layer covering the end surface of the first insulating layer, to obtain a third stacked structure, wherein the conductive portion sacrificial layer and the coupling portion sacrificial layer are in contact with each other; forming a protective layer covering the third stacked structure; The third stacked structure covered with the protective layer is divided to obtain the intermediate semiconductor structure, wherein the gate sacrificial layer, the conductive part sacrificial layer and the coupling part sacrificial layer located below the first insulating layer and in contact with the first insulating layer are respectively divided into multiple first gate line sacrificial parts, multiple conductive part sacrificial parts and multiple coupling sacrificial parts.

21. The method for manufacturing a semiconductor device according to claim 20, wherein: In the step region, forming a coupling portion sacrificial layer covering an end surface of the first insulating layer includes: The end surface of the first insulating layer is subjected to surface treatment to form a coupling portion sacrificial layer covering the end surface of the first insulating layer.

22. The method for preparing a semiconductor device according to claim 20, wherein: The forming of the intermediate semiconductor structure on the substrate further comprises: Before dividing the third stacked structure covered with the protection layer, the upper surface of the third stacked structure covered with the protection layer is planarized to remove the uppermost conductive sacrificial layer.

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