Fingerprint Recognition Device and Fingerprint Recognition Method

Abstract

Embodiments of the present disclosure disclose a fingerprint recognition device and a fingerprint recognition method. By arranging an acquisition unit and a comparison unit on a substrate, and configuring the storage capacitors of the first column of acquisition units as reference capacitors with fixed capacitance values, and the storage capacitors of the remaining column of acquisition units as acquisition capacitors whose capacitance values change when a finger presses; in this way, the comparison unit can output a first comparison level when the capacitance values of the acquisition capacitors connected electrically are the same as the capacitance value of the reference capacitor, and output a second comparison level when the capacitance value of the acquisition capacitor connected is greater than the capacitance value of the reference capacitor. Thus, the binary value of the fingerprint can be directly output through a hardware circuit, and a binary image of the fingerprint can be directly obtained through the binary value, reducing the power consumption of fingerprint detection.

Description

Technical Field

[0001] The present disclosure relates to the technical field of fingerprint detection, and particularly to a fingerprint recognition device and a fingerprint recognition method. Background Art

[0002] With the rapid development of technology, mobile products with biometric functions have gradually entered people's lives. Since fingerprints are innate, unique, and distinguishable from others in the human body, they are composed of a series of valleys and ridges on the surface of the fingertip skin. The compositional details of these valleys and ridges usually include details such as ridge bifurcations, ridge endings, arches, tent arches, left-handed, right-handed, helical, or double helical, which determine the unique characteristics of fingerprints and have thus received extensive attention. Summary of the Invention

[0003] The fingerprint recognition device and fingerprint recognition method provided by the present disclosure are used to reduce the computational amount of fingerprint detection.

[0004] An embodiment of the present disclosure provides a fingerprint recognition device, including:

[0005] A substrate;

[0006] A plurality of acquisition units, arranged in an array on the substrate; wherein, each acquisition unit includes: a storage capacitor; and the storage capacitors of the first column of acquisition units are configured as reference capacitors with a fixed capacitance value, and the storage capacitors of the remaining columns of acquisition units are configured as acquisition capacitors whose capacitance values change when a finger presses.

[0007] A plurality of comparison units, located on the substrate; wherein, one of the comparison units is electrically connected to the first electrode plate of the storage capacitor in a row of acquisition units; and the comparison unit is configured to: output a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as the capacitance value of the reference capacitor, and output a second comparison level when the capacitance value of the connected acquisition capacitor is greater than the capacitance value of the reference capacitor.

[0008] In some examples, each acquisition unit further includes: a first control circuit and a second control circuit;

[0009] The first control circuit is configured to conduct and disconnect the first reference voltage terminal from the second electrode plate of the storage capacitor in response to a signal at the first control terminal;

[0010] The second control circuit is configured to conduct and disconnect the second reference voltage terminal from the second electrode plate of the storage capacitor in response to a signal at the second control terminal.

[0011] In some examples, the first control circuit includes: a first transistor;

[0012] The gate of the first transistor is electrically connected to the first control terminal, a first pole of the first transistor is electrically connected to the first reference voltage terminal, and a second pole of the first transistor is electrically connected to a second electrode plate of the storage capacitor.

[0013] In some examples, the second control circuit includes: a second transistor;

[0014] The gate of the second transistor is electrically connected to the second control terminal, a first pole of the second transistor is electrically connected to the second reference voltage terminal, and a second pole of the second transistor is electrically connected to the second electrode plate of the storage capacitor.

[0015] In some examples, the fingerprint recognition device further includes:

[0016] Multiple first control lines; wherein, one of the first control lines is electrically connected to the first control terminal corresponding to the first control circuit of a column of the acquisition units;

[0017] Multiple second control lines; wherein, one of the second control lines is electrically connected to the second control terminal corresponding to the second control circuit of a column of the acquisition units;

[0018] Multiple acquisition lines; wherein, the first electrode plates of the storage capacitors in a row of the acquisition units are electrically connected to the corresponding comparison units through one of the acquisition lines.

[0019] In some examples, the comparison unit includes: a comparator and a control switch;

[0020] The control terminal of the control switch is electrically connected to the acquisition control terminal, a first end of the control switch is electrically connected to the reference voltage terminal, and a second end of the control switch is electrically connected to the negative input terminal of the comparator;

[0021] The positive input terminal of the comparator is electrically connected to the reference voltage terminal, and the output terminal of the comparator is configured to output the first comparison level and the second comparison level.

[0022] In some examples, the fingerprint recognition device further includes: a data processing unit;

[0023] The data processing unit is electrically connected to multiple comparison units respectively; the data processing unit is configured to receive the first comparison level and the second comparison level output by the comparison units, generate a binary image according to the received first comparison level and second comparison level, and perform fingerprint recognition according to the generated binary image.

[0024] The embodiments of the present disclosure further provide a fingerprint recognition method for a fingerprint recognition device, including:

[0025] Time-division control is used to output the capacitance value of the acquisition capacitor connected to the same comparison unit, and when the acquisition capacitor outputs the capacitance value, control the reference capacitor connected to the same comparison unit to output the capacitance value; moreover, when the capacitance value of the acquisition capacitor electrically connected to the same comparison unit is the same as that of the reference capacitor, output a first comparison level; when the capacitance value of the acquisition capacitor connected to the same comparison unit is greater than that of the reference capacitor, output a second comparison level;

[0026] Generate a binary image according to the first comparison level and the second comparison level;

[0027] Perform fingerprint recognition according to the generated binary image.

[0028] In some examples, the time-division control is used to output the capacitance value of the acquisition capacitor connected to the same comparison unit, and when the acquisition capacitor outputs the capacitance value, control the reference capacitor connected to the same comparison unit to output the capacitance value; including:

[0029] Divide one frame of acquisition time into multiple acquisition stages; among them, one column of acquisition units with the acquisition capacitor corresponds to one acquisition stage; the acquisition stage includes a first sub-acquisition stage and a second sub-acquisition stage;

[0030] In the first sub-acquisition stage, load a signal with a first level to the acquisition control end of the control switch in each comparison unit, load a signal with a first level to the first control line connected to the first column of acquisition units, load a signal with a second level to the second control line connected to the first column of acquisition units, load a signal with a first level to the first control line electrically connected to the acquisition units corresponding to the acquisition stage, and load a signal with a second level to the second control line electrically connected to the acquisition units corresponding to the acquisition stage;

[0031] In the second sub-acquisition stage, load a signal with a second level to the acquisition control end of the control switch in each comparison unit, load a signal with a second level to the first control line connected to the first column of acquisition units, load a signal with a first level to the second control line connected to the first column of acquisition units, load a signal with a second level to the first control line electrically connected to the acquisition units corresponding to the acquisition stage, and load a signal with a second level to the second control line electrically connected to the acquisition units corresponding to the acquisition stage.

[0032] In some examples, the performing fingerprint recognition according to the generated binary image includes:

[0033] According to the generated binary image, sequentially perform feature extraction and feature comparison, and then determine the information of the valleys and ridges of the fingerprint.

[0034] The beneficial effects of the embodiments of the present disclosure are as follows:

[0035] The fingerprint recognition device and method provided by the present disclosure set an acquisition unit and a comparison unit on a substrate, and configure the storage capacitors of the first column of acquisition units as reference capacitors with fixed capacitance values, and configure the storage capacitors of the remaining column of acquisition units as acquisition capacitors whose capacitance values change when a finger presses; in this way, the comparison unit can output a first comparison level when the capacitance values of the electrically connected acquisition capacitors are the same as the capacitance value of the reference capacitor, and output a second comparison level when the capacitance value of the connected acquisition capacitor is greater than the capacitance value of the reference capacitor. Thus, the binary value of the fingerprint can be directly output through the hardware circuit, and the binary image of the fingerprint can be directly obtained through the binary value, reducing the power consumption of fingerprint detection. Moreover, this can make the fingerprint recognition process more concise, and a large amount of additional programming code is not required to generate a binary image, thereby avoiding situations of overprocessing and insufficient image processing of the image and improving the accuracy of fingerprint detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic structural diagram of the fingerprint recognition device in an embodiment of the present disclosure;

[0037] Figure 2 It is a specific structural schematic diagram of the fingerprint recognition device in an embodiment of the present disclosure;

[0038] Figure 3 It is a flowchart of the fingerprint recognition method in an embodiment of the present disclosure;

[0039] Figure 4 It is a signal timing diagram in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. And, without conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0042] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of this disclosure. Also, the same or similar reference numerals throughout indicate the same or similar elements or elements having the same or similar functions.

[0043] Fingerprint recognition technology is the most commonly used method of identity authentication in modern society, and it has high social value. Capacitive fingerprint recognition technology is one of the more mainstream fingerprint recognition technologies at present. When a finger touches a capacitive fingerprint recognition device, the finger can act as one plate of a capacitor. Since the distances between the valleys and ridges on the finger and the substrate of the storage capacitor in the capacitive fingerprint recognition device are not equal, the capacitance values of the storage capacitors in the capacitive fingerprint recognition device are also different. Generally, when performing fingerprint recognition, first, a grayscale image of the fingerprint is collected through a hardware device such as a capacitive fingerprint recognition device. Then, after processing such as image segmentation and image enhancement of the grayscale image, image binarization processing is performed to obtain a binary image of the fingerprint image. After that, based on the obtained binary image, feature extraction and feature comparison are performed to complete the fingerprint recognition process. However, the processes of image segmentation, image enhancement, etc. of the grayscale image need to be carried out in a software platform, which not only requires a large amount of programming code for operation and verification, but also is extremely prone to situations of over-processing and under-processing of the image, resulting in situations where fingerprints cannot be recognized and fingerprints are misrecognized.

[0044] The fingerprint recognition device provided in an embodiment of this disclosure, as Figure 1 shown, may include:

[0045] A substrate 100;

[0046] A plurality of acquisition units 110, arranged in an array on the substrate 100; wherein, the acquisition unit 110 includes: a storage capacitor; and, the storage capacitors of the first column of acquisition units 110 are configured as reference capacitors having a fixed capacitance value, and the storage capacitors of the remaining columns of acquisition units 110 are configured as acquisition capacitors whose capacitance values change when a finger presses.

[0047] A plurality of comparison units 120 are located on the substrate 100. Among them, one comparison unit 120 is electrically connected to the first electrode plate of the storage capacitor in a row of acquisition units 110. And the comparison unit 120 is configured to output a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as that of the reference capacitor, and output a second comparison level when the capacitance value of the connected acquisition capacitor is greater than that of the reference capacitor.

[0048] The fingerprint recognition device provided by the embodiment of the present disclosure sets an acquisition unit and a comparison unit on the substrate, and configures the storage capacitor of the first column of acquisition units as a reference capacitor with a fixed capacitance value, and configures the storage capacitors of the remaining column of acquisition units as acquisition capacitors whose capacitance values change when a finger presses. In this way, the comparison unit can output a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as that of the reference capacitor, and output a second comparison level when the capacitance value of the connected acquisition capacitor is greater than that of the reference capacitor. Thus, the binary value of the fingerprint can be directly output through the hardware circuit, and the binary image of the fingerprint can be directly obtained through the binary value, reducing the power consumption of fingerprint detection. And, in this way, the process of fingerprint recognition can be made more concise, and a large amount of additional programming code is not required to generate a binary image, thereby avoiding the situations of over-processing and insufficient image processing of the image, and improving the accuracy of fingerprint detection.

[0049] It should be noted that the columns in the embodiments of the present disclosure can be columns in actual applications, and the rows can be rows in actual applications. Or, the columns in the embodiments of the present disclosure can be rows in actual applications, and the rows can be columns in actual applications, which is not limited herein.

[0050] Exemplarily, as Figure 1 shown, the storage capacitors of the first column of acquisition units 110 are configured as reference capacitors with fixed capacitance values. That is, the storage capacitors C11, C21, and C31 are reference capacitors.

[0051] Exemplarily, as Figure 1 shown, except for the first column of acquisition units 110, the storage capacitors of the remaining column of acquisition units 110 are configured as acquisition capacitors whose capacitance values change when a finger presses. That is, the storage capacitors C12, C22, and C32 in the second column are acquisition capacitors, and the storage capacitors C13, C23, and C33 in the third column are acquisition capacitors.

[0052] It should be noted that the capacitance values of each reference capacitor can be the same. Moreover, the capacitance value of the reference capacitor can be determined during the preparation of the fingerprint recognition device, and when a finger touches the fingerprint recognition device, its capacitance value will not change due to the influence of the finger. For example, during the preparation of the fingerprint recognition device, a shielding layer can be provided on the side of the reference capacitor facing the finger to prevent the capacitance value of the reference capacitor from being affected by the finger. Alternatively, other preparation means can also be adopted to ensure that the capacitance value of the reference capacitor remains unchanged under the influence of the finger. It should be noted that the above "same" refers to being the same within the allowable error range.

[0053] It should be noted that when a finger touches the fingerprint recognition device, the capacitance value of the acquisition capacitor can change due to the influence of the finger.

[0054] In the embodiments of the present disclosure, as Figure 1 shown, the fingerprint recognition device further includes: a data processing unit 130; wherein, the data processing unit 130 is electrically connected to a plurality of comparison units 120 respectively; the data processing unit 130 is configured to receive the first comparison level and the second comparison level output by the comparison unit 120, generate a binary image according to the received first comparison level and the second comparison level, and perform fingerprint recognition according to the generated binary image. Exemplarily, according to the generated binary image, feature extraction and feature comparison can be performed in sequence to determine the information of the valleys and ridges of the fingerprint, so as to complete fingerprint recognition.

[0055] In the embodiments of the present disclosure, as Figure 1 shown, the acquisition unit 110 may further include: a first control circuit 111 and a second control circuit 112; wherein, the first control circuit 111 is configured to connect and disconnect the first reference voltage terminal VR1 and the second electrode plate of the storage capacitor in response to the signal of the first control terminal VM1. The second control circuit 112 is configured to connect and disconnect the second reference voltage terminal VR2 and the second electrode plate of the storage capacitor in response to the signal of the second control terminal VM2.

[0056] In the embodiments of the present disclosure, as Figure 2 shown, the first control circuit 111 includes: a first transistor; wherein, the gate of the first transistor is electrically connected to the first control terminal VM1, the first pole of the first transistor is electrically connected to the first reference voltage terminal VR1, and the second pole of the first transistor is electrically connected to the second electrode plate of the storage capacitor.

[0057] In the embodiments of the present disclosure, as Figure 2 shown, the second control circuit 112 includes: a second transistor; wherein, the gate of the second transistor is electrically connected to the second control terminal VM2, the first pole of the second transistor is electrically connected to the second reference voltage terminal VR2, and the second pole of the second transistor is electrically connected to the second electrode plate of the storage capacitor.

[0058] In the embodiments of the present disclosure, in order to reduce the manufacturing process, for example Figure 2 As shown, the first transistor and the second transistor may be N-type transistors. Moreover, the N-type transistor conducts under the action of a high level and cuts off under the action of a low level.

[0059] In the embodiments of the present disclosure, in order to reduce the manufacturing process, the first transistor and the second transistor may also be P-type transistors. Moreover, the P-type transistor cuts off under the action of a high level and conducts under the action of a low level.

[0060] It should be noted that in the embodiments of the present disclosure, the first transistor and the second transistor may be thin film transistors (TFTs, Thin Film Transistors) or metal oxide semiconductor field effect transistors (MOSs, Metal Oxide Semiconductor), which are not limited herein. In a specific implementation, the first pole of these transistors may be the source pole, and the second pole may be the drain pole, or the first pole may be the drain pole and the second pole may be the source pole, which are not specifically distinguished herein.

[0061] In the embodiments of the present disclosure, for example Figure 2 As shown, the comparison unit 120 may include a comparator and a control switch; wherein, the control end of the control switch is electrically connected to the acquisition control end, the first end of the control switch is electrically connected to the reference voltage end VG, and the second end of the control switch is electrically connected to the negative input end of the comparator. The positive input end of the comparator is electrically connected to the reference voltage end VG, and the output end of the comparator is configured to output a first comparison level and a second comparison level.

[0062] Exemplarily, when the voltage at the positive input end of the comparator is equal to the voltage at the negative input end, the comparator outputs "0" as the first comparison level. When the voltage at the negative input end of the comparator is greater than the voltage at the positive input end, the comparator outputs "1" as the second comparison level.

[0063] In the embodiments of the present disclosure, for example Figure 1 And Figure 2 As shown, the fingerprint recognition device may further include a plurality of first control lines; wherein, one first control line is electrically connected to the first control end VM1 corresponding to the first control circuit 111 of one column of the acquisition units 110. Exemplarily, one first control line is electrically connected to the gate of the first transistor of one column of the acquisition units 110.

[0064] In the embodiments of the present disclosure, for example Figure 1 And Figure 2As shown, the fingerprint recognition device may further include: a plurality of second control lines; wherein, one second control line is electrically connected to the second control terminal VM2 corresponding to the second control circuit 112 of one column of the acquisition units 110. Exemplarily, one second control line is electrically connected to the gate of the second transistor of one column of the acquisition units 110.

[0065] In the embodiments of the present disclosure, as Figure 1 With Figure 2 shown, the fingerprint recognition device may further include: a plurality of acquisition lines; wherein, the first electrode plate of the storage capacitor in one row of the acquisition units 110 is electrically connected to the corresponding comparison unit 120 through one acquisition line. Exemplarily, the first electrode plate of the storage capacitor in one row of the acquisition units 110 is electrically connected to the negative input terminal of the comparator in the corresponding comparison unit 120 through one acquisition line.

[0066] Exemplarily, as Figure 2 shown, only the 3×3 array of acquisition units 110 is taken as an example. In practical applications, the number of acquisition units 110 can be determined according to the actual application requirements and is not limited herein.

[0067] Among them, the first row and first column acquisition unit 110 has: a storage capacitor C11, a first transistor MA11, and a second transistor MB11. The first row and second column acquisition unit 110 has: a storage capacitor C21, a first transistor MA21, and a second transistor MB21. The first row and third column acquisition unit 110 has: a storage capacitor C31, a first transistor MA31, and a second transistor MB31.

[0068] The second row and first column acquisition unit 110 has: a storage capacitor C12, a first transistor MA12, and a second transistor MB12. The second row and second column acquisition unit 110 has: a storage capacitor C22, a first transistor MA22, and a second transistor MB22. The second row and third column acquisition unit 110 has: a storage capacitor C32, a first transistor MA32, and a second transistor MB32.

[0069] The third row and first column acquisition unit 110 has: a storage capacitor C13, a first transistor MA13, and a second transistor MB13. The third row and second column acquisition unit 110 has: a storage capacitor C23, a first transistor MA23, and a second transistor MB23. The third row and third column acquisition unit 110 has: a storage capacitor C33, a first transistor MA33, and a second transistor MB33.

[0070] Moreover, the gates of the first transistors MA11, MA21, and MA31 are all electrically connected to the first control line CA-1. The gates of the second transistors MB11, MB21, and MB31 are all electrically connected to the second control line CB-1. The gates of the first transistors MA12, MA22, and MA32 are all electrically connected to the first control line CA-2. The gates of the second transistors MB12, MB22, and MB32 are all electrically connected to the second control line CB-2. The gates of the first transistors MA13, MA23, and MA33 are all electrically connected to the first control line CA-3. The gates of the second transistors MB13, MB23, and MB33 are all electrically connected to the second control line CB-3.

[0071] Moreover, the first electrode plates of the storage capacitors C11, C12, and C13 are electrically connected to the inverting input terminal of the comparator VC1 through the acquisition line CC-1. The first electrode plates of the storage capacitors C21, C22, and C23 are electrically connected to the inverting input terminal of the comparator VC2 through the acquisition line CC-2. The first electrode plates of the storage capacitors C31, C32, and C33 are electrically connected to the inverting input terminal of the comparator VC3 through the acquisition line CC-3.

[0072] Moreover, the inverting input terminal of the comparator VC1 is electrically connected to the reference voltage terminal VG through the control switch K1, and the control terminal of the control switch K1 is electrically connected to the acquisition control terminal VS1. The inverting input terminal of the comparator VC2 is electrically connected to the reference voltage terminal VG through the control switch K2, and the control terminal of the control switch K2 is electrically connected to the acquisition control terminal VS2. The inverting input terminal of the comparator VC3 is electrically connected to the reference voltage terminal VG through the control switch K3, and the control terminal of the control switch K3 is electrically connected to the acquisition control terminal VS3. Exemplarily, the acquisition control terminals VS1, VS2, and VS3 can be independent signal terminals. Alternatively, the acquisition control terminals VS1, VS2, and VS3 can be the same signal terminal, which is not limited herein.

[0073] Exemplarily, the voltage vr1 of the first reference voltage terminal VR1 can be a fixed voltage. For example, the voltage vr2 of the second reference voltage terminal VR2 can be a ground voltage of 0V. Of course, in practical applications, the voltage vr1 of the first reference voltage terminal VR1 can be determined according to the requirements of practical applications, which is not limited herein.

[0074] Exemplarily, the voltage vr2 of the second reference voltage terminal VR2 may be a fixed voltage, for example, the voltage vr2 of the second reference voltage terminal VR2 may be a ground voltage of 0 V. Of course, in practical applications, the voltage vr2 of the second reference voltage terminal VR2 may be determined according to the requirements of the practical application and is not limited here.

[0075] Exemplarily, the voltage vcom of the reference voltage terminal VG may be a fixed voltage. Of course, in practical applications, the voltage vg of the reference voltage terminal VG may be determined according to the requirements of the practical application and is not limited here.

[0076] The present disclosure also provides a fingerprint recognition method for a fingerprint recognition device, such as Figure 3 As shown, the following steps may be included:

[0077] S01, time-sharingly controlling the output capacitance value of the collection capacitor connected to the same comparison unit, and when the collection capacitor outputs the capacitance value, controlling the output capacitance value of the reference capacitor connected to the same comparison unit; and outputting a first comparison level when the capacitance value of the collection capacitor electrically connected to the same comparison unit is the same as the capacitance value of the reference capacitor; and outputting a second comparison level when the capacitance value of the collection capacitor connected to the same comparison unit is greater than the capacitance value of the reference capacitor;

[0078] S02, generating a binary image according to the first comparison level and the second comparison level;

[0079] S03. Perform fingerprint recognition based on the generated binary image.

[0080] In the disclosed embodiment, fingerprint recognition based on the generated binary image may include: extracting features and comparing features in sequence based on the generated binary image to determine information about valleys and ridges of the fingerprint.

[0081] In the embodiment of the present disclosure, the output capacitance value of the collection capacitor connected to the same comparison unit 120 is controlled in time-sharing manner, and when the collection capacitor outputs the capacitance value, the output capacitance value of the reference capacitor connected to the same comparison unit 120 is controlled; including:

[0082] A frame acquisition time is divided into a plurality of acquisition phases; wherein a column of acquisition units 110 having acquisition capacitors corresponds to one acquisition phase; and an acquisition phase includes a first sub-acquisition phase and a second sub-acquisition phase;

[0083] In the first sub - acquisition stage, a signal of the first level is loaded to the acquisition control terminal of the control switch in each comparison unit 120, a signal of the first level is loaded to the first control line connected to the first - column acquisition unit 110, a signal of the second level is loaded to the second control line connected to the first - column acquisition unit 110, a signal of the first level is loaded to the first control line electrically connected to the acquisition unit 110 corresponding to the acquisition stage, and a signal of the second level is loaded to the second control line electrically connected to the acquisition unit 110 corresponding to the acquisition stage;

[0084] In the second sub - acquisition stage, a signal of the second level is loaded to the acquisition control terminal of the control switch in each comparison unit 120, a signal of the second level is loaded to the first control line connected to the first - column acquisition unit 110, a signal of the first level is loaded to the second control line connected to the first - column acquisition unit 110, a signal of the second level is loaded to the first control line electrically connected to the acquisition unit 110 corresponding to the acquisition stage, and a signal of the second level is loaded to the second control line electrically connected to the acquisition unit 110 corresponding to the acquisition stage.

[0085] In the embodiments of the present disclosure, the first level may be a high level, and the second level may be a low level. Or, the first level may also be a low level, and the second level is a high level, which is not limited herein.

[0086] Next, taking Figure 2 the structure of the fingerprint recognition device shown and vr2 = 0V as an example, combined with Figure 4 the signal timing diagram shown, the working process of the fingerprint recognition device provided in the embodiments of the present disclosure will be described. It should be noted that this embodiment is for better explaining the present disclosure, but does not limit the present disclosure.

[0087] As Figure 4 shown, one - frame acquisition time F0 is divided into two acquisition stages T10 and T20. Among them, the acquisition stage T10 may include: the first sub - acquisition stage T11 and the second sub - acquisition stage T12. The acquisition stage T20 may include: the first sub - acquisition stage T21 and the second sub - acquisition stage T22. And, the acquisition stage T10 corresponds to the second - column acquisition unit 110, and the acquisition stage T20 corresponds to the third - column acquisition unit 110.

[0088] And, vs1 represents the signal loaded to the acquisition control terminal VS1, vs2 represents the signal loaded to the acquisition control terminal VS2, and vs3 represents the signal loaded to the acquisition control terminal VS3. ca - 1 represents the signal transmitted on the first control line CA - 1, ca - 2 represents the signal transmitted on the first control line CA - 2, and ca - 3 represents the signal transmitted on the first control line CA - 3. cb - 1 represents the signal transmitted on the second control line CB - 1, cb - 2 represents the signal transmitted on the second control line CB - 2, and cb - 3 represents the signal transmitted on the second control line CB - 3.

[0089] In the first sub-acquisition stage T11, when vs1 controls the control switch K1 to close, the voltage on the acquisition line CC-1 is the voltage vcom of the reference voltage terminal VG. The signal cb-1 can control the second transistor MB11 to cut off. The signal ca-1 can control the first transistor MA11 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C11. And, the signal ca-2 can control the first transistor MA12 to cut off. The signal cb-2 can control the second transistor MB12 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C12. Also, the signal ca-3 can control the first transistor MA13 to cut off. The signal cb-3 can control the second transistor MB13 to cut off. Therefore, the electric charge amount Q1-1 on the acquisition line CC-1 satisfies the formula: Q1-1 = c11 * (vcom - vr1) + c12 * vcom. Wherein, c11 represents the capacitance value of the storage capacitor C11, and c12 represents the capacitance value of the storage capacitor C12.

[0090] Also, when vs2 controls the control switch K2 to close, the voltage on the acquisition line CC-2 is the voltage vcom of the reference voltage terminal VG. The signal cb-1 can control the second transistor MB21 to cut off. The signal ca-1 can control the first transistor MA21 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C21. And, the signal ca-2 can control the first transistor MA22 to cut off. The signal cb-2 can control the second transistor MB22 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C22. Also, the signal ca-3 can control the first transistor MA23 to cut off. The signal cb-3 can control the second transistor MB23 to cut off. Therefore, the electric charge amount Q1-2 on the acquisition line CC-2 satisfies the formula: Q1-2 = c21 * (vcom - vr1) + c22 * vcom. Wherein, c21 represents the capacitance value of the storage capacitor C21, and c22 represents the capacitance value of the storage capacitor C22.

[0091] Moreover, when vs3 controls the control switch K3 to close, the voltage on the acquisition line CC-3 is the voltage vcom of the reference voltage terminal VG. The signal cb-1 can control the second transistor MB31 to turn off. The signal ca-1 can control the first transistor MA31 to turn on, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C31. And the signal ca-2 can control the first transistor MA32 to turn off. The signal cb-2 can control the second transistor MB32 to turn on, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C32. Moreover, the signal ca-3 can control the first transistor MA33 to turn off. The signal cb-3 can control the second transistor MB33 to turn off. Therefore, the electric charge amount Q1-3 on the acquisition line CC-3 satisfies the formula: Q1-3 = c31*(vcom - vr1) + c32*vcom. Wherein, c31 represents the capacitance value of the storage capacitor C31, and c32 represents the capacitance value of the storage capacitor C32.

[0092] In the second sub-acquisition stage T12, when vs1 controls the control switch K1 to open, the acquisition line CC-1 is disconnected from the reference voltage terminal VG. The signal ca-1 can control the first transistor MA11 to turn off. The signal cb-1 can control the second transistor MB11 to turn on, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C11. And the signal cb-2 can control the second transistor MB12 to turn off. The signal ca-2 can control the first transistor MA12 to turn on, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C12. Moreover, the signal ca-3 can control the first transistor MA13 to turn off. The signal cb-3 can control the second transistor MB13 to turn off. Therefore, the electric charge amount Q2-1 on the acquisition line CC-1 satisfies the formula: Q2-1 = c12*(v1 - vr1) + c11*v1. Wherein, c11 represents the capacitance value of the storage capacitor C11, c12 represents the capacitance value of the storage capacitor C12, and v1 represents the voltage on the acquisition line CC-1. According to the principle of charge conservation, the electric charge amount on the acquisition line CC-1 does not change during the first sub-acquisition stage T11 and the second sub-acquisition stage T12. Therefore, Q2-1 = Q1-1. Then v1 satisfies the formula: Therefore, the voltage difference v1 - vcom across the comparator VC1 is If c12 = c11, the comparator VC1 outputs "0" as the first comparison level. If c12 > c11, the comparator VC1 outputs "1" as the second comparison level.

[0093] Moreover, when vs2 controls the control switch K2 to disconnect, the acquisition line CC-2 is disconnected from the reference voltage terminal VG. The signal ca-1 can control the first transistor MA21 to cut off. The signal cb-1 can control the second transistor MB21 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C21. And, the signal cb-2 can control the second transistor MB22 to cut off. The signal ca-2 can control the first transistor MA22 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C22. Also, the signal ca-3 can control the first transistor MA23 to cut off. The signal cb-3 can control the second transistor MB23 to cut off. Therefore, the electric charge amount Q2-2 on the acquisition line CC-2 satisfies the formula: Q2-2 = c22*(v2 - vr1) + c21*v2. Wherein, c21 represents the capacitance value of the storage capacitor C21, c22 represents the capacitance value of the storage capacitor C22, and v2 represents the voltage on the acquisition line CC-2. According to the principle of conservation of charge, the electric charge amount on the acquisition line CC-2 does not change during the first sub-acquisition stage T11 and the second sub-acquisition stage T12. Therefore, Q2-2 = Q1-2. Then v2 satisfies the formula: Therefore, the voltage difference v2 - vcom across the comparator VC2 is If c22 = c21, the comparator VC2 outputs "0" as the first comparison level. If c22 > c21, the comparator VC2 outputs "1" as the second comparison level.

[0094] Also, when vs3 controls the control switch K3 to disconnect, the acquisition line CC-3 is disconnected from the reference voltage terminal VG. The signal ca-1 can control the first transistor MA31 to cut off. The signal cb-1 can control the second transistor MB31 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C31. And, the signal cb-2 can control the second transistor MB32 to cut off. The signal ca-2 can control the first transistor MA32 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C32. Also, the signal ca-3 can control the first transistor MA33 to cut off. The signal cb-3 can control the second transistor MB33 to cut off. Therefore, the electric charge amount Q3-2 on the acquisition line CC-3 satisfies the formula: Q3-2 = c32*(v3 - vr1) + c31*v3. Wherein, c31 represents the capacitance value of the storage capacitor C31, c32 represents the capacitance value of the storage capacitor C32, and v3 represents the voltage on the acquisition line CC-3. According to the principle of conservation of charge, the electric charge amount on the acquisition line CC-3 does not change during the first sub-acquisition stage T11 and the second sub-acquisition stage T12. Therefore, Q2-3 = Q1-3. Then v3 satisfies the formula: Therefore, the voltage difference v3 - vcom across the comparator VC3 is If c32 = c31, the comparator VC3 outputs "0" as the first comparison level. If c32 > c31, the comparator VC3 outputs "1" as the second comparison level.

[0095] In the first sub - acquisition phase T21, when vs1 controls the control switch K1 to close, the voltage on the acquisition line CC - 1 is the voltage vcom of the reference voltage terminal VG. The signal cb - 1 can control the second transistor MB11 to cut off. The signal ca - 1 can control the first transistor MA11 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C11. And the signal ca - 2 can control the first transistor MA12 to cut off. The signal cb - 2 can control the second transistor MB12 to cut off. Also, the signal ca - 3 can control the first transistor MA13 to cut off. The signal cb - 3 can control the second transistor MB13 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C13. Therefore, the electric charge amount Q1 - 1' on the acquisition line CC - 1 satisfies the formula: Q1 - 1' = c11*(vcom - vr1)+c13*vcom. Where c13 represents the capacitance value of the storage capacitor C13.

[0096] And when vs2 controls the control switch K2 to close, the voltage on the acquisition line CC - 2 is the voltage vcom of the reference voltage terminal VG. The signal cb - 1 can control the second transistor MB21 to cut off. The signal ca - 1 can control the first transistor MA21 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C21. And the signal ca - 2 can control the first transistor MA22 to cut off. The signal cb - 2 can control the second transistor MB22 to cut off. Also, the signal ca - 3 can control the first transistor MA23 to cut off. The signal cb - 3 can control the second transistor MB23 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C23. Therefore, the electric charge amount Q2 - 1' on the acquisition line CC - 2 satisfies the formula: Q2 - 1' = c11*(vcom - vr1)+c23*vcom. Where c23 represents the capacitance value of the storage capacitor C13.

[0097] Also, when vs3 controls the control switch K3 to close, the voltage on the acquisition line CC-3 is the voltage vcom of the reference voltage terminal VG. The signal cb-1 can control the second transistor MB31 to cut off. The signal ca-1 can control the first transistor MA31 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C31. And, the signal ca-2 can control the first transistor MA32 to cut off. The signal cb-2 can control the second transistor MB32 to cut off. Also, the signal ca-3 can control the first transistor MA33 to cut off. The signal cb-3 can control the second transistor MB33 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C33. Therefore, the electric charge amount Q3-1' on the acquisition line CC-3 satisfies the formula: Q3-1' = c11*(vcom - vr1) + c33*vcom. Wherein, c33 represents the capacitance value of the storage capacitor C33.

[0098] In the second sub-acquisition stage T22, when vs1 controls the control switch K1 to open, the acquisition line CC-1 is disconnected from the reference voltage terminal VG. The signal ca-1 can control the first transistor MA11 to cut off. The signal cb-1 can control the second transistor MB11 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C11. And, the signal cb-2 can control the second transistor MB12 to cut off. The signal ca-2 can control the first transistor MA12 to cut off. Also, the signal cb-3 can control the second transistor MB13 to cut off. The signal ca-3 can control the first transistor MA13 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C13. Therefore, the electric charge amount Q2-1' on the acquisition line CC-1 satisfies the formula: Q2-1' = c13*(v1' - vr1) + c11*v1'. Wherein, c13 represents the capacitance value of the storage capacitor C13, and v1' represents the voltage on the acquisition line CC-1. According to the principle of charge conservation, the electric charge amount on the acquisition line CC-1 does not change during the first sub-acquisition stage T21 and the second sub-acquisition stage T22. Therefore, Q2-1' = Q1-1'. Then v1' satisfies the formula: Therefore, the voltage difference v1' - vcom across the comparator VC1 is If c13 = c11, the comparator VC1 outputs "0" as the first comparison level. If c13 > c11, the comparator VC1 outputs "1" as the second comparison level.

[0099] Moreover, when vs2 controls the control switch K2 to disconnect, the acquisition line CC-2 is disconnected from the reference voltage terminal VG. The signal ca-1 can control the first transistor MA21 to cut off. The signal cb-1 can control the second transistor MB21 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C21. And the signal cb-2 can control the second transistor MB22 to cut off. The signal ca-2 can control the first transistor MA22 to cut off. Also, the signal cb-3 can control the second transistor MB23 to cut off. The signal ca-3 can control the first transistor MA23 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C23. Therefore, the electric charge amount Q2-2’ on the acquisition line CC-2 satisfies the formula: Q2-2’ = c23*(v2’ - vr1) + c21*v2’. Wherein, c23 represents the capacitance value of the storage capacitor C23, and v2’ represents the voltage on the acquisition line CC-2. According to the principle of charge conservation, the electric charge amount on the acquisition line CC-2 does not change during the first sub-acquisition stage T21 and the second sub-acquisition stage T22. Therefore, Q2-2’ = Q1-2’. Then v2’ satisfies the formula: Therefore, the voltage difference v2’ - vcom across the comparator VC2 is If c23 = c21, the comparator VC2 outputs "0" as the first comparison level. If c23 > c21, the comparator VC2 outputs "1" as the second comparison level.

[0100] Also, when vs3 controls the control switch K3 to disconnect, the acquisition line CC-3 is disconnected from the reference voltage terminal VG. The signal ca-1 can control the first transistor MA31 to cut off. The signal cb-1 can control the second transistor MB31 to conduct, so as to supply the 0V voltage of the second reference voltage terminal VR2 to the second electrode plate of the storage capacitor C31. And the signal cb-2 can control the second transistor MB32 to cut off. The signal ca-2 can control the first transistor MA32 to cut off. Also, the signal cb-3 can control the second transistor MB33 to cut off. The signal ca-3 can control the first transistor MA33 to conduct, so as to supply the voltage vr1 of the first reference voltage terminal VR1 to the second electrode plate of the storage capacitor C33. Therefore, the electric charge amount Q3-2’ on the acquisition line CC-3 satisfies the formula: Q3-2’ = c33*(v3’ - vr1) + c31*v3’. Wherein, c33 represents the capacitance value of the storage capacitor C33, and v3’ represents the voltage on the acquisition line CC-3. According to the principle of charge conservation, the electric charge amount on the acquisition line CC-3 does not change during the first sub-acquisition stage T21 and the second sub-acquisition stage T22. Therefore, Q3-2’ = Q3-2’. Then v3’ satisfies the formula: Therefore, the voltage difference v3’ - vcom across the comparator VC3 is If c33 = c31, the comparator VC3 outputs "0" as the first comparison level. If c33 > c31, the comparator VC3 outputs "1" as the second comparison level.

[0101] For example, in the second sub-acquisition stage T12, the output terminal VO1 of the comparator VC1 outputs "0", the output terminal VO2 of the comparator VC2 outputs "1", and the output terminal VO3 of the comparator VC3 outputs "1". The data processing unit 130 can receive the "0" output by the output terminal VO1 of the comparator VC1, the "1" output by the output terminal VO2 of the comparator VC2, and the "1" output by the output terminal VO3 of the comparator VC3.

[0102] Also, in the second sub-acquisition stage T22, the output terminal VO1 of the comparator VC1 outputs "1", the output terminal VO2 of the comparator VC2 outputs "0", and the output terminal VO3 of the comparator VC3 outputs "1". The data processing unit 130 can receive the "1" output by the output terminal VO1 of the comparator VC1, the "0" output by the output terminal VO2 of the comparator VC2, and the "1" output by the output terminal VO3 of the comparator VC3.

[0103] After that, based on the received "0"s and "1"s, the data processing unit 130 can generate a binary image. Thus, based on the generated binary image, feature extraction and feature comparison can be performed in sequence to determine the information of the valleys and ridges of the fingerprint, so as to complete fingerprint recognition.

[0104] In the embodiments of the present disclosure, the fingerprint recognition device can be combined with a display panel so that the display panel can implement fingerprint recognition.

[0105] In the embodiments of the present disclosure, the fingerprint recognition device can also directly perform fingerprint recognition independently. For example, the fingerprint recognition device can be a fingerprint card punching machine, a fingerprint lock, etc.

[0106] The fingerprint recognition device and fingerprint recognition method provided by the present disclosure set an acquisition unit and a comparison unit on a substrate, and configure the storage capacitors of the first column of acquisition units as reference capacitors with a fixed capacitance value, and the storage capacitors of the remaining column of acquisition units are configured as acquisition capacitors whose capacitance values change when a finger presses; in this way, the comparison unit can output a first comparison level when the capacitance value of the connected acquisition capacitor is the same as the capacitance value of the reference capacitor, and output a second comparison level when the capacitance value of the connected acquisition capacitor is greater than the capacitance value of the reference capacitor. Thus, the binary value of the fingerprint can be directly output through the hardware circuit, and the binary image of the fingerprint can be directly obtained through the binary value, reducing the power consumption of fingerprint detection. Moreover, this can make the fingerprint recognition process more concise, and a large amount of additional programming code is not required to generate a binary image, thereby avoiding the situations of over-processing and under-processing of the image and improving the accuracy of fingerprint detection.

[0107] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.

Claims

1. A fingerprint recognition device, characterized in that, Comprising: A substrate; A plurality of acquisition units, arranged in an array on the substrate; wherein, each acquisition unit includes: a storage capacitor; and, the storage capacitors of the first column of acquisition units are configured as reference capacitors with a fixed capacitance value, and the storage capacitors of the remaining columns of acquisition units are configured as acquisition capacitors whose capacitance values change when a finger presses; A plurality of comparison units, located on the substrate; wherein, one of the comparison units is electrically connected to the first electrode plate of the storage capacitor in a row of acquisition units; and, the comparison unit is configured to: sequentially compare the acquisition capacitor with the reference capacitor through time-division control, and output a first comparison level when the capacitance value of the electrically connected acquisition capacitor is the same as the capacitance value of the reference capacitor, and output a second comparison level when the capacitance value of the connected acquisition capacitor is greater than the capacitance value of the reference capacitor.

2. The fingerprint recognition device according to claim 1, characterized in that, The acquisition unit further includes: a first control circuit and a second control circuit; The first control circuit is configured to conduct and disconnect the first reference voltage terminal and the second electrode plate of the storage capacitor in response to a signal at the first control terminal; The second control circuit is configured to conduct and disconnect the second reference voltage terminal and the second electrode plate of the storage capacitor in response to a signal at the second control terminal.

3. The fingerprint recognition device according to claim 2, wherein The first control circuit includes: a first transistor; The gate of the first transistor is electrically connected to the first control terminal, the first pole of the first transistor is electrically connected to the first reference voltage terminal, and the second pole of the first transistor is electrically connected to the second electrode plate of the storage capacitor.

4. The fingerprint recognition device according to claim 2, wherein The second control circuit includes: a second transistor; The gate of the second transistor is electrically connected to the second control terminal, the first pole of the second transistor is electrically connected to the second reference voltage terminal, and the second pole of the second transistor is electrically connected to the second electrode plate of the storage capacitor.

5. The fingerprint recognition device according to claim 2, wherein The fingerprint recognition device further includes: A plurality of first control lines; wherein, one of the first control lines is electrically connected to the first control terminal corresponding to the first control circuit of a column of the acquisition units; A plurality of second control lines; wherein, one of the second control lines is electrically connected to the second control terminal corresponding to the second control circuit of a column of the acquisition units; A plurality of acquisition lines; wherein, the first electrode plates of the storage capacitors in a row of acquisition units are electrically connected to the corresponding comparison units through one of the acquisition lines.

6. The fingerprint recognition device according to any one of claims 1-5, characterized in that, The comparison unit includes; a comparator and a control switch; The control terminal of the control switch is electrically connected to the acquisition control terminal, the first terminal of the control switch is electrically connected to the reference voltage terminal, and the second terminal of the control switch is electrically connected to the negative input terminal of the comparator; The positive input terminal of the comparator is electrically connected to the reference voltage terminal, and the output terminal of the comparator is configured to output the first comparison level and the second comparison level.

7. The fingerprint recognition device according to claim 6, characterized in that, The fingerprint recognition device further includes: a data processing unit; The data processing unit is electrically connected to a plurality of the comparison units respectively; the data processing unit is configured to receive the first comparison level and the second comparison level output by the comparison units, generate a binary image according to the received first comparison level and second comparison level, and perform fingerprint recognition according to the generated binary image.

8. A fingerprint recognition method for a fingerprint recognition device according to any one of claims 1-7, characterized in that, Comprising: Time-division control is used to output the capacitance value of the acquisition capacitor connected to the same comparison unit, and when the acquisition capacitor outputs the capacitance value, control the reference capacitor connected to the same comparison unit to output the capacitance value; Moreover, when the capacitance value of the acquisition capacitor electrically connected to the same comparison unit is the same as the capacitance value of the reference capacitor, a first comparison level is output; When the capacitance value of the acquisition capacitor connected to the same comparison unit is greater than the capacitance value of the reference capacitor, a second comparison level is output; Generate a binary image based on the first comparison level and the second comparison level; Perform fingerprint recognition based on the generated binary image.

9. The fingerprint recognition method of the fingerprint recognition device according to claim 8, characterized in that, The time-division control is used to output the capacitance value of the acquisition capacitor connected to the same comparison unit, and when the acquisition capacitor outputs the capacitance value, control the reference capacitor connected to the same comparison unit to output the capacitance value; It includes: Divide one frame of acquisition time into multiple acquisition stages; among them, a column of acquisition units with the acquisition capacitor corresponds to one acquisition stage; the acquisition stage includes a first sub-acquisition stage and a second sub-acquisition stage; In the first sub-acquisition stage, a signal with a first level is loaded on the acquisition control terminal of the control switch in each comparison unit, a signal with a first level is loaded on the first control line connected to the first column of acquisition units, a signal with a second level is loaded on the second control line connected to the first column of acquisition units, a signal with a first level is loaded on the first control line electrically connected to the acquisition units corresponding to the acquisition stage, and a signal with a second level is loaded on the second control line electrically connected to the acquisition units corresponding to the acquisition stage; In the second sub-acquisition stage, a signal with a second level is loaded on the acquisition control terminal of the control switch in each comparison unit, a signal with a second level is loaded on the first control line connected to the first column of acquisition units, a signal with a first level is loaded on the second control line connected to the first column of acquisition units, a signal with a second level is loaded on the first control line electrically connected to the acquisition units corresponding to the acquisition stage, and a signal with a second level is loaded on the second control line electrically connected to the acquisition units corresponding to the acquisition stage.

10. The fingerprint recognition method of the fingerprint recognition device according to claim 8, characterized in that, The performing fingerprint recognition based on the generated binary image includes: According to the generated binary image, perform feature extraction and feature comparison in sequence to determine the information of the valleys and ridges of the fingerprint.

Images