A method for preventing NiSi from being recessed in HK metal gate process

Abstract

The present invention provides a method for preventing NiSi from generating depressions in a HK metal gate process, wherein a substrate is provided with a dense area, a sparse area and an empty area where a pseudo gate is distributed; the pseudo gate includes an amorphous silicon structure and a side wall thereof; a NiSi layer is formed on the substrate; an interlayer dielectric layer covering the pseudo gate is deposited on the substrate, the interlayer dielectric layer consisting of a three-layer structure of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer from bottom to top; the second oxide layer is ground with a selectivity of silicon oxide to silicon nitride greater than 1, and the grinding stops on the silicon nitride layer; the silicon nitride layer and the first silicon oxide layer are etched, and the amorphous silicon structure in the pseudo gate is removed. The method of the present invention can control the final height of the interlayer dielectric layer in each graphic area within a range with little difference, so that the pseudo gate polysilicon will not damage the active area surface of the empty area during the removal process, thereby avoiding the generation of NiSi depression defects.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preventing NiSi from generating depressions in a HK metal gate process. Background Art

[0002] With the development of the times, chips have become a "necessity" in global life. With the advancement of chip technology, people's lives are becoming more and more intelligent, travel is becoming more and more convenient, and the amount of information available every day is increasing. Today, with the increasingly high requirements for integrated circuit design and manufacturing, the characteristic size of MOS tubes is becoming smaller and smaller, and many processes are even constantly squeezing the limits of the process.

[0003] One of the important steps to reduce the feature size is to reduce the line width of the polysilicon gate (metal gate), and then the spacing between the gates also becomes smaller, so as to achieve the goal of reducing the overall size of the device.

[0004] As the requirements for fine processes become higher and higher, the sparse and dense (ISO / Dense) patterns of chip patterns have an increasingly greater impact on the process. For example, in the HKMG process, the gate amorphous silicon (A-Si PO) will first pass through the interlayer dielectric layer (ILD0 CMP) and then the polysilicon dummy gate removal (Dummy poly remove) will be performed. During the chemical mechanical polishing CMP process, if there is a large open area, ILD0 will be ground lower, and in the subsequent polysilicon dummy gate removal process, NiSi may be damaged and produce peeling defects.

[0005] Therefore, a new method needs to be proposed to solve the above problems. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for preventing NiSi from being recessed in HK metal gate process, so as to solve the problem of NiSi defects after grinding due to sparse and dense patterns in the prior art metal gate process.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preventing NiSi from being recessed in a HK metal gate process, the method at least comprising:

[0008] Step 1, providing a substrate, wherein an area on the substrate where a plurality of dummy gates are densely distributed is a dense area, an area where a single dummy gate is distributed is a sparse area, and an area where no dummy gate is distributed is an open area; the dummy gate comprises an amorphous silicon structure and a sidewall attached to a sidewall of the amorphous silicon structure;

[0009] Step 2, forming a NiSi layer on the substrate; the NiSi layer is located on the substrate between the dummy gates in the dense area and the sparse area, and is located on the substrate in the open area;

[0010] Step 3: depositing an interlayer dielectric layer covering the dummy gate on the substrate, wherein the interlayer dielectric layer is composed of a three-layer structure of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer from bottom to top;

[0011] Step 4, grinding the second oxide layer with a selectivity of silicon oxide to silicon nitride greater than 1, and grinding to the upper surface of the silicon nitride layer;

[0012] Step five: etching the silicon nitride layer and the first silicon oxide layer, and removing the amorphous silicon structure in the dummy gate.

[0013] Preferably, the sidewall in step one is silicon nitride.

[0014] Preferably, in step five, the method for etching the silicon nitride layer and the first silicon oxide layer is dry etching.

[0015] Preferably, in step five, etching the silicon nitride layer and the first silicon oxide layer and etching away the amorphous silicon structure in the dummy gate are completed in one process step.

[0016] Preferably, in step five, the silicon nitride layer and the first silicon oxide layer are etched with a selectivity ratio of silicon oxide to silicon nitride equal to 1.

[0017] Preferably, in step five, etching the silicon nitride layer and the first silicon oxide layer and etching away the amorphous silicon structure in the dummy gate are successively completed in two process steps.

[0018] Preferably, in step five, the silicon nitride layer and the first silicon oxide layer are first etched with a selectivity ratio of silicon oxide to silicon nitride equal to 1, and the etching stops at the upper surface of the dummy gate; then, the amorphous silicon structure in the dummy gate is removed.

[0019] As described above, the method for avoiding NiSi depression in the HK metal gate process of the present invention has the following beneficial effects: the method of the present invention can control the final height of the interlayer dielectric layer in each graphic area within a range with little difference, so that the pseudo gate polysilicon will not damage the active area surface of the open area during the removal process, thereby avoiding the generation of NiSi depression defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown is a schematic diagram of a pseudo gate structure located on a substrate in the present invention;

[0021] Figure 2 It is a schematic diagram of the structure after forming an interlayer dielectric layer covering a dummy gate in the present invention;

[0022] Figure 3 It is a schematic diagram of the structure after the second oxide layer is removed by grinding in the present invention;

[0023] Figure 4 It is a schematic diagram of the structure after the silicon nitride layer and the first silicon oxide layer are etched and removed in the present invention;

[0024] Figure 5 It is a schematic diagram of the structure after the amorphous silicon structure in the dummy gate is etched away in the present invention;

[0025] Figure 6 It is a flow chart of a method for preventing NiSi from being recessed in the HK metal gate process of the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0028] The present invention provides a method for preventing NiSi from being recessed in a HK metal gate process, such as Figure 6 Shown Figure 6 The flowchart of the method for preventing NiSi from being recessed in the HK metal gate process of the present invention is shown. The method comprises at least the following steps:

[0029] Step 1, providing a substrate, wherein an area on the substrate where a plurality of dummy gates are densely distributed is a dense area, an area where a single dummy gate is distributed is a sparse area, and an area where no dummy gate is distributed is an open area; the dummy gate includes an amorphous silicon structure and a sidewall attached to the sidewall of the amorphous silicon structure; Figure 1 As shown, Figure 1 The schematic diagram of the pseudo gate structure on the substrate in the present invention is shown. The area where multiple pseudo gates are densely distributed on the substrate 01 in step 1 is a dense area (such as Figure 1The area on the left separated by the dotted line in the figure) is a sparse area (such as Figure 1 The middle area separated by the dotted line in the figure), and the area without pseudo gate distribution is an empty area (such as Figure 1 The dummy gate includes an amorphous silicon structure 04 and a sidewall 03 attached to the sidewall of the amorphous silicon structure 04.

[0030] According to the present invention, the sidewall 03 in step 1 of this embodiment is made of silicon nitride.

[0031] Step 2: forming a NiSi layer on the substrate; the NiSi layer is located on the substrate between the dummy gates in the dense area and the sparse area, and is located on the substrate in the open area; Figure 1 As shown, in step 2, a NiSi layer 02 is formed on the substrate 01; the NiSi layer 02 is located on the substrate 01 between the dummy gates in the dense area and the sparse area, and is located on the substrate in the open area.

[0032] Step 3: depositing an interlayer dielectric layer covering the dummy gate on the substrate, wherein the interlayer dielectric layer is composed of a three-layer structure of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer from bottom to top; Figure 2 As shown, Figure 2 The schematic diagram of the structure after forming the interlayer dielectric layer covering the dummy gate in the present invention is shown. In step 3, an interlayer dielectric layer covering the dummy gate is deposited on the substrate 01, and the interlayer dielectric layer is composed of a three-layer structure of a first silicon oxide layer 05, a silicon nitride layer 06, and a second silicon oxide layer 07 from bottom to top.

[0033] Step 4: grinding the second oxide layer with a selectivity of silicon oxide to silicon nitride greater than 1, and grinding to the upper surface of the silicon nitride layer; Figure 3 As shown, Figure 3 The structure diagram after grinding and removing the second oxide layer in the present invention is shown. In step 4, the second oxide layer 07 is ground with a selectivity of silicon oxide to silicon nitride greater than 1, and the grinding stops at the upper surface of the silicon nitride layer 06. That is, when grinding the second silicon oxide layer in step 4, the grinding rate of silicon oxide is greater than the grinding rate of silicon nitride, so that after grinding the second silicon oxide layer, the top of the silicon nitride layer is exposed. And by Figure 3 It can be seen that part of the second silicon oxide layer on the empty area has not been completely removed by grinding, and in the sparse area and the dense area, the top of the second silicon oxide layer is exposed after grinding.

[0034] Step five: etching the silicon nitride layer and the first silicon oxide layer, and removing the amorphous silicon structure in the dummy gate.

[0035] Furthermore, in the present invention, in step five of this embodiment, the method of etching the silicon nitride layer and the first silicon oxide layer is dry etching.

[0036] The present invention further includes that in step 5 of the present embodiment, etching the silicon nitride layer, the first silicon oxide layer and etching and removing the amorphous silicon structure in the dummy gate are completed in one process step. And the present invention further includes that in step 5 of the present embodiment, a selectivity ratio of silicon oxide to silicon nitride equal to 1 is used to etch the silicon nitride layer and the first silicon oxide layer. That is, the present embodiment uses an etching rate of 1:1 between silicon nitride and silicon oxide, and etches and removes the silicon nitride layer, the first silicon oxide layer and the amorphous silicon structure in the dummy gate in one etching step.

[0037] In other embodiments, etching the silicon nitride layer and the first silicon oxide layer and etching away the amorphous silicon structure in the dummy gate in step 5 may be completed in two process steps. That is, the silicon nitride layer and the first silicon oxide layer are first etched away in one etching step, and then the amorphous silicon structure in the dummy gate is etched away in another etching step.

[0038] The present invention further comprises that in step 5 of this embodiment, the silicon nitride layer and the first silicon oxide layer are first etched with a selectivity ratio of silicon oxide to silicon nitride equal to 1, and the etching stops at the upper surface of the dummy gate; and then the amorphous silicon structure in the dummy gate is removed. Figure 4 As shown, Figure 4 It is a schematic diagram of the structure after the silicon nitride layer and the first silicon oxide layer are etched and removed in the present invention; Figure 5 It is a schematic diagram of the structure after etching away the amorphous silicon structure in the dummy gate in the present invention. It can be seen that after etching, the first silicon oxide layer 05 on the active area of ​​the empty area has no depression, thereby avoiding etching from touching the active area of ​​the empty area.

[0039] In summary, the method of the present invention can control the final height of the interlayer dielectric layer in each graphic area within a range with little difference, so that the pseudo gate polysilicon will not damage the active area surface of the open area during the removal process, thereby avoiding the generation of NiSi recess defects. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0040] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preventing NiSi from being recessed in HK metal gate process, characterized in that: The method at least comprises: Step 1, providing a substrate, wherein an area on the substrate where a plurality of dummy gates are densely distributed is a dense area, an area where a single dummy gate is distributed is a sparse area, and an area where no dummy gate is distributed is an open area; the dummy gate comprises an amorphous silicon structure and a sidewall attached to a sidewall of the amorphous silicon structure; Step 2, forming a NiSi layer on the substrate; the NiSi layer is located on the substrate between the dummy gates in the dense area and the sparse area, and is located on the substrate in the open area; Step 3: depositing an interlayer dielectric layer covering the dummy gate on the substrate, wherein the interlayer dielectric layer is composed of a three-layer structure of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer from bottom to top; Step 4: grinding the second silicon oxide layer with a selectivity of silicon oxide to silicon nitride greater than 1, and grinding to the upper surface of the silicon nitride layer; Step five: etching the silicon nitride layer and the first silicon oxide layer, and removing the amorphous silicon structure in the dummy gate.

2. The method for preventing NiSi from being recessed in a HK metal gate process according to claim 1, characterized in that: The sidewall in step 1 is silicon nitride.

3. The method for preventing NiSi from being recessed in a HK metal gate process according to claim 1, characterized in that: In step five, the method for etching the silicon nitride layer and the first silicon oxide layer is dry etching.

4. The method for preventing NiSi from being recessed in a HK metal gate process according to claim 1, characterized in that: In step five, etching the silicon nitride layer and the first silicon oxide layer and etching away the amorphous silicon structure in the dummy gate are completed in one process step.

5. The method for preventing NiSi from being recessed in a HK metal gate process according to claim 4, characterized in that: In step five, the silicon nitride layer and the first silicon oxide layer are etched with a selectivity ratio of silicon oxide to silicon nitride equal to 1.

6. The method for preventing NiSi from being recessed in a HK metal gate process according to claim 1, characterized in that: In step five, etching the silicon nitride layer and the first silicon oxide layer and etching away the amorphous silicon structure in the dummy gate are completed in two process steps.

7. The method for preventing NiSi from being recessed in a HK metal gate process according to claim 6, characterized in that: In step five, the silicon nitride layer and the first silicon oxide layer are first etched with a selectivity ratio of silicon oxide to silicon nitride equal to 1, and the etching stops at the upper surface of the dummy gate; then, the amorphous silicon structure in the dummy gate is removed.

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