Three-dimensional NAND memory devices and methods of forming the same

Abstract

A semiconductor device is provided. The semiconductor device includes a stack of word line layers and insulating layers alternately stacked on a substrate. The semiconductor device also includes a first dielectric trench structure. The first dielectric trench structure is placed in a bottom select gate (BSG) layer of the word line layers to separate the BSG layer and extends in a first direction of the substrate. The semiconductor device also includes a second dielectric trench structure. The second dielectric trench structure is placed in a top select gate (TSG) layer of the word line layers to separate the TSG layer and extends in the first direction of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second direction of the substrate perpendicular to the first direction.

Description

BACKGROUND

[0001] As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technology, designers have looked to stacked multiple die memory areas for memory cells to achieve greater storage capacity and to achieve lower cost per bit. A 3D-NAND memory device is an exemplary device that stacks multiple die memory areas for memory cells to achieve greater storage capacity and to achieve lower cost per bit. As 3D NAND technology migrates to higher densities and large capacities, particularly from 64L to 128L architectures, the number of word line layers (or gate control layers) in the longitudinal direction perpendicular to the substrate has been growing significantly. The growing number of word line layers causes a dramatic increase in the block size of the 3D-NAND memory device, which in turn can result in longer read and erase times, longer data transfer times, and lower storage efficiency. SUMMARY

[0002] According to one aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of word line layers and insulating layers stacked alternately on a substrate. The semiconductor device also includes a first dielectric trench structure. The first dielectric trench structure is placed in a bottom select gate (BSG) layer of the word line layers to separate the BSG layer into two portions and extends in a first direction of the substrate. The semiconductor device further includes a second dielectric trench structure. The second dielectric trench structure is placed in a top select gate (TSG) layer of the word line layers to separate the TSG layer into two portions and extends in the first direction (e.g., length direction) of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second direction (e.g., width direction) of the substrate that is perpendicular to the first direction.

[0003] The semiconductor device can include a first slit structure and a second slit structure. The first slit structure can be placed at a first boundary of the stack, where the first slit structure extends through the stack and extends along the first direction of the substrate. The second slit structure can be placed at a second boundary of the stack, where the second slit structure extends through the stack and extends along the first direction of the substrate.

[0004] In some embodiments, the first and second dielectric trench structures can be arranged between the first and second slit structures in the second direction of the substrate. Additionally, the first and second dielectric trench structures, the first and second slit structures can extend parallel to each other in the first direction of the substrate.

[0005] The semiconductor device can include a plurality of channel structures formed on the substrate and further extending through the stack, wherein the channel structures are arranged between the first slit structure and the second slit structure. The semiconductor device can further include a plurality of dummy channel structures formed on the substrate and further extending through the stack, wherein the dummy channel structures are arranged between the first slit structure and the second slit structure.

[0006] In some embodiments, the first dielectric trench structure extends across a first set of the dummy channel structures, and the second dielectric trench structure extends across a second set of the dummy channel structures.

[0007] In some embodiments, the TSG layer can be a highest word line layer among the word line layers, and the BSG layer can be a lowest word line layer among the word line layers.

[0008] In some embodiments, the semiconductor device can include a first region, a second region, and a third region. The first region is defined by the first slit structure and the second dielectric trench structure. The second region is defined by the first dielectric trench structure and the second dielectric trench structure. The third region is defined by the first dielectric trench structure and the second slit structure. The first region, the second region, and the third region are configured to be independently operated.

[0009] According to another aspect of the disclosure, a method for manufacturing a semiconductor device is provided. In the disclosed method, a plurality of first insulating layers and a dummy bottom select gate (BSG) layer are formed on a substrate. The dummy BSG layer is arranged between the first insulating layers. A first dielectric trench structure is then formed. The first dielectric trench structure extends through the dummy BSG layer and in a first direction (e.g., length direction) of the substrate. The dummy BSG layer is divided into two portions by the first dielectric trench structure. A plurality of sacrificial word line layers and a plurality of second insulating layers are then formed on the first insulating layers, wherein the second insulating layers and the sacrificial word line layers are arranged alternately. Further, a second dielectric trench structure is formed, wherein the second dielectric trench structure extends through a sacrificial top select gate (TSG) layer among the sacrificial word line layers to divide the sacrificial TSG layer into two portions and in the first direction of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second (or width) direction of the substrate.

[0010] In some embodiments, a trim etch process can be performed on the first insulating layer, the dummy BSG layer, the sacrificial word line layer, and the second insulating layer to form an array region and a staircase region on the substrate before forming the second dielectric trench structure, wherein the staircase region is placed at both sides of the array region.

[0011] In some embodiments, a channel structure can be formed in the array region, wherein the channel structure extends from the substrate and extends in the array region through the first insulating layer, the dummy BSG layer, the sacrificial word line layer, and the second insulating layer. Further, a first slit structure can be formed to be placed at a first boundary of the array region and the staircase region, and a second slit structure can be formed to be placed at a second boundary of the array region and the staircase region. The first slit structure and the second slit structure extend through the first insulating layer, the dummy BSG layer, the sacrificial word line layer, and the second insulating layer, and further extend along the first direction of the substrate. Subsequently, the dummy BSG layer can be replaced with a BSG layer, and the sacrificial word line layer can be replaced with a word line layer. A contact structure can be formed on the staircase region, wherein the contact structure is connected to the BSG layer and the word line layer in the staircase region.

[0012] In the disclosed method, the first dielectric trench structure and the second dielectric trench structure are arranged between the first slit structure and the second slit structure in the second direction of the substrate. In addition, the first dielectric trench structure, the second dielectric trench structure, the first slit structure, and the second slit structure extend parallel to each other in the first direction of the substrate.

[0013] According to yet another aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes an array region and a staircase region formed in a stack, wherein the staircase region is placed at both sides of the array region, and the stack includes word line layers and insulating layers alternately stacked on a substrate. The semiconductor device includes a first slit structure and a second slit structure. The first slit structure is placed at a first boundary of the array region and the staircase region, and extends through the stack and along a first (or length) direction of the substrate. The second slit structure is placed at a second boundary of the array region and the staircase region, and extends through the stack and along the first direction of the substrate.

[0014] The semiconductor device further has a first dielectric trench structure and a second dielectric trench structure. The first dielectric trench structure is arranged between the first and second slit structures, is placed in a bottom select gate (BSG) layer in the word line layers to separate the BSG layer into two portions, and extends in the first direction of the substrate. The second dielectric trench structure is arranged between the first and second slit structures, is placed in a top select gate (TSG) layer in the word line layers to separate the TSG layer into two portions, and extends in the first direction of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second direction of the substrate.

[0015] In some embodiments, the first dielectric trench structure, the second dielectric trench structure, the first slit structure, and the second slit structure extend parallel to one another in the first direction of the substrate.

[0016] In some embodiments, the semiconductor device includes a plurality of channel structures and a plurality of contact structures. The channel structures are formed on the substrate and further extend through the word line layers and the insulating layers in the array region of the stack. The contact structures are formed on the staircase region and are connected to the word line layers in the staircase region.

[0017] The semiconductor device further includes a plurality of dummy channel structures. The dummy channel structures are formed on the substrate and further extend through the word line layers and the insulating layers in the array region of the stack, wherein the first dielectric trench structure extends across a first set of the dummy channel structures and the second dielectric trench structure extends across a second set of the dummy channel structures. BRIEF DESCRIPTION OF DRAWINGS

[0018] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be exaggerated or reduced in order to more clearly discuss the pertinent aspects.

[0019] Figure 1A is a cross-sectional view of an exemplary 3D-NAND memory device according to an exemplary embodiment of the disclosure.

[0020] Figure 1B is a top view of an exemplary 3D-NAND memory device according to an exemplary embodiment of the disclosure.

[0021] Figure 1Cis a three-dimensional view of one exemplary 3D-NAND memory device according to exemplary embodiments of the present disclosure.

[0022] Figure 2 is a cross-sectional view of a channel structure in one exemplary 3D-NAND memory device according to exemplary embodiments of the present disclosure.

[0023] Figure 3A is a top view of a first 3D-NAND memory device.

[0024] Figure 3B is a top view of a second 3D-NAND memory device.

[0025] Figure 4A 、 4B , 5, 6, 7A, 7B, 8A, 8B, 9A, 9B, and 10 are cross-sectional and top views of various intermediate steps in fabricating one exemplary 3D-NAND memory device according to exemplary embodiments of the present disclosure.

[0026] Figure 11 is a flowchart of a process for fabricating one exemplary 3D-NAND memory device according to exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of a first feature over or on a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features do not make direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0028] Further, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0029] Concepts relate to, for example, formation of 3D-NAND memory devices having partitioned memory block structures, and each of the partitioned memory block structures can be independently operated (e.g., programmed, erased, or read).

[0030] A 3D-NAND memory device can include a plurality of memory cell memory blocks (or memory blocks). Each of the memory blocks can include a plurality of longitudinal NAND memory cell strings. Each of the longitudinal NAND memory cell strings can have one or more bottom select transistors (BSTs), one or more dummy BSTs, a plurality of memory cells (MCs), one or more dummy top select transistors (TSTs), and one or more TSTs sequentially and contiguously arranged on a substrate along a height direction (or Z direction) of the substrate. A source region of a lowest BST in each of the longitudinal NAND memory cell strings is connected to a common source line (CSL), and a drain region of a highest TST in each of the longitudinal NAND memory cell strings is connected to a respective bit line. In the 3D-NAND memory device, the longitudinal NAND memory cell strings of a same memory block can share one or more top select gates (TSGs). The shared one or more TSGs correspondingly simultaneously control the TSTs of the longitudinal NAND memory cell strings in the same memory block during operation related to the 3D-NAND memory device, such as programming or reading the 3D-NAND memory device.

[0031] In the 3D-NAND memory device, the longitudinal NAND memory cell strings of a same memory block can share one or more bottom select gates (BSGs). The shared one or more BSGs correspondingly simultaneously control the BSTs of the longitudinal NAND memory cell strings in the same memory block during operation of the 3D-NAND memory device, such as erasing the 3D-NAND memory device. As the 3D-NAND memory device migrates to higher capacities with increased memory block sizes, the shared one or more TSGs or BSGs can result in longer operation times, longer data transfer times, and lower storage efficiency.

[0032] In a related 3D-NAND memory device, one memory block can be divided into multiple sub-memory blocks by dividing one or more shared TSGs into multiple sub-TSGs using one or more dielectric trench structures. The sub-memory blocks can be independently operated so that operation time and data transfer time can be reduced accordingly. In a first example, one dielectric trench structure can be applied to divide a memory block into two sub-memory blocks. However, such a configuration can result in a low storage cell density. In a second example, two dielectric trench structures can be applied to divide a memory block into three sub-memory blocks. However, the sub-memory blocks between the two dielectric trench structures can not function because a sacrificial word line layer in the sub-memory blocks cannot be replaced with a word line layer, for example, as described below. Figure 3B

[0033] In the disclosed 3D-NAND memory device, one memory block can have a first dielectric trench structure placed in a bottom select gate (BSG) layer for dividing the BSG layer into two parts and a second dielectric trench structure placed in a top select gate (TSG) layer for dividing the TSG layer into two parts. The second dielectric trench structure is offset from the first dielectric trench structure. The disclosed configuration allows a higher channel structure density in a memory block by dividing the memory block into three independent and functional sub-memory blocks.

[0034] Figure 1A is a cross-sectional view of an exemplary 3D-NAND memory device 100, and Figure 1B is a top view of the exemplary 3D-NAND memory device 100, wherein, Figure 1A the cross-sectional view of the 3D-NAND memory device 100 in Figure 1B is obtained along a Z direction (or a height direction) of the substrate in Figure 1B the dashed line in indicates a perspective view. Figure 1C is a 3D view of the exemplary 3D-NAND memory device 100. For simplicity and clarity, only one memory block of the 3D-NAND memory device 100 is provided in Figure 1A , 1B and 1C.

[0035] As shown in Figure 1A , the 3D-NAND memory device 100 can have a substrate 10. A plurality of word line layers and a plurality of insulating layers are alternately stacked on the substrate 10. In the exemplary embodiment of Figure 1A , sixteen word line layers and seventeen insulating layers are included. However, Figure 1A ​This is merely an example, and any number of word line layers and insulating layers can be included based on the device structure. In some embodiments, the lowest word line layer 12a may act as a bottom select gate (BSG) layer connected to the gate of the BST. In some embodiments, one or more word line layers above the BSG layer 12a (such as word line layers 12b-12c) may be virtual word line layers (or virtual BSG layers) connected to the gate of a virtual memory cell (virtual MC). The BST and the virtual MC together control data transfer between the array common source (ACS) region 16 and the memory cell. In some embodiments, the highest word line layer 12p may act as a top select gate (TSG) layer connected to the gate of the TST. In some embodiments, one or more word line layers below the TSG layer 12p (such as word line layers 12n-12o) may be virtual word line layers (or virtual TSG layers) connected to the gate of a virtual memory cell (virtual MC). The TST and the virtual MC together control data transfer between the bit line (not shown) and the memory cell.

[0036] An insulating layer is placed on the substrate 10 and is arranged alternately with the word line layers. The word line layers are separated from each other by the insulating layer. In addition, the word line layers are separated from the substrate 10 by the lowest insulating layer 14a in the insulating layer.

[0037] In some embodiments, a sacrificial word line layer (e.g., SiN) is first used to form Figure 1A The word line layer described herein can be removed and replaced with a high-k layer, an adhesive layer, and one or more metal layers. The high-k layer can be made of alumina (Al₂O₃) and / or hafnium oxide (HfO₂) and / or tantalum oxide (Ta₂O₅) and / or another high-k (dielectric constant) material. The metal layers can be made of, for example, tungsten (W) or cobalt (Co). Depending on product specifications, equipment operation, manufacturing capabilities, etc., the word lines can have a thickness ranging from 10 nm to 100 nm. Figure 1A In some embodiments, the insulating layer may be made of SiO2 with a thickness ranging from 5 nm to 50 nm.

[0038] In some embodiments, the 3D-NAND memory device 100 may have an array region 100A and two stepped regions 100B-100C. The stepped regions 100B-100C may be placed on both sides of the array region 100A. Word line layers and insulating layers may extend into the stepped regions 100B-100C, having a stepped or stepped profile.

[0039] The 3D-NAND memory device 100 may include a plurality of channel structures 18 in an array region 100A. The channel structures 18 are formed on the substrate 10 along the Z-direction (or height direction) of the substrate. Figure 1AAs shown in FIG. 1, five channel structures 18 are included. However, Figure 1A This is just one example, and any number of channel structures 18 can be included in the 3D-NAND memory device 100. The channel structures 18 can extend through the word line layers and the insulating layers, and further extend into the substrate 10 to form an array of longitudinal memory cell strings. Each of the longitudinal memory cell strings can include a corresponding channel structure that is coupled to the word line layers to form one or more bottom select transistors (BSG), a plurality of memory cells (MC), and one or more top select transistors (TST). The BSG, MC, and TST are sequentially and contiguously arranged on the substrate. Additionally, each of the channel structures 18 can further include a channel layer, a tunneling layer, a charge trapping layer, and a blocking layer, which are shown in further detail in Figures 3A-3B FIG. 2.

[0040] The 3D-NAND memory device 100 can have a plurality of slit structures. For example, two slit structures 20a-20b are included in Figure 1A FIG. 3. In some embodiments, the 3D-NAND memory device 100 is formed using a gate-last fabrication technique, and thus, the slit structures are formed to assist in removing sacrificial word line layers and forming real gates. In some embodiments, the slit structures can be made of a conductive material and placed on an array common source (ACS) region 16 to act as a contact, where the ACS region is formed on the substrate 10 to act as a common source. In some embodiments, the slit structures can be made of a dielectric material to act as a spacer structure. In Figure 1A the example embodiment of FIG. 3, the slit structures 20a-20b are placed at two opposite boundaries of the array region 100A and connected to the ACS region 16.

[0041] In some embodiments, the slit structures 20a-20b can extend through the word line layers and the insulating layers, and further extend along a first direction (also referred to as a length direction or X direction) of the substrate 10. In some embodiments, the slit structures 20a-20b can have a dielectric spacer 26, a conductive layer 30, and a contact 28. The dielectric spacer 26 is formed along sidewalls of a slit height and has direct contact with the word line layers and the insulating layers. The conductive layer 30 is formed along the dielectric spacer 26 and on the ACS region 16. The contact 28 is formed along the dielectric spacer 26 and on the conductive layer 30. In Figure 1A In the embodiment of FIG. 3, the dielectric spacer 26 is made of Si02, the conductive layer 30 is made of polysilicon, and the contact 28 is made of tungsten.

[0042] 3D-NAND memory device 100 can have a plurality of contact structures 22. Contact structures 22 are formed in dielectric layer 24 and are placed on word line layers to connect to the word line layers. For simplicity and clarity, only three contact structures 22 are illustrated in each of the stepped regions 100B and 100C. Contact structures 22 can be further coupled to a gate voltage. The gate voltage can be applied to the gates of the BST, MC, and TST through the word line layers to operate the BST, MC, and TST, respectively.

[0043] 3D-NAND memory device 100 can have a first dielectric trench structure 34 extending in a first direction of substrate 10. In some embodiments, first dielectric trench structure 34 can be placed in BSG layer 12a to separate BSG layer 12a into two portions (or sub-BSG layers) 12a-1 and 12a-2. In some embodiments, first dielectric trench structure 34 can further extend through one or more dummy word line layers (such as 12b-12c) to separate the dummy word line layers into two portions (or sub-dummy word line layers) depending on the device design. In Figure 1A In the exemplary embodiment, first dielectric trench structure 34 is placed only in BSG layer 12a to separate BSG layer 12a into two sub-BSG layers 12a-1 and 12a-2.

[0044] Still referring to Figure 1A Second dielectric trench structure 32 is placed in top select gate (TSG) layer 12p and dummy word line layers 12n-12o to separate TSG layer 12p and dummy word line layers 12n-12o into two portions. For example, upon the introduction of second dielectric trench structure 32, TSG layer 12p becomes 12p-1 and 12p-2. Second dielectric trench structure 32 extends in the first direction of substrate 10. Accordingly, TSG layer 12p and dummy word line layers 12n-12o are divided into two sub-TSG layers and two sub-dummy word line layers along the first direction of the substrate. It should be noted that Figure 1A This is merely an example, and second dielectric trench structure 32 can separate any number of word line layers at the top of 3D-NAND memory device 100.

[0045] First dielectric trench structure 34 is offset from second dielectric trench structure 32 in a second direction of substrate 10 (also referred to as a width direction or Y direction) that is perpendicular to the first direction. First dielectric trench structure 34 is also separated from second dielectric trench structure 32 along the Z direction (or height direction) of substrate 10 by one or more word line layers and insulating layers.

[0046] In some embodiments, the first and second dielectric trench structures 34 and 32 can have a critical dimension (CD) from 50 nm to 150 nm. In some embodiments, the first and second dielectric trench structures 34 and 32 can be empty structures. In some embodiments, the first and second dielectric trench structures 34 and 32 can be filled with SiN, Si02, SiON, SiOCN, SiCN, or other suitable dielectric materials. In some embodiments, the first and second dielectric trench structures 34 and 32 can extend along the first direction of the substrate 10 with a depth between 10 nm to 100 nm. In some embodiments, the first dielectric trench structure 34 and the second dielectric trench structure 32 are arranged between the slit structures 20a-20b in the second direction of the substrate 10. In some embodiments, the first dielectric trench structure 34, the second dielectric trench structure 32, and the slit structures 20a-20b extend parallel to each other in the first direction of the substrate 10.

[0047] By introducing the first and second dielectric trench structures 34 and 32 in the 3D-NAND memory device 100, the BSG layer and the TSG layer can be separated into multiple sub-BSG layers and sub-TSG layers. The sub-BSG layers and the sub-TSG layers can divide the 3D-NAND memory device 100 into multiple sub-memory blocks. Each of the sub-memory blocks can have a respective sub-BSG layer and a respective sub-TSG layer. Accordingly, each of the sub-memory blocks can be independently operated by controlling the respective sub-BSG layer and the respective sub-TSG layer. Correspondingly, the 3D-NAND memory device 100 can precisely control the desired sub-memory block (or sub-array region) in order to effectively reduce the programming time, the read time, the erase time, and the data transfer time, and greatly improve the data storage efficiency.

[0048] Figure 1B is a top view of a 3D-NAND memory device 100 according to some embodiments of the present disclosure. As shown in Figure 1B The 3D-NAND memory device 100 can have four boundaries 1-4. Two slit structures 20a-20b are placed at the first boundary 1 and the second boundary 2, respectively, and further extend along the first direction (or length direction) of the substrate 10. The slit structure 20a is arranged at the first boundary (or top boundary) of the array region 100A and the staircase region 100B-100C. The slit structure 20b is arranged at the second boundary (or bottom boundary) of the array region 100A and the staircase region 100B-100C. According to some embodiments, the second boundary is opposite to the first boundary. The slit structures 20a-20b can serve as contacts for connecting the ACS region 16 of the 3D-NAND memory device 100, and further isolate the 3D-NAND memory device 100 from adjacent components.

[0049] Still referring to Figure 1B , the first dielectric trench structure 34 and the second dielectric trench structure 32 are arranged between the gap structures 20a-20b in the second direction of the substrate 10. The first dielectric trench structure 34, the second dielectric trench structure 32, and the gap structures 20a-20b extend parallel to each other in the first direction of the substrate 10. In some embodiments, the first and second dielectric trench structures 34 and 32 are intentionally offset from each other along the second direction (width direction) of the substrate 10.

[0050] Several benefits can be obtained by introducing the misaligned profile between the first and second dielectric trench structures 34 and 32. First, the first dielectric trench structure 34 and the second dielectric trench structure 32 can divide the 3D-NAND memory device 100 into three sub-memory blocks 102, 104, and 106. The three sub-memory blocks 102, 104, and 106 can be independently operated by applying appropriate control voltages on the sub-BSG layers 12a-1 and 12a-2 and the sub-TSG layers 12p-1 and 12p-2. In one example, to program the sub-memory block 102, a Vcc voltage (such as 1.0 volt) can be applied to the sub-TSG layer 12p-1, and a zero voltage can be applied to the sub-BSG layer 12a-1. In another example, to erase the sub-memory block 104, the sub-TSG layer 12p-2 can be in the up-float phase, and the sub-BSG layer 12a-1 can be switched from the ground phase (e.g., zero volt) to the up-float phase.

[0051] Second, the misaligned profile between the first and second dielectric trench structures 34 and 32 allows replacement of the sacrificial word line layers in each sub-memory block with word line layers. During the replacement of the sacrificial word line layers with the word line layers, a wet etch chemistry can be introduced from the gap structures and flow towards the first and second dielectric trench structures 34 and 32. The wet etch chemistry has a good etch selectivity between the sacrificial word line layers and the insulating layers. Thus, the sacrificial word line layers can be removed to form empty spaces, and the insulating layers remain. A deposition process can be subsequently introduced to fill the empty spaces to form the word line layers.

[0052] The 3D-NAND memory device 100 can further include a plurality of dummy channel structures 36 formed on the substrate and extending through the word line layers and the insulating layers in the Z direction (or height direction) of the substrate. In some embodiments, the dummy channel structures are formed only in the staircase regions 100B and 100C. In some embodiments, the dummy channel structures 36 can be formed in both the staircase regions 100B and 100C and the array region 100A. The dummy channel structures act as support members for supporting the staircase regions and / or the array region when the sacrificial word line layers are removed. In some embodiments, the dummy channel structures 36 can be formed in the array region 100A only. In some embodiments, the dummy channel structures 36 can be formed in the array region 100A and the staircase regions 100B and 100C. Figure 1BIn some embodiments, a virtual channel structure 36 is formed in the array region 100A. In some embodiments, the virtual channel structure 36 may be formed together with the channel structure 18 and have a similar structure to the channel structure 18. Therefore, the virtual structure may also include a barrier layer, a trapping layer, a tunneling layer, and a channel layer. In some embodiments, the virtual channel structure 36 has a different structure from the channel structure 18. For example, the virtual channel structure 36 is made of a dielectric material (such as SiO, SiN, or other suitable dielectric materials).

[0053] As in Figure 1B As shown, a channel structure 18 is formed on the substrate 10 and extends further through the word line layer and the insulating layer. The channel structure 18 is arranged between slot structures 20a-20b. A virtual channel structure 36 is also arranged between the first slot structure and the second slot structure. In some embodiments, a first dielectric trench structure 34 extends across a first set of virtual channel structures, and a second dielectric trench structure 32 extends across a second set of virtual channel structures. Further, contact structures 22 are placed on the word line layer in the stepped regions 100B and 100C. It should be understood that... Figure 1B This is just one example. The 3D-NAND storage device 100 may include any number of channel structures 18, any number of contact structures 22, and any number of virtual channel structures 36.

[0054] Figure 1C This is a three-dimensional view of a 3D-NAND storage device 100 according to an exemplary embodiment of the present disclosure. (As shown in...) Figure 2 As shown, word line layers and insulating layers are alternately stacked on substrate 10. A second dielectric trench structure 32 is placed within the top select gate (TSG) layer 12p and virtual word line layers 12n-12o in the word line layer to separate the TSG layer 12p and the virtual word line layers 12n-12o into two portions. The second dielectric trench structure 32 further extends in a first direction (or X direction) of substrate 10. A first dielectric trench structure 34 is placed within the bottom select gate (BSG) layer 12a in the word line layer to separate the BSG layer 12a into two portions and extends in the first direction of substrate 10. The first dielectric trench structure 34 is offset from the second dielectric trench structure 32 in a second direction (or Y direction) of substrate 10.

[0055] Figure 2 This is a cross-sectional view of the channel structure 18 in the 3D-NAND memory device 100. (As shown in...) Figure 2As shown in FIG. 1, the channel structure 18 can have a cylindrical shape with a sidewall and a bottom region. Of course, other shapes are possible. The channel structure 18 is formed along the Z direction perpendicular to the substrate 10 and is electrically coupled together with the substrate 10 via a bottom channel contact 202 placed at the bottom region of the channel structure. The channel structure 18 further includes a channel layer 206, a tunneling layer 208, a charge trapping layer 210, and a blocking layer 212. The blocking layer 212 is formed along the sidewall of the channel structure 18 and on the bottom channel contact 202. The blocking layer 212 has direct contact with the word line and the insulating layer. The charge trapping layer 210 is formed along the blocking layer 212 and on the bottom channel contact 202, and the tunneling layer 208 is formed along the charge trapping layer 210 and on the bottom channel contact 202. The channel layer 206 has a side formed along the tunneling layer 208 and has a T-shaped bottom extending bottom-ward through the tunneling layer 208, the charge trapping layer 210, and the blocking layer 212 placed on the bottom channel contact 202. The T-shaped bottom of the channel layer 206 is further placed on the bottom channel contact 202 and has direct contact with the bottom channel contact 202. In addition, the tunneling layer 208, the charge trapping layer 210, and the blocking layer 212 can form an "L-foot" configuration in the channel structure 18. The L-foot configuration can include a side formed along the sidewall of the channel structure 18 and a bottom over the bottom channel contact 202.

[0056] The channel structure 18 can further have a channel insulating layer 204 formed along the channel layer 206 to fill the channel structure 18. The channel insulating layer 204 can have a T-shaped bottom extending bottom-ward through the channel layer 206, the tunneling layer 208, the charge trapping layer 210, and the blocking layer 212 and landing on the channel layer 206. In some embodiments, the channel insulating layer 204 can include a hole placed at a middle position of the channel insulating layer 204. The channel structure 18 can further include a top channel contact 214 formed along the channel insulating layer 204 and having direct contact with the channel layer 206. The top channel contact 214 is placed over the TSG layer 12p to prevent any electrical interference between the top channel contact 214 and the TSG layer 12p. In the channel structure 18, a gate dielectric layer 216 is further formed between the BSG layer 12a and the bottom channel contact 202. The gate dielectric layer 216 can be placed between the insulating layers 14b and 14a and has a ring shape to surround the bottom channel contact 202.

[0057] In Figure 2 In some embodiments, the blocking layer 212 is made of Si02. In another embodiment, the blocking layer 212 can include multiple layers such as Si02and Al203. In Figure 2In an embodiment, the charge trapping layer 210 is made of SiN. In another embodiment, the charge trapping layer 210 can include a multi-layer configuration such as a SiN / SiON / SiN multi-layer configuration. In some embodiments, the tunneling layer 208 can include a multi-layer configuration such as a SiO / SiON / SiO multi-layer configuration. In Figure 2 In an embodiment, the channel layer 206 is made of polysilicon via a furnace tube low pressure chemical vapor deposition (CVD) process. The channel insulating layer 204 can be made of SiO2, and the top and bottom channel contacts 214 and 202 can be made of polysilicon.

[0058] As shown in Figure 2 , the channel structure 18 can have a cylindrical shape. However, the present disclosure is not limited thereto, and the channel structure 18 can be formed in other shapes such as a square pillar shape, an elliptical pillar shape, or any other suitable shape.

[0059] Figure 3A is a top view of a first related 3D-NAND memory device 300A. For simplicity and clarity, only one memory block of the 3D-NAND memory device 300A is illustrated in Figure 3A . As shown in Figure 3A , the 3D-NAND memory device 300A has a first slit structure 302 placed at a first boundary of the 3D-NAND memory device 300A and a second slit structure 304 placed at an opposite second boundary of the 3D-NAND memory device 300A. The first and second slit structures 302 and 304 extend in a length (or X) direction of the 3D-NAND memory device 300A. A plurality of channel structures 306 are arranged between the first and second slit structures 302 and 304. A plurality of dummy channel structures 312 are arranged between the first and second slit structures. The dummy channel structures 312 can have the same structure as the channel structures 306 or a different structure from the channel structures 306. A dielectric trench structure 308 is placed in the 3D-NAND memory device 300A and extends in the length direction of the 3D-NAND memory device 300A. The dielectric trench structure 308 separates a TSG layer of the 3D-NAND memory device 300A into two sub-TSG layers, which in turn divides the 3D-NAND memory device 300A into two sub-memory blocks. The dielectric trench structure 308 further extends across the set of dummy channel structures 312. The 3D-NAND memory device 300A is limited by high memory block spacing and low channel structure density.

[0060] Figure 3B is a top view of a second related 3D-NAND memory device 300B. For simplicity and clarity, only one memory block of the 3D-NAND memory device 300B is illustrated in Figure 3BA single memory block of the 3D-NAND memory device 300B is illustrated. The memory device 300B has a first slit structure 314 placed at a first boundary of the 3D-NAND memory device 300B and a second slit structure 316 placed at a second boundary of the 3D-NAND memory device 300B. The first and second slit structures 314 and 316 extend in a length (or X) direction of the 3D-NAND memory device 300B. A plurality of channel structures 322 are arranged between the first and second slit structures 314 and 316. A plurality of dummy channel structures 324 are arranged between the first and second slit structures 314 and 316. The dummy channel structures 324 can have the same structure as the channel structures 322 or a different structure from the channel structures 322. A first dielectric trench structure 318 and a second dielectric trench structure 320 are placed in the 3D-NAND memory device 300B and extend in the length direction of the 3D-NAND memory device 300B. The first and second dielectric trench structures 318 and 320 separate the TSG layer of the 3D-NAND memory device 300B into three sub-TSG layers, which in turn divide the 3D-NAND memory device 300B into three sub-memory blocks 326-328. The 3D-NAND memory device 300B can have a greater channel structure density than the 3D-NAND memory device 300A. However, the sacrificial word line layer arranged between the first and second dielectric trench structures 318 and 320 in the sub-memory block 327 can not be able to be removed by an etching process because the first and second dielectric trench structures 318 and 320 can block etching chemicals to avoid the etching process. Accordingly, the sub-memory block 327 can not function.

[0061] Figure 4A 、 4B , 5, 6, 7A, 7B, 8A, 8B, 9A, 9B, and 10 are cross-sectional and top views of various intermediate steps of fabricating the 3D-NAND memory device 100 according to example embodiments of the present disclosure.

[0062] Figure 4A and 4B illustrates the formation of the first dielectric trench structure 34. Figure 4A is a cross-sectional view of the substrate 10, and Figure 4B is a top view of the substrate 10, wherein, Figure 4A the cross-sectional view in Figure 4B is obtained from a line A-A’ along the Z direction (or height direction) of the substrate 10 in Figure 4A As shown in Figure 4AIn the exemplary embodiment, the BSG layer 12a and two first insulating layers 14a-14b are formed on the substrate 10. Thus, the lowermost first insulating layer 14a is formed on the substrate 10, and the BSG layer 12a is disposed between the first insulating layers 14a-14b.

[0063] The BSG layer 12a can be a dummy BSG layer made of SiN. The dummy BSG layer can be removed and replaced with a high-K layer and a metal layer in subsequent manufacturing steps. The BSG layer 12a can have a thickness in the range from 10 nm to 100 nm. The first insulating layers can comprise SiO, SiCN, SiOCN, or other suitable materials. The first insulating layers 14a-14b can have a thickness from 5 nm to 50 nm. Any suitable deposition process can be applied to form the BSG layer, the first insulating layers, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof.

[0064] Still referring to FIG. 1, the exemplary embodiment includes a second insulating layer 16 formed on the BSG layer 12a. The second insulating layer 16 can be formed on the BSG layer 12a by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof. The second insulating layer 16 can have a thickness in the range from 5 nm to 50 nm. The second insulating layer 16 can comprise SiO, SiCN, SiOCN, or other suitable materials. Figure 4AA first dielectric trench structure 34 can be formed in the BSG layer 12a to separate the BSG layer 12a into two portions (or sub-BSG layers) 12a-1 and 12a-2. The first dielectric trench structure 34 extends in a first direction (also referred to as a length direction or X direction) of the substrate 10. Although the first dielectric trench structure 34 is illustrated as being formed in the lowest BSG layer, in other embodiments, the first dielectric trench structure 34 can be formed in another BSG layer. The first dielectric trench structure 34 can have a CD from 50 nm to 150 nm. The first dielectric trench structure 34 can be made of SiCN, Si02, SiON, SiOCN, SiN, or other suitable dielectric material. In some embodiments, the first dielectric trench structure 34 can extend into the substrate 10 with a depth between 10 nm to 100 nm. To form the first dielectric trench structure 34, an imaging mask stack can be formed on the first insulating layer 14b by a lithography process. An etch process can then be introduced to etch through the first insulating layer, the BSG layer, and further extend into the substrate 10 to form a trench opening (not shown). The trench opening can then be filled with a dielectric material, such as Si02, SiON, SiOCN, SiN, SiCN, or other suitable material, by applying CVD, PVD, ALD, diffusion, or any combination thereof. A surface planarization process, such as a chemical mechanical polishing (CMP) process, can be performed to remove any excess dielectric material on the first insulating layer 14b. The dielectric material remaining in the trench opening becomes the first dielectric trench structure 34. In some embodiments, once the trench opening is formed, the trench opening can remain empty and becomes the first dielectric trench structure 34. Accordingly, the first dielectric trench structure 34 can be an empty structure.

[0065] In Figure 5 In some embodiments, a plurality of word line layers and a plurality of second insulating layers are deposited on the first insulating layer 14b. The word line layers, the second insulating layers, the first insulating layers 14a-14b, and the BSG layer 12a form a stack 500, respectively. The word line layers and the second insulating layers are alternately placed such that the word line layers are spaced apart from each other by the second insulating layers. For example, as in Figure 5As shown in FIG. 1C, word line tiers 12b are placed on first insulating tiers 14b, and second insulating tiers 14c are placed on word line tiers 12b. The highest word line tier 12p is placed between the highest second insulating tier 14q and the second insulating tier 14p. In some embodiments, the highest word line tier 12p among the word line tiers can function as a TSG tier. In other embodiments, the TSG tier can be a word line tier different from the highest word line tier 12p (such as word line tier 12n or word line tier 12o placed below word line tier 12p). In some embodiments, word line tier 12p functions as the TSG tier, and word line tiers 12n-12o can be dummy word line tiers. In yet other embodiments, one or more of the word line tiers above BSG tier 12a (such as word line tiers 12b-12c) can be dummy word line tiers.

[0066] The word line tiers can also be sacrificial tiers made of SiN and having a thickness in a range from 10 nm to 100 nm. The sacrificial tiers can be removed in subsequent fabrication steps and replaced with high-K tiers and metal tiers. The second insulating tiers can have a thickness between 5 nm to 50 nm and include SiO2, SiCN, SiOCN, or other suitable materials. Any suitable deposition process can be applied to form the word line tiers and the second insulating tiers, such as CVD, PVD, ALD, diffusion, or any combination thereof.

[0067] In Figure 6 In the stack 500, two stepped regions 100B and 100C are formed. The formation of the two stepped regions 100B and 100C can be formed by a trim etch process. The trim etch process can be applied to the second insulating tiers, the word line tiers, BSG tier 12a, and first insulating tiers 14a-14b to form the two stepped regions 100B and 100C. Once the stepped regions 100B and 100C are formed, the array region 100A is placed between the stepped regions 100B and 100C.

[0068] Figure 7A And 7B The formation of the second dielectric trench structure 32 in the stack 500 is illustrated. Figure 7A is a cross-sectional view of the substrate 10, and Figure 7B is a top view of the substrate 10, where, Figure 7A The cross-sectional view in FIG. 1A is obtained from line A-A’ along the Z direction (or height direction) of the substrate 10 in FIG. 1B. As in FIG. 1A, Figure 7B The cross-sectional view in FIG. 1A is obtained from line A-A’ along the Z direction (or height direction) of the substrate 10 in FIG. 1B. As in FIG. 1A, Figure 7AAs shown in FIG. 1, a second dielectric trench structure 32 can be formed in the word line layers 12n-12p. In some embodiments, the word line layer 12p can be a TSG layer of the 3D-NAND memory device 100, and the word line layers 12n-12o can be two dummy word line layers. The second dielectric trench structure 32 extends in the first direction of the substrate 10 to separate the TSG layer 12p and the dummy word line layers 12n-12o into two portions. For example, two sub-TSG layers 12p-1 and 12p-2 can be formed in Figure 7A In some embodiments, the second dielectric trench structure 32 can be offset from the first dielectric trench structure 34 in the second direction (also referred to as the width direction, or Y direction) of the substrate 10. In some embodiments, the second dielectric trench structure 32 can have a CD from 50 nm to 150 nm, and include Si02, SiON, SiOCN, SiN, SiCN, or other suitable dielectric material. In some embodiments, the second dielectric trench structure 32 can be an empty structure. The second dielectric trench structure 32 can be formed based on a similar process as the process mentioned above for forming the first dielectric trench structure 34.

[0069] It should be noted that, Figure 7A and 7B are examples only, the first dielectric trench structure 34 can further extend in the Z direction so as to be placed in any number of word line layers above the BSG layer 12a. Depending on the device structure, the second dielectric trench structure 32 can further extend towards the substrate so as to be placed in any number of word line layers below the word line layer 12n.

[0070] Figure 8A and 8B illustrates forming the channel structures 18 and the dummy channel structures 36 in the stack 500. Figure 8A is a cross-sectional view of the substrate 10, and Figure 8B is a top view of the substrate 10, wherein, Figure 8A is a cross-sectional view of the substrate 10 from Figure 8B is obtained from a line A-A' along the Z direction (or height direction) of the substrate 10 in FIG. 1. To form the channel structures 18, a plurality of channel openings can be formed first. The channel openings can be formed by a lithography process for forming an imaging mask and a subsequent etching process for transferring the pattern of the mask. The formed channel openings can go through the word line layers, the BSG layer 12a, and the first and second insulating layers, and further extend into the substrate 10. Each of the channel openings can have a side and a bottom for exposing the substrate 10. When the channel openings are formed, a plurality of bottom channel contacts (such as Figure 2bottom channel contacts 202). Each of the channel notches can have a respective bottom contact at the bottom. The bottom channel contacts can protrude from the BSG layer 12a, and a top surface of each of the bottom channel contacts can be placed between the BSG layer 12a and the word line layer 12b.

[0071] Still referring to Figure 8A Once the bottom channel contacts are formed, a barrier layer, a charge trapping layer, and a tunneling layer can be sequentially formed along the sides of the channel notches and over the bottom channel contacts. A subsequent anisotropic plasma etch can be applied to remove portions of the barrier layer, the charge trapping layer, and the tunneling layer arranged over the bottom channel contacts to form a plurality of interconnect notches. Each of the interconnect notches exposes a respective bottom channel contact. A channel layer can then be formed along the sides of the channel notches and further extends through the interconnect notches to connect the bottom channel contacts.

[0072] Once the channel layer is formed, the channel layer can have a T-shaped bottom formed along the sides of the tunneling layer and extending through the bottom of the tunneling layer, the charge trapping layer, and the barrier layer placed over the bottom channel contacts. The T-shaped bottom of the channel layer is in direct contact with the bottom channel contacts, which can be shown in Figure 2 Additionally, the tunneling layer, the charge trapping layer, and the barrier layer can form an L-foot configuration in the channel notches. The L-foot configuration can include sides formed along the sidewalls of the channel notches and a bottom over the bottom channel contacts.

[0073] In some embodiments, once the channel layer is formed, a subsequent annealing process can be applied to release wafer stress and also reduce defects (dangling bonds). In some cases, the annealing process is also used to transform the channel layer to be poly crystalline. In some embodiments, the formation of the channel structure further includes forming a channel insulating layer over the channel layer to fill the channel notches, and forming top channel contacts over the channel insulating layer such that the top channel contacts are in direct contact with the channel layer. The detailed channel structure can be illustrated in Figure 2

[0074] Figure 8B is a top view for illustrating the formation of the channel structure 18. As in Figure 8B ​As shown in FIG. 1, channel structures 18 can be formed in array region 100A. In addition, a plurality of dummy channel structures 36 can also be formed in array region 100A. In some embodiments, dummy channel structures 36 can be formed together with channel structures 18 and have similar structures as channel structures 18. Thus, dummy structures can also include a blocking layer, a trapping layer, a tunneling layer, and a channel layer. In some embodiments, dummy channel structures 36 have different structures from channel structures 18. For example, dummy channel structures 36 are made of a dielectric material such as SiO, SiN, or any suitable dielectric material. In some embodiments, second dielectric trench structures 32 can extend across a first set of dummy channel structures 36, and first dielectric trench structures 34 can extend across a second set of dummy channel structures 36. In some embodiments, dummy channel structures 36 can be placed away from first and second dielectric trench structures 34 and 32. In some embodiments, dummy channel structures 36 can be further formed in step regions 100B and 100C. In Figure 8B In some embodiments, channel structures 18 and dummy channel structures 36 can be arranged into 14 rows along a second direction (e.g., Y direction) of the substrate, where dummy channel structures 36 can be placed in the 5th and 10th rows. Further, four rows (e.g., 6th-9th rows) of channel structures can be arranged between first dielectric trench structures 34 and second dielectric trench structures 32.

[0075] Figure 9A and 9B FIG. 1 illustrates the formation of slit structures 20a and 20b in stack 500. Figure 9A is a cross-sectional view of substrate 10, and Figure 9B is a top view of substrate 10, where, Figure 9A is a cross-sectional view of substrate 10 taken along line A-A’ in Figure 9B In order to form slit structures 20a and 20b, an imaging mask can be placed on the highest second insulating layer 14q of stack 500 by a lithography process, and a subsequent etching process can transfer the pattern of the imaging mask into the word line layers and the first and second insulating layers of stack 500 to form slit openings (not shown). Stack 500 can have four boundaries 1-4. Slit openings can be placed at first boundary 1 and second boundary 2 of stack 500. Slit openings can extend through the word line layers, the second insulating layers, the first insulating layers 14a-14b, and the BSG layers 12a. Slit openings can further extend into substrate 10. Each of the slit openings can have a side portion and a bottom portion that extend into substrate 10. Slit openings can further extend along a first direction (or length direction) of the substrate and be arranged parallel to first and second dielectric trench structures 34 and 32.

[0076] After the formation of the slit openings, the subsequent fabrication steps for completing the formation of the slit structures can be different (e.g., between a gate-first fabrication flow and a gate-last fabrication flow). In a gate-first fabrication flow, ion implantation can be subsequently applied to form a doped region, such as doped region (also referred to as an array common source region) 16, at the bottom of each of the slit openings. A dielectric spacer, such as dielectric spacer 26, can be formed along the sides of the slit openings and over the doped region. An anisotropic plasma etch can be implemented to remove the bottom of the dielectric spacer 26 formed over the doped region 16 to expose the doped region 16. A conductive layer, such as conductive layer 30, can be deposited along the dielectric spacer 26 and fill the slit openings. The conductive layer 30 can then be recessed by an etching process, and a contact, such as contact 28, can be formed along the dielectric spacer 26 and over the conductive layer 30. Upon formation of the contact, the slit structures with the same profile as the slit structures 20a and 20b in Figure 9A The slit structures in the stack 500 are formed in the same profile as the slit structures 20a and 20b in

[0077] However, in a gate-last fabrication flow, upon formation of the slit openings, the wordline and BSG layers 12a are subsequently removed by a wet etch chemistry introduced through the slit openings to form a plurality of voids (or empty spaces). Ion implantation can then be applied to form a doped region (e.g., ACS region 16) at the bottom of each of the slit openings. After the implantation step, the wordline and BSG layers 12a are reformed via filling the voids with a high-K layer plus metal layer through the slit openings. Next, a dielectric spacer, such as dielectric spacer 26, can be formed along the sides of the slit openings and over the doped region 16. Subsequently, an anisotropic plasma etch can be implemented to remove the bottom of the dielectric spacer 26 formed over the doped region 16 to expose the doped region 16. A conductive layer, such as conductive layer 30, can be deposited along the dielectric spacer 26 and fill the common source openings. The conductive layer 30 can then be recessed by an etching process, and a contact, such as contact 28, can be formed along the dielectric spacer 26 and over the conductive layer 30. Upon formation of the contact, the slit structures with the same profile as the slit structures 20a and 20b in Figure 9A The slit structures in the stack 500 are formed in the same profile as the slit structures 20a and 20b in

[0078] In Figure 10In some embodiments, a plurality of contact structures 22 can be formed in the staircase regions 100B and 100C. In some embodiments, a dielectric layer 24 can be formed on the substrate 10 prior to forming the contact structures 22. The dielectric layer 24 can further cover the staircase regions 100B and 100C. An imaging process can be applied to form a plurality of contact openings in the dielectric layer 24. The contact openings can land on the first and second insulating layers and further extend through the first and second insulating layers to expose the word line layers and the BSG layer 12a. A deposition process can then be applied to deposit a conductive material into the contact openings, and a CMP process can be applied to remove any excess conductive material on the top surface of the dielectric layer 24. Upon completion of the CMP process, the conductive material that remains in the contact openings becomes the contact structures 22. After forming the contact structures 22, the 3D-NAND memory device 100 is formed Figure 10 such as the 3D-NAND memory device 100 described in Figure 1A .

[0079] Figure 11 is a flowchart of a process 1100 for fabricating a 3D-NAND memory device 100 according to some embodiments. The process 1100 starts at step S1104, at which a plurality of first insulating layers and a dummy bottom select gate (BSG) layer can be formed on a substrate. The dummy BSG layer is arranged among the first insulating layers. In step S1106 of the process 1100, a first dielectric trench structure can be formed. The first dielectric trench structure extends through the dummy BSG layer and in a first direction of the substrate such that the dummy BSG layer is divided into two portions by the first dielectric trench structure. In some embodiments, steps S1104 and S1106 can be performed as described with reference to Figure 4A and 4B .

[0080] The process 1100 then proceeds to step S1108, at which a plurality of sacrificial word line layers and a plurality of second insulating layers are formed on the first insulating layers. The second insulating layers and the sacrificial word line layers are alternately arranged. In some embodiments, step S1108 can be performed as described with reference to Figure 5 .

[0081] In step S1110, a second dielectric trench structure can be formed. The second dielectric trench structure can extend through a sacrificial top select gate (TSG) layer in the sacrificial word line layer to separate the sacrificial TSG layer into two portions, and extend in a first direction of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second direction of the substrate. In some embodiments, prior to forming the second dielectric trench structure, a trim etch process can be applied to the first insulating layer, the dummy BSG layer, the second insulating layer, and the sacrificial word line layer to form the array region and the staircase region. In some embodiments, step S1110 can be performed as described with reference to Figure 6 , 7A and 7B.

[0082] Process 1100 proceeds to step S1112, where a channel structure, a dummy channel structure, and a slit structure can be formed. In some embodiments, prior to forming the slit structure, the dummy BSG layer and the sacrificial word line layer can be replaced with a BSG layer and a word line layer, respectively. In some embodiments, step S1112 can be performed as described with reference to Figure 8A , 8B , 9A, 9B, and 10.

[0083] It should be noted that additional steps can be provided before, during, and after process 1100, and that some of the steps described can be replaced by other steps, eliminated, or performed in a different order depending on the embodiment of process 1100. In one example, the staircase region can be formed after the second dielectric trench structure is formed. In another example, the channel structure can be formed before the staircase region is formed. In some embodiments, the dummy channel structure can be formed in the staircase region.

[0084] In subsequent process steps of process 1100, various additional interconnect structures (e.g., metallization layers having wires and / or vias) can be formed on 3D-NAND memory device 100. Such interconnect structures electrically connect 3D-NAND memory device 100 with other contact structures and / or active devices to form functional circuitry. Additional device features (such as passivation layers, input / output structures, etc.) can also be formed.

[0085] Various embodiments described herein provide several advantages over related memory devices. For example, related memory devices either have a lower storage cell density or have non-functional sub-storage blocks. In the disclosed 3D-NAND memory device, a storage block of storage cells can have a first dielectric trench structure placed in a bottom select gate (BSG) layer for separating the BSG layer into two portions and a second dielectric trench structure placed in a top select gate (TSG) layer for separating the TSG layer into two portions. The second dielectric trench structure is offset from the first dielectric trench structure. The disclosed configuration allows for a higher channel structure density in the storage block by dividing the storage block into three independent and functional sub-storage blocks.

[0086] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device, comprising: a stack of word line layers and insulating layers stacked alternately on a substrate; a first dielectric trench structure placed in a bottom select gate (BSG) layer in the word line layers to separate the bottom select gate layer and extending in a first direction of the substrate; a second dielectric trench structure placed in a top select gate (TSG) layer in the word line layers to separate the top select gate layer and extending in the first direction of the substrate, the second dielectric trench structure being offset from the first dielectric trench structure in a second direction of the substrate perpendicular to the first direction; a first slit structure placed in the stack, the first slit structure extending through the stack and along the first direction of the substrate; and a second slit structure placed in the stack, the second slit structure extending through the stack and along the first direction of the substrate, and wherein there is one of the first dielectric trench structure and one of the second dielectric trench structure between the first slit structure and the second slit structure. The first dielectric trench structure and the second dielectric trench structure are arranged between the first slit structure and the second slit structure in the second direction of the substrate.

2. The semiconductor device of claim 1, wherein, The first dielectric trench structure, the second dielectric trench structure, the first slit structure, and the second slit structure extend parallel to each other in the first direction of the substrate.

3. The semiconductor device of claim 2, wherein, 4. The semiconductor device of claim 3, further comprising: a plurality of channel structures formed on the substrate and also extending through the stack, the channel structures being arranged between the first slit structure and the second slit structure.

5. The semiconductor device of claim 4, further comprising: a plurality of dummy channel structures formed on the substrate and also extending through the stack, the dummy channel structures being arranged between the first slit structure and the second slit structure. The first dielectric trench structure extends across a first set of the dummy channel structures, and the second dielectric trench structure extends across a second set of the dummy channel structures.

6. The semiconductor device of claim 5, wherein, The top select gate layer is a highest word line layer of the word line layers.

7. The semiconductor device of claim 6, wherein, The bottom select gate layer is a lowest word line layer of the word line layers.

8. The semiconductor device of claim 7, wherein, 9. The semiconductor device of claim 8, further comprising: a first region defined by the first slit structure and the second dielectric trench structure; a second region defined by the first dielectric trench structure and the second dielectric trench structure; and a third region defined by the first dielectric trench structure and the second slit structure, wherein the first region, the second region, and the third region are configured to be operated independently. The channel structures and the dummy channel structures are arranged in 14 rows along the second direction of the substrate.

11. A method for manufacturing a semiconductor device, comprising:

10. The semiconductor device of claim 9, wherein, ​ ​ forming a plurality of first insulating layers and a dummy bottom select gate (BSG) layer on a substrate, the dummy bottom select gate layer being arranged between the first insulating layers; forming a first dielectric trench structure extending through the dummy bottom select gate layer and in a first direction of the substrate, the dummy bottom select gate layer being separated by the first dielectric trench structure; forming a plurality of sacrificial word line layers and a plurality of second insulating layers on the first insulating layers, the second insulating layers and the sacrificial word line layers being alternately arranged; forming a second dielectric trench structure extending through a sacrificial top select gate (TSG) layer in the sacrificial word line layers to separate the sacrificial top select gate layer and in the first direction of the substrate, the second dielectric trench structure being offset from the first dielectric trench structure in a second direction of the substrate; and forming a first slit structure and a second slit structure extending through the first insulating layers, the dummy bottom select gate layer, the sacrificial word line layers and the second insulating layers and further extending in the first direction of the substrate, and wherein there is one of the first dielectric trench structure and one of the second dielectric trench structure between the first slit structure and the second slit structure.

12. The method of claim 11, before the forming the second dielectric trench structure, the method further comprising: performing a trim etch process on the first insulating layers, the dummy bottom select gate layer, the sacrificial word line layers and the second insulating layers to form an array region and a step region on the substrate, the step region being placed at both sides of the array region.

13. The method of claim 12, further comprising: forming a channel structure in the array region, the channel structure extending from the substrate and through the first insulating layers, the dummy bottom select gate layer, the sacrificial word line layers and the second insulating layers; replacing the dummy bottom select gate layer with a bottom select gate layer, and replacing the sacrificial word line layers with word line layers; and forming a contact structure on the step region, the contact structure being connected to the bottom select gate layer and the word line layers in the step region.

14. The method of claim 13, wherein, the first dielectric trench structure and the second dielectric trench structure being arranged between the first slit structure and the second slit structure in the second direction of the substrate.

15. The method of claim 13, wherein, the first dielectric trench structure, the second dielectric trench structure, the first slit structure and the second slit structure extending parallel to each other in the first direction of the substrate.

16. A semiconductor device, comprising: a stack comprising word line layers and insulating layers alternately stacked on a substrate; a first slit structure placed in the stack, the first slit structure extending through the stack and in a first direction of the substrate; a second slit structure placed in the stack, the second slit structure extending through the stack and in the first direction of the substrate; a first dielectric trench structure arranged between the first slit structure and the second slit structure, placed in a bottom select gate (BSG) layer in the word line tiers to separate the bottom select gate layer, and extending in the first direction of the substrate; and a second dielectric trench structure arranged between the first slit structure and the second slit structure, placed in a top select gate (TSG) layer in the word line tiers to separate the top select gate layer and extending in the first direction of the substrate, the second dielectric trench structure being offset from the first dielectric trench structure in a second direction of the substrate, and wherein there is one of the first dielectric trench structure and one of the second dielectric trench structure between the first slit structure and the second slit structure.

17. The semiconductor device of claim 16, wherein, The first dielectric trench structure, the second dielectric trench structure, the first slit structure and the second slit structure extend parallel to each other in the first direction of the substrate.

18. The semiconductor device of claim 16, further comprising: a plurality of channel structures formed on the substrate and also extending through the word line tiers and the insulating layers in the stack; and a plurality of dummy channel structures formed on the substrate and also extending through the word line tiers and the insulating layers in the stack, the first dielectric trench structure extending across a first set of the dummy channel structures, and the second dielectric trench structure extending across a second set of the dummy channel structures.

19. The semiconductor device of claim 18, wherein, The channel structures and the dummy channel structures are arranged in 14 rows along the second direction of the substrate.

Images