Chip packaging, chip structure and manufacturing method thereof

Abstract

The present disclosure provides a chip package, a chip structure, and a manufacturing method thereof. The chip package is used in a power module and includes at least one thin die to reduce resistance when used as a power module; a drive circuit for controlling the at least one die; a protective layer formed over the at least one die and the drive circuit, the protective layer having multiple protective layer openings; a metal unit including at least one metal feature; and a plastic encapsulation layer encapsulating the at least one die, the drive circuit, the protective layer, and the metal unit. The chip package is connected to an external circuit via the at least one metal feature.

Description

[0001] Cross-references

[0002] This disclosure claims priority to Singapore Patent Application No. 10202010557R filed on October 24, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and more particularly to a chip package with an embedded leadframe, a chip structure, and a manufacturing method thereof. Background Art

[0004] Panel-level packaging involves dicing a wafer into numerous dies, arranging and attaching these dies to a carrier board, and packaging these dies simultaneously in a single process. As a recently emerging technology, panel-level packaging has garnered widespread attention. Compared to traditional wafer-level packaging, panel-level packaging offers advantages such as high production efficiency, low production costs, and suitability for large-scale production.

[0005] At the same time, the demand for chip packaging in today's power modules has increased significantly. However, traditional chip packaging still uses copper clips and wire bonding, so there are many disadvantages. For example, the copper clips are large in size, which makes it difficult to thin traditional chip packaging. Moreover, in traditional chip packaging, the copper clips located on the die may cause the die to crack due to its weight. This disadvantage becomes more serious when power modules require thinner chips. In addition, wire bonding may result in poor electrical and thermal performance of traditional chip packaging. Summary of the Invention

[0006] Therefore, the present application discloses a chip package, a chip structure and a manufacturing method thereof to solve one or more defects of traditional chip packaging, especially a chip structure and a packaged chip with an embedded lead frame having better electrical and thermal performance for power modules.

[0007] The present disclosure provides a chip package for a power module, comprising at least one die having opposing die active surfaces and die back surfaces, wherein the at least one die has a relatively thin thickness to reduce resistance when used as a power module; a drive circuit for controlling the at least one die, the drive circuit having opposing drive active surfaces and drive back surfaces; a protective layer formed on the die active surfaces and the drive active surfaces, the protective layer having a plurality of protective layer openings for exposing the die active surfaces and the drive active surfaces from the protective layer; a metal unit including at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front and connection pad back surfaces; and a plastic encapsulation layer for encapsulating the at least one die, the drive circuit, the protective layer, and the metal unit. The chip package is connected to an external circuit via the at least one metal feature.

[0008] The at least one die includes a first die and a second die, which respectively have a first die active surface and a second die active surface, wherein the first die, the second die and the driving circuit are surrounded by the metal unit, and the first die active surface, the second die active surface and the driving active surface are basically flush.

[0009] The chip package also includes a first conductive structure formed on at least one metal feature of the metal unit, the protective layer and the plastic encapsulation layer, wherein the first conductive structure is connected to the die active surface and the driving active surface, and is used to connect the at least one die and the driving circuit to the metal unit.

[0010] The first conductive structure has a plurality of conductive filled through-holes connected to the active surface of the die and the driving active surface, and a panel-level conductive layer is formed on at least one metal feature of the metal unit, the protective layer and the plastic encapsulation layer, wherein the conductive filled through-holes are formed by filling the openings of the protective layer with conductive material.

[0011] The chip package also includes a second conductive structure formed on at least one metal feature of the metal unit and the plastic layer, the second conductive structure and the first conductive structure are on opposite sides of the at least one bare die, wherein the second conductive structure is connected to the first conductive structure through at least one metal feature of the metal unit.

[0012] The first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the die active side and the die backside.

[0013] The second conductive structure is in direct contact with a backside of at least one die, and is used to electrically ground the backside of the chip package.

[0014] The chip package further includes forming at least one gap in the plastic layer for exposing the back side of the die from the plastic layer, wherein the at least one gap is filled with a conductive medium to form a conductive filled gap for connecting to the second conductive structure.

[0015] The chip package also includes an additional plastic encapsulation layer formed on the back side of the at least one die and encapsulated by the plastic encapsulation layer; and at least one gap in the additional plastic encapsulation layer, used to expose the back side of the die from the plastic encapsulation layer, wherein a conductive medium is filled in the at least one gap to form a conductive filled gap, which is used to connect to the second conductive structure.

[0016] The chip package also includes a first dielectric layer for encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for connecting to the external circuit; and a second dielectric layer for encapsulating the second conductive structure, wherein the second conductive structure is exposed from the second dielectric layer for connecting to an external component.

[0017] The present disclosure further provides a chip structure comprising at least one die having an opposing die active surface and a die back surface; a protective layer formed on the die active surface, the protective layer having a plurality of protective layer openings for exposing the die active surface from the protective layer; a metal unit, the metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front and connection pad back surfaces; a plastic layer for encapsulating the die, the protective layer, and the metal unit; and a first conductive structure formed on the at least one metal feature of the metal unit, the protective layer, and the plastic layer, wherein the first conductive structure is connected to the die active surface, for connecting the at least one die to the metal unit. The chip structure is connected to an external circuit via the at least one metal feature.

[0018] The external circuit includes a printed circuit board, and the first conductive structure is in direct contact with the printed circuit board for directly connecting the at least one bare die to the printed circuit board.

[0019] The chip structure also includes a second conductive structure formed on at least one metal feature of the metal unit and the plastic encapsulation layer, the second conductive structure and the first conductive structure are on opposite sides of the at least one bare die, wherein the second conductive structure is connected to the at least one bare die through the first conductive structure and at least one metal feature of the metal unit, for electrically grounding the chip structure.

[0020] The second conductive structure is in direct contact with a backside of at least one die, and is configured to transfer heat from the backside of the die to out of the chip structure.

[0021] The first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the die active side and the die backside.

[0022] The present disclosure also aims to provide a method for manufacturing a chip package for a power module, comprising providing at least one bare chip having relative bare chip active surfaces and bare chip back surfaces, wherein the thickness between the bare chip active surface and the bare chip back surface of the at least one bare chip is relatively thin, for reducing the resistance of the power module; providing a driving circuit for controlling the at least one bare chip, which has relative driving active surfaces and driving back surfaces; forming a protective layer on the bare chip active surface and the driving active surface, which has a plurality of protective layer openings for exposing the bare chip active surface and the driving active surface from the protective layer; placing a metal unit around the at least one bare chip and the driving circuit, wherein the metal unit has at least one metal feature, the at least one metal feature has at least one connection pad, the at least one connection pad has relative connection pad front and connection pad back surfaces; forming a plastic encapsulation layer for encapsulating the at least one bare chip, the driving circuit, the protective layer and the metal unit; and connecting the chip package to an external circuit through the at least one metal feature of the metal unit.

[0023] The manufacturing method also includes forming a first conductive structure so as to directly contact the front surface of the connection pad of the at least one connection pad, the second surface of the protective layer, and the front surface of the plastic layer, wherein the front surface of the connection pad, the second surface of the protective layer, and the front surface of the plastic layer are basically flush.

[0024] The manufacturing method further includes forming a second conductive structure in direct contact with the back surface of the at least one connection pad and the back surface of the plastic layer, wherein the back surface of the plastic layer is opposite to the front surface of the plastic layer.

[0025] The manufacturing method further includes forming at least one gap in the plastic encapsulation layer to expose the back side of the at least one die; and filling the at least one gap with a conductive medium to form a conductive filled gap connected to the second conductive structure.

[0026] The manufacturing method also includes forming a first dielectric layer encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for connection to the external circuit; and forming a second dielectric layer encapsulating the second conductive structure, wherein the second conductive structure is exposed from the second dielectric layer for connection to an external component. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a flow chart of a chip packaging method proposed according to an exemplary embodiment of the present disclosure;

[0028] Figures 2 to 25 is based on Figure 1 A schematic diagram of a process for manufacturing a panel assembly using a chip packaging method;

[0029] Figure 26 is based on Figures 2 to 25 Schematic diagram of the packaged chip formed after cutting the manufactured panel assembly;

[0030] Figure 27 is a flow chart of another chip packaging method proposed according to an exemplary embodiment of the present disclosure;

[0031] Figures 28 to 30 is based on Figure 27 A schematic diagram of an additional process for manufacturing another panel assembly using the chip packaging method;

[0032] Figure 31 is based on Figures 28 to 30 Schematic diagram of the packaged chip formed after cutting the manufactured panel assembly;

[0033] Figures 32 to 34 yes Figures 28 to 30 A flow chart of another variation of the panel assembly;

[0034] Figure 35 is based on Figures 32 to 34 Schematic diagram of packaged chips formed after cutting a variant of the manufactured panel assembly;

[0035] Figure 36 is based on Figure 1 A schematic diagram of a packaged chip having two wafers manufactured by the chip packaging method in FIG.

[0036] FIG37 is a schematic diagram of a chip package for a power module according to an exemplary embodiment of the present disclosure;

[0037] FIG38 is a schematic diagram of another chip package for a power module according to an exemplary embodiment of the present disclosure;

[0038] FIG39 is a schematic diagram of another chip package for a power module according to an exemplary embodiment of the present disclosure;

[0039] Figure 40 A schematic diagram of a traditional chip package used in power modules.

[0040] Reference numerals:

[0041] 10: Chip packaging method, 20: Chip packaging method, 100: Wafer, 1001: Wafer active surface, 1002: Wafer backside, 103: Electrical connection point, 105: Insulation layer, 106: Wafer conductive trace, 107: Protective layer, 109: Protective layer opening, 109a: Protective layer opening lower surface, 109b: Protective layer opening upper surface, 109c: Protective layer opening sidewall, 111: Conductive filled via, 113: Bare die, 1131: Bare die active surface, 113 2: back side of die, 117: (first) carrier, 1171: front side of carrier, 1172: back side of carrier, 118: (second) carrier, 121: adhesive layer, 122: adhesive layer, 123: plastic layer, 1231: front side of plastic layer, 1232: back side of plastic layer, 124: conductive filled via, 125: (first) panel-level conductive trace, 127: first panel-level conductive pillar, 129: first conductive structure, 130: wafer conductive layer, 140: second conductive structure;142: Second panel-level conductive trace, 144: Second panel conductive post, 146: First dielectric layer, 150: Panel assembly, 152: Panel assembly, 154: Panel assembly, 160: Dry film, 162: Patterned dry film, 163: Dry film opening, 164: Dry film, 166: Patterned dry film, 167: Dry film opening, 170: Second dielectric layer, 1701: Second dielectric layer front side, 1702: Second dielectric layer back side, 200: Metal frame, 201: Connection pad , 2011: Connection pad front, 2012: Connection pad back, 202: Void, 203: Connecting rod, 300: Temporary support plate, 301: Adhesive layer, 400: Packaged chip, 402: Side surface, 410: Printed circuit board (PCB) / substrate, 412: Solder bump or solder ball, 420: Passive component, 430: Heat sink, 440: Grounding tag, 500: Packaged chip, 502: Void, 504: Conductive filling void, 550: Packaged chip, 600 : Packaged chip, 602: First die, 6021: Active surface of first die, 6022: Back side of first die, 604: Second die, 6041: Active surface of second die, 6042: Back side of second die, 610: Plastic layer, 700: Chip package, 710: Panel assembly, 720: Drive circuit, 7201: Drive active surface, 7202: Drive back side, 730: Space, 740: Resistor, 742: Capacitor, 744: Inductor, 800: Core Chip packaging, 850: Chip packaging, 900: Traditional chip packaging, 902: First die, 9021: Active surface of first die, 9022: Back side of first die, 904: Second die, 9041: Active surface of second die, 9042: Back side of second die, 906: Copper clip, 908: Back metal layer of die, 910: Wire bond, 912: Lead frame, 916: Die attach material, 918: Spot plating, 920: Molding layer, 922: Solder bumps or solder balls. DETAILED DESCRIPTION

[0042] In order to make the technical solution of the present disclosure clearer and the technical effects more obvious, the following detailed and specific description and illustration of the preferred embodiments of the present disclosure are given in conjunction with the accompanying drawings. It should not be understood that the following description is the only implementation form of the present disclosure or a limitation to the present disclosure.

[0043] Figure 1 is a flowchart of a chip packaging method 10 according to embodiment 1 of the present disclosure. Figures 2 to 25 is based on Figure 1 Schematic diagram of the process of manufacturing a panel assembly using the chip packaging method in FIG.

[0044] Reference Figure 1 The chip packaging method 10 disclosed herein comprises the following steps:

[0045] Step S1 , providing a wafer 100 .

[0046] like Figure 2 As shown, at least one wafer 100 is provided. The wafer 100 has an active surface 1001 and a back surface 1002. The wafer 100 includes multiple dies 113, wherein the active surface of each die constitutes the active surface 1001 of the wafer. The active surface of each die in the wafer 100 is formed into a series of active components and passive components through a series of processes such as doping, deposition, and etching. Active components include diodes, transistors, etc., and passive components include transformers, capacitors, resistors, inductors, etc. These active and passive components are connected by connecting wires to form functional circuits, thereby realizing various functions. The active surface 1001 of the wafer also includes electrical connection points 103 for leading out the functional circuits and an insulating layer 105 for protecting the electrical connection points 103.

[0047] Step S2 , applying a protective layer 107 on the active surface 1001 of the wafer.

[0048] Figure 3a-3b The optional process step of applying a protective layer 107 to the active surface 1001 of the wafer is shown:

[0049] like Figure 3a As shown, a protective layer 107 is applied to the active surface 1001 of the wafer.

[0050] Preferably, the protective layer 107 is applied to the active surface 1001 of the wafer by lamination.

[0051] Optionally, before applying the protective layer 107 to the active surface 1001 of the wafer, the active surface 1001 of the wafer and / or the side of the protective layer 107 applied to the wafer 100 is subjected to physical and / or chemical treatment to strengthen the bond between the protective layer 107 and the wafer 100. Optional treatment methods include plasma surface treatment to roughen the surface and increase the bonding area and / or chemical promoter treatment to introduce promoter-modifying groups, such as surface modifiers with both organic and inorganic affinity groups, between the wafer 100 and the protective layer 107 to increase the adhesion between the organic / inorganic interface layer.

[0052] like Figure 3b As shown, a protection layer opening 109 is formed on the surface of the protection layer 107 .

[0053] A protective layer opening 109 is formed at a position of the protective layer 107 corresponding to the electrical connection point 103 on the wafer active surface 1001 , exposing the electrical connection point 103 on the wafer active surface 1001 .

[0054] Preferably, there is a one-to-one correspondence between the protective layer openings 109 and the electrical connection points 103 on the wafer active surface 1001 .

[0055] Optionally, each of the protection layer openings 109 in at least a portion of the protection layer openings 109 corresponds to a plurality of electrical connection points 103 .

[0056] Optionally, at least a portion of the electrical connection points 103 corresponds to a plurality of protection layer openings 109 .

[0057] Optionally, at least a portion of the protection layer openings 109 do not have corresponding electrical connection points 103 , or at least a portion of the electrical connection points 103 do not have corresponding protection layer openings 109 .

[0058] The protective layer opening is formed by laser patterning or photolithography patterning.

[0059] If laser patterning is used to form the protective layer openings, preferably, before applying the protective layer 107 to the wafer active surface 1001, an electroless plating process is performed on the wafer active surface 1001 to form a conductive covering layer over the electrical connection points 103. Optionally, the conductive covering layer is one or more layers of Cu, Ni, Pd, Au, or Cr; preferably, the conductive protective layer is a Cu layer; and the thickness of the conductive protective layer is preferably 2-3 μm. The conductive covering layer is not shown in the figure. The conductive covering layer protects the electrical connection points 103 on the wafer active surface 1001 from laser damage during the subsequent protective layer opening formation step.

[0060] Preferably, Figure 3b As shown in the partial enlarged view in FIG, there is a gap between the lower surface 109 a of the protective layer opening and the insulating layer 105. Preferably, the lower surface 109 a of the protective layer opening is located near the center of the electrical connection point 103.

[0061] In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of ​​the upper surface 109b of the protective layer opening is larger than the area of ​​the lower surface 109a of the protective layer opening, and the area ratio of the lower surface 109a of the protective layer opening to the upper surface 109b of the protective layer opening is 60% to 90%.

[0062] At this time, the slope of the sidewall 109 c of the protective layer opening can facilitate the filling of the conductive material. During the filling process, the conductive material will be uniformly and continuously formed on the sidewall.

[0063] Optionally, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the carrier is peeled off.

[0064] Optionally, a conductive medium is filled in the protective layer opening 109, so that the protective layer opening 109 becomes a conductive filled via 124. At least a portion of the conductive filled via 111 is connected to the electrical connection point 103 on the wafer active surface 1001. The conductive filled via 111 extends the electrical connection point 103 on the wafer active surface 1001 to the surface of the protective layer, and the protective layer is formed around the conductive filled via 111. The conductive medium can be gold, silver, copper, tin, aluminum, or a combination thereof, or other suitable conductive materials formed in the protective layer opening 109 by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes to form the conductive filled via 111.

[0065] Figures 4a-4c Another optional process step for applying a protective layer 107 on the active surface 1001 of the wafer is shown:

[0066] like Figure 4a As shown, a wafer conductive layer 130 is formed on the wafer active surface 1001 .

[0067] Wafer conductive layer 130 is wafer conductive trace 106. Wafer conductive trace 106 can be made of copper, gold, silver, tin, aluminum, or a combination thereof, or other suitable conductive materials formed by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes.

[0068] At least a portion of the wafer conductive traces 106 are connected to at least a portion of the electrical connection points 103 on the wafer active surface 1001 .

[0069] Optionally, the wafer conductive traces 106 interconnect and lead out a plurality of electrical connection points 103 in at least a portion of the wafer active surface 1001, thereby forming a die. Figure 6b Schematic diagram of the bare die A.

[0070] The formation of the chip conductive traces 106 can reduce the number of protective layer openings 109 formed in the subsequent process. The chip conductive traces 106 are used to first interconnect multiple electrical connection points 103 according to the circuit design, eliminating the need to form a protective layer opening 109 on each electrical connection point 103.

[0071] Optionally, the chip conductive traces 106 lead out at least a portion of the electrical connection points 103 on the chip active surface 1001 separately, and the bare chip formed thereby is shown in FIG. Figure 6b Schematic diagram of the bare die in B.

[0072] The formation of the chip conductive trace 106 helps to reduce the difficulty of the subsequent formation process of the protective layer opening 109. Due to the existence of the chip conductive trace 106, the lower surface 109a of the protective layer opening can have a larger area. Correspondingly, the protective layer opening 109 can have a larger area, especially on the chip 100 with a smaller exposed electrical connection point 103, making the formation of the protective layer opening possible.

[0073] Although not shown in the figure, it can be understood that the wafer conductive traces 106 lead out a portion of the electrical connection points 103 on the wafer active surface 1001 separately and interconnect and lead out another portion of the electrical connection points 103 on the wafer active surface 1001.

[0074] like Figure 4b As shown, a protective layer 107 is applied over the wafer active surface 1001 and the wafer conductive layer 130 .

[0075] In one embodiment, the protective layer 107 is applied by lamination.

[0076] Optionally, before applying the protective layer 107, the wafer active surface 1001 and / or the side of the protective layer 107 applied to the wafer 100 is subjected to physical and / or chemical treatment to strengthen the bond between the protective layer 107 and the wafer 100. Optional treatment methods include plasma surface treatment to roughen the surface and increase the bonding area and / or chemical promoter treatment to introduce promoter-modifying groups, such as surface modifiers with both organic and inorganic affinity groups, between the wafer 100 and the protective layer 107 to increase the adhesion between the organic / inorganic interface layer.

[0077] like Figure 4c As shown, a protection layer opening 109 is formed on the surface of the protection layer 107 .

[0078] At least a portion of the protective layer opening 109 is located corresponding to the wafer conductive layer 130 , and the wafer conductive layer 130 is exposed through the protective layer opening 109 ; the protective layer opening 109 has a protective layer opening lower surface 109 a and a protective layer opening upper surface 109 b .

[0079] In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of ​​the upper surface 109b of the protective layer opening is larger than the area of ​​the lower surface 109a of the protective layer opening. At this time, the slope of the side wall 109c of the protective layer opening can facilitate the filling of the conductive material. During the filling process, the conductive material will be evenly and continuously formed on the side wall.

[0080] Preferably, the contact area of ​​a single contact region between the wafer conductive layer 130 and the electrical connection point 103 is smaller than the contact area of ​​a single contact region between the wafer conductive layer 130 and the protective layer opening 109 .

[0081] When the chip 100 is a type in which the exposed electrical connection point 103 is relatively small in area, a conductive layer is formed on the active surface 1001 of the chip, and then a protective layer opening is formed. This can effectively reduce the difficulty of forming the protective layer opening and avoid the protective layer opening 109 being difficult to form due to the lower surface 109a of the protective layer opening being too small.

[0082] The protective layer opening is formed by laser patterning or photolithography patterning.

[0083] Optionally, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the carrier is peeled off.

[0084] Optionally, a conductive medium is filled in the protective layer opening 109 , so that the protective layer opening 109 becomes a conductive filled via 124 , at least a portion of the conductive filled via 124 is connected to the wafer conductive layer 130 , and the protective layer surrounds the conductive filled via 124 .

[0085] Figures 5a to 5c A further optional process step of applying a protective layer 107 on the active surface 1001 of the wafer is shown.

[0086] like Figure 5a As shown, wafer conductive traces 106 are formed on the active surface 1001 of the wafer.

[0087] The wafer conductive traces 106 may be made of copper, gold, silver, tin, aluminum, or a combination thereof, or other suitable conductive materials formed by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes.

[0088] The at least one portion of the wafer conductive traces 106 may interconnect a plurality of the electrical connection points 103 in at least a portion and lead out.

[0089] The at least one portion of the wafer conductive traces 106 may also be formed by separately leading out at least one portion of the electrical connection points 103. Figure 6c Schematic diagram of the bare die in B.

[0090] like Figure 5b As shown, wafer conductive studs 111 are formed on the pads or connection points of the wafer conductive traces 106 .

[0091] The shape of the wafer conductive protrusion 111 can be round or other shapes such as oval, square, linear, etc. The wafer conductive protrusion 111 can be made of one or more layers of copper, gold, silver, tin, aluminum, or a combination thereof, or other suitable conductive materials formed by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes.

[0092] Optionally, the conductive protrusion 111 of the chip can also be directly formed at the electrical connection point 103 on the active surface 1001 of the chip, and the electrical connection point 103 is led out, and the bare chip thus formed is shown in FIG. Figure 6c Schematic diagram of the bare die in C.

[0093] The wafer conductive traces 106 and / or the wafer conductive bumps 111 are referred to as a wafer conductive layer 130 .

[0094] like Figure 5c As shown, a protective layer 107 is applied over the conductive layer 130 of the wafer.

[0095] The protection layer 107 is applied on the wafer conductive layer 130 to cover the wafer conductive layer 130 .

[0096] In one embodiment, the protective layer is applied by lamination.

[0097] In one embodiment, the protective layer 107 is applied so that the protective layer 107 completely covers the wafer conductive layer 130 . In this case, after the protective layer 107 is applied, the thickness of the protective layer 107 is reduced to expose the surface of the wafer conductive layer.

[0098] In another embodiment, the thickness of the applied protection layer 107 is just enough to expose the surface of the wafer conductive layer 130 .

[0099] Optionally, before applying the protective layer 107, the wafer active surface 1001 on which the wafer conductive layer 130 is formed and / or the side of the protective layer 107 applied to the wafer 100 are subjected to physical and / or chemical treatment to strengthen the bond between the protective layer 107 and the wafer 100. Optional treatment methods include plasma surface treatment to roughen the surface and increase the bonding area and / or chemical promoter treatment to introduce promoter-modifying groups, such as surface modifiers with both organic and inorganic affinity groups, between the wafer 100 and the protective layer 107 to increase the adhesion between the organic / inorganic interface layer.

[0100] In step S2, during the process of applying the protective layer 107 to the active surface 1001 of the chip, the protective layer 107 can protect the active surface 1131 of the die from the infiltration of the molding material during the molding process, thereby protecting the active surface 1131 of the die from damage; at the same time, during the molding process, the molding pressure is not likely to cause the die 113 to move on the carrier (or called the first carrier) 117; in addition, it can also reduce the alignment accuracy requirements of the subsequent panel-level conductive layer formation process.

[0101] The protective layer 107 is made of insulating material, such as BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole, polymer matrix dielectric film, organic polymer film, or other materials with similar insulating and structural properties, and is formed by lamination, coating, printing, etc.

[0102] Preferably, the Young's modulus of the protective layer 107 is in the range of 1000 to 20000 MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000 to 10000 MPa; further preferably, the Young's modulus of the protective layer 107 is in the range of 1000 to 7000, 4000 to 7000 or 4000 to 8000 MPa; in the best embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.

[0103] Preferably, the thickness of the protective layer 107 is in the range of 15 to 50 μm; more preferably, the thickness of the protective layer is in the range of 20 to 50 μm; in a preferred embodiment, the thickness of the protective layer 107 is 35 μm; in another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in yet another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

[0104] When the Young's modulus of protective layer 107 is in the range of 1000-20000 MPa, on the one hand, protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide sufficient support for the conductive layer formed on its surface. Furthermore, when the thickness of protective layer 107 is in the range of 15-50 μm, it ensures that protective layer 107 can provide sufficient cushioning and support.

[0105] In particular, some chip types require both a thin die for packaging and a conductive layer with a certain thickness to generate a high electrical flux. In this case, the thickness of protective layer 107 is preferably in the range of 15 to 50 μm, and the Young's modulus of protective layer 107 is in the range of 1000-10000 MPa. The soft and flexible protective layer 107 forms a buffer between the die 113 and the conductive layer formed on its surface. This prevents excessive pressure on the die 113 during chip use, preventing the pressure of the thick conductive layer from causing the die 113 to break. Furthermore, protective layer 107 possesses sufficient material strength to provide adequate support for the thick conductive layer.

[0106] When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa, and the thickness of the protective layer 107 is 20-50 μm, due to the material properties of the protective layer 107, the protective layer 107 can effectively protect the die against the ejector pin pressure of the die transfer equipment during the subsequent die transfer process.

[0107] The die transfer process involves rearranging and bonding the separated die 113 to the carrier 117 (reconstruction process). This process requires the use of a die transfer machine (bonder machine). The die transfer machine includes ejector pins that lift the die 113 off the wafer 100. A bonder head then sucks the lifted die 113 up and transfers it to the carrier 117 for bonding.

[0108] During the process of the ejector pins lifting the die 113, the die 113, especially the thin die 113, is fragile and easily broken by the lifting pressure of the ejector pins. The protective layer 107 with material properties can protect the fragile die 113 in this process and keep the die 113 intact even under a large lifting pressure.

[0109] Preferably, the protective layer 107 is an organic / inorganic composite material layer including filler particles. Furthermore, the filler particles are inorganic oxide particles; further, the filler particles are SiO2 particles; in one embodiment, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, such as SiO2 mixed with TiO2 particles. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, such as SiO2 mixed with TiO2 particles, are spherical or quasi-spherical. In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, such as SiO2 mixed with TiO2 particles, have a filling amount of 50% or more.

[0110] Organic materials have the advantages of being easy to operate and apply. The bare die 113 to be encapsulated is an inorganic material such as silicon. When the protective layer 107 is made of organic material alone, due to the differences in the material properties between organic materials and inorganic materials, the encapsulation process will be difficult and the encapsulation effect will be affected. By using an organic / inorganic composite material with inorganic particles added to the organic material, the material properties of the organic material can be modified, making the material have the characteristics of both organic and inorganic materials.

[0111] Especially the coefficient of thermal expansion (CTE) of the material. The silicon die 113 has a relatively low coefficient of thermal expansion, usually about 3 ppm / K. The protective layer 107 being an organic / inorganic composite material layer including filler particles can reduce the coefficient of thermal expansion of the protective layer, reducing the property differences between the organic layer and the inorganic layer in the encapsulation structure.

[0112] In a preferred embodiment, when (T < Tg), the range of the coefficient of thermal expansion of the protective layer 107 is 3 - 10 ppm / K; in a preferred embodiment, the coefficient of thermal expansion of the protective layer 107 is 5 ppm / K; in a preferred embodiment, the coefficient of thermal expansion of the protective layer 107 is 7 ppm / K; in a preferred embodiment, the coefficient of thermal expansion of the protective layer 107 is 10 ppm / K.

[0113] In the subsequent plastic encapsulation process, the die 113 with the protective layer 107 applied will expand and contract correspondingly during the heating and cooling processes of the plastic encapsulation. When the coefficient of thermal expansion of the protective layer 107 is in the range of 3 - 10 ppm / K, the degrees of expansion and contraction between the protective layer 107 and the die 113 remain relatively consistent, and the interfacial stress is not easily generated at the connection interface between the protective layer 107 and the die 113, and the bond between the protective layer 107 and the die 113 is not easily damaged, making the encapsulated chip structure more stable.

[0114] During the use of the encapsulated chip, it often needs to undergo thermal cycling. The coefficient of thermal expansion of the protective layer 107 ranges from 3 - 10 ppm / K and has the same or similar coefficient of thermal expansion as the die 113. During the thermal cycling process, the protective layer 107 and the die 113 maintain relatively consistent degrees of expansion and contraction, avoiding the accumulation of interfacial fatigue at the interface between the protective layer 107 and the die 113, making the encapsulated chip durable and extending the service life of the chip.

[0115] On the other hand, if the coefficient of thermal expansion of the protective layer is too small, it is necessary to fill too many filler particles in the composite material of the protective layer 107. While further reducing the coefficient of thermal expansion, it will also increase the Young's modulus of the material, reducing the flexibility of the protective layer material and making it too rigid, resulting in poor buffering effect of the protective layer 107. It is optimal to limit the coefficient of thermal expansion of the protective layer to 5 - 10 ppm / k.

[0116] When the step of forming a protective layer opening by laser patterning is included, preferably, the diameter of the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, is less than 3 μm, and preferably, the diameter of the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, is between 1 and 2 μm.

[0117] Controlling the diameter of the filler particles to be less than 3 μm is beneficial to forming a protective layer opening with smoother side walls on the protective layer 107 during the laser patterning process, so that the material can be fully filled during the conductive material filling process, avoiding the situation where the protective layer opening side wall 109c with large-sized bumps cannot be filled with conductive material on the back side of the side wall blocked by the protrusion, thereby affecting the conductive performance of the conductive filled through hole 124.

[0118] At the same time, the filling size of 1 to 2 μm will expose small-particle fillers during the laser patterning process, so that the side wall 109c of the protective layer opening has a certain degree of roughness. This side wall with a certain degree of roughness will have a larger contact area with the conductive material and a closer contact, forming a conductive filled through hole 124 with good conductive performance.

[0119] The diameter of the filler mentioned above is the average value of the particle diameter.

[0120] Optionally, the tensile strength of the protective layer 107 ranges from 20 to 50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

[0121] Optionally, after applying the protective layer 107 on the active surface 1001 of the wafer, the back surface 1002 of the wafer is ground to thin the wafer 100 to a desired thickness.

[0122] Modern electronic devices are becoming smaller and lighter, and chips are becoming thinner. During this process, wafer 100 may need to be thinned to a very thin thickness. However, thin wafers 100 are difficult to process and transfer, and the grinding and thinning process is complex, making it often difficult to thin wafer 100 to the desired thickness. When a protective layer 107 is provided on the surface of wafer 100, the material properties of protective layer 107 provide support for wafer 100, reducing the difficulty of processing, transferring, and thinning wafer 100.

[0123] In step S3 , the wafer 100 with the protective layer 109 applied thereon is cut into dies 113 with the protective layer 109 .

[0124] like Figure 6aAs shown, the wafer 100 with the protective layer 107 applied thereon is cut along the dicing streets to obtain a plurality of die 113 with the protective layer formed thereon. The die 113 has a die active surface 1131 and a die back surface 1132 .

[0125] like Figure 6b As shown, the wafer 100 having a conductive layer 130 formed thereon and a protective layer 107 applied thereon with protective layer openings 109 is cut along the sawing lines to obtain a plurality of dies 113 . The dies 113 have an active surface 1131 and a back surface 1132 .

[0126] in, Figure 6b The die diagram A in the middle shows that the wafer conductive traces 106 interconnect and lead out multiple electrical connection points 103 on the die active surface 1131 .

[0127] Figure 6b The middle die diagram B shows that the wafer conductive traces 106 lead out the electrical connection points 103 on the die active surface 1131 separately.

[0128] like Figure 6c As shown, the wafer 100 formed with the wafer conductive layer 130 and the protective layer 107 is cut along the dicing streets to obtain a plurality of dies 113 . The dies 113 have a die active surface 1131 and a die back surface 1132 .

[0129] in, Figure 6c The die diagram A in the middle shows that the wafer conductive traces 106 interconnect and lead out multiple electrical connection points 103 on the die active surface 1131 .

[0130] Figure 6c The middle die diagram B shows that the wafer conductive traces 106 lead out the electrical connection points 103 on the die active surface 1131 separately.

[0131] Figure 6c The middle die diagram C shows that the conductive bumps 111 of the chip are directly formed at the electrical connection points 103 on the active surface 1001 of the chip, and the electrical connection points 103 are led out.

[0132] Optionally, before the step of cutting the wafer 100 to separate the die 113, the step also includes performing plasma surface treatment on the side of the wafer 100 with the protective layer 107 applied thereto to increase the surface roughness, so as to increase the adhesion of the die 113 to the carrier 117 in subsequent processes and to prevent the die 113 from moving under the pressure of the plastic package.

[0133] Due to the material properties of the protection layer, during the dicing process of the wafer 100 , the separated dies 113 are free of burrs and chip debris.

[0134] It is understood that, if the process permits, and based on specific practical circumstances, a wafer conductive layer 130 and / or a protective layer 107 may be formed on the active surface 1131 of each die 113 after the wafer 100 is cut into die 113 to be packaged. The wafer conductive layer 130 refers to the conductive layer formed before the die 113 cut from the wafer 100 are mounted on a carrier.

[0135] Step S4: providing a metal structure.

[0136] according to Figure 7 In the embodiment shown, the metal structure is a metal frame 200, which is composed of an array of metal units. The metal frame 200 can use the existing lead frame in the industry, or it can be formed by etching or mechanical stamping a piece or piece of metal according to actual needs. The metal to be engraved can be a single metal, such as copper, or an alloy. A second metal, such as nickel and / or gold, can be partially or completely coated on the surface of the metal to protect the metal sheet from environmental corrosion, such as oxidation. In some embodiments, the thickness of the metal is not less than the thickness of the bare chip 113. In other embodiments, the thickness of the metal may initially be less than the thickness of the bare chip 113, but after the bare chip 113 is ground to reduce the thickness of the packaged chip, the thickness of the metal and the bare chip 113 will be substantially the same. The metal to be engraved can be rectangular, square or other shapes, such as Figure 7 As shown in the figure, the metal is engraved to include 4 identical metal units, and the outer contour of each metal unit is a rectangle. This is also exemplary. The number of metal units is not limited to 4 and can be set according to actual needs. The shape of the metal unit can also be rectangular or other shapes. The blank area in the metal unit indicates that the metal is completely etched away, and the retained metal part includes metal features. Different metal features can bring different performance improvements.

[0137] The lead frame will be embedded in the plastic layer 1213 described below; therefore, it is also called an embedded lead frame. Alternatively, the metal frame 200 may also include a molded interconnect substrate or other conductive substrate having the same or similar functions as the lead frame.

[0138] exist Figure 7The metal features include at least one connection pad 201, which is arranged inside the outline edge of the metal frame 200 and can also be arranged at other locations according to actual needs. The connection pads 201 are connected by connecting rods 203 of metal that have not been etched. The connection pads 201 are equivalent to the pins of the packaged bare die. According to the present disclosure, after the bare die 113 is packaged, the connection pads 201 are exposed. The packaged bare die 113 is soldered to the circuit board through these connection pads 201 to achieve connection with other circuit components. The connecting rods 203 are retained during the metal engraving to ensure that the connection pads 201 and other features formed by the engraving are connected to the outer contour line of the metal frame 200. This ensures that the features engraved thereon will not fall off when the metal frame 200 is transferred. Optionally, the metal sheet can be mounted on a temporary support for engraving. After the engraving is completed, the support is used to transfer the position of the metal frame. This method does not require engraving connecting wires / connecting rods.

[0139] like Figure 7 Each metal unit in the metal frame 200 shown includes a void 202, which is shown as a blank area in the figure. This void area is formed by completely etching a portion of the metal. Its area is larger than the surface area of ​​the die 113, so that the die 113 and the metal frame 200 are attached to the carrier in the subsequent steps without contacting the die 113. According to the example in the figure, each metal unit includes one void 202. In other examples, a metal unit may also include two or more voids 202, each void 202 accommodating one or more die 113. Adjacent metal frames 200 have a common outer contour edge, such as Figure 7 As shown, the metal frame 200 at the upper left corner and the metal frames 200 on its right and bottom sides each have a common outer contour edge, so that all the metal frames 200 are connected into one body.

[0140] like Figure 7 The metal frame 200 of the present disclosure shown is only exemplary. The area of ​​a whole piece of metal can be the same as the surface area of ​​the carrier 117, and the shape is also the same as the shape of the carrier 117, preferably a rectangle or an oblong, but it can also be designed into other shapes according to actual needs. However, it was found during the experiment that when the area of ​​the carrier 117 is relatively large, if a metal of the same size as the carrier 117 is used to etch the metal frame 200, since the metal is relatively thin, when its area is large, it will easily cause deformation during the transfer process, making it difficult to operate. Therefore, preferably, two or more pieces of metal whose total area is the same as the surface area of ​​the carrier 117 can be used, and one or more metal frames 200 can be etched on each piece of metal. During the manufacturing process, each piece of etched metal is sequentially placed on the carrier 117 and pieced together to have the same surface area as the carrier 117.

[0141] In step S5 , the bare chip 113 with the protection layer 107 and the metal structure are placed on the carrier 117 .

[0142] Figure 8a-Figure 9 A preferred embodiment of placing the metal frame on the carrier plate in step S5 is shown.

[0143] Since the metal material used in the metal frame 200 is relatively thin, especially when the area is relatively large, the surface is easily bent and deformed when being taken and placed. Therefore, in order to more conveniently and accurately stick the metal frame 200 to the carrier board 117 while maintaining a flat surface, the following method can be used:

[0144] like Figure 8a and 8b As shown, a temporary support plate 300 is provided, on which an adhesive layer 301 is formed. The metal frame 200 to be patterned is attached to the temporary support plate 300 by gluing. Alternatively, the temporary support plate 300 may be omitted, and the thick adhesive layer 301 may be used directly as a temporary support plate 300 to transport the patterned metal frame 200. Preferably, the temporary support plate 300, the adhesive layer 301, and the carrier plate 117 have the same shape and size. In addition, the two opposing surfaces of the metal frame 200, where the connection pads 201 are in contact with and away from the adhesive layer 301, are defined as the connection pad back surface 2012 and the connection pad front surface 2011, respectively.

[0145] Preferably, Figure 8a As shown, after the metal frame 200 is pasted onto the temporary support plate 300, the connecting rods 203 are cut to separate the metal frame 200. Optionally, each connecting rod 203 connecting each metal unit is cut, thereby separating the metal units pasted onto the temporary support plate 300 from each other; or the connecting rods 203 in a specific area can be cut to separate the metal frame 200 on the entire temporary support plate 300 into two parts, four parts, six parts, or any other number of parts. Preferably, the cutting line is along the center line of the connecting rod 203. The advantage of this method is that during the packaging process, it is often necessary to undergo heating and cooling steps to separate an entire metal frame 200 into units with smaller areas, or directly separate them into metal units separated from each other. In this way, during the heating and cooling steps of the packaging, the metal frames 200 or metal units with smaller areas expand and contract independently of each other. Due to the smaller area, the degree of expansion and contraction of each unit or unit is smaller, making the packaging process easier to control and operate.

[0146] Preferably, Figure 8b As shown, after the metal frame 200 is attached to the temporary support plate 300, the connecting rod 203 is separated and removed from the metal frame 200, thereby separating the metal units in the metal frame 200. Figure 8bIn the embodiment, the connection pads 201 are formed into independent parts. Since the features on the metal frame can be independent of each other, board-level testing can be performed before cutting, which can greatly reduce testing costs and time.

[0147] like Figure 9 As shown, a carrier 117 is provided. Carrier 117 has a carrier front 1171 and a carrier back 1172. Carrier 117 can be circular, triangular, quadrilateral, or any other shape. Carrier 117 can be the size of a small wafer substrate or a rectangular carrier of various sizes, particularly large sizes. Carrier 117 can be made of metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, carrier 117 is a large-sized quadrilateral panel made of stainless steel.

[0148] The carrier 117 has a carrier front 113 and a carrier back 115 , and the carrier front 113 is a plane.

[0149] The die 113 is bonded and fixed on the carrier 117 using the adhesive layer 121 .

[0150] The adhesive layer 121 can be formed on the front side of the carrier 1171 by lamination, printing, spraying, coating, etc. In order to facilitate separation of the carrier 117 from the back-molded die 113 in the subsequent process, the adhesive layer 121 is preferably made of an easily separable material, such as a thermally separable material.

[0151] The temporary support plate 300 is mounted with the side of the metal frame 200 facing the front side 1171 of the carrier. The surface area of ​​the temporary support plate 300 is the same as the surface area of ​​the carrier 117, and the shape is also the same. The two are aligned and in contact, and the metal frame 200 can be mounted on the adhesive layer 121. Then, the temporary support plate 300 is peeled off, and the adhesive layer 301 on the metal frame 200 is removed, and the mounting of the metal frame 200 is completed.

[0152] In this step, preferably, the metal frame 200 is aligned onto the carrier 117 through an alignment mark pre-formed on the carrier 117 and the metal frame 200 (the mark is not shown in the figure), and the metal frame 200 is adhered to the carrier 117 through the adhesive layer 301.

[0153] In addition, the metal foil or metal sheet can be attached to the temporary support plate 300 through the adhesive layer 301 on the temporary support plate 300, and then the metal foil or metal sheet can be etched into a desired pattern to form an engraved metal frame 200, and then the metal frame 200 can be transferred to the carrier 117.

[0154] The side of the metal frame 200 facing the carrier 117 is defined as the front side of the metal frame, and the side facing away from the carrier 117 is defined as the back side of the metal frame. The front and back sides of the metal structure, the front and back sides of the metal unit, and the front and back sides of the metal feature are also defined in the same way.

[0155] Figure 10 The embodiment of placing the die 113 on the carrier 117 in step S5 is shown.

[0156] Since the metal frame 200 has been pasted on the adhesive layer 121 on the front side 1171 of the carrier board, Figure 10 The connection pads 201 are shown in the figure. Therefore, when the die 113 is continued to be attached, it is necessary to ensure that the die 113 does not contact the metal frame 200. In the present disclosure, the die 113 is attached to the empty spaces 202 of the metal frame 200. Optionally, one empty space 202 corresponds to one die 113 or one empty space 202 corresponds to multiple die 113. Preferably, position marks for the arrangement of the die 113 are provided on the carrier 117. The marks can be formed on the carrier 117 by laser, mechanical engraving, or other methods. At the same time, the die 113 is also provided with alignment marks to ensure alignment with the attachment positions on the carrier 117 during attachment. Figure 10 This is just an example image. Figure 10 The figure only shows the bare chip 113 attached to the adhesive layer 121 of the carrier 117. Figure 6a The die 113 shown has a protective layer 107 and an opening in the protective layer; the die attached to the adhesive layer 121 of the carrier 117 can also be Figure 6b The bare chip form with the wafer conductive layer 130, the protective layer 107 and the protective layer opening 109 shown in FIG can also be Figure 6c The bare chip form with the wafer conductive layer 130 and the protective layer 107 is shown in FIG. Meanwhile, the metal frame 200 pasted on the adhesive layer 121 can also be as follows Figure 8a The metal frame 200 shown is only cut but the connecting rods 203 are not removed, but the metal frame 200 can also be a metal frame 200 with complete connecting rods 203.

[0157] like Figure 10 As shown, one metal unit corresponds to one bare die 113, the number of bare die 113 on the carrier 117 is the same as the number of metal units on the carrier 117, and the arrangement of the bare die 113 corresponds to the arrangement of the metal units on the carrier 117. The number and arrangement of the metal units are not limited to Figure 10 The method shown is not limited to the one shown in the figure, but can be customized according to actual needs.

[0158] In addition, one metal unit may correspond to multiple bare dies 113, and the multiple bare dies 113 are placed in predetermined spaces 202. In particular, the multiple bare dies are multiple bare dies with different functions, which are arranged in the metal unit on the carrier 117 according to the needs of the actual product and packaged. After the packaging is completed, they are cut into multiple packages; thus, one package includes multiple bare dies to form a multi-chip module (MCM), and the positions of the multiple bare dies can be freely set according to the needs of the actual product.

[0159] Figure 9-10 The installation sequence shown in the figure is to first install the metal frame 200 on the carrier 117 and then install the bare chip 113 on the carrier 117. However, this is only exemplary and the bare chip 113 can also be installed on the carrier 117 first and then install the metal frame 200 on the carrier 117.

[0160] Step S6 , forming a plastic layer 123 on the carrier 117 .

[0161] like Figure 11 As shown, the plastic layer 123 covers the entire carrier 117 and is used to encapsulate all the bare chips 113 and the metal frame 200. Figure 11 The connection pads 201 are embodied in the figure to reconstruct a flat plate structure, so that after the carrier 117 is peeled off, the next packaging step can be continued on the reconstructed flat plate structure.

[0162] The side of the plastic layer 123 that contacts the carrier front 1171 or the adhesive layer 121 is defined as the plastic layer front side 1231 , and the side of the plastic layer 123 that faces away from the carrier front 1171 or the adhesive layer 121 is defined as the plastic layer back side 1232 .

[0163] Preferably, the front surface 1231 of the plastic packaging layer and the back surface 1232 of the plastic packaging layer are substantially flat and parallel to the front surface 1171 of the carrier board.

[0164] The plastic layer 123 can be formed by slurry printing, injection molding, hot pressing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. The plastic layer 123 can be made of an organic composite material, a resin composite material, a polymer composite material, or a polymer composite material, such as epoxy resin with fillers, ABF (Ajinomoto buildup film), or other polymers with suitable fillers.

[0165] In one embodiment, the plastic layer 123 is formed by compression molding using an organic / inorganic composite material.

[0166] Optionally, before forming the plastic encapsulation layer 123, some pre-processing steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities on the surface of the bare chip 113 and the metal frame 200, so that the plastic encapsulation layer 123 can be more closely connected to the bare chip 113, the metal frame 200 and the carrier 117 without delamination or cracking.

[0167] Preferably, the thermal expansion coefficient of the plastic sealing layer 123 is 3 to 10 ppm / K; in a preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 5 ppm / K; in another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 7 ppm / K; in yet another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 10 ppm / K.

[0168] Preferably, the plastic encapsulation layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

[0169] The thermal expansion coefficient of the molding layer 123 is selected to be 3 to 10 ppm / K and is selected to have the same or similar thermal expansion coefficient as the protective layer 107. During the heating and cooling process of the molding process, the expansion and contraction degrees between the protective layer 107 and the molding layer 123 are consistent, and the two materials are less likely to generate interface stress. The low thermal expansion coefficient makes the thermal expansion coefficients of the molding layer, the protective layer and the bare chip close, so that the interfaces of the molding layer 123, the protective layer 107 and the bare chip 113 are tightly bonded, avoiding interface layer separation.

[0170] During use, the packaged chip often needs to undergo hot and cold cycles. Since the thermal expansion coefficients of the protective layer 107, the plastic layer 123 and the bare chip 113 are similar, during the hot and cold cycles, the interface fatigue of the protective layer 107, the plastic layer 123 and the bare chip 113 is small, and it is not easy to have an interface gap between the protective layer 107, the plastic layer 123 and the bare chip 113, which increases the service life of the chip and expands the application fields of the chip.

[0171] The difference in thermal expansion coefficients between the bare chip 113 and the plastic layer 123 will also cause the panel assembly to warp after plastic sealing. Due to the warping phenomenon, it is difficult to locate the precise position of the bare chip 113 in the panel assembly in the subsequent conductive layer formation process, which has a great impact on the conductive layer formation process.

[0172] In particular, in the large-panel packaging process, due to the large size of the panel, even a slight warping of the panel will cause the position of the bare chips in the outer surrounding parts of the panel away from the center to change significantly relative to before molding. Therefore, in the large-panel packaging process, solving the warping problem becomes one of the keys to the entire process. The warping problem even limits the expansion of the panel size and becomes a technical barrier in large-size panel packaging.

[0173] The thermal expansion coefficients of the protective layer 107 and the plastic layer 123 are limited to the range of 3 to 10 ppm / K, and preferably the plastic layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, which can effectively avoid the warping of the panel assembly and realize the packaging process using large panels.

[0174] At the same time, during the molding process, the molding pressure will generate pressure on the back of the bare chip 113 toward the carrier 117. This pressure can easily press the bare chip 113 into the adhesive layer 121, so that the bare chip 113 is sunken into the adhesive layer 121 during the formation of the molding layer 123. After the molding layer 123 is formed, the bare chip 113 and the front side 1231 of the molding layer are not in the same plane. The surface of the bare chip 113 protrudes outside the front side 1231 of the molding layer, forming a step-like structure. In the subsequent panel-level conductive layer formation process, the panel-level conductive layer will also have a step-like structure accordingly, making the packaging structure unstable.

[0175] When the die active surface 1131 has a protective layer 107 with material properties, it can play a buffering role under the molding pressure, preventing the die 113 from sinking into the adhesive layer 121, thereby avoiding the formation of a step-like structure on the front side 1231 of the molding layer.

[0176] In order to expose the metal frame 200, the plastic layer 123 needs to be thinned. The plastic layer 123 can be thinned by mechanically grinding or polishing the front surface 1231 of the plastic layer. The thickness of the plastic layer 123 is thinned to the back surface of the metal frame 200, thereby exposing the surface features of the metal frame 200. Figure 12 As shown, when the metal frame 200 is thicker than the die 113, the plastic layer can be further thinned to the back of the die 113, exposing both the metal frame 200 (shown as the back of the connection pad 2012 of the connection pad 201 in the figure) and the back of the die 113. For another example, if the die 113 is thicker than the metal frame 200, the mold layer 123 is thinned until the back of the connection pad 2012 is exposed from the mold layer 123. During this process, the die 113 is further thinned to the same thickness as the connection pad 201; thus, the die 113 has a shorter conductive path and lower resistance, making it suitable for power modules.

[0177] In step S7 , a second conductive structure 140 is formed on the die back side 1132 and the second dielectric layer 170 .

[0178] The second conductive structure 140 may be formed by patterning a conductive layer at a panel level.

[0179] For example, the second conductive structure 140 can be formed by a photolithography process. Figure 13, forming a dry film 160 to cover the die back side 1132, the molding layer back side 1232, and the connection pad back side 2012. Dry film 160 is a photosensitive film that can be used as an electroplating mold. Dry film 160 can be adhered by a rolling process, in which a heated roller applies controlled pressure to press dry film 160 onto the die back side 1132, the molding layer back side 1232, and the connection pad back side 2012 while heating the dry film 160. Alternatively, dry film 160 can be adhered by a vacuum process, in which when air near dry film 160 is sucked to form a vacuum, an elastic device presses dry film 160 onto the die back side 1132, the molding layer back side 1232, and the connection pad back side 2012.

[0180] Reference Figure 14 , a photolithography process is performed on the dry film 160 to form a patterned dry film 162. In the photolithography process, a mask (not shown) is positioned over the dry film 160 to cover selected portions of the dry film 160, while unselected portions of the dry film 160 are exposed to a light source through the mask to form a plurality of dry film openings 163 in the patterned dry film 162. As a result, (all or part of) the die backside 1132 and at least a portion of the connection pad backside 2012 are exposed through the dry film openings 163 in the patterned dry film 162.

[0181] Reference Figure 15 The second panel level conductive trace 142 is formed by filling the dry film opening 163 of the patterned dry film 162 with copper, gold, silver, tin, aluminum or a combination thereof, or other suitable conductive materials by utilizing PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes.

[0182] Reference Figure 16 , another dry film 164 is formed to cover the patterned dry film 162 and the second panel-level conductive trace 142. Similar to the dry film 160, the dry film 164 is a photosensitive film, which can be formed by the rolling process or the vacuum process as described above.

[0183] Reference Figure 17 The dry film 164 may also be subjected to a photolithography process to form a patterned dry film 166. The patterned dry film 166 has a plurality of dry film openings 167, through which at least a portion of the second panel-level conductive traces 142 is exposed. The patterned dry film 162 may be completely or partially covered by the patterned dry film 166.

[0184] Reference Figure 18Second panel-level conductive pillars 144 are formed by filling dry film openings 167 with a conductive material, such as copper, gold, silver, tin, and aluminum, or a combination thereof, or are made of other suitable conductive materials by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes. Thus, second panel-level conductive pillars 144 are electrically connected to second panel-level conductive traces 162 and further electrically connected to connection pads 201 of metal frame 200.

[0185] like Figure 19 As shown, patterned dry film 162 and patterned dry film 166 are removed; while second panel-level conductive traces 142 and second panel-level conductive pillars 144 remain on die back side 1132 and connection pad back side 2012. Second panel-level conductive traces 142 and second panel-level conductive pillars 144 collectively define second conductive structure 140. In particular, second conductive structure 140 is manufactured at the panel level, thereby increasing throughput and reducing manufacturing costs.

[0186] Figure 19 The pattern of the second conductive structure 140 is merely exemplary, and it may have various patterns according to specific circuit designs.

[0187] Reference Figure 20 , forming a second dielectric layer 170 to completely encapsulate the second conductive structure 140 (including the second panel-level conductive traces 142 and the second panel-level conductive pillars 144). In addition, the second dielectric layer 170 may also cover the portion of the back side 1232 of the plastic layer and the back side 2012 of the connection pad that is not covered by the second panel-level conductive traces 142. The second dielectric layer 170 may include an epoxy molding compound in the form of a film, particles, or liquid. As described above, the second dielectric layer 170 may have similar components and properties to the plastic layer 123. For example, the second dielectric layer 170 has the same or similar coefficient of thermal expansion (CTE) as the plastic layer 123, so that interface stress is not easily generated between the second dielectric layer 170 and the plastic layer 123.

[0188] In order to expose the second panel-level conductive pillars 144, the second dielectric layer 170 needs to be thinned. Figure 21 The second dielectric layer 170 is thinned by mechanically grinding or polishing the back surface 1702 of the second dielectric layer, thereby exposing the second panel-level conductive pillars 144 from the second dielectric layer 170 .

[0189] In step S8 , the carrier (or referred to as the first carrier) 117 is peeled off to form a panel assembly 150 having the second conductive structure 140 .

[0190] refer to Figure 22After the carrier 117 is peeled off, the protective layer 107 on the active surface 1131 of the die, the lower surface of the metal frame 200 (represented by the connection pad front surface 2011 of the connection pad 201 in the figure) and the front surface 1231 of the plastic layer are exposed. Figure 22 The arrows in show the separation of the carrier 117 from the panel assembly 150 .

[0191] After the carrier 117 is separated, the plastic layer 123 structure covering the die 113 and the metal frame 200 is defined as a panel assembly 150 having a second conductive structure 140 .

[0192] Figures 13 to 22 The second panel-level conductive traces 142 and the second panel-level conductive posts 144 are shown to each have a conductive layer. However, it is understood that the second panel-level conductive traces 142 and the second panel-level conductive posts 144 can also be formed by repeated bonding before separating the first carrier 117 from the panel assembly 150. Figures 13 to 20 Instead, it has multiple conductive layers.

[0193] Step S9: Figure 23a As shown, the panel assembly 150 with the second conductive structure 140 is inverted onto another carrier (also referred to as a second carrier) 118 .

[0194] In some embodiments, the adhesive layer 122 may be formed between the second carrier 118 and the back surface of the second dielectric layer 1702 by lamination, printing, spraying, coating, etc. To facilitate separation of the carrier 118 and the back surface of the second dielectric layer 1702 in subsequent processes, the adhesive layer 122 is preferably made of an easily separable material, such as a thermally separable material.

[0195] In step S10 , a first conductive structure 129 is formed on the active surface 1131 of the die through a panel-level process.

[0196] Reference Figure 23b , filling the protective layer opening 109 to form a conductive filled via 124. A panel-level conductive layer is formed on the surface of the protective layer 107. The panel-level conductive layer is connected to the electrical connection points 103 on the active surface 1131 of the die through the wafer conductive layer 130 and / or the conductive filled via 124, and is also connected to the metal frame 200 (shown as connection pad 201 in the figure). The panel-level conductive layer can be a single layer or multiple layers.

[0197] like Figure 23bAs shown, the panel-level conductive layer is embodied in the figure as a panel-level conductive trace (or referred to as a first panel-level conductive trace) 125. Optionally, the conductive filled via 124 and the panel-level conductive trace 125 are formed in the same panel-level conductive layer formation step. Similar to the second panel-level conductive trace 142, the conductive filled via 124 and the panel-level conductive trace 125 can be formed using a patterned conductive layer formation method, such as a photolithography process. The conductive filled via 124 and the panel conductive trace 125 can be made of materials such as copper, gold, silver, tin, aluminum, or a combination thereof, or can be other suitable conductive materials formed by utilizing PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.

[0198] At least a portion of panel-level conductive traces 125 are connected to electrical connection points 103 on the die active surface 1131 via conductive-filled vias 124 and to connection pads 201. Panel-level conductive traces 125 and conductive-filled vias 124 connect the electrical connection points 103 on the die active surface to connection pads 201. Simultaneously, panel-level conductive traces 125 are also electrically connected to second conductive structure 140 via connection pads 201. Therefore, die 113 can be electrically back-grounded to second conductive structure 140 via conductive-filled vias 124, panel-level conductive traces 125, and connection pads 201 (i.e., the die 113 is grounded at the die back surface 1132). Because second conductive structure 140 provides a large grounding contact area for the electrically back-grounded die 113, die 113 exhibits superior electrical performance when used in a power module.

[0199] Figure 23b The pattern of the panel-level conductive trace 125 is merely exemplary, and it may have various pattern traces according to specific circuit design.

[0200] Optionally, the conductive filled vias 124 and the panel-level conductive traces 125 may also be formed in separate steps, with the conductive filled vias 124 being formed first and then the panel-level conductive traces 125 being formed.

[0201] When the conductive filled vias 124 have been formed in the previous step of applying a protective layer, the step of forming a panel-level conductive layer can be directly performed.

[0202] When the protective layer opening 109 has not been formed in the previous step of applying the protective layer, a step of forming the protective layer opening 109 is required.

[0203] In some embodiments, the first panel-level conductive pillars 127 are formed on the first panel-level conductive traces 125 by forming a patterned conductive layer at the panel level.

[0204] For example, the first panel-level conductive pillar 127 can be formed by a photolithography process, similar to the second panel-level conductive pillar 127. The first panel-level conductive pillar 127 can be made of copper, gold, silver, tin, aluminum, or a combination thereof, or can be made of other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes. The panel-level conductive trace 125 and the first panel-level conductive pillar 127 are collectively defined as a first conductive structure 129. Therefore, the die 113 can be electrically connected to an external component (e.g., a printed circuit board (PCB)) by filling the through-hole 124 and the first conductive structure 129 (including the panel-level conductive trace 125 and the first panel-level conductive pillar 127).

[0205] Figure 23b The pattern of the first panel-level conductive pillars 127 in FIG. 1 is merely exemplary and may have various patterns according to specific circuit designs.

[0206] A first dielectric layer 146 is formed to encapsulate the first conductive structure 129. After a grinding process (e.g., mechanical grinding or polishing), the first panel-level conductive pillars 127 are exposed from the first dielectric layer 146. The first dielectric layer 146 can include an epoxy molding compound in a film, granular, or liquid form. In addition, the first dielectric layer 146 can have similar composition and properties as the aforementioned mold layer 123. For example, the first dielectric layer 146 has the same or similar coefficient of thermal expansion (CTE) as the mold layer 123, so that interfacial stress is not easily generated between the first dielectric layer 146 and the mold layer 123.

[0207] Figure 24 The first panel-level conductive trace 125 and the first panel-level conductive post 127 are shown as each having one conductive layer. However, it should be understood that the first panel-level conductive trace 125 and the first panel-level conductive post 127 can have multiple conductive layers by repeating the above process before separating the second carrier 118 from the panel assembly 150.

[0208] Additionally, the second carrier 118 is stripped to form a panel assembly 150 having the second conductive structure 140 encapsulated in the second dielectric layer 170 and the first conductive structure 129 encapsulated in the first dielectric layer 146 .

[0209] Reference Figure 24 After the second carrier 118 is peeled off, the second dielectric layer 170 and the second panel-level conductive pillars 144 of the second conductive structure 140 are exposed. Figure 24 The arrows in show the separation of the second carrier 118 from the panel assembly 150. Thus, the die 113 can be electrically and thermally connected to external components via the first conductive structures 129 of the die active side 1131 and the second conductive structures 140 of the die back side 1132.

[0210] Step S11 : cutting to form a plurality of packaged chips 400 .

[0211] refer to Figure 25 The packaged units are separated by cutting the panel assembly 150 to form a plurality of packaged chips 400. The cutting can be performed by, for example, a machine or a laser. Figure 25 The dot-dash line in shows the cutting line (also called saw line) along which separation is performed.

[0212] When the metal frame 200 is encapsulated as Figure 8a When the metal frame 200 shown includes the connecting rod 203, it is necessary to cut around the periphery of the connecting rod 203 to remove the connecting rod 203 during cutting and separation, so that the packaged chip 500 formed after the package is completed does not include the connecting rod, thereby making each metal feature in the metal unit of the metal frame 200 independent.

[0213] Preferably, before or after the cutting and separation step, a surface treatment layer 131 is formed on the first conductive structure 129 and / or the second conductive structure 140 exposed from the packaged chip 400. Optionally, the surface treatment layer 131 is formed by electroplating, electroless plating, or other suitable methods. For example, the surface treatment layer 131 is formed by electroless nickel immersion gold (ENIG), electroless nickel electroless palladium immersion gold (ENEPIG), tin plating, nickel gold plating (NiAu plating), or a combination thereof.

[0214] Optionally, the surface treatment layer 131 can also be configured to achieve electrical back grounding of the bare chip 113 in the packaged chip 400, that is, the surface treatment layer 131 electrically connects the back side 1132 of the bare chip and the connection pad 201 with a specific connection back grounding according to the specific design of the circuit (the connection pad with a specific connection back grounding is: the connection pad is connected to the electrical connection point of the back grounding on the active surface of the bare chip through a conductive structure).

[0215] Figure 26 FIG4 is an exemplary diagram of a packaged chip 400 separated from a panel assembly 150 and in use. During use, the packaged chip 400 is connected to a printed circuit board (PCB) or substrate 410 via at least one metal feature, shown as a connection pad 201. Additionally, a passive component 420 may be mounted on the second conductive structure 140 and electrically connected to the die 113 within the packaged chip 400. The passive component 420 may be a resistor, a capacitor, an inductor, or a combination thereof.

[0216] In addition to dissipating heat to a printed circuit board (PCB) or substrate 410 via the first conductive structure 129, a heat sink 430 can also be mounted on the second conductive structure 140 to dissipate heat generated by the die 113 through the conductive-filled vias 124, the first conductive structure 129, the connection pads 201 of the metal frame 200, and the second conductive structure 140. In particular, the connection pads 201 are exposed from the side surface 402 of the packaged chip 400. Thus, the packaged chip 400 has a three-sided heat dissipation design, providing efficient cooling: on the first side, heat is dissipated from the die active surface 1131 via the first conductive structure 129; on the second side, heat is dissipated from the second conductive structure 140 on the die backside 1132; and on the third side, heat is dissipated from the side surface 402 via the connection pads 201.

[0217] In addition, the grounding label 440 shows that the packaged chip 400 is electrically grounded from the back side 1132 of the die through the second conductive structure 140. Compared with traditional grounding, the electrical back grounding through the second conductive structure 140 can provide a larger contact area, making the packaged chip 400 more stable and safer to be electrically grounded, especially when used in power modules with large electric flux.

[0218] Instead of the passive component 420 and / or the heat sink 430 , another packaged chip 400 may be mounted on the second conductive structure 140 of the packaged chip 400 to form a package-on-package (POP) configuration.

[0219] Figure 27 FIG2 is a flow chart of another chip packaging method 20 according to an exemplary embodiment of the present disclosure. Compared with the chip packaging method 10, the chip packaging method 20 includes all steps from S1 to S11, and an additional step between S6 and S7, namely, forming and filling a plurality of voids 502 in the molding layer 123.

[0220] Figures 28 to 30 An additional schematic diagram of a panel assembly 152 is shown using the chip packaging method 20. The chip packaging method 20 has the same steps S1 to S11 and additional steps AS as the chip packaging method 10. Therefore, the second chip packaging method 20 will not repeat the same steps S1 to S11, and will also use the same steps S1 to S11. Figures 2 to 25 The same reference numerals are used to indicate the same or similar features. Additional steps are described below.

[0221] like Figure 28As shown, the height of the connection pads 201 is greater than the thickness of the die 113, causing the mold layer 123 to be thinned until the back side 2012 of the connection pads is exposed from the mold layer 123, while the die 113 is still completely encapsulated within the mold layer 123. A plurality of voids 502 are then formed through the mold layer 123 to the back side 1132 of the die 113. As a result, a portion of the back side 1132 of the die is exposed from the mold layer 123 through the voids 502. The voids 502 can be formed by any suitable process, such as a laser patterning process, a mechanical patterning process, laser drilling, or a combination thereof.

[0222] Similar to conductive filled via 124, void 502 is also filled with a conductive medium. The conductive medium can be gold, silver, copper, tin, aluminum, or a combination thereof, or can be other suitable conductive materials formed by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive medium is then filled into void 502 to form conductive filled void 504.

[0223] Reference Figure 30 , the second panel-level conductive trace 142 is formed on and connected to the conductive filled void 504. Therefore, the die 113 can still be electrically back-grounded from the die back side 1132 through the second panel-level conductive trace 142 and the second panel conductive pillar 144 of the second conductive structure 140.

[0224] Similarly, a second dielectric layer 170 is formed to encapsulate the second conductive structure 140, wherein the second conductive structure 140 is exposed from the second dielectric layer 170 after a grinding process (e.g., mechanical grinding or polishing). In addition, the second dielectric layer 170 can have similar composition and properties as the mold layer 132 described above.

[0225] refer to Figure 30 The packaged units are separated by cutting the panel assembly 152 to form a plurality of packaged chips 500. The cutting can be performed by, for example, a machine or a laser. Figure 30 The dot-dash line in shows the cutting line (also called saw line) along which separation is performed.

[0226] Figure 31 is based on Figures 28 to 30 Schematic diagram of the packaged chip 500 formed after cutting the manufactured panel assembly 152. Figure 26 The same reference numerals are used to describe Figure 30 Similar to the packaged chip 400, the connection pads 201 are also exposed on the side surface 402 of the packaged chip 500. Therefore, the packaged chip 500 also has a three-sided heat dissipation design, which is conducive to efficient cooling.

[0227] Compared to package structure 400, when gap 502 is filled with mold layer 123, second panel-level conductive trace 142 has a larger contact area. Therefore, second conductive structure 140 of package structure 500 applies less stress to die 113 from die back side 1132. Furthermore, the larger contact area more securely connects second panel-level conductive trace 142 and mold layer 123, allowing second panel-level conductive trace 142 to be thinner. Furthermore, second panel-level conductive trace 142 correspondingly has a smaller weight, further reducing the stress applied to die 113 from die back side 1132.

[0228] In place of the passive components 420 and / or the heat sink 430, another packaged chip 500 may be mounted on the second conductive structure 140 of the packaged chip 500 to form a package-on-package (POP) configuration. Alternatively, one packaged chip 400 may be mounted on the second conductive structure 140 of the packaged chip 500 to form a package-on-package (POP) configuration. Alternatively, the packaged chip 500 may be mounted on the second conductive structure 140 of one packaged chip 400 to form a package-on-package (POP) configuration.

[0229] Figures 32 to 34 yes Figures 28 to 30 Similarly, steps S1 to S11 of the chip packaging method 10 are not described in detail; therefore, the same reference numerals are used here to describe the steps. Figures 2 to 25 as well as Figures 28 to 30 In addition, Figures 28 to 30 Compared to the illustrated panel assembly 152, additional steps of the chip packaging method 20 are modified to manufacture the panel assembly 154. Therefore, the changes to the additional steps for manufacturing the panel assembly 154 are described below.

[0230] Reference Figure 32 , the panel assembly 154 has Figure 28 The structure of the panel assembly 152 is similar to that of the panel assembly 152 in FIG, except that a molding layer 610 is formed on the back side 1132 of the die 113, which is exposed from the molding layer 123. The molding layer 610 can be formed by slurry printing, injection molding, hot pressing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. For example, the molding layer 610 is formed on the back side 1132 of the die by film molding.

[0231] Molding layer 610 can be made of the same material as molding layer 123, such as an organic composite material, a resin composite material, a polymer composite material, or a polymer composite material, such as epoxy resin with fillers, ABF (Ajinomoto buildup film), or other polymers with suitable fillers. Alternatively, molding layer 610 can be made of a different material than molding layer 123. Compared to molding layer 123, a different material can have better compatibility with second panel-level conductive traces 142, thereby more stably fixing second conductive structure 140 and molding layer 123.

[0232] Reference Figure 33 A gap 502 is formed in the plastic layer 610 by any suitable process, such as a laser patterning process, a mechanical patterning process, a laser drilling process, or a combination thereof; thus, a portion of the back side 1132 of the die 113 is exposed from the plastic layer 610 through the gap 502. The gap 502 is then filled with a conductive medium, which may be gold, silver, copper, tin, aluminum, or a combination thereof, or other suitable conductive materials, by using PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes to form a conductive filled gap 504.

[0233] As reference Figure 34 The packaged units are separated by cutting the panel assembly 154 to form a plurality of packaged chips 550. The cutting can be performed by, for example, a machine or a laser. Figure 34 The dot-dash line in shows the cutting line (also called saw line) along which separation is performed.

[0234] Figure 35 is based on Figures 32 to 34 Schematic diagram of a packaged chip formed after dicing a variation of the manufactured panel assembly. Packaged chip 550 has the same structure as packaged chip 500, except that void 510 is formed in mold layer 610 on die back side 1132, as described above. In addition, passive components 420 and / or heat sink 430 may be mounted on second conductive structure 140 of packaged chip 550.

[0235] Alternatively, another packaged chip 550 may be mounted on the second conductive structure 140 of the packaged chip 550 to form a package-on-package (POP) configuration. Alternatively, one packaged chip 400 or 500 may be mounted on the second conductive structure 140 of the packaged chip 550 to form a package-on-package configuration. Alternatively, the packaged chip 550 may be mounted on the second conductive structure 140 of one packaged chip 400 or 500 to form a package-on-package configuration.

[0236] When the first conductive structure 129 and the second conductive structure 140 are made of metal or a metallic material (e.g., copper), they are relatively heavy compared to the die 113, the metal frame (herein represented as connection pads 201), the mold layer 123, and the other components described above (e.g., the protective layer 107). Preferably, the first conductive structure 129 and the second conductive structure 140 have substantially the same weight to balance the packaged chips 400, 500, 550 as a whole. In other words, if the first conductive structure 129 and the second conductive structure 140 are both made of the same metal or metallic material (e.g., copper), they have substantially equal mass.

[0237] Figure 36a A schematic diagram of a packaged chip 600 having a first die 602 and a second die 604 is shown. Figure 1 The chip packaging method 10 in the embodiment of the present invention. The dies 602 and 604 can be conventional silicon cores, silicon carbide (SiC) cores, gallium nitride (GaN) cores, or a combination thereof. The dies 602 and 604 can be of any suitable design depending on the desired application. For example, the dies 602 and 604 can be a first field effect transistor (FET) and a second field effect transistor (FET) placed side by side.

[0238] The packaged chip 600 has a similar package structure to the packaged chip 400; therefore, the same reference numerals are used to describe the packaged chip 600. Figure 26 The first conductive structure 129 and the second conductive structure 140 are formed on both sides of the first and second dies 602 and 604. Thus, the first conductive structure 129 is connected to the first die active surface 6021 of the first die 602 and the second die active surface 6041 of the second die 604; while the second conductive structure 140 is connected to the first die back surface 6022 of the first die 602 and the second die back surface 6042 of the second die 604.

[0239] Likewise, the first conductive structure 129 and the second conductive structure 140 are also connected via the connection pads 201 in the packaged chip 600. Therefore, the first and second die active surfaces 6021, 6041 are electrically connected to the second conductive structure 140 for achieving electrical back grounding of the first and second dies 602, 604 in the packaged chip 600.

[0240] Similarly, packaged chip 600 also features a three-sided heat dissipation design, facilitating efficient cooling. The first side dissipates heat from the die active surfaces 6021 and 6041 via the first conductive structure 129; the second side dissipates heat from the die back surfaces 6022 and 6042 via the second conductive structure 140; and the third side dissipates heat from the side surface 402 via the connection pads 201. Furthermore, a heat sink 430 can be mounted on the second conductive structure 140 to accelerate heat dissipation from packaged chip 600.

[0241] Optionally, the packaged chip 600 may include a large-sized heat sink 430 (referred to as a large heat sink) to further enhance heat dissipation from the first and second dies 602 and 604. For example, if the first die 602 occupies more space than the second die 604, the large heat sink 430 may be mounted above the first die 602. In this case, heat generated by the second die 604 can still be dissipated to the large heat sink 430 via the first conductive structure 129, the connection pad 201, and the second conductive structure 140.

[0242] Alternatively, the large passive component 420 can be mounted on the second conductive structure 140 and the first die 602, while the small heat sink 430 (referred to as a small heat sink) can be mounted on the second conductive structure 140 and the second die 604. In this case, the heat generated by the first die 602 can still be dissipated to the small heat sink 430 through the first conductive structure 129, the connection pad 201, and the second conductive structure 140.

[0243] Specifically, the first die 602 and the second die 604 are both arranged face-down and connected to an external component (e.g., a printed circuit board (PCB) or substrate) via a direct flip-chip process, without the use of solder bumps or solder balls. For example, both the first die active surface 6021 and the second die active surface 6041 are directly connected to an external component (e.g., a printed circuit board or substrate) via conductive filled vias 124 and first conductive structures 129. In other words, the packaged chip 600 using the direct flip-chip process eliminates the need for the bumping and reflowing processes typically used in conventional flip-chip processes. Given the low electrical and thermal conductivity of solder bumps or solder balls, the direct flip-chip process of the present application enables the packaged chip 600 to exhibit improved electrical and thermal performance, which is crucial for power modules that experience significant electrical flux and associated heat during operation. Figure 36a It is shown that the packaged chip 600 can be directly connected to a printed circuit board (PCB) or substrate 410 through the first panel-level conductive pillars 127 of the first conductive structures 129 .

[0244] Alternatively, if desired, a conventional flip-chip process may also be applied to package the chip 600 . Figure 36bSolder bumps or balls 412 are shown formed below the first panel-level conductive posts 127 of the first conductive structures 129 for connecting the packaged chip 600 to a printed circuit board (PCB) or substrate 410 .

[0245] The face-down configuration of the first and second dies 602, 604 will make the panel-level packaging method easier and more efficient. For example, in step S5 (called the die transfer process (reconstruction process) of the panel-level packaging), the first and second dies 602, 604 (in the panel-level packaging) can be placed on the panel-level packaging. Figure 10 The first and second dies 602, 604 are accurately arranged and adhered to the carrier 117 because features (such as alignment marks (not shown)) on the active surfaces 6021, 6041 of the dies can be easily observed through the protective layer 107 before the first and second dies 602, 604 are bonded to the carrier 117.

[0246] In place of the passive component 420 and / or the heat sink 430, another packaged chip 600 may be mounted on the second conductive structure 140 of the packaged chip 600 to form a package-on-package (POP) configuration. Alternatively, one or more packaged chips 400, 500, 550 may be mounted on the second conductive structure 140 of the packaged chip 600 to form a package-on-package (POP) configuration.

[0247] Similarly, when the first conductive structure 129 and the second conductive structure 140 are made of metal or a metallic material (e.g., copper), they are relatively heavy compared to the die 113, the connection pads 201, the mold layer 123, and the other components described above (e.g., the protective layer 107). Preferably, the first conductive structure 129 and the second conductive structure 140 have substantially the same weight to balance the packaged chip 600 as a whole. In other words, if the first conductive structure 129 and the second conductive structure 140 are made of the same metal or metallic material (e.g., copper), they have substantially equal mass.

[0248] FIG37 is a schematic diagram of a chip package 700 for a power module according to an exemplary embodiment of the present disclosure. The chip package 700 is composed of Figure 1 Therefore, with the chip packaging method 10 in Figures 2 to 25 The same or similar features are marked with the same reference numerals.

[0249] Figure 37a The embodiment shows a package 700 including a plurality of chips (eg Figure 37a700). A plurality of chip packages 700 are arranged in a matrix configuration. The chip package 700 includes a first die 602 and a second die 604 of a metal oxide semiconductor field effect transistor (MOSFET), and a drive circuit (also referred to as a drive element) 720 for controlling the first die 602 and the second die 604. Thus, the chip package 700 can be used as a power module for DrMOS. For example, the first die 602 is a low-side MOSFET optimized for ultra-fast switching, while the second die 604 is a high-side MOSFET optimized for minimal conduction losses.

[0250] Therefore, the metal frame 200 includes a plurality of metal units (eg Figure 37a Each metal unit surrounds the first die 602, the second die 604, and the driving circuit 720 to form a chip package 700. In addition, the chip package 700 is manufactured by cutting the panel assembly 710. Figure 37a The cutting line (also called saw line) along which the separation takes place is shown.

[0251] Figure 37b Shown along Figure 37a FIG. 7 is a cross-sectional view of the chip package 700 along the dotted line AA in FIG. The chip package 700 has a similar structure to the packaged chip 600, except that the second die 604 is replaced by a driver circuit 720. The driver circuit 720 is thinner than the first die 602, and the driver back surface 7042 of the driver circuit 720 does not directly contact the second conductive structure 140. Therefore, a space 730 is formed between the driver back surface 7022 and the second conductive structure 140. Using the chip packaging method 10, the space 730 is filled with Figure 11 In this way, heat can still be dissipated from the driver back surface 7202 to the second conductive structure 140 through the plastic layer 123.

[0252] Passive components 420 may be mounted on the second conductive structure 140, such as a resistor 740 and a capacitor 742 mounted above the first die 602 and the driver circuit 720, respectively, and an inductor 744 mounted between the resistor 740 and the driver circuit 720. Thus, the first die 602 and the driver circuit 720 are electrically connected to the passive components 420 through the filled conductive vias 124, the first conductive structure 129, the connection pads 201, and the second conductive structure 140 for transmitting electrical signals. Similarly, the chip package 700 may also be electrically back-grounded via the second conductive structure 140.

[0253] In particular, the chip package 700 is arranged along Figure 37aThe dotted line AA in the figure retains the three-sided heat dissipation design, thereby having an efficient cooling function, namely, on the first side, heat is dissipated from the active surface 6021 of the first die and the driving active surface 7201 of the driving circuit 720 via the first conductive structure 129; on the second side, heat is dissipated from the active surface 6022 of the second die and the driving back surface 7202 of the driving circuit 720 via the second conductive structure 140; and on the third side, heat is dissipated from the side 402 by the connection pad 201.

[0254] Figure 37c Shown along Figure 37a FIG2 is a cross-sectional view of chip package 700 along dashed line BB in FIG2 . Chip package 700 has a similar structure to packaged chip 600, with first die 602 and second die 604 making direct contact with second conductive structure 140 at first die back side 6022 and second die back side 6042, respectively. Inductor 744 is also mounted on second conductive structure 140 exposed from plastic encapsulation layer 123.

[0255] Similarly, the chip package 700 still retains the Figure 37a The three-sided heat dissipation design of the middle dotted line BB has an efficient cooling function, namely, on the first side, heat is dissipated from the active surfaces 6021 and 6041 of the first and second dies via the first conductive structure 129; on the second side, heat is dissipated from the back surfaces 6022 and 6042 of the first and second dies via the second conductive structure 140; and on the third side, heat is dissipated from the side surface 402 via the connection pad 201 exposed by the plastic layer 123.

[0256] Instead of passive components 420 (eg, resistor 740 , capacitor 742 , and inductor 744 ) and / or heat sink 430 , another chip package 700 may be mounted on the second conductive structure 140 of the chip package 700 to form a package-on-package (POP) configuration of the power module.

[0257] FIG38 is a schematic diagram of another chip package 800 for a power module according to an exemplary embodiment of the present disclosure. Figure 2 Therefore, with the chip packaging method 20 in Figures 2 to 25 as well as Figures 28 to 30 The same or similar features are denoted by the same reference numerals.

[0258] Similar to the chip package 700, Figure 37a As shown in the top view of FIG, the display chip package 800 is also manufactured by separating the panel assembly 710.

[0259] Figure 38a Shown along Figure 37a The chip package 800 is a cross-sectional view of the chip package 800 along the dotted line AA. Figure 37bThe chip package 700 shown has a similar structure, that is, the space 730 formed between the driver back surface 7022 and the second conductive structure 140 is filled with the plastic layer 123, so that heat can still be dissipated from the driver back surface 7202 to the second conductive structure 140 through the plastic layer 123.

[0260] However, if Figure 28 The plurality of gaps 502 described in the above can be formed in the plastic layer 123 and extended to the back side 6022 of the first die by any suitable process, such as a laser patterning process, a mechanical patterning process, a drilling process or a combination thereof. Figure 29 As shown, the void 502 is filled with a conductive medium or other suitable conductive material such as gold, silver, copper, tin, aluminum, etc. or combinations thereof.

[0261] Figure 38b Shown along Figure 37a The cross-sectional view of the chip package 800 is shown along the dotted line BB. Figure 37c Compared with the chip package 700 shown in FIG, a hole can be formed by any suitable process, such as a laser patterning process, a mechanical patterning process, a drilling process, or a combination thereof, through the plastic layer 123 to the back side 6042 of the second die. Figure 28 Then, as Figure 29 The void 502 is shown filled with a conductive medium or other suitable conductive material such as gold, silver, copper, tin, aluminum, etc. or combinations thereof, thereby forming a conductive filled void 504.

[0262] Instead of the passive components 420 (e.g., the resistor 740, the capacitor 742, and the inductor 744) and / or the heat sink 430, another chip package 800 may be mounted on the second conductive structure 140 of the chip package 800 to form a package-on-package (POP) configuration. Alternatively, one chip package 700 may be mounted on the second conductive structure 140 of the chip package 800 to form a package-on-package (POP) configuration. Alternatively, the chip package 800 may be mounted on the second conductive structure 140 of one chip package 700 to form a package-on-package (POP) configuration.

[0263] FIG39 is a schematic diagram of another chip package 850 for a power module according to an exemplary embodiment of the present disclosure. Figure 27 Therefore, the same or similar features are used Figures 2 to 25 and Figures 32 to 34 The same reference numerals are used to represent the same figures in FIG.

[0264] Similar to the chip package 700, Figure 37aAs shown in the top view of , the display chip package 850 is also manufactured by separating the panel assembly 710.

[0265] Figure 39a Shown along Figure 37a The chip package 850 is a cross-sectional view of the chip package 850 along the dotted line AA in FIG. Figure 38a The chip package 800 shown has a similar structure. However, the space 730 in the chip package 800 is filled with the molding layer 123 ; and the gap 502 is formed in the molding layer 123 and then filled with a conductive medium to form a conductive filled gap 504 .

[0266] In comparison, Figure 32 As shown, the gap 502 in the chip package 850 is formed in the molding layer 610. The molding layer 610 can be formed by slurry printing, injection molding, thermoforming, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. For example, the molding layer 610 is formed on the backsides 6022 and 6042 of the first and second dies 602 and 604 by film molding.

[0267] Instead of the passive components 420 (e.g., the resistor 740, the capacitor 742, and the inductor 744) and / or the heat sink 430, another chip package 850 may be mounted on the second conductive structure 140 of the chip package 850 to form a package-on-package (POP) configuration. Alternatively, one chip package 700 or 800 may be mounted on the second conductive structure 140 of the chip package 850 to form a package-on-package configuration. Alternatively, the chip package 850 may be mounted on the second conductive structure 140 of the chip package 700 or 800 to form a package-on-package configuration.

[0268] When the first conductive structure 129 and the second conductive structure 140 are made of metal or a metallic material (e.g., copper), they are relatively heavy compared to the die 113, the connection pads 201, the mold layer 123, and the other components described above (e.g., the protective layer 107). Preferably, the first conductive structure 129 and the second conductive structure 140 have substantially the same weight to balance the chip package 700, 800, 850 as a whole. In other words, if the first conductive structure 129 and the second conductive structure 140 are made of the same metal or metallic material (e.g., copper), they have substantially equal mass.

[0269] Figure 40FIG. 1 is a schematic diagram of a conventional chip package 900 for a power module. The conventional chip package 900 comprises a first semiconductor die 902 in a face-down configuration, i.e., a first die active surface 9021 of the first semiconductor die 902 faces a lead frame 912 and is connected to the lead frame 912 using solder bumps or solder balls via a conventional flip-chip process; and a second semiconductor die 904 in a face-up configuration, i.e., a second die active surface 9041 of the second semiconductor die 904 faces away from the lead frame 912 and is connected to the lead frame 912 via wire bonds 910. These two different configurations (i.e., the face-down configuration of the first semiconductor die 902 and the face-up configuration of the second semiconductor die 904) will make the manufacturing process of the traditional chip package 900 complicated and costly, and the bonding accuracy of the first and second semiconductor dies is low during the die transfer process (reconstruction process) of transferring the semiconductor dies 902 and 904 to the carrier 117.

[0270] In contrast, the first and second dies 602, 604 in the chip packages 700, 800, 850 are both face-down configured and connected to the first conductive structure 129 by a direct flip-chip process without solder bumps or solder balls, and further connected to the printed circuit board (PCB) or substrate 410; therefore, the chip packaging methods 10, 20 are simpler, less expensive, and more accurate in manufacturing the chip packages 700, 800, 850, especially as Figure 10 The die transfer process (reconstruction process) of bonding the first and second dies 602, 604 and the driving circuit 720 to the carrier 117 is shown (die 113 represents Figure 10 The first and second dies 602, 604 in FIG.

[0271] like Figure 40As shown, a copper clip 906 is attached to the first semiconductor die 902 and the second semiconductor die 904. However, due to the bulky size of the copper clip 906, the conventional chip package 900 requires a thicker and bulkier form factor. Consequently, the heavy weight of the copper clip 906 may cause cracks in the first and second semiconductor dies 902 and 904. Furthermore, in conventional chip package 900, wires 910 are often used to connect the second semiconductor die 904 to a lead frame 912. The wires 910 also require a larger space (both vertically and laterally), thereby making the conventional chip package 900 even thicker and bulkier.

[0272] In contrast, the present disclosure utilizes a direct flip-chip process without solder bumps or solder balls to directly connect the first and second dies 602, 604 and the driver circuit 720 to a printed circuit board (PCB) or substrate 410. Consequently, the chip packages 700, 800, and 850 have a thinner and smaller form factor, making them more suitable for today's increasingly popular portable electronic devices (e.g., mobile phones, touchpads, and notebook computers).

[0273] like Figure 40 As shown, a die attach material 916 is used to attach the first and second semiconductor dies 902 and 904 to the lead frame 912. Compared to the conductive material (e.g., copper) used in the first conductive structure 129, the die attach material 916, although it may also be conductive (e.g., conductive paste or solder), still has a larger resistance. Therefore, the conventional chip package 900 with the die attach material 916 is not suitable for power modules that require low resistance and high current. Alternatively, the die attach material 916 can also be made of a non-conductive material (e.g., an adhesive or a film adhesive), but these non-conductive materials cannot effectively dissipate heat. Therefore, the conventional chip package 900 with the die attach material 916 having non-conductive properties is also not suitable for power modules that generate a lot of heat due to large currents.

[0274] In contrast, in chip packages 700, 800, and 850, the first and second dies 602 and 604 and the driver circuit 720 are directly connected to the connection pads 201 of the metal frame 200 (e.g., a lead frame) via the first and second conductive structures 129 and 140, eliminating the need for the die attach material 916 of the conventional chip package 900. The first and second conductive structures 129 and 140 can be made of a highly conductive material (e.g., copper), allowing a large current to flow within the power module. Furthermore, due to the low resistance of the first and second conductive structures 129 and 140, less heat is generated.

[0275] In particular, in the conventional chip package 900, in order to allow current to flow vertically through the first and second semiconductor dies 902, 904, a die back metal layer 908 (e.g., copper) must be added to the first and second die back surfaces 9022, 9042. For example, the die back metal layer 908 is applied to the first die back surface 9022 for vertical conduction from the first die active surface 9021 to the first die back surface 9022. However, at the same time, Figure 12 The illustrated grinding process cannot be used for the die back metal layer 908 ; therefore, the first and second semiconductor dies 902 , 904 cannot be thinned by the grinding process to reduce resistance, which would degrade the performance of a power module employing the conventional chip package 900 .

[0276] In contrast, the chip packages 700, 800, 850 do not have the die back metal layer 908, because the vertical conduction is conducted through the connection pads 201 of the metal frame 200 and the second conductive structure 140 on the die back side 6022, 6042 and the driver back side 7202. Figure 12 The illustrated grinding process thins the first and second dies 602 , 604 and the driver circuit 720 to enhance the electrical performance of the chip package 700 , 800 , 850 when used as a power module.

[0277] Furthermore, conventional chip package 900 utilizes discrete metal components (e.g., copper clip 906 and lead frame 912) that are fabricated separately prior to packaging. Consequently, expensive metals (e.g., silver or nickel-palladium-gold (NiPdAu)) are also required during the packaging process to connect any two discrete metal components. For example, a spot plating layer 918 is applied between the copper clip 906 and the lead frame 912 to secure the copper clip 906 to the lead frame 912. For another example, a spot plating layer 918 (not shown) is also applied between the copper clip 906 and the die back metal layer 908 to secure the copper clip 906 to the first die back side 9022 of the first semiconductor die 902.

[0278] In contrast, chip packages 700, 800, and 850 do not use discrete metal components. Instead, the metal components of chip packages 700, 800, and 850 (e.g., conductive filled vias 124, first and second conductive structures 129, 140) are formed during packaging using a suitable metal deposition process (e.g., PVD, CVD, sputtering, electrolytic plating, or electroless plating). For example, first panel-level conductive traces 125 are formed directly on conductive filled vias 124 and connection pad front surfaces 2011; then, first panel-level conductive posts 127 are formed directly on first panel-level conductive traces 125. Thus, all conductive components in chip packages 700, 800, and 850 are directly connected, eliminating the need for a process to form a spot plating layer 918 during packaging. Consequently, the direct connections in chip packages 700, 800, and 850 improve the reliability and mechanical stability of the connections between conductive components, which further enhances their performance in moisture senility level tests.

[0279] In addition, the chip packages 700, 800, and 850 do not require solder bumps or solder balls 922 in the conventional chip package 900 to connect to a printed circuit board (PCB) or substrate, passive components, or a heat sink. For example, the first and second dies 602, 604 and the driver circuit 720 are directly connected to the printed circuit board (PCB) or substrate 410 via the first conductive structure 129 without using solder bumps or solder balls. For another example, the first and second dies 602, 604 and the driver circuit 720 are directly connected to the passive components 420 (such as the resistor 740, the capacitor 742, and the inductor 744) or the heat sink 430 via the second conductive structure, also without using solder bumps or solder balls. Compared to the conventional chip package 900, direct connection has multiple benefits for the chip packages 700, 800, and 850, especially when used as power modules.

[0280] Solder is relatively soft; therefore, solder bumps or balls 922 can easily deform when mounting the components of conventional chip package 900 (including semiconductor dies 902 and 904, copper clip 906, leadframe 912, and mold layer 920). Furthermore, solder has a low melting point; when a conventional chip package (especially a power module) generates significant heat, solder bumps or balls 922 may melt and move, potentially affecting or even damaging the electrical connections within conventional chip package 900.

[0281] Solder also has high resistance and impedance for large currents, and electromigration may also occur when the current flow in the power module is large. In contrast, the directly connected conductive material (such as copper) in chip packages 700, 800, and 850 has much lower resistance and impedance and is not easily affected by electromigration, making it suitable for use as a power module.

[0282] Furthermore, the conventional chip package 900 has long conductive paths along the copper clip 906 and wire bonds 910, which can cause severe parasitic effects and conduction losses. In contrast, the direct connections in the chip packages 700, 800, and 850 have shorter conductive paths through the first and second conductive structures 129, 140 and the connection pads 201 of the metal frame 200, thereby reducing parasitic effects and conduction losses.

[0283] Furthermore, a seed layer (not shown) may be formed to further enhance direct connection before forming direct connection in chip packages 700, 800, 850. The seed layer may be formed by sputtering Ti / Cu, sputtering SUS / Cu / SUS, electroless copper plating, or a combination thereof.

[0284] Reference Figure 40 Conventional chip package 900 primarily dissipates heat from the plastic layer 920, which completely encapsulates the first and second semiconductor dies 902, 904, and the C-copper clip 906. Consequently, heat generated by the first and second semiconductor dies 902, 904, as well as heat generated by the electrical flux flowing within conventional chip package 900, may not be effectively transferred to the surrounding environment. Consequently, conventional chip package 900 is not well-suited for power modules.

[0285] In contrast, chip packages 700, 800, and 850 feature the aforementioned three-sided heat dissipation design, facilitating efficient cooling. Specifically, on the first side, heat is dissipated from the first and second die active surfaces 6021, 6041, and the active driving surface 7201 of the driver circuit 720, via the first conductive structure 129; on the second side, heat is dissipated from the first and second die back surfaces 6022, 6042, and the driving back surface 7202 of the driver circuit 720, via the second conductive structure 140; and on the third side, heat is dissipated from the side surface 402 via the connection pads 201. Furthermore, a heat sink 430 can be mounted on the second conductive structure 140 to accelerate heat dissipation from the chip packages 700, 800, and 850.

[0286] The specific embodiments described above are intended to provide further detailed description of the technical solutions and technical effects of the present disclosure. However, those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the scope of the invention of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A chip package for a power module, characterized in that: include: at least one die having opposing die active sides and die back sides, wherein the at least one die has a relatively thin thickness for reducing resistance when used as a power module; a driver circuit for controlling the at least one die, the driver circuit having an opposed driver active side and a driver back side; A protective layer formed on the die active surface and the driver active surface, wherein the protective layer has a plurality of protective layer openings for exposing the die active surface and the driver active surface from the protective layer; a metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front and connection pad back surfaces; a plastic encapsulation layer, used to encapsulate the at least one bare chip, the driving circuit, the protective layer and the metal unit; a first conductive structure formed on at least one metal feature of the metal unit, the protective layer, and the plastic layer, wherein the first conductive structure is connected to the die active surface and the driver active surface, for connecting the at least one die and the driver circuit to the metal unit; a second conductive structure formed on at least one metal feature of the metal unit and the mold layer, the second conductive structure and the first conductive structure being on opposite sides of the at least one die, wherein the second conductive structure is connected to the first conductive structure via at least one connection pad of the metal unit; A back surface of the at least one connection pad is in direct contact with the second conductive structure; an additional plastic encapsulation layer formed on a back surface of the at least one die and encapsulated by the plastic encapsulation layer; and at least one gap in the additional plastic layer, for exposing the back side of the die from the plastic layer, wherein the at least one gap is filled with a conductive medium to form a conductive filled gap for connecting to the second conductive structure; The chip package is connected to an external circuit via at least one metal feature.

2. The chip package according to claim 1, wherein: The at least one die includes a first die and a second die, which respectively have a first die active surface and a second die active surface, wherein the first die, the second die and the driving circuit are surrounded by the metal unit, and the first die active surface, the second die active surface and the driving active surface are basically flush.

3. The chip package according to claim 1, wherein: The first conductive structure has a plurality of conductive filled through-holes connected to the active surface of the die and the driving active surface, and a panel-level conductive layer is formed on at least one metal feature of the metal unit, the protective layer and the plastic encapsulation layer, wherein the conductive filled through-holes are formed by filling the openings of the protective layer with conductive material.

4. The chip package according to claim 1, wherein: The first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the die active side and the die backside.

5. The chip package according to claim 1, wherein: The second conductive structure is in direct contact with a back surface of at least one die, and is used to electrically ground the back surface of the chip package.

6. The chip package according to claim 1, wherein: Also includes: a first dielectric layer for encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for connection to the external circuit; and a second dielectric layer for encapsulating the second conductive structure, wherein the second conductive structure is exposed from the second dielectric layer for connection with an external component.

7. A chip package for a power module, characterized in that: include: at least one die having opposing die active sides and die back sides, wherein the at least one die has a relatively thin thickness for reducing resistance when used as a power module; a driver circuit for controlling the at least one die, the driver circuit having an opposed driver active side and a driver back side; A protective layer formed on the die active surface and the driver active surface, wherein the protective layer has a plurality of protective layer openings for exposing the die active surface and the driver active surface from the protective layer; a metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front and connection pad back surfaces; a plastic encapsulation layer, used to encapsulate the at least one bare chip, the driving circuit, the protective layer and the metal unit; a first conductive structure formed on at least one metal feature of the metal unit, the protective layer, and the plastic layer, wherein the first conductive structure is connected to the die active surface and the driver active surface, for connecting the at least one die and the driver circuit to the metal unit; a second conductive structure formed on at least one metal feature of the metal unit and the mold layer, the second conductive structure and the first conductive structure being on opposite sides of the at least one die, wherein the second conductive structure is connected to the first conductive structure via at least one connection pad of the metal unit; A back surface of the at least one connection pad is in direct contact with the second conductive structure; At least two separated gaps are formed on the plastic layer, wherein the gaps are smaller than the chip, and are used to expose the back side of the die from the plastic layer, wherein a conductive medium is filled in at least one of the gaps to form a conductive filled gap, which is used to connect to the second conductive structure; The chip package is connected to an external circuit via at least one metal feature.

8. A chip structure, characterized in that: include: at least one die having opposing die active and die back surfaces; A protective layer formed on the active surface of the die has a plurality of protective layer openings for exposing the active surface of the die from the protective layer; a metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front and connection pad back surfaces; A plastic encapsulation layer, used for encapsulating the bare chip, the protective layer and the metal unit; a first conductive structure formed on at least one metal feature of the metal unit, the protective layer, and the plastic layer, wherein the first conductive structure is connected to the active surface of the die, for connecting the at least one die to the metal unit; a second conductive structure formed on at least one metal feature of the metal unit and the plastic layer, the second conductive structure and the first conductive structure being on opposite sides of the at least one die, wherein the second conductive structure is connected to the at least one die via the first conductive structure and at least one connection pad of the metal unit, for electrically grounding the back of the chip structure; A back surface of the at least one connection pad is in direct contact with the second conductive structure; At least two separated gaps are formed on the plastic layer, wherein the gaps are smaller than the chip, and are used to expose the back side of the die from the plastic layer, wherein a conductive medium is filled in at least one of the gaps to form a conductive filled gap, which is used to connect to the second conductive structure; The chip structure is connected to an external circuit via at least one metal feature.

9. A chip structure, characterized in that: include: at least one die having opposing die active and die back surfaces; A protective layer formed on the active surface of the die has a plurality of protective layer openings for exposing the active surface of the die from the protective layer; a metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front and connection pad back surfaces; A plastic encapsulation layer, used for encapsulating the bare chip, the protective layer and the metal unit; a first conductive structure formed on at least one metal feature of the metal unit, the protective layer, and the plastic layer, wherein the first conductive structure is connected to the active surface of the die, for connecting the at least one die to the metal unit; a second conductive structure formed on at least one metal feature of the metal unit and the plastic layer, the second conductive structure and the first conductive structure being on opposite sides of the at least one die, wherein the second conductive structure is connected to the at least one die via the first conductive structure and at least one connection pad of the metal unit, for electrically grounding the back of the chip structure; A back surface of the at least one connection pad is in direct contact with the second conductive structure; an additional plastic encapsulation layer formed on a back surface of the at least one die and encapsulated by the plastic encapsulation layer; and forming at least one gap in the additional plastic layer for exposing the back side of the die from the plastic layer, wherein the at least one gap is filled with a conductive medium to form a conductive filled gap for connecting to the second conductive structure; The chip structure is connected to an external circuit via at least one metal feature.

10. The chip structure according to claim 9, wherein: The external circuit includes a printed circuit board, and the first conductive structure is in direct contact with the printed circuit board for directly connecting the at least one bare die to the printed circuit board.

11. The chip structure according to claim 9, wherein: The second conductive structure is in direct contact with a backside of at least one die, and is configured to transfer heat from the backside of the die to out of the chip structure.

12. The chip structure according to claim 11, wherein: The first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the die active side and the die backside.

13. A method for manufacturing a chip package for a power module, characterized in that: include: providing at least one die having an opposing die active surface and a die back surface, wherein the at least one die has a thinner thickness between the die active surface and the die back surface for reducing resistance of the power module; providing a driver circuit for controlling the at least one die, the driver circuit having opposing driver active and driver back surfaces; forming a protective layer on the die active surface and the driver active surface, wherein the protective layer has a plurality of protective layer openings for exposing the die active surface and the driver active surface from the protective layer; placing a metal unit around the at least one die and the driver circuitry, wherein the metal unit has at least one metal feature, the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front sides and connection pad back sides; forming a plastic encapsulation layer for encapsulating the at least one bare chip, the driving circuit, the protective layer, and the metal unit; forming a first conductive structure so as to directly contact the connection pad front surface of the at least one connection pad, the second surface of the protective layer, and the plastic layer front surface of the plastic layer; forming a second conductive structure in direct contact with a back surface of the at least one connection pad and a back surface of the plastic encapsulation layer; an additional plastic encapsulation layer formed on a back surface of the at least one die and encapsulated by the plastic encapsulation layer; And forming at least one gap in the additional plastic layer to expose the back side of the die from the plastic layer, wherein a conductive medium is filled in the at least one gap to form a conductive filled gap for connecting to the second conductive structure; and connecting the chip package to an external circuit through at least one metal feature of the metal unit.

14. The manufacturing method according to claim 13, wherein: Also includes: The front surface of the connection pad, the second surface of the protection layer and the front surface of the plastic packaging layer are substantially flush.

15. The manufacturing method according to claim 13, wherein: Also includes: forming a first dielectric layer encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for connection with the external circuit; and forming a second dielectric layer encapsulating the second conductive structure, wherein the second conductive structure is exposed from the second dielectric layer for connection with an external component.

16. A method for manufacturing a chip package for a power module, characterized in that: include: providing at least one die having an opposing die active surface and a die back surface, wherein the at least one die has a thinner thickness between the die active surface and the die back surface for reducing resistance of the power module; providing a driver circuit for controlling the at least one die, the driver circuit having opposing driver active and driver back surfaces; forming a protective layer on the die active surface and the driver active surface, wherein the protective layer has a plurality of protective layer openings for exposing the die active surface and the driver active surface from the protective layer; placing a metal unit around the at least one die and the driver circuitry, wherein the metal unit has at least one metal feature, the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front sides and connection pad back sides; forming a plastic encapsulation layer for encapsulating the at least one bare chip, the driving circuit, the protective layer, and the metal unit; forming a first conductive structure so as to directly contact the connection pad front surface of the at least one connection pad, the second surface of the protective layer, and the plastic layer front surface of the plastic layer; forming a second conductive structure in direct contact with a back surface of the at least one connection pad and a back surface of the plastic encapsulation layer; At least two separated gaps are formed on the plastic layer, wherein the gaps are smaller than the chip, and are used to expose the back side of the die from the plastic layer, wherein a conductive medium is filled in at least one of the gaps to form a conductive filled gap, which is used to connect to the second conductive structure; The chip package is connected to an external circuit via at least one metal feature of the metal unit.

17. A chip package for a power module, characterized in that: include: at least one die having opposing die active sides and die back sides, wherein the at least one die has a relatively thin thickness for reducing resistance when used as a power module; a driver circuit for controlling the at least one die, the driver circuit having an opposed driver active side and a driver back side; A protective layer formed on the die active surface and the driver active surface, wherein the protective layer has a plurality of protective layer openings for exposing the die active surface and the driver active surface from the protective layer; a metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front and connection pad back surfaces; a plastic encapsulation layer, used to encapsulate the at least one bare chip, the driving circuit, the protective layer and the metal unit, a first conductive structure formed on at least one metal feature of the metal unit, the protective layer and the plastic layer, a second conductive structure formed on at least one metal feature of the metal unit and the mold layer, the second conductive structure and the first conductive structure being on opposite sides of the at least one die; The plastic sealing layer has a back surface of the plastic sealing layer away from the first conductive structure, the back surface of the plastic sealing layer is substantially flush with the back surface of the connection pad, and the second conductive structure is located on the back surface of the plastic sealing layer; an additional plastic encapsulation layer formed on a back surface of the at least one die and encapsulated by the plastic encapsulation layer; and forming at least one gap in the additional plastic layer for exposing the back side of the die from the plastic layer, wherein the at least one gap is filled with a conductive medium to form a conductive filled gap for connecting to the second conductive structure; The chip package is connected to an external circuit via at least one metal feature.

18. A chip structure, characterized in that: include: at least one die having opposing die active and die back surfaces; A protective layer formed on the active surface of the die has a plurality of protective layer openings for exposing the active surface of the die from the protective layer; a metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad having opposing connection pad front and connection pad back surfaces; A plastic encapsulation layer, used for encapsulating the bare chip, the protective layer and the metal unit; a first conductive structure formed on at least one metal feature of the metal unit, the protective layer, and the plastic layer, wherein the first conductive structure is connected to the active surface of the die, for connecting the at least one die to the metal unit; a second conductive structure formed on at least one metal feature of the metal unit and the plastic layer, the second conductive structure and the first conductive structure being on opposite sides of the at least one die, wherein the second conductive structure is connected to the at least one die via the first conductive structure and at least one connection pad of the metal unit, for electrically grounding the back of the chip structure; The plastic sealing layer has a back surface of the plastic sealing layer away from the first conductive structure, the back surface of the plastic sealing layer is substantially flush with the back surface of the connection pad, and the second conductive structure is located on the back surface of the plastic sealing layer; an additional plastic encapsulation layer formed on a back surface of the at least one die and encapsulated by the plastic encapsulation layer; and forming at least one gap in the additional plastic layer for exposing the back side of the die from the plastic layer, wherein the at least one gap is filled with a conductive medium to form a conductive filled gap for connecting to the second conductive structure; The chip structure is connected to an external circuit via at least one metal feature.

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