Dead time adjustable complementary signal generation circuit

Abstract

The application discloses a dead time adjustable complementary signal generation circuit, and belongs to the technical field of power electronics. The application mainly comprises a signal phase-shifting circuit, a signal comparison circuit and a signal combination circuit. The signal phase-shifting circuit performs phase-shifting processing on an input pulse signal, and the phase-shifting phase is adjustable; the signal comparison circuit compares the pulse signal output by the signal phase-shifting circuit with a specific voltage, and performs amplification and shaping on the pulse signal; and the signal combination circuit is used for performing logic combination processing on the signals and outputting a complementary signal with a dead time. The application can provide conditions for driving power electronic devices, and can change the length of the dead time by changing the parameters of resistors and capacitors in the circuit, so that the needs of different occasions can be met, normal work of the devices can be realized, and the reliability and stability of the system can be improved. The application does not depend on the dead time generation function of a control chip, is not limited by the number of pins and hardware resources of a micro control chip, and can better meet actual needs.

Description

Technical Field

[0001] The present invention relates to a complementary signal generating circuit with adjustable dead time, which can be used in various types of power electronic equipment to generate complementary signals containing dead time and drive power electronic devices to work, belonging to the field of power electronic technology. Background Art

[0002] Currently, in power electronic devices used in half-bridge circuits, full-bridge circuits, and three-phase bridge inverter circuits, the upper and lower power electronic devices in the same bridge arm need to be driven using complementary signals, and dead zones are added to the signal edges to improve reliability. Currently, the two complementary signals are primarily generated using microcontroller chips. For example, based on the advanced timer function of the control chip, two complementary pulses with adjustable dead zones can be generated. However, using microcontroller chips to generate complementary pulses has many limitations. For example, it requires the use of specific microcontroller chip models, and only some control chips with advanced timer functions can generate complementary pulses with built-in dead zones, resulting in high costs and poor flexibility. Furthermore, when a large number of complementary pulses are required, a single microcontroller chip is insufficient. Increasing the number of microcontroller chips leads to complex clock synchronization, difficulty in data sharing, and low reliability. Therefore, the present invention designs a complementary pulse generation circuit with adjustable dead zones. The circuit has the advantages of low cost, simple structure, fast response, and low power consumption. It can be used in power electronic devices to generate an output signal complementary to the input signal and including a dead zone based on an input signal, thereby driving the power electronic devices. The circuit proposed in this invention consists of three circuits: a signal phase shift circuit, a signal comparison circuit, and a signal combination circuit. The signal phase shift circuit is constructed using basic components such as an adjustable resistor, a resistor, a capacitor, a diode, and a transistor. The signal comparison circuit is constructed using a resistor, a Zener diode, and an operational amplifier. It outputs a low level when the input signal voltage of the signal comparison circuit exceeds a larger threshold, and a high level when the input signal of the signal comparison circuit is below a smaller threshold. The signal combination circuit is composed of a NOT gate, an AND gate, and an OR gate, ultimately generating a complementary signal that is opposite to the input signal and has a dead zone.

[0003] In power electronic devices with bridge structures (such as half-bridge circuits, full-bridge circuits, and three-phase bridge circuits), the upper and lower switching devices in the same bridge arm need to be driven using complementary signals with dead-zones. This invention proposes a complementary signal generation circuit with adjustable dead-zone time. Based on the drive signal from one power electronic device, this circuit generates a pair of complementary drive signals with dead-zones, driving the two power electronic switching devices in the same bridge arm to operate normally, ensuring the long-term stable operation of the system.

[0004] Currently, microcontroller chips are mainly used to generate a pair of complementary signals and insert dead zones in the signals. This technical solution has some drawbacks:

[0005] 1. Only specific microcontrollers that provide the function of generating dead zones and complementary signals can be used, resulting in high system costs and low flexibility.

[0006] 2. Limited by the number of microcontroller chip pins and hardware resources, only a small number of complementary signals containing dead zones can be generated, which cannot meet actual needs;

[0007] 3. When the microcontroller chip freezes or the program runs incorrectly, it may generate an erroneous signal, causing the power electronic device to be incorrectly turned on or off. Summary of the Invention

[0008] In view of the disadvantages of high cost, low flexibility and low reliability of the method of generating complementary signals using a microcontroller chip mentioned in the above background technology, the purpose of the present invention is to provide a complementary signal generating circuit with adjustable dead time, which is used to generate a set of signals that are logically opposite to the input signal and include a dead zone, providing conditions for driving power electronic devices in power electronic equipment, and can change the length of the dead zone by changing the parameters of the resistors and capacitors in the circuit, thereby meeting the needs of different occasions, realizing normal operation of the equipment, and improving the reliability and stability of the system.

[0009] The purpose of the present invention is achieved through the following technical solutions.

[0010] The present invention discloses a complementary signal generation circuit with adjustable dead time, primarily consisting of a signal phase shift circuit, a signal comparison circuit, and a signal combination circuit. The signal phase shift circuit performs an adjustable phase shift on the input pulse signal; the signal comparison circuit compares the pulse signal output by the phase shift circuit with a specific voltage, amplifying and shaping it; and the signal combination circuit logically combines the signals to output a complementary signal with a dead time.

[0011] The signal phase shift circuit performs phase shifting processing on the input pulse signal, and the phase shift phase is adjustable. The signal phase shift circuit is mainly composed of resistors (R1, R2), capacitor C1, diode D1 and PNP transistor Q1; when the input signal x is at a high level, transistor Q1 is turned off, capacitor C1 is charged through resistor R1, and the charging time t1 of the capacitor is changed by adjusting the values ​​of resistor R1 and capacitor C1. The calculation method of t1 is shown in formula (1); when the input signal x is at a low level, transistor Q1 is turned on, capacitor C1 is discharged through resistor R2, and the discharge time t2 of the capacitor is changed by adjusting the values ​​of resistor R2 and capacitor C1. The calculation method of t2 is shown in formula (2). The signal comparison circuit is used to shape and amplify the output signal y1 of the phase shift circuit. The signal comparison circuit includes resistors (R3, R4, R5), capacitors (C2, C3), voltage-stabilizing diodes (D2, D3) and a comparator U2. The signal combination circuit logically combines the input signal with the signal generated by the signal comparison circuit to generate a signal that includes a dead zone and is opposite to the input signal. The signal combination circuit is composed of an OR gate U2, an AND gate U3 and a NOT gate U4. The two input signals of the AND gate U3 are x and y2, and the output signal is z1. The two input signals of the OR gate U2 are x and y2, and the output signal of the OR gate U2 generates the output signal z2 after passing through the NOT gate U4.

[0012] t1=5R1C1 (1)

[0013] t2=5R2C1 (2)

[0014] The anode of diode D1 is connected to the input signal, represented by x. The anode of diode D1 is connected to the base of transistor Q1, and the cathode of diode D1 is connected to one end of resistor R1. The other end of resistor R1 is connected to the positive electrode of capacitor C1. One end of resistor R2 is connected to the positive electrode of capacitor C1, and the other end of resistor R2 is connected to the emitter of diode Q1. The collector of transistor Q1 is connected to the negative electrode of DC power supply E1. The negative electrode of capacitor C1 is connected to the negative electrode of DC voltage E1. The positive electrode voltage of capacitor C1 is represented by y1, which is the signal obtained after phase shifting the input signal x. One end of resistor R3 is connected to the positive electrode of DC voltage E1, and the other end of resistor R3 is connected to the positive electrode of capacitor C2. The positive electrode of capacitor C2 is connected to the cathode of Zener diode D2, and the negative electrode of capacitor C2 is connected to the negative electrode of DC voltage E1. The anode of Zener diode D2 is connected to the negative electrode of DC voltage E1. One end of resistor R4 is connected to the positive electrode of DC voltage E1, and the other end of resistor R4 is connected to the positive electrode of capacitor C3. The positive electrode of capacitor C3 is connected to the cathode of Zener diode D3, and the negative electrode of capacitor C3 is connected to the negative electrode of DC voltage E1. The anode of Zener diode D3 is connected to the negative electrode of DC voltage E1. The voltage of capacitor C3 is determined by the breakdown voltage of Zener diode D3. The positive electrode of capacitor C3 is connected to the inverting input of comparator U1, and the non-inverting input of comparator U1 is connected to signal y1. One end of resistor R5 is connected to the positive electrode of capacitor C2, and the other end of resistor R5 is connected to the output of comparator U1. The output signal of comparator U1 is represented by y2. The signal combination circuit combines the circuit input signal x with the output signal of comparator U1. The two input signals of AND gate U3 are x and y2, and the output signal is z1. The two input signals of OR gate U2 are x and y2, and the output signal of OR gate U2 is generated by NOT gate U4 to generate output signal z2.

[0015] By changing the parameters of the resistors and capacitors in the circuit, the length of the dead zone can be changed to meet the needs of different occasions, ensure the normal operation of the equipment, and improve the reliability and stability of the system.

[0016] The working method of a complementary signal generating circuit with adjustable dead time disclosed in the present invention is as follows:

[0017] Step 1: When the input signal x is high, transistor Q1 is in the off state. The input signal charges C1 via diode D1 and resistor R1, and the voltage at C1's anode slowly increases. When the input pulse signal is low, transistor Q1 is in the on state, and capacitor C1 discharges through the series circuit formed by resistor R2 and transistor Q1, gradually reducing the voltage drop at the anode of capacitor C1. This results in a signal y that lags behind x by a certain phase, achieving a phase shift function. For signal y, the charge and discharge process of the capacitor is not instantaneous, so the rising and falling edges of signal y are not strictly vertical transitions, but rather have a certain slope. Furthermore, by adjusting the resistance value of R1, the charging time of capacitor C1 is adjusted, and by adjusting the resistance value of resistor R2, the discharge time of capacitor C1 is adjusted, thereby achieving the purpose of adjusting the phase delay.

[0018] Step 2: When signal y1 is greater than the positive voltage of capacitor C3, the voltage at comparator output y2 is high. When signal y1 is less than the positive voltage of capacitor C3, the voltage at comparator output y2 is low. Therefore, although the edge of signal y1 changes slowly, after passing through the signal comparison circuit, the edge of output signal y2 becomes steeper. By selecting Zener diodes D3 with different breakdown voltages, the flipping moment of signal y2 is changed, further adjusting the signal shape. By selecting Zener diodes D3 with different breakdown voltages, the comparator's supply voltage is varied, and the voltage amplitude when signal y2 is high is also altered.

[0019] Step 3: After the signal x and the signal y2 pass through the AND gate U3, the high level time of the output signal z2 is shorter than the high level time of the signal x; after the signal x and the signal y2 pass through the OR gate U2, the high level time of the obtained signal is longer than the high level time of the signal x; after passing through the NOT gate U4, the low level time of the generated signal z2 is longer than the high level time of the signal x; that is, two complementary signals z1 and z2 containing dead zones are generated according to the signal x, and the dead zone time is adjustable.

[0020] Preferably, the present invention discloses a complementary signal generating circuit with adjustable dead time, which is suitable for power electronic devices including a bridge structure, including half-bridge, full-bridge, and three-phase bridge circuits. The complementary signal generating circuit with adjustable dead time generates a pair of complementary signals including a dead zone based on an input signal. After electrical isolation and voltage amplitude processing, the two signals drive the power electronic switching devices in the power electronic device. The length of the dead zone can be changed by changing the parameters of the resistors and capacitors in the circuit, thereby meeting the needs of different occasions, ensuring normal operation of the equipment, and improving the reliability and stability of the system.

[0021] The power electronic switching devices include MOSFET and IGBT.

[0022] Beneficial effects:

[0023] 1. The present invention discloses a complementary signal generating circuit with adjustable dead time. Based on an input signal, it performs phase shifting, shaping amplification, and logical combination processing on it to generate a pair of complementary signals containing a dead zone. The circuit can be used in power electronic equipment to achieve normal driving of power electronic switching devices with higher reliability and stability.

[0024] 2. The complementary signal generating circuit with adjustable dead time disclosed in the present invention does not rely on the dead zone generation function of the control chip itself, so it has lower functional requirements for the control chip and can use any ordinary pin of the control chip as an input signal, which is more flexible. That is, the present invention is no longer limited by the number of pins and hardware resources of the micro control chip, and can better meet actual needs.

[0025] 3. The present invention discloses a complementary signal generating circuit with adjustable dead time, which mainly uses resistors, capacitors, diodes, voltage-stabilizing diodes, transistors, comparators, NOT gates, AND gates and OR gates. It has the advantages of simple circuit structure, low cost and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The dead zone adjustable complementary pulse generating circuit of the present invention is composed of three parts: a phase shift circuit, a signal comparison circuit and a signal combination circuit.

[0027] Figure 2 Schematic diagram of key signal waveforms in the circuit of the present invention. DETAILED DESCRIPTION

[0028] In order to better illustrate the purpose and advantages of the present invention, the invention is further described below with reference to the accompanying drawings and examples.

[0029] like Figure 1 As shown, this embodiment discloses a complementary signal generating circuit with adjustable dead time, which consists of three parts: a signal phase shifting circuit, a signal comparison circuit, and a signal combining circuit. The overall circuit includes resistors R1, R2, R3, R4, R5, capacitors C1, C2, C3, diode D1, Zener diode D2, Zener diode D3, PNP transistor Q1, comparator U1, OR gate U2, AND gate U3, and NOT gate U4. The DC voltage is E1.

[0030] The specific connection method and working principle of a complementary signal generating circuit with adjustable dead time disclosed in this embodiment are as follows:

[0031] 1. The signal phase shift circuit is used to perform phase shift processing on the input pulse signal, and the phase shift phase is adjustable.

[0032] The anode of diode D1 is connected to the input signal, represented by x. The anode of diode D1 is connected to the base of transistor Q1, and the cathode of diode D1 is connected to one end of resistor R1. The other end of resistor R1 is connected to the positive electrode of capacitor C1. One end of resistor R2 is connected to the positive electrode of capacitor C1, and the other end of resistor R2 is connected to the emitter of diode Q1. The collector of transistor Q1 is connected to the negative electrode of DC power supply E1. The negative electrode of capacitor C1 is connected to the negative electrode of DC voltage E1. The positive electrode voltage of capacitor C1 is represented by y1, which is the signal obtained after the input signal x is phase-shifted.

[0033] The signal phase shift circuit works as follows:

[0034] When the input signal x is high, transistor Q1 is off. The input signal charges C1 via diode D1 and resistor R1, causing the voltage at C1's anode to slowly increase. When the input pulse signal is low, transistor Q1 is on, and capacitor C1 discharges through the series circuit formed by resistor R2 and transistor Q1, gradually reducing the voltage drop at the anode of capacitor C1. This results in signal y lagging behind x by a certain phase, achieving a phase shift function. For signal y, the charge and discharge process of the capacitor is not instantaneous, so the rising and falling edges of signal y are not strictly vertical transitions, but rather occur slowly. Furthermore, the charging time of capacitor C1 can be adjusted by adjusting the resistance of R1, and the discharge time of capacitor C1 can be adjusted by adjusting the resistance of resistor R2, thereby adjusting the phase delay.

[0035] 2. The signal comparison circuit compares the pulse signal output by the phase shift circuit with a specific voltage, amplifies and shapes it.

[0036] One end of resistor R3 is connected to the positive electrode of DC voltage E1, and the other end of resistor R3 is connected to the positive electrode of capacitor C2. The positive electrode of capacitor C2 is connected to the cathode of Zener diode D2, and the negative electrode of capacitor C2 is connected to the negative electrode of DC voltage E1. The anode of Zener diode D2 is connected to the negative electrode of DC voltage E1. The voltage of capacitor C2 is determined by the breakdown voltage of Zener diode D2 and is used to power comparator U1.

[0037] One end of resistor R4 is connected to the positive electrode of DC voltage E1, and the other end of resistor R4 is connected to the positive electrode of capacitor C3. The positive electrode of capacitor C3 is connected to the cathode of Zener diode D3, and the negative electrode of capacitor C3 is connected to the negative electrode of DC voltage E1. The anode of Zener diode D3 is connected to the negative electrode of DC voltage E1. The voltage of capacitor C3 is determined by the breakdown voltage of Zener diode D3. The positive electrode of capacitor C3 is connected to the inverting input of comparator U1, and the non-inverting input of comparator U1 is connected to signal y1. One end of resistor R5 is connected to the positive electrode of capacitor C2, and the other end of resistor R5 is connected to the output of comparator U1. The output signal of comparator U1 is represented by y2.

[0038] The signal comparison circuit works as follows:

[0039] When signal y1 is greater than the positive voltage of capacitor C3, the voltage at comparator output y2 is high. When signal y1 is less than the positive voltage of capacitor C3, the voltage at comparator output y2 is low. Therefore, although the edge of signal y1 changes slowly, after passing through the signal comparison circuit, the edge of output signal y2 becomes steeper. By selecting Zener diodes D3 with different breakdown voltages, the flipping moment of signal y2 can be changed, further adjusting the signal shape. By selecting Zener diodes D3 with different breakdown voltages, the comparator's supply voltage can be varied, and the voltage amplitude when signal y2 is high can be altered. As a result, signal y2 has a shape approximately identical to input signal x1, but with a phase lag.

[0040] 3. The signal combination circuit is used to perform logical combination processing on the signals and output complementary signals with dead zones.

[0041] The signal combination circuit combines the circuit's input signal x with the output signal of comparator U1. AND gate U3's two input signals are x and y2, and its output signal is z1. OR gate U2's two input signals are x and y2, and its output signal passes through NOT gate U4 to generate output signal z2.

[0042] The signal combination circuit works as follows:

[0043] After signal x and signal y2 pass through AND gate U3, the high level time of the output signal z2 is shorter than the high level time of signal x; after signal x and signal y2 pass through OR gate U2, the high level time of the obtained signal is longer than the high level time of signal x; after passing through NOT gate U4, the low level time of the generated signal z2 is longer than the high level time of signal x.

[0044] The waveforms of signal x, signal y1, signal y2, signal z1 and signal z2 are as follows: Figure 2In summary, this embodiment can generate two complementary signals z1 and z2 containing dead zones according to the signal x, and the dead zone time is adjustable, thus providing conditions for driving the power electronic equipment to operate normally.

[0045] This embodiment is applied to power electronic devices with bridge structures, such as half-bridge, full-bridge, and three-phase bridge circuits. The circuit proposed in the present invention can generate a pair of complementary signals containing a dead zone based on an input signal. After electrical isolation and voltage amplitude processing, the two signals drive various types of power electronic switching devices such as MOSFETs and IGBTs in the power electronic device. The length of the dead zone can be changed by changing the parameters of the resistors and capacitors in the circuit, thereby meeting the needs of different occasions, ensuring normal operation of the equipment, and improving the reliability and stability of the system.

[0046] The above specific description further illustrates the purpose, technical solutions and beneficial effects of the invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A complementary signal generating circuit with adjustable dead time, characterized in that: The working method is: Step 1: When the input signal x is high, transistor Q1 is in the off state, and the input signal charges C1 through diode D1 and resistor R1, and the voltage at the positive electrode of C1 will slowly increase; when the input pulse signal is low, transistor Q1 is in the on state, and capacitor C1 discharges through the series circuit of resistor R2 and transistor Q1, and the voltage drop at the positive electrode of capacitor C1 gradually decreases; thereby, a signal y is obtained that lags behind x by a certain phase, realizing a phase shift function; for signal y, the charging and discharging process of the capacitor is not instantaneous, so the rising and falling edges of signal y are not strictly vertical jump processes, but have a certain slope; and the charging time of capacitor C1 is adjusted by adjusting the resistance value of R1, or the discharge time of capacitor C1 is adjusted by adjusting the resistance value of resistor R2, so as to achieve the purpose of adjusting the phase delay; Step 2: When signal y1 is greater than the positive voltage of capacitor C3, the voltage at output terminal y2 of the comparator is high. When signal y1 is less than the positive voltage of capacitor C3, the voltage at output terminal y2 of the comparator is low. Therefore, although the edge of signal y1 changes slowly, after passing through the signal comparison circuit, the edge of output signal y2 becomes steeper. By selecting Zener diodes D3 with different breakdown voltages, the flipping moment of signal y2 is changed, further adjusting the signal shape. By selecting Zener diodes D3 with different breakdown voltages, the supply voltage of the comparator is changed, and the voltage amplitude when signal y2 is high is also changed. Step 3: After signal x and signal y2 pass through AND gate U3, the high-level time of the output signal z2 is shorter than the high-level time of signal x; after signal x and signal y2 pass through OR gate U2, the high-level time of the obtained signal is longer than the high-level time of signal x; after passing through NOT gate U4, the low-level time of the generated signal z2 is longer than the high-level time of signal x; that is, two complementary signals z1 and z2 containing dead zones are generated according to signal x, and the dead zone time is adjustable; The anode of the diode D1 of the circuit is connected to the input signal, which is represented by x; the anode of the diode D1 is connected to the base of the transistor Q1, the cathode of the diode D1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the positive electrode of the capacitor C1; one end of the resistor R2 is connected to the positive electrode of the capacitor C1, and the other end of the resistor R2 is connected to the emitter of the diode Q1; the collector of the transistor Q1 is connected to the negative electrode of the DC power supply E1; the negative electrode of the capacitor C1 is connected to the negative electrode of the DC voltage E1; the positive electrode voltage of the capacitor C1 is represented by y1, which is the signal obtained after the input signal x is phase-shifted; one end of the resistor R3 is connected to the positive electrode of the DC voltage E1, and the other end of the resistor R3 is connected to the positive electrode of the capacitor C2; the positive electrode of the capacitor C2 is connected to the cathode of the Zener diode D2, and the negative electrode of the capacitor C2 is connected to the negative electrode of the DC voltage E1; the anode of the Zener diode D2 is connected to the negative electrode of the DC voltage E1; one end of the resistor R4 is connected to the DC The positive electrode of the DC voltage E1 is connected to the positive electrode of the resistor R4, and the other end of the resistor R4 is connected to the positive electrode of the capacitor C3; the positive electrode of the capacitor C3 is connected to the cathode of the Zener diode D3, and the negative electrode of the capacitor C3 is connected to the negative electrode of the DC voltage E1; the anode of the Zener diode D3 is connected to the negative electrode of the DC voltage E1; the voltage of the capacitor C3 is determined by the breakdown voltage of the Zener diode D3, the positive electrode of the capacitor C3 is connected to the inverting input terminal of the comparator U1, and the non-inverting input terminal of the comparator U1 is connected to the signal y1; one end of the resistor R5 is connected to the positive electrode of the capacitor C2, and the other end of the resistor R5 is connected to the output terminal of the comparator U1; the output signal of the comparator U1 is represented by y2; the signal combination circuit combines the input signal x of the circuit and the output signal of the comparator U1, the two input signals of the AND gate U3 are x and y2, and the output signal is z1; the two input signals of the OR gate U2 are x and y2, and the output signal of the OR gate U2 generates the output signal z2 after passing through the NOT gate U4.

2. The complementary signal generating circuit with adjustable dead time according to claim 1, wherein: The invention is particularly suitable for power electronic devices including a bridge structure, including half-bridge, full-bridge, and three-phase bridge circuits. The complementary signal generating circuit with adjustable dead time generates a pair of complementary signals including a dead time based on an input signal. After electrical isolation and voltage amplitude processing, the two signals drive the power electronic switching device in the power electronic device. The length of the dead time can be changed by changing the parameters of the resistor and capacitor in the circuit, thereby meeting the needs of different occasions, ensuring normal operation of the equipment, and improving the reliability and stability of the system. The power electronic switching devices include MOSFET and IGBT.

3. The complementary signal generating circuit with adjustable dead time according to claim 1, wherein: It is mainly composed of a signal phase shift circuit, a signal comparison circuit and a signal combination circuit; the signal phase shift circuit performs phase shift processing on the input pulse signal, and the phase shift phase is adjustable; the signal comparison circuit compares the pulse signal output by the phase shift circuit with a specific voltage, amplifies and shapes it, and the signal combination circuit is responsible for logically combining the signals and outputting complementary signals with dead zones.

4. The complementary signal generating circuit with adjustable dead time according to claim 3, wherein: The signal phase shift circuit performs phase shift processing on the input pulse signal, and the phase shift phase is adjustable; the signal phase shift circuit is mainly composed of resistors (R1, R2), capacitor C1, diode D1 and PNP type transistor Q1; when the input signal x is at a high level, the transistor Q1 is turned off, and the capacitor C1 is charged through the resistor R1. By adjusting the values ​​of the resistor R1 and the capacitor C1, the charging time t1 of the capacitor is changed. The calculation method of t1 is shown in formula (1); when the input signal x is at a low level, the transistor Q1 is turned on, and the capacitor C1 is discharged through the resistor R2. By adjusting the values ​​of the resistor R2 and the capacitor C1, the discharge time t2 of the capacitor is changed. The calculation method of t2 is shown in formula (2) The signal comparison circuit is used to shape and amplify the output signal y1 of the phase shift circuit. The signal comparison circuit includes resistors (R3, R4, R5), capacitors (C2, C3), voltage-stabilizing diodes (D2, D3) and a comparator U1. The signal combination circuit logically combines the input signal with the signal generated by the signal comparison circuit to generate a signal that includes a dead zone and is opposite to the input signal. The signal combination circuit is composed of an OR gate U2, an AND gate U3 and a NOT gate U4. The two input signals of the AND gate U3 are x and y2, and the output signal is z1. The two input signals of the OR gate U2 are x and y2, and the output signal of the OR gate U2 generates the output signal z2 after passing through the NOT gate U4. t1=5R1C1 (1) t2=5R2C1 (2).

5. The complementary signal generating circuit with adjustable dead time according to claim 4, wherein: By changing the parameters of the resistors and capacitors in the circuit, the length of the dead zone can be changed to meet the needs of different occasions, ensure the normal operation of the equipment, and improve the reliability and stability of the system.

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