Non-volatile boolean logic operation circuit and method based on sot-mtj

Abstract

This invention discloses a non-volatile Boolean logic operation circuit based on SOT-MTJ, including an MTJ write circuit module, an MTJ logic tree module, and a pre-charge amplifier module. The MTJ write circuit module is used to write an MTJ state to each of the SOT-MTJs, and the MTJ states include parallel states and antiparallel states. The MTJ logic tree module is used to control the resistance value of the circuit formed by the SOT-MTJs according to the MTJ states. The pre-charge amplifier module is used to output the Boolean logic result corresponding to the MTJ state according to the resistance value. This invention achieves non-volatile Boolean logic by writing MTJ states to the SOT-MTJs in the MTJ logic tree module, controlling the resistance value of the SOT-MTJs, and outputting the Boolean logic result according to the resistance value of the circuit formed by the SOT-MTJs. Furthermore, the resistance value of the SOT-MTJs is not lost due to power loss. Due to the small size design of SOT-MTJs and compatibility with CMOS technology, an in-memory computing architecture for small-size devices is realized. This invention can be widely applied in the field of electronic technology.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic technology, in particular to a non-volatile Boolean logic operation circuit and method based on SOT-MTJ. BACKGROUND

[0002] As a mainstream computer architecture, the Von Neumann architecture is characterized by separating data computation and storage, and data needs to be transmitted to the storage unit through an additional transmission line after being processed by the computing unit. With the reduction of device feature size, the Von Neumann architecture has obvious problems of low data transmission efficiency and high leakage power, i.e., the "memory wall" problem. At the same time, the existing logic device is mainly composed of CMOS circuits. However, as the CMOS device feature size gradually approaches the quantum limit, the quantum effect and short channel effect of the device become more and more obvious, and the effect of electron spin becomes more and more difficult to ignore, resulting in high power consumption and slow performance improvement of the existing logic device, and poor stability of the device. Moreover, the existing CMOS logic circuit loses data after power failure, and does not have data non-volatility, which needs to be powered continuously to maintain data, thereby generating additional power consumption.

[0003] In order to break through the bottleneck of the Von Neumann architecture, relevant researchers have proposed several new devices and circuit structures, among which the most famous one is the magnetic tunnel junction (MTJ). MTJ represents the logic "0" state and "1" state through two different resistance states, replacing the voltage representation method of traditional CMOS circuits. The resistance state of MTJ will not be lost due to power failure, and has non-volatility; MTJ has small read-write current, fast read-write speed, unlimited erasing and small size, and can be compatible with CMOS process to realize in-memory computing and solve the "memory wall" problem. As a new MTJ device, spin-orbit torque magnetic tunnel junction (SOT-MTJ) has attracted widespread attention. In-memory computing requires the design of circuits to realize 16 non-volatile Boolean logics, so that the stored data can be computed in situ without being transmitted to an additional processing module for computation. However, there is no mature SOT-MTJ-based storage system or in-memory computing architecture. Therefore, the design and implementation of non-volatile logic based on the mixing of SOT-MTJ and CMOS not only conforms to the evolution direction of modern computer systems, but also has great potential in solving the "memory wall" limitation of the Von Neumann computing architecture, and has important research significance and potential economic value. SUMMARY

[0004] In order to solve the above technical problems, the application aims to provide a SOT-MTJ-based nonvolatile Boolean logic operation circuit and method, which can realize 16 kinds of nonvolatile Boolean logic and one-bit full adder and realize in-memory calculation of data.

[0005] In one aspect, the application adopts the technical solution to solve its technical problems:

[0006] A SOT-MTJ-based nonvolatile Boolean logic operation circuit comprises:

[0007] An MTJ writing circuit module is configured to write an MTJ state into each SOT-MTJ, and the MTJ state comprises a parallel state and an anti-parallel state.

[0008] An MTJ logic tree module is configured to control the resistance value of a circuit connected by the SOT-MTJ according to the MTJ state.

[0009] A precharge amplifier module is configured to output a Boolean logic result corresponding to the MTJ state according to the resistance value.

[0010] Further, the MTJ writing circuit module comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first inverter, a second inverter, an AND gate, and an NAND gate, the output end of the NAND gate is connected with the gate of the first PMOS tube, the drain of the first PMOS tube is connected with the drain of the first NMOS tube, the gate of the first NMOS tube is connected with the output end of the AND gate, the output end of the AND gate is connected with the input end of the first inverter, the output end of the first inverter is connected with the gate of the second PMOS, the drain of the second PMOS tube is connected with the drain of the second NMOS tube, the gate of the second NMOS tube is connected with the output end of the second inverter, and the input end of the second inverter is connected with the output end of the NAND gate.

[0011] Further, the signals input into the two input ends of the AND gate are respectively a first enable signal and an input data signal, the first enable signal is used to control the start and stop of the MTJ writing circuit module, and the signals input into the two input ends of the NAND gate are respectively the first enable signal and the inverse signal of the input data signal.

[0012] Further, the MTJ writing circuit module is connected with the SOT-MTJ, the SOT-MTJ comprises a first writing port, a second writing port, and a first reading port, the drain of the first PMOS tube is connected with the first writing port of the SOT-MTJ, and the drain of the second PMOS tube is connected with the second writing port of the SOT-MTJ.

[0013] Further, each of the SOT-MTJ in the MTJ logic tree module is connected with one MTJ write circuit module.

[0014] Further, the pre-charge amplifier module comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, the drain of the third PMOS tube is connected with the drain of the fifth PMOS tube, the drain of the third PMOS tube is also connected with the drain of the third NMOS tube, the gate of the third NMOS tube is connected with the gate of the fifth PMOS tube, the source of the third NMOS tube is connected with the drain of the fifth NMOS tube, the gate of the fifth NMOS tube is connected with the gate of the sixth NMOS tube, the drain of the sixth NMOS tube is connected with the source of the fourth NMOS tube, the drain of the fourth NMOS tube is connected with the drain of the fourth PMOS tube, the drain of the fourth NMOS tube is also connected with the drain of the sixth PMOS tube, the gate of the sixth PMOS tube is connected with the gate of the fourth NMOS tube, the input signal of the gate of the third PMOS tube, the gate of the fourth PMOS tube, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube is a second enable signal, the second enable signal is used to control the on-off of the MOS tube.

[0015] Further, the MTJ logic tree module comprises a first topology and a second topology.

[0016] Further, the first topology comprises a first SOT-MTJ, a second SOT-MTJ, a third SOT-MTJ, a fourth SOT-MTJ, a fifth SOT-MTJ and a seventh NMOS tube, the read port of the first SOT-MTJ is connected with the source of the fifth NMOS tube, the write port of the first SOT-MTJ is connected with the read port of the second SOT-MTJ, the write port of the second SOT-MTJ is connected with the drain of the seventh NMOS tube, the drain of the seventh NMOS tube is connected with the write port of the fourth SOT-MTJ, the drain of the seventh NMOS tube is also connected with the write port of the fifth SOT-MTJ, the read port of the fifth SOT-MTJ is connected with the read port of the fourth SOT-MTJ, the read port of the fifth SOT-MTJ is connected with the write port of the third SOT-MTJ, the read port of the third SOT-MTJ is connected with the source of the sixth NMOS tube, the input signal of the gate of the seventh NMOS tube is the second enable signal.

[0017] Furthermore, the second topology includes a sixth SOT-MTJ, a seventh SOT-MTJ, an eighth SOT-MTJ, a ninth SOT-MTJ, a tenth SOT-MTJ, an eleventh SOT-MTJ, a twelfth SOT-MTJ, and an eighth NMOS transistor. The read port of the sixth SOT-MTJ is connected to the source of the fifth NMOS transistor, the write port of the sixth SOT-MTJ is connected to the read port of the seventh SOT-MTJ, the write port of the seventh SOT-MTJ is connected to the drain of the eighth NMOS transistor, and the drain of the eighth NMOS transistor is connected to the eleventh SOT-MTJ. The write port of the OT-MTJ is connected, the drain of the eighth NMOS transistor is also connected to the write port of the twelfth SOT-MTJ, the read port of the twelfth SOT-MTJ is connected to the read port of the eleventh SOT-MTJ, the read port of the twelfth SOT-MTJ is connected to the write port of the tenth SOT-MTJ, the read port of the tenth SOT-MTJ is connected to the write port of the ninth SOT-MTJ, the read port of the ninth SOT-MTJ is connected to the source of the sixth NMOS transistor, and the input signal of the gate of the eighth NMOS transistor is the second enable signal.

[0018] On the other hand, the technical solution adopted by the present invention to solve its technical problem is:

[0019] A non-volatile Boolean logic operation method based on SOT-MTJ, applied to a non-volatile Boolean logic operation circuit based on SOT-MTJ as described above, includes the following steps:

[0020] Write the MTJ state;

[0021] The resistance value of each circuit formed by connecting the SOT-MTJs is controlled according to the MTJ state.

[0022] Based on the resistance value, output the Boolean logic result corresponding to the MTJ state.

[0023] The beneficial effects of this invention are:

[0024] This invention discloses a non-volatile Boolean logic operation circuit based on SOT-MTJ. By writing the MTJ state to the SOT-MTJ in the MTJ logic tree module, the resistance value of the SOT-MTJ is controlled, and the Boolean logic result is output according to the resistance value of the circuit formed by the SOT-MTJ connection. Moreover, the resistance value of the SOT-MTJ will not be lost due to power failure, thus realizing non-volatile Boolean logic. Due to the small size design of SOT-MTJ and compatibility with CMOS technology, an in-memory computing architecture of small-size devices is realized. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a circuit schematic diagram of an MTJ write circuit module based on a non-volatile Boolean logic operation circuit of SOT-MTJ according to the present invention.

[0027] Figure 2 This is a circuit schematic diagram of a precharge amplifier module based on a non-volatile Boolean logic operation circuit of SOT-MTJ according to the present invention.

[0028] Figure 3 This is a circuit schematic diagram of an MTJ logic tree module based on a non-volatile Boolean logic operation circuit of SOT-MTJ according to the present invention;

[0029] Figure 4 This invention relates to a non-volatile Boolean logic operation circuit based on SOT-MTJ to implement A+B, Logic circuit schematic;

[0030] Figure 5 This invention relates to a non-volatile Boolean logic operation circuit based on SOT-MTJ to implement A·B, Logic circuit schematic;

[0031] Figure 6 This invention relates to a non-volatile Boolean logic operation circuit based on SOT-MTJ to implement A, B. Logic circuit schematic;

[0032] Figure 7 This is a circuit schematic diagram of a non-volatile Boolean logic operation circuit based on SOT-MTJ to implement 0 and 1 logic according to the present invention;

[0033] Figure 8 This invention relates to a non-volatile Boolean logic operation circuit based on SOT-MTJ. Logic circuit schematic;

[0034] Figure 9 This invention relates to a non-volatile Boolean logic operation circuit based on SOT-MTJ to implement A⊙B, The logic and circuit schematic of a one-bit full adder.

[0035] Wherein, P1 is the first PMOS transistor; P2 is the second PMOS transistor; P3 is the third PMOS transistor; P4 is the fourth PMOS transistor; P5 is the fifth PMOS transistor; P6 is the sixth PMOS transistor; N1 is the first NMOS transistor; N2 is the second NMOS transistor; N3 is the third NMOS transistor; N4 is the fourth NMOS transistor; N5 is the fifth NMOS transistor; N6 is the sixth NMOS transistor; N7 is the seventh NMOS transistor; N8 is the eighth NMOS transistor; G1 is a NAND gate; G2 is an AND gate; G3 is the first inverter; G4 is the second inverter; VDD is the power supply; Data_input is the input data signal; Write_EN is the first enable. Signals; EN_SA, Second Enable Signal; MTJ1, First SOT-MTJ; MTJ2, Second SOT-MTJ; MTJ3, Third SOT-MTJ; MTJ4, Fourth SOT-MTJ; MTJ5, Fifth SOT-MTJ; MTJ6, Sixth SOT-MTJ; MTJ7, Seventh SOT-MTJ; MTJ8, Eighth SOT-MTJ; MTJ9, Ninth SOT-MTJ; MTJ10, Tenth SOT-MTJ; MTJ11, Eleventh SOT-MTJ; MTJ12, Twelfth SOT-MTJ; w1, First Write Port; w2, Second Write Port; r, Read Port. Detailed Implementation

[0036] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0037] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0038] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0039] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0040] Reference Figure 1 , Figure 2 and Figure 3 This invention provides a non-volatile Boolean logic operation circuit based on SOT-MTJ, comprising:

[0041] The MTJ writing circuit module is used to write an MTJ state to each of the SOT-MTJs, the MTJ state including a parallel state and an antiparallel state;

[0042] The MTJ logic tree module is used to control the resistance value of each circuit formed by connecting the SOT-MTJs according to the MTJ state.

[0043] The precharge amplifier module is used to output the Boolean logic result corresponding to the MTJ state based on the magnitude of the resistance value.

[0044] Specifically, SOT-MTJ consists of a fixed layer and a free layer. The magnetic effect of the current can reverse the magnetization direction of the free layer. When the magnetization direction of the free layer is the same as that of the fixed layer, it is in a parallel state (P-state); when the magnetization direction of the free layer is opposite to that of the fixed layer, it is in an antiparallel state (AP-state). The resistance of SOT-MTJ in the AP state is much greater than that in the P state, satisfying the relationship 2*R. P <R P +R AP / 2 <R P +R AP .

[0045] Reference Figure 1As an optional implementation, the MTJ write circuit module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, a second inverter, an AND gate, and a NAND gate. The output of the NAND gate is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the output of the AND gate, the output of the AND gate is connected to the input of the first inverter, the output of the first inverter is connected to the gate of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the output of the second inverter, and the input of the second inverter is connected to the output of the NAND gate.

[0046] As an optional implementation, the signals input to the two input terminals of the AND gate are a first enable signal and an input data signal, respectively, and the signals input to the two input terminals of the NAND gate are the inverted signals of the first enable signal and the input data signal, respectively.

[0047] The first enable signal is used to control the start and stop of the MTJ write circuit module.

[0048] Specifically, when the first enable signal is "0", the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are turned off, and the MTJ write circuit module is in a stopped working state; when the first enable signal is "1", the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are determined to be turned on in combination with the input data signal.

[0049] As an optional implementation, the MTJ write circuit module is connected to the SOT-MTJ. The SOT-MTJ includes a first write port, a second write port, and a first read port. The drain of the first PMOS transistor is connected to the first write port of the SOT-MTJ, and the drain of the second PMOS transistor is connected to the second write port of the SOT-MTJ. This is used to write an MTJ state to the SOT-MTJ through the MTJ write circuit module.

[0050] Specifically, if current flows in from the first write port and out from the second write port, the SOT-MTJ flips to the P state; if current flows in from the second write port and out from the first write port, the SOT-MTJ flips to the AP state.

[0051] As an optional implementation, each SOT-MTJ in the MTJ logic tree module is connected to an MTJ write circuit module for writing MTJ states to each SOT-MTJ in the MTJ logic tree module.

[0052] Reference Figure 2 As an optional implementation, the precharge amplifier module includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the third PMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the third PMOS transistor is also connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fifth PMOS transistor, and the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor is also connected to the drain of the sixth PMOS transistor, and the gate of the sixth PMOS transistor is connected to the gate of the fourth NMOS transistor. The input signals of the gates of the third PMOS transistor, the fourth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are the second enable signals.

[0053] The second enable signal is used to control the on / off state of the MOS transistors, and the fifth PMOS transistor and the third NMOS transistor, the sixth PMOS transistor and the fourth NMOS transistor constitute two coupled inverters.

[0054] Specifically, when the second enable signal is "0", the third and fourth PMOS transistors are turned on, and the fifth and sixth NMOS transistors are turned off. At this time, the drains of the fifth and sixth NMOS transistors are charged to the power supply voltage VDD. When the second enable signal is "1", the third and fourth PMOS transistors are turned off, and the fifth and sixth NMOS transistors are turned on. At this time, the drains of the fifth and sixth NMOS transistors begin to discharge, and the current flows into the MTJ logic tree module through two branches.

[0055] Reference Figure 3 As an optional implementation, the MTJ logic tree module includes a first topology and a second topology.

[0056] like Figure 3As shown in (a), as an optional implementation, the first topology includes a first SOT-MTJ, a second SOT-MTJ, a third SOT-MTJ, a fourth SOT-MTJ, a fifth SOT-MTJ, and a seventh NMOS transistor. The read port of the first SOT-MTJ is connected to the source of the fifth NMOS transistor. The write port of the first SOT-MTJ is connected to the read port of the second SOT-MTJ. The write port of the second SOT-MTJ is connected to the drain of the seventh NMOS transistor. The drain of the seventh NMOS transistor is connected to the write port of the fourth SOT-MTJ. The drain of the seventh NMOS transistor is also connected to the write port of the fifth SOT-MTJ. The read port of the fifth SOT-MTJ is connected to the read port of the fourth SOT-MTJ. The read port of the fifth SOT-MTJ is connected to the write port of the third SOT-MTJ. The read port of the third SOT-MTJ is connected to the source of the sixth NMOS transistor. The input signal of the gate of the seventh NMOS transistor is the second enable signal.

[0057] In the MTJ logic tree module, the SOT-MTJ read port is connected to either of the two write ports.

[0058] Specifically, when the second enable signal is "1", the seventh NMOS transistor is turned on. The discharge current of the fifth NMOS transistor flows to ground through the first SOT-MTJ, the second SOT-MTJ, and the seventh NMOS transistor. The discharge current of the sixth NMOS transistor flows to ground through the third SOT-MTJ, the fourth SOT-MTJ, the fifth SOT-MTJ, and the seventh NMOS transistor, forming two discharge branches. The discharge speed is compared based on the resistance values ​​of the two discharge branches. The smaller the resistance value of the discharge branch, the faster the discharge speed, and the level signal input to the inverter of that branch is low, resulting in an inverter output of "1". Conversely, the larger the resistance value of the discharge branch, the slower the discharge speed, and the level signal input to the inverter of that branch is high, resulting in an inverter output of "0".

[0059] like Figure 3As shown in (b), in an optional implementation, the second topology includes a sixth SOT-MTJ, a seventh SOT-MTJ, an eighth SOT-MTJ, a ninth SOT-MTJ, a tenth SOT-MTJ, an eleventh SOT-MTJ, a twelfth SOT-MTJ, and an eighth NMOS transistor. The read port of the sixth SOT-MTJ is connected to the source of the fifth NMOS transistor, the write port of the sixth SOT-MTJ is connected to the read port of the seventh SOT-MTJ, and the write port of the seventh SOT-MTJ is connected to the drain of the eighth NMOS transistor. The eighth NMOS transistor is connected to the write port of the eleventh SOT-MTJ, and its drain is also connected to the write port of the twelfth SOT-MTJ. The read port of the twelfth SOT-MTJ is connected to the read port of the eleventh SOT-MTJ, the read port of the twelfth SOT-MTJ is connected to the write port of the tenth SOT-MTJ, the read port of the tenth SOT-MTJ is connected to the write port of the ninth SOT-MTJ, and the read port of the ninth SOT-MTJ is connected to the source of the sixth NMOS transistor. The input signal of the gate of the eighth NMOS transistor is the second enable signal.

[0060] In the MTJ logic tree module, the SOT-MTJ read port is connected to either of the two write ports.

[0061] Specifically, when the second enable signal is "1", the seventh NMOS transistor is turned on. The discharge current from the fifth NMOS transistor flows to ground through the sixth, seventh, and eighth SOT-MTJ transistors and the seventh NMOS transistor. The discharge current from the sixth NMOS transistor flows to ground through the ninth, tenth, eleventh, and twelfth SOT-MTJ transistors and the seventh NMOS transistor, forming two discharge branches. The discharge speed is compared based on the resistance values ​​of the two discharge branches. The smaller the resistance value of the discharge branch, the faster the discharge speed, and the level signal input to the inverter of that branch is low, resulting in an inverter output of "1". Conversely, the larger the resistance value of the discharge branch, the slower the discharge speed, and the level signal input to the inverter of that branch is high, resulting in an inverter output of "0".

[0062] On the other hand, the present invention provides a non-volatile Boolean logic operation method based on SOT-MTJ, comprising the following steps:

[0063] Write the MTJ state;

[0064] The resistance value of each circuit formed by connecting the SOT-MTJs is controlled according to the MTJ state.

[0065] Based on the resistance value, output the Boolean logic result corresponding to the MTJ state.

[0066] The following combination Figures 4-9 The present invention provides a detailed explanation of a non-volatile Boolean logic operation method based on SOT-MTJ.

[0067] The P state is set to represent "0" and the AP state to represent "1".

[0068] The writing of the MTJ state is accomplished through the MTJ write circuit module.

[0069] Specifically, when the first enable signal is "1", the MTJ write circuit module enters the startup state. When the input data signal is "0", the inputs of the NAND gate are "1" and "1", and the output is "0". The input of the second inverter is "0", and the output is "1". The inputs of the AND gate are "1" and "0", and the output is "0". The input of the first inverter is "0", and the output is "1". Therefore, the first PMOS transistor and the second NMOS transistor are turned on, and the second PMOS transistor and the first NMOS transistor are turned off. Current flows from the first write port to the second write port, writing to the P state, that is, writing "0" data to the SOT-MTJ. When the input data signal is "1", the NAND gate's inputs are both "1" and "0", and its output is "1". The second inverter's input is "1", and its output is "0". Similarly, the AND gate's inputs are both "1" and "1", and its output is "1". The first inverter's input is "1", and its output is "0". Therefore, the second PMOS transistor and the first NMOS transistor are turned on, while the first PMOS transistor and the second NMOS transistor are turned off. Current flows from the second write port to the first write port, writing to the AP state, i.e., writing "1" to the SOT-MTJ.

[0070] Reference Figure 4 Using the first SOT-MTJ as Boolean logic input A and the second SOT-MTJ as Boolean logic input B, the MTJ write circuit module sets the state of the third SOT-MTJ to P state and sets the states of the fourth and fifth SOT-MTJs to AP state. The values ​​of A and B are the values ​​of the data written by the MTJ write circuit module ("0" or "1").

[0071] At this point, the resistance value of the right branch composed of the third SOT-MTJ, the fourth SOT-MTJ, and the fifth SOT-MTJ is fixed at R. P +R AP / 2, and there exists a relation 2*R P <R P +R AP / 2 <R P +R AP .

[0072] When A and B simultaneously write the data "0", the resistance value of the left branch composed of the first SOT-MTJ and the second SOT-MTJ is 2*R. P Since the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high. OUT1 is "0" and OUT2 is "1".

[0073] When at least one of A and B is written with a data value of "1", the minimum resistance value of the left branch composed of the first SOT-MTJ and the second SOT-MTJ is R. P +R AP Since the resistance value of the left branch is greater than that of the right branch, the discharge speed of the left branch is slower than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is high level, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is low level. OUT1 is "1" and OUT2 is "0".

[0074] In summary, when both A and B write the data "0", OUT1 is "0" and OUT2 is "1"; when at least one of A and B writes the data "1", OUT1 is "1" and OUT2 is "0". Therefore, OUT1 = A + B.

[0075] Reference Figure 5 Using the first SOT-MTJ as Boolean logic input A and the second SOT-MTJ as Boolean logic input B, the MTJ write circuit module sets the states of the third, fourth, and fifth SOT-MTJ to AP state. The values ​​of A and B are the values ​​of the data written by the MTJ write circuit module ("0" or "1").

[0076] At this point, the resistance value of the right branch composed of the third SOT-MTJ, the fourth SOT-MTJ, and the fifth SOT-MTJ is fixed at R. AP +R AP / 2, and there exists a relation R P +R AP <R AP +R AP / 2<2*R AP .

[0077] When A and B simultaneously write the data "1", the resistance value of the left branch composed of the first SOT-MTJ and the second SOT-MTJ is 2*R. APSince the resistance value of the left branch is greater than that of the right branch, the discharge speed of the left branch is slower than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is high level, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is low level. OUT1 is "1" and OUT2 is "0".

[0078] When at least one of A and B has a written data value of "0", the resistance value of the left branch composed of the first SOT-MTJ and the second SOT-MTJ is at most R. P +R AP Since the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high. OUT1 is "0" and OUT2 is "1".

[0079] In summary, when both A and B write the data "1", OUT1 is "1" and OUT2 is "0"; when at least one of A and B writes the data "0", OUT1 is "0" and OUT2 is "1". Therefore, OUT1 = A·B.

[0080] Reference Figure 6 (a) Using the first SOT-MTJ as Boolean logic input A and the second SOT-MTJ as Boolean logic input B, the state of the third SOT-MTJ is set to the inverse of the MTJ state of the first SOT-MTJ via the MTJ write circuit module, i.e. Set the states of the fourth SOT-MTJ and the fifth SOT-MTJ to AP state, with values ​​A and B representing the data written by the MTJ write circuit module ("0" or "1").

[0081] When A writes the data "0", the resistance value of the right branch composed of the third SOT-MTJ, the fourth SOT-MTJ, and the fifth SOT-MTJ is R. AP +R AP / 2, and there exists a relation R AP +R AP / 2>R P +R AP >2*R P The highest resistance value of the left branch, composed of the first SOT-MTJ and the second SOT-MTJ, is R. P +R APSince the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high. OUT1 is "0" and OUT2 is "1".

[0082] When A writes the data "1", the resistance value of the right branch composed of the third SOT-MTJ, the fourth SOT-MTJ, and the fifth SOT-MTJ is R. P +R AP / 2, and there exists a relation R P +R AP / 2 <R P +R AP <2*R AP The minimum resistance value of the left branch composed of the first SOT-MTJ and the second SOT-MTJ is R. P +R AP Since the resistance value of the left branch is greater than that of the right branch, the discharge speed of the left branch is slower than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is high level, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is low level. OUT1 is "1" and OUT2 is "0".

[0083] In summary, when A writes data "0", regardless of whether B writes data "0" or "1", OUT1 will be "0" and OUT2 will be "1"; when A writes data "1", regardless of whether B writes data "0" or "1", OUT1 will be "1" and OUT2 will be "0". Therefore, OUT1 = A.

[0084] Reference Figure 6 (b) Using the first SOT-MTJ as Boolean logic input A and the second SOT-MTJ as Boolean logic input B, the state of the third SOT-MTJ is set to the inverse of the MTJ state of the second SOT-MTJ via the MTJ write circuit module. Set the states of the fourth SOT-MTJ and the fifth SOT-MTJ to AP state, with values ​​A and B representing the data written by the MTJ write circuit module ("0" or "1").

[0085] When B writes the data "0", the resistance value of the right branch composed of the third SOT-MTJ, the fourth SOT-MTJ, and the fifth SOT-MTJ is R. AP +R AP / 2, and there exists a relation R AP +R AP / 2>RP +R AP >2*R P The highest resistance value of the left branch, composed of the first SOT-MTJ and the second SOT-MTJ, is R. P +R AP Since the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high. OUT1 is "0" and OUT2 is "1".

[0086] When B writes the data "1", the resistance value of the right branch composed of the third SOT-MTJ, the fourth SOT-MTJ, and the fifth SOT-MTJ is R. P +R AP / 2, and there exists a relation R P +R AP / 2 <R P +R AP <2*R AP The minimum resistance value of the left branch composed of the first SOT-MTJ and the second SOT-MTJ is R. P +R AP Since the resistance value of the left branch is greater than that of the right branch, the discharge speed of the left branch is slower than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is high level, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is low level. OUT1 is "1" and OUT2 is "0".

[0087] In summary, when B writes data "0", regardless of whether A writes data "0" or "1", OUT1 will be "0" and OUT2 will be "1"; when B writes data "1", regardless of whether A writes data "0" or "1", OUT1 will be "1" and OUT2 will be "0". Therefore, OUT1 = B.

[0088] Reference Figure 7 Using the first SOT-MTJ as Boolean logic input A and the second SOT-MTJ as Boolean logic input B, the MTJ write circuit module sets the states of the third, fourth, and fifth SOT-MTJ to P state. The values ​​of A and B are the values ​​of the data written by the MTJ write circuit module ("0" or "1").

[0089] At this point, the resistance value of the right branch composed of the third SOT-MTJ, the fourth SOT-MTJ, and the fifth SOT-MTJ is fixed at R. P +RP / 2, and there exists a relation R P +R P / 2<2*R P The minimum resistance value of the left branch, composed of the first SOT-MTJ and the second SOT-MTJ, is 2*R. P Therefore, the resistance value of the left branch is greater than that of the right branch, and the discharge speed of the left branch is slower than that of the right branch. As a result, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is high level, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is low level. OUT1 is "1" and OUT2 is "0".

[0090] In summary, regardless of whether the data written to A and B is "0" or "1", OUT1 will be "1" and OUT2 will be "0". Therefore, OUT1 = 1 and OUT2 = 0.

[0091] Reference Figure 8 (a) Using the sixth SOT-MTJ as the Boolean logic input A and the seventh SOT-MTJ as the Boolean logic input B, the state of the eighth SOT-MTJ is set to the P state through the MTJ write circuit module, the states of the ninth and tenth SOT-MTJ are set to the MTJ state of the sixth SOT-MTJ, i.e., A, and the states of the eleventh and twelfth SOT-MTJ are set to the AP state. The values ​​of A and B are the values ​​of the data written by the MTJ write circuit module ("0" or "1").

[0092] When A writes the data "1", the resistance value of the right branch composed of the ninth SOT-MTJ, the tenth SOT-MTJ, the eleventh SOT-MTJ, and the twelfth SOT-MTJ is 2*R. AP +R AP / 2, and there exists a relation 2*R AP +R AP / 2>2*R AP +R P The left branch, composed of the sixth, seventh, and eighth SOT-MTJs, has a maximum resistance of 2*R. AP +R P Since the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high. OUT1 is "0" and OUT2 is "1".

[0093] When A writes the data "0", the resistance value of the right branch composed of the ninth SOT-MTJ, the tenth SOT-MTJ, the eleventh SOT-MTJ, and the twelfth SOT-MTJ is 2*R. P +R AP / 2, and there exists a relation 3*R P <2*R P +R AP / 2<2*R P +R AP When B writes the data "1", the resistance value of the left branch composed of the sixth SOT-MTJ, the seventh SOT-MTJ, and the eighth SOT-MTJ is 2*R. P +R AP The resistance of the left branch is greater than that of the right branch, therefore the discharge speed of the left branch is slower than that of the right branch. Consequently, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is high, while the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is low. OUT1 is "1", and OUT2 is "0". When B writes data "0", the resistance of the left branch is 3*R. P Since the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high. OUT1 is "0" and OUT2 is "1".

[0094] In summary, when A writes the data "1", regardless of whether B writes the data "0" or "1", OUT1 will be "0" and OUT2 will be "1"; when A writes the data "0" and B writes the data "1", OUT1 will be "1" and OUT2 will be "0"; when A writes the data "0" and B writes the data "0", OUT1 will be "0" and OUT2 will be "1". Therefore,

[0095] Reference Figure 8 (b) Using the sixth SOT-MTJ as the Boolean logic input A and the seventh SOT-MTJ as the Boolean logic input B, the state of the eighth SOT-MTJ is set to the P state through the MTJ write circuit module, the states of the ninth and tenth SOT-MTJ are set to the MTJ state of the seventh SOT-MTJ, i.e., B, and the states of the eleventh and twelfth SOT-MTJ are set to the AP state. The values ​​of A and B are the values ​​of the data written by the MTJ write circuit module ("0" or "1").

[0096] When B writes the data "1", the resistance value of the right branch composed of the ninth SOT-MTJ, the tenth SOT-MTJ, the eleventh SOT-MTJ, and the twelfth SOT-MTJ is 2*R. AP +R AP / 2, and there exists a relation 2*R AP +R AP / 2>2*R AP +R P The left branch, composed of the sixth, seventh, and eighth SOT-MTJs, has a maximum resistance of 2*R. AP +R P Since the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high. OUT1 is "0" and OUT2 is "1".

[0097] When B writes the data "0", the resistance value of the right branch composed of the ninth SOT-MTJ, the tenth SOT-MTJ, the eleventh SOT-MTJ, and the twelfth SOT-MTJ is 2*R. P +R AP / 2, and there exists a relation 3*R P <2*R P +R AP / 2<2*R P +R AP When A writes the data "1", the resistance value of the left branch composed of the sixth SOT-MTJ, the seventh SOT-MTJ, and the eighth SOT-MTJ is 2*R. P +R AP The resistance of the left branch is greater than that of the right branch, therefore the discharge speed of the left branch is slower than that of the right branch. Consequently, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is high, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is low. OUT1 is "1", and OUT2 is "0". When A writes data "0", the resistance of the left branch is 3*R. P Since the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high. OUT1 is "0" and OUT2 is "1".

[0098] In summary, when B writes the data "1", regardless of whether A writes the data "0" or "1", OUT1 will be "0" and OUT2 will be "1"; when B writes the data "0" and A writes the data "1", OUT1 will be "1" and OUT2 will be "0"; when B writes the data "0" and A writes the data "0", OUT1 will be "0" and OUT2 will be "1". Therefore,

[0099] Reference Figure 9 (a) Using the sixth SOT-MTJ as Boolean logic input A and the seventh SOT-MTJ as Boolean logic input B, the MTJ write circuit module sets the states of the eighth and ninth SOT-MTJs to P state and the states of the tenth, eleventh, and twelfth SOT-MTJs to AP state. The values ​​of A and B are the values ​​of the data written by the MTJ write circuit module ("0" or "1"). The resistance value of the right branch composed of the ninth, tenth, eleventh, and twelfth SOT-MTJs is R. P +R AP +R AP / 2, and there exists a relation 2*R AP +R P >R P +R AP +R AP / 2>2*R P +R AP >3*R P .

[0100] When A and B simultaneously write the data "1", the resistance of the left branch composed of the sixth SOT-MTJ, the seventh SOT-MTJ, and the eighth SOT-MTJ is 2*R. AP +R P Since the resistance value of the left branch is greater than that of the right branch, the discharge speed of the left branch is slower than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is high level, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is low level, and Cout is "1".

[0101] When A and B simultaneously write the data "0", the resistance value of the left branch composed of the sixth SOT-MTJ, the seventh SOT-MTJ, and the eighth SOT-MTJ is 3*R. PSince the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high, and Cout is "0".

[0102] When either A or B writes the data "0", the resistance of the left branch composed of the sixth SOT-MTJ, the seventh SOT-MTJ, and the eighth SOT-MTJ is 2*R. P +R AP Since the resistance value of the left branch is less than that of the right branch, the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low, the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high, and Cout is "0".

[0103] Reference Figure 9 (b) Using the sixth SOT-MTJ as Boolean logic input A and the seventh SOT-MTJ as Boolean logic input B, the MTJ write circuit module sets the state of the eighth SOT-MTJ to P state, writes Cout to the ninth and tenth SOT-MTJs, and sets the states of the eleventh and twelfth SOT-MTJs to AP state. The values ​​of A and B are the values ​​of the data written by the MTJ write circuit module ("0" or "1"). The resistance of the right branch composed of the ninth, tenth, eleventh, and twelfth SOT-MTJs is R. P +R AP +R AP / 2, and there exists a relation 2*R AP +R AP / 2>2*R P +R AP >2*R P +R AP / 2>3*R P .

[0104] When A and B simultaneously write the data "1", Cout is "1", and the resistance of the left branch is 2*R. AP +R P The resistance value of the right branch is 2*R AP +R AP / 2, the resistance value of the left branch is less than that of the right branch, so the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low level, the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high level, and SUM is "0".

[0105] When A and B simultaneously write the data "0", Cout is "0", and the resistance of the left branch is 3*R. P The resistance value of the right branch is 2*R P +R AP / 2, the resistance value of the left branch is less than that of the right branch, so the discharge speed of the left branch is faster than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is low level, the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is high level, and SUM is "0".

[0106] When either A or B writes the data "0", Cout is "0", and the resistance of the left branch is 2*R. P +R AP The resistance value of the right branch is 2*R P +R AP / 2, the resistance value of the left branch is greater than that of the right branch, so the discharge speed of the left branch is slower than that of the right branch. Therefore, the input of the inverter composed of the fifth PMOS transistor and the third NMOS transistor is high level, and the input of the inverter composed of the sixth PMOS transistor and the fourth NMOS transistor is low level. SUM is "1".

[0107] In summary, when both A and B write the data "1" or "0", SUM is "0"; when either A or B writes the data "0", SUM is "1". Therefore,

[0108] Reference Figure 9 (a) Using the sixth SOT-MTJ as input A of the full adder, the seventh SOT-MTJ as input B, and the eighth SOT-MTJ as carry input C, the MTJ write circuit module sets the state of the ninth SOT-MTJ to P state and the states of the tenth, eleventh, and twelfth SOT-MTJs to AP state. The values ​​of A, B, and C are the values ​​of the data written by the MTJ write circuit module ("0" or "1"). The resistance of the right branch composed of the ninth, tenth, eleventh, and twelfth SOT-MTJs is R. P +R AP +R AP / 2, and there exists a relation 3*R AP >2*R AP +R P >R P +R AP +R AP / 2>2*R P +RAP >3*R P .

[0109] From the above As discussed in the Boolean logic implementation of A⊙B, the resistance value of the left branch can only be greater than the resistance value of the right branch when two or more of the sixth, seventh, and eighth SOT-MTJs are written to the AP state. That is, when at least two or more of A, B, and C are written with the data "1", the resistance value of the left branch is greater than the resistance value of the right branch, and the output Cout is "1". When fewer than two of A, B, and C are written with the data "1", the resistance value of the left branch is less than the resistance value of the right branch, and the output Cout is "0".

[0110] Reference Figure 9 (b) Using the sixth SOT-MTJ as the input A of the full adder, the seventh SOT-MTJ as the input B of the full adder, and the eighth SOT-MTJ as the carry input C of the full adder, the state of the ninth SOT-MTJ is set to P state through the MTJ write circuit module, the ninth and tenth SOT-MTJs are written to Cout, and the states of the eleventh and twelfth SOT-MTJs are set to AP state.

[0111] When Cout is "1", at least two or more of A, B, and C have written the data "1", and the resistance of the right branch is 2*R. AP +R AP / 2, the resistance value of the left branch is 2*R AP +R P Or 3*R AP And there exists a relationship 3*R AP >2*R AP +R AP / 2>2*R AP +R P Therefore, when A, B, and C simultaneously write the data "1", the resistance value of the left branch is greater than the resistance value of the right branch, and SUM is "1"; when only two of A, B, and C write the data "1", the resistance value of the left branch is less than the resistance value of the right branch, and SUM is "0".

[0112] When Cout is "0", there are fewer than two "1" values ​​written to A, B, and C. At this time, the resistance value of the right branch is 2*R. P +R AP / 2, the resistance value of the left branch is 2*R P +R AP Or 3*R P And there exists a relationship 2*R P +R AP >2*R P+R AP / 2>3*R P Therefore, when one of A, B, and C writes the data "1", the resistance value of the left branch is greater than the resistance value of the right branch, and SUM is "1"; when A, B, and C write the data "0" at the same time, the resistance value of the left branch is less than the resistance value of the right branch, and SUM is "0".

[0113] In summary, when A, B, and C are all written with the data "1" or one of A, B, and C is written with the data "1", SUM is "1". When only two of A, B, and C are written with the data "1" or when A, B, and C are all written with the data "0", SUM is "0". Therefore, a one-bit full adder is implemented.

[0114] In summary, the embodiments of the present invention implement 16 types of non-volatile Boolean logic and a one-bit full adder.

[0115] This invention controls the resistance value of SOT-MTJ by writing MTJ states into the SOT-MTJ in the MTJ logic tree module, and outputs Boolean logic results based on the resistance value of the circuit formed by the SOT-MTJ connections. The resistance value of SOT-MTJ will not be lost due to power failure, realizing 16 non-volatile Boolean logic types and a one-bit full adder. Due to the small size design of SOT-MTJ and its compatibility with CMOS technology, an in-memory computing architecture for small-sized devices is realized.

[0116] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A non-volatile Boolean logic operation circuit based on SOT-MTJ, characterized in that, include: The MTJ writing circuit module is used to write an MTJ state to each of the SOT-MTJs, the MTJ state including a parallel state and an antiparallel state; The MTJ logic tree module is used to control the resistance value of each circuit formed by connecting the SOT-MTJs according to the MTJ state. The precharge amplifier module is used to output the Boolean logic result corresponding to the MTJ state according to the magnitude of the resistance value; The MTJ logic tree module is implemented through a first topology, which includes a first SOT-MTJ, a second SOT-MTJ, a third SOT-MTJ, a fourth SOT-MTJ, a fifth SOT-MTJ, and a seventh NMOS transistor. The read port of the first SOT-MTJ is connected to the source of the fifth NMOS transistor in the precharge amplifier module, the write port of the first SOT-MTJ is connected to the read port of the second SOT-MTJ, and the write port of the second SOT-MTJ is connected to the drain of the seventh NMOS transistor. The drain of the seventh NMOS transistor is connected to the write port of the fourth SOT-MTJ, the drain of the seventh NMOS transistor is also connected to the write port of the fifth SOT-MTJ, the read port of the fifth SOT-MTJ is connected to the read port of the fourth SOT-MTJ, the read port of the fifth SOT-MTJ is connected to the write port of the third SOT-MTJ, the read port of the third SOT-MTJ is connected to the source of the sixth NMOS transistor in the precharge amplifier module, and the input signal of the gate of the seventh NMOS transistor is a second enable signal, which is used to control the switching on and off of the MOS transistor.

2. The non-volatile Boolean logic operation circuit based on SOT-MTJ according to claim 1, characterized in that, The MTJ write circuit module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, a second inverter, an AND gate, and a NAND gate. The output of the NAND gate is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the output of the AND gate, the output of the AND gate is connected to the input of the first inverter, the output of the first inverter is connected to the gate of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the output of the second inverter, and the input of the second inverter is connected to the output of the NAND gate.

3. The non-volatile Boolean logic operation circuit based on SOT-MTJ according to claim 2, characterized in that, The signals input to the two input terminals of the AND gate are a first enable signal and an input data signal, respectively. The first enable signal is used to control the start and stop of the MTJ write circuit module. The signals input to the two input terminals of the NAND gate are the inverted signals of the first enable signal and the input data signal, respectively.

4. The non-volatile Boolean logic operation circuit based on SOT-MTJ according to claim 3, characterized in that, The MTJ write circuit module is connected to the SOT-MTJ. The SOT-MTJ includes a first write port, a second write port, and a first read port. The drain of the first PMOS transistor is connected to the first write port of the SOT-MTJ, and the drain of the second PMOS transistor is connected to the second write port of the SOT-MTJ.

5. A non-volatile Boolean logic operation circuit based on SOT-MTJ according to claim 4, characterized in that, Each SOT-MTJ in the MTJ logic tree module is connected to an MTJ write circuit module.

6. The non-volatile Boolean logic operation circuit based on SOT-MTJ according to claim 1, characterized in that, The precharge amplifier module includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the third PMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the third PMOS transistor is also connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fifth PMOS transistor, and the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the transistor is connected to the gate of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor is also connected to the drain of the sixth PMOS transistor, and the gate of the sixth PMOS transistor is connected to the gate of the fourth NMOS transistor. The input signals of the gates of the third PMOS transistor, the fourth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are the second enable signals.

7. A non-volatile Boolean logic operation circuit based on SOT-MTJ according to claim 1, characterized in that, The MTJ logic tree module is further implemented through a second topology, which includes a sixth SOT-MTJ, a seventh SOT-MTJ, an eighth SOT-MTJ, a ninth SOT-MTJ, a tenth SOT-MTJ, an eleventh SOT-MTJ, a twelfth SOT-MTJ, and an eighth NMOS transistor. The read port of the sixth SOT-MTJ is connected to the source of the fifth NMOS transistor, the write port of the sixth SOT-MTJ is connected to the read port of the seventh SOT-MTJ, and the write port of the seventh SOT-MTJ is connected to the drain of the eighth NMOS transistor. The drain of the eighth NMOS transistor is connected to the write port of the eleventh SOT-MTJ, and the drain of the eighth NMOS transistor is also connected to the write port of the twelfth SOT-MTJ. The read port of the twelfth SOT-MTJ is connected to the read port of the eleventh SOT-MTJ, the read port of the twelfth SOT-MTJ is connected to the write port of the tenth SOT-MTJ, the read port of the tenth SOT-MTJ is connected to the write port of the ninth SOT-MTJ, and the read port of the ninth SOT-MTJ is connected to the source of the sixth NMOS transistor. The input signal of the gate of the eighth NMOS transistor is the second enable signal.

8. A non-volatile Boolean logic operation method based on SOT-MTJ, applied to a non-volatile Boolean logic operation circuit based on SOT-MTJ as described in any one of claims 1-7, wherein the non-volatile Boolean logic operation circuit includes an MTJ write circuit module, an MTJ logic tree module, and a pre-charge amplifier module, characterized in that, The method includes the following steps: The MTJ writing circuit module writes an MTJ state to each of the SOT-MTJs, and the MTJ state includes a parallel state and an antiparallel state. The MTJ logic tree module controls the resistance value of each circuit formed by connecting the SOT-MTJs according to the MTJ state. The precharge amplifier module outputs the Boolean logic result corresponding to the MTJ state based on the resistance value. The MTJ logic tree module is implemented through a first topology, which includes a first SOT-MTJ, a second SOT-MTJ, a third SOT-MTJ, a fourth SOT-MTJ, a fifth SOT-MTJ, and a seventh NMOS transistor. The read port of the first SOT-MTJ is connected to the source of the fifth NMOS transistor in the precharge amplifier module, the write port of the first SOT-MTJ is connected to the read port of the second SOT-MTJ, and the write port of the second SOT-MTJ is connected to the drain of the seventh NMOS transistor. The drain of the seventh NMOS transistor is connected to the write port of the fourth SOT-MTJ, the drain of the seventh NMOS transistor is also connected to the write port of the fifth SOT-MTJ, the read port of the fifth SOT-MTJ is connected to the read port of the fourth SOT-MTJ, the read port of the fifth SOT-MTJ is connected to the write port of the third SOT-MTJ, the read port of the third SOT-MTJ is connected to the source of the sixth NMOS transistor in the precharge amplifier module, and the input signal of the gate of the seventh NMOS transistor is a second enable signal, which is used to control the switching on and off of the MOS transistor.

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