Data processing method and device, electronic device and storage medium

Abstract

The present invention provides a data processing method and a data processing device, an electronic device and a storage medium. The data processing method comprises: judging whether a first operand is less than a second operand to obtain a first judgment result, and setting a first register based on the first judgment result; judging whether a second operand is less than or equal to the first operand to obtain a second judgment result, and setting a second register based on the second judgment result; and comparing the value of the first register and the value of the second register, and when the value of the first register and the value of the second register are equal, adding 1 to the value of the first register to obtain an addition result, and using the addition result as a target value, or when the value of the first register and the value of the second register are not equal, using the value of the first register as a target value. The data processing method is simple to implement and can improve the efficiency of floating-point operations, for example.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data processing method, a data processing device, an electronic device, and a computer-readable storage medium. Background Art

[0002] RISCV is an open source instruction set architecture (ISA) based on the Reduced Instruction Set Computer (RISC) principle. An instruction set with fixed instruction length and concise single instruction function is called a reduced instruction set. The instruction set architecture defines the interface between hardware and software, including: instruction format and function, program registers, control registers, memory addressing, virtual address conversion, permission management, interrupts, exception handling, input and output systems, system management, and debugging. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a data processing method, including: judging whether a first operand is less than a second operand to obtain a first judgment result, and setting a first register based on the first judgment result; judging whether a second operand is less than or equal to the first operand to obtain a second judgment result, and setting a second register based on the second judgment result; and comparing the value of the first register with the value of the second register, and when the value of the first register and the value of the second register are equal, adding 1 to the value of the first register to obtain an addition result, and using the addition result as a target value, or, when the value of the first register and the value of the second register are not equal, using the value of the first register as the target value.

[0004] For example, in the data processing method provided in at least one embodiment of the present disclosure, the first register is set based on the first judgment result, including: when the first operand is less than the second operand, the value of the first register is set to 1, otherwise the value of the first register is set to 0.

[0005] For example, in the data processing method provided in at least one embodiment of the present disclosure, the second register is set based on the second judgment result, including: when the second operand is less than or equal to the first operand, the value of the second register is set to 1, otherwise the value of the second register is set to 0.

[0006] For example, in the data processing method provided by at least one embodiment of the present disclosure, when the value of the first register is equal to the value of the second register, the first operand or the second operand is a non-number.

[0007] For example, in the data processing method provided by at least one embodiment of the present disclosure, when the first operand or the second operand is a non-number, the value of the first register and the value of the second register are set to 0.

[0008] For example, in the data processing method provided by at least one embodiment of the present disclosure, the first operand and the second operand are floating-point data, and the first register and the second register are floating-point registers.

[0009] For example, in the data processing method provided by at least one embodiment of the present disclosure, when the first operand and the second operand are single-precision floating-point data, the flt.s instruction is executed to determine whether the first operand is less than the second operand to obtain a first judgment result, and the fle.s instruction is executed to determine whether the second operand is less than or equal to the first operand to obtain a second judgment result; or when the first operand and the second operand are double-precision floating-point data, the flt.d instruction is executed to determine whether the first operand is less than the second operand to obtain a first judgment result, and the fle.d instruction is executed to determine whether the second operand is less than or equal to the first operand to obtain a second judgment result.

[0010] For example, in the data processing method provided by at least one embodiment of the present disclosure, a Bne instruction or a Beq instruction is executed to compare the value of the first register with the value of the second register.

[0011] At least one embodiment of the present disclosure provides a data processing device, including a first judgment unit, a second judgment unit, a comparison unit and a result acquisition unit. The first judgment unit is configured to judge whether the first operand is less than the second operand to obtain a first judgment result, and set the first register based on the first judgment result. The second judgment unit is configured to judge whether the second operand is less than or equal to the first operand to obtain a second judgment result, and set the second register based on the second judgment result. The comparison unit is configured to compare the value of the first register with the value of the second register. The result acquisition unit is configured to add 1 to the value of the first register to obtain an addition result when the value of the first register and the value of the second register are equal, and use the addition result as a target value, or use the value of the first register as the target value when the value of the first register and the value of the second register are not equal.

[0012] At least one embodiment of the present disclosure provides an electronic device, including a processor and a memory, storing computer executable instructions, wherein the computer executable instructions, when executed by the processor, implement the data processing method provided by at least one embodiment of the present disclosure.

[0013] At least one embodiment of the present disclosure provides a computer-readable storage medium for non-transitory storage of computer-executable instructions, wherein the computer-executable instructions implement the data processing method provided by at least one embodiment of the present disclosure when executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0015] Figure 1 A schematic flow chart of a data processing method provided by at least one embodiment of the present disclosure is shown;

[0016] Figure 2 An exemplary flow chart of using RISCV instructions to complete the data processing method provided by the embodiment of the present disclosure is shown;

[0017] Figure 3 A schematic block diagram of a data processing device provided by at least one embodiment of the present disclosure is shown;

[0018] Figure 4 A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0020] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0021] When comparing floating - point registers based on the existing RISC - V instruction set, the comparison results shown in Table 1 below will be obtained. In Table 1 below, both a and b are floating - point data, and a < b. In the case where the left operand is a and the right operand is b, the comparison result is 1; in the case where the left operand is a and the right operand is a, the comparison result is 0; in the case where the left operand is b and the right operand is a, the comparison result is 0. In the case where the left operand is a Not - a - Number (NaN) and the right operand is any floating - point number, the comparison result is 1. It should be noted that NaN is a numerical data type representing an undefined or unrepresentable value and is often used in floating - point operations. When any one of the operands is NaN, the comparison result is 1.

[0022] Table 1

[0023] Left operand Right operand Comparison results a b 1 a a 0 b a 0 NaN Any floating point number 1

[0024] The existing RISC - V instructions can directly compare two floating - point data, but cannot directly compare operands of the NaN type. Therefore, if two floating - point registers need to be compared and special handling for the NaN scenario is required, then the existing RISC - V instructions cannot be directly used for comparison.

[0025] The following are the steps for handling scenarios involving single - precision floating - point numbers and NaN while comparing floating - point registers based on the existing RISC - V instruction set:

[0026] The first step: Take the value f1 of one floating - point register as the left operand and the value f2 of another floating - point register as the right operand, and use the flt.s instruction to compare the two floating - point operands. The result is placed in the register dst.

[0027] The instruction corresponding to the first step is flt.s dst,f1,f2. This instruction is used to compare single - precision floating - point registers. Among them, dst represents a register, and the register types are RV32F and RV64F, f1 is the left operand, and f2 is the right operand. If f1 is less than f2, then 1 is written into dst, otherwise 0 is written.

[0028] The second step: Read the value in the floating - point status register and store this value in the temporary register tmp.

[0029] The instruction corresponding to the second step is Csrrci tmp,fcsr,15. This instruction is used to write the result of the bit - wise AND operation between the value of the current floating - point status register fcsr and the 5 - bit zero - extended immediate number 15 ( = 0xf) into the temporary register tmp.

[0030] Step 3: Take out the value of the NV status bit in the temporary register tmp and store it back into the temporary register tmp.

[0031] The NV status bit indicates the location of the exception flag generated in the register. For the flt.s instruction, if any operand is NaN, the NV exception flag will be generated in the register.

[0032] The instructions corresponding to the third step are Andi tmp,tmp,16 and Srli tmp,tmp,4. The instruction Andi tmp,tmp,16 is used to clear the non-NV status bit to 0 and store the result in the temporary register tmp. The instruction Srli tmp,tmp,4 is used to right shift the value of the temporary register tmp by 4 bits and store the result in the temporary register tmp.

[0033] Step 4: Add the values ​​of register dst and temporary register tmp, and store them in register dst. The value of register dst is the target value.

[0034] The instruction corresponding to the fourth step is Add dst,dst,tmp. This instruction is used to add the value of register dst and temporary register tmp and store them in register dst.

[0035] The following is an example of comparing two floating-point data to illustrate the above steps.

[0036] For example, f1=1.1, f2=1.2. After executing instruction flt.s dst,f1,f2, the value of dst is 1. Since both f1 and f2 are floating point numbers, the NV status bit in register fcsr is not set. After executing instructions Csrrci tmp,fcsr,15, Andi tmp,tmp,16, and Srli tmp,tmp,4, the value of tmp is 0. After executing instruction Add dst,dst,tmp, the value of dst is 1, and the value of dst is consistent with the target value.

[0037] For example, f1=1.0, f2=NaN, and the initial value of register fcsr is 0. After executing instruction flt.s dst,f1,f2, the value of dst is 0. Because of the existence of NaN, the NV status bit in register fcsr is set. After executing instruction Csrrcitmp,fcsr,15, the NV status bit in register fcsr is cleared. After executing Andi tmp,tmp,16, the value of tmp remains unchanged. After executing Srli tmp,tmp,4, the value of tmp is 1. After executing Add dst,dst,tmp, the value of dst is 1, and the value of dst is consistent with the target value.

[0038] It should be noted that the above steps are described using a single-precision floating-point register as an example. If two double-precision floating-point registers need to be compared and special processing is required for the NaN scenario, the instruction flt.d is used to replace the above instruction flt.s.

[0039] As mentioned above, if two floating-point registers are to be compared and special processing is required for the NaN scenario, multiple RISCV instructions are required, which is not easy to operate and takes a long time.

[0040] At least one embodiment of the present disclosure provides a data processing method, including: judging whether a first operand is less than a second operand to obtain a first judgment result, and setting a first register based on the first judgment result; judging whether the second operand is less than or equal to the first operand to obtain a second judgment result, and setting a second register based on the second judgment result; and comparing the value of the first register with the value of the second register, and when the value of the first register and the value of the second register are equal, adding 1 to the value of the first register to obtain an addition result, and using the addition result as a target value, or, when the value of the first register and the value of the second register are not equal, using the value of the first register as the target value.

[0041] The data processing method provided by the above embodiments of the present disclosure can, while comparing floating-point registers, simply distinguish NaN and perform corresponding processing. The implementation is simple and there is no need to read the value of the floating-point status register fcsr, thereby greatly improving the operation efficiency.

[0042] At least one embodiment of the present disclosure also provides a data processing device, an electronic device, and a computer-readable storage medium that non-temporarily stores computer-executable instructions for implementing the above-mentioned method corresponding to the above-mentioned data processing method.

[0043] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0044] Figure 1 A schematic flow chart of a data processing method provided by at least one embodiment of the present disclosure is shown.

[0045] like Figure 1 As shown, the data processing method includes the following steps S101 to S103.

[0046] Step S101: Determine whether the first operand is smaller than the second operand to obtain a first determination result, and set a first register based on the first determination result.

[0047] Step S102: Determine whether the second operand is less than or equal to the first operand to obtain a second determination result, and set the second register based on the second determination result.

[0048] For example, the first operand and the second operand are floating point data, and correspondingly, the first register and the second register are floating point registers.

[0049] Step S103: Compare the value of the first register with the value of the second register. If the value of the first register is equal to the value of the second register, add 1 to the value of the first register to obtain an addition result, and use the addition result as the target value. Alternatively, if the value of the first register is not equal to the value of the second register, use the value of the first register as the target value.

[0050] In some embodiments of the present disclosure, an example of step S101 includes: if the first operand is smaller than the second operand, setting the value of the first register to 1; otherwise, setting the value of the first register to 0.

[0051] For example, if the first operand and the second operand are single-precision floating-point data, the flt.s instruction is executed to determine whether the first operand is less than the second operand to obtain a first determination result.

[0052] The flt.s instruction can be found in the above description and will not be described again here.

[0053] For another example, if the first operand and the second operand are double-precision floating point data, the flt.d instruction is executed to determine whether the first operand is less than the second operand to obtain a first determination result.

[0054] The flt.d instruction is used to compare double-precision floating-point registers. The general format of the flt.d instruction is flt.drd,rs1,rs2, where rd represents a register, the register type is RV32D and RV64D, rs1 is the left operand, and rs2 is the right operand. If rs1 is less than rs2, 1 is written to rd, otherwise 0 is written.

[0055] In some embodiments of the present disclosure, an example of step S102 includes: if the second operand is less than or equal to the first operand, setting the value of the second register to 1; otherwise, setting the value of the second register to 0.

[0056] For example, if the first operand and the second operand are single-precision floating-point data, the fle.s instruction is executed to determine whether the second operand is less than or equal to the first operand to obtain a second determination result.

[0057] The fle.s instruction is used to compare single-precision floating-point registers. The general format of the fle.s instruction is fle.srd,rs1,rs2, where rd represents a register, the register type is RV32F and RV64F, rs1 is the left operand, and rs2 is the right operand. If rs1 is less than or equal to rs2, 1 is written to rd, otherwise 0 is written.

[0058] For another example, if the first operand and the second operand are double-precision floating point data, the fle.d instruction is executed to determine whether the second operand is less than or equal to the first operand to obtain a second determination result.

[0059] The fle.d instruction is used to compare double-precision floating-point registers. The general format of the fle.d instruction is fle.drd,rs1,rs2, where rd represents a register, the register type is RV32D and RV64D, rs1 is the left operand, and rs2 is the right operand. If rs1 is less than or equal to rs2, 1 is written to rd, otherwise 0 is written.

[0060] For example, in the data processing method provided by at least one embodiment of the present disclosure, when the value of the first register is equal to the value of the second register, the first operand or the second operand is a non-number (NaN).

[0061] For example, in the data processing method provided by at least one embodiment of the present disclosure, when the first operand or the second operand is a non-number, the value of the first register and the value of the second register are set to 0.

[0062] As mentioned above, when any operand is a non-number, the comparison result is 1. Therefore, when the first operand or the second operand is a non-number, the value of the first register is equal to the value of the second register. However, when the first operand and the second operand are both floating-point data, the value of the first register is not equal to the value of the second register.

[0063] For example, in the data processing method provided by at least one embodiment of the present disclosure, a Bne instruction is executed to compare the value of the first register with the value of the second register.

[0064] The Bne instruction is a jump instruction. When the value in the first register and the value in the second register are not equal, the instruction jumps. In another example, the Beq instruction can also be used. Beq dst, tmp, Label This instruction means that if the value in register dst is equal to the value in register tmp, the instruction jumps to the statement labeled Lable, that is, if they are equal, the instruction branches.

[0065] For example, if the first operand and the second operand are single-precision floating-point data, the above data processing method needs to be completed using the following RISCV instructions:

[0066] For example, step S101 corresponds to the instruction flt.s dst,f1,f2, where dst is the first register, f1 is the first operand, and f2 is the second operand. If the value of f1 is less than f2, the value of register dst is set to 1, otherwise the value of register dst is set to 0.

[0067] Step S102 corresponds to the instruction fle.s tmp,f2,f1, where tmp is the second register. If the value of f2 is less than or equal to f1, the value of register tmp is set to 1, otherwise the value of register tmp is set to 0.

[0068] Step S103 corresponds to the instruction Bne dst, tmp, Label and the instruction Addi dst, dst, 1. Label is used to identify the starting position of the next code segment. If the value of register dst is not equal to the value of register tmp, the next instruction of the Bne instruction is skipped, and the instruction after Label is directly executed, and the value of register dst is used as the target value; or, if the value of register dst is equal to the value of register tmp, the next instruction of the Bne instruction Addi dst, dst, 1 is executed, and the value of register dst and the immediate value 1 are added to obtain the addition result, and the addition result is stored in register dst as the target value.

[0069] An exemplary flow chart of a data processing method provided by at least one embodiment of the present disclosure using the above RISCV instructions is shown in Figure 2 Shown in.

[0070] like Figure 2 As shown, first, the instruction flt.s dst,f1,f2 is executed.

[0071] For example, dst is the first register, f1 is the first operand, and f2 is the second operand. If the value of f1 is less than f2, the value of register dst is set to 1, otherwise the value of register dst is set to 0.

[0072] Then, if Figure 2 As shown, execute instruction fle.s tmp,f2,f1.

[0073] For example, tmp is the second register. If the value of f2 is less than or equal to f1, the value of register tmp is set to 1; otherwise, the value of register tmp is set to 0.

[0074] Then, if Figure 2 As shown, execute the instruction Bne dst, tmp, Label.

[0075] For example, when the value of register dst is not equal to the value of register tmp, the instruction Addi dst,dst,1 is skipped and the instruction after Label is directly executed, using the value of register dst as the target value.

[0076] For example, when dst and tmp are equal, execute the instruction Addi dst,dst,1, add the value of register dst and the immediate value 1 to obtain the addition result, store the addition result in register dst, and use the value of register dst as the target value.

[0077] The following two examples of comparing floating-point data are used to illustrate the data processing method provided by the embodiments of the present disclosure.

[0078] For example, f1=1.1, f2=1.2. After executing the instruction flt.s dst,f1,f2, the value of dst is 1. After executing the instruction fle.s tmp,f2,f1, the value of tmp is 0. Since the value of dst is not equal to the value of tmp, after executing the instruction Bne dst,tmp,Label, the next instruction Addi dst,dst,1 is skipped. The value of dst is consistent with the target value, and the value of dst is used as the target value.

[0079] For example, f1=1.0, f2=NaN. After executing the instruction flt.s dst,f1,f2, the value of dst is 0. After executing the instruction fl.s tmp,f2,f1, the value of tmp is 0. Since the value of dst is equal to the value of tmp, after executing the instruction Bne dst,tmp,Label, the next instruction Addi dst,dst,1 is executed to add the value of dst to 1 to obtain the addition result 1, and the addition result 1 is stored in the register dst. At this time, the value of dst is 1, which is consistent with the target value.

[0080] It should be noted that in this embodiment, a single-precision floating-point register is used as an example for explanation. If two double-precision floating-point registers are to be compared and special processing is required for the NaN scenario, the instruction flt.d is used to replace the above instruction flt.s and the instruction fle.d is used to replace the above instruction fle.s. The present disclosure does not limit the type of floating-point data.

[0081] Furthermore, in the above embodiment, the Bne instruction is used as an example for explanation, but the Beq instruction may also be used, and it is only necessary to exchange the jump branch with the non-jump branch.

[0082] Figure 3 A schematic block diagram of a data processing device 300 provided by at least one embodiment of the present disclosure is shown. The data processing device 300 can be used to execute Figure 1 The data processing method shown.

[0083] like Figure 3 As shown, the data processing device 300 includes a first judgment unit 301 , a second judgment unit 302 , a comparison unit 303 and a result acquisition unit 304 .

[0084] The first determination unit 301 is configured to determine whether the first operand is smaller than the second operand to obtain a first determination result, and to set the first register based on the first determination result.

[0085] The second determination unit 302 is configured to determine whether the second operand is less than or equal to the first operand to obtain a second determination result, and set the second register based on the second determination result.

[0086] The comparison unit 303 is configured to compare the value of the first register with the value of the second register.

[0087] The result acquisition unit 304 is configured to, when the value of the first register is equal to the value of the second register, add 1 to the value of the first register to obtain an addition result, and use the addition result as the target value; or, when the value of the first register is not equal to the value of the second register, use the value of the first register as the target value.

[0088] For example, in at least one embodiment, the first determination unit 301 is further configured to set the value of the first register to 1 if the first operand is smaller than the second operand, and to set the value of the first register to 0 otherwise.

[0089] For example, in at least one embodiment, the first determination unit 301 is further configured to set the value of the first register to 0 when the first operand or the second operand is a non-number.

[0090] For example, in at least one embodiment, the second determination unit 302 is further configured to set the value of the second register to 1 if the second operand is less than or equal to the first operand, and to set the value of the second register to 0 otherwise.

[0091] For example, in at least one embodiment, the second determination unit 302 is further configured to set the value of the second register to 0 when the first operand or the second operand is a non-number.

[0092] For example, in at least one embodiment, the first judgment unit 301 is further configured to, when the first operand and the second operand are single-precision floating-point data, execute the flt.s instruction to determine whether the first operand is less than the second operand to obtain a first judgment result, or, when the first operand and the second operand are double-precision floating-point data, execute the flt.d instruction to determine whether the first operand is less than the second operand to obtain a first judgment result.

[0093] For example, in at least one embodiment, the second judgment unit 302 is further configured to, when the first operand and the second operand are single-precision floating-point data, execute the fle.s instruction to determine whether the second operand is less than or equal to the first operand to obtain a second judgment result, or, when the first operand and the second operand are double-precision floating-point data, execute the fle.d instruction to determine whether the second operand is less than or equal to the first operand to obtain a second judgment result.

[0094] For example, in at least one embodiment, the comparison unit 302 is further configured to execute a Bne instruction to compare the value of the first register with the value of the second register.

[0095] For example, the data processing device 300 may be implemented using hardware, software, firmware, or any feasible combination thereof, and the present disclosure is not limited thereto.

[0096] The data processing device 300 and Figure 1 The technical effect of the data processing method shown is the same, which can improve the computing efficiency, and will not be repeated here.

[0097] At least one embodiment of the present disclosure further provides an electronic device, comprising: a memory for non-temporarily storing computer-executable instructions; and a processor for executing the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, execute the data processing method provided by at least one embodiment of the present disclosure.

[0098] Figure 4 FIG. 4 is a schematic diagram of an electronic device 400 according to an embodiment of the present disclosure. Figure 4 As shown, the electronic device 400 according to an embodiment of the present disclosure may include a processing device 401 and a memory 402 , which may be interconnected via a bus 403 .

[0099] The processing device 401 can perform various actions and processes according to the program or code stored in the memory 402. Specifically, the processing device 401 can be an integrated circuit chip with signal processing capabilities. For example, the above-mentioned processing device can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps, processes and logic block diagrams disclosed in the embodiments of the present disclosure can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can be an X86 architecture or an ARM architecture, etc.

[0100] The memory 402 stores computer executable instructions, wherein the computer executable instructions implement the data processing method provided by at least one embodiment of the present disclosure when executed by the processing device 401. The memory 402 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronously connected dynamic random access memory (SLDRAM), and direct main memory bus random access memory (DRRAM). It should be noted that memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0101] At least one embodiment of the present disclosure further provides a computer-readable storage medium for non-transitorily storing computer-executable instructions, which, when executed by a processor, implement the data processing method provided by at least one embodiment of the present disclosure.

[0102] Similarly, the computer-readable storage medium in the embodiments of the present disclosure may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. It should be noted that the memory described in the present disclosure is intended to include but is not limited to these and any other suitable types of memory.

[0103] At least one embodiment of the present disclosure further provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the data processing method according to an embodiment of the present disclosure.

[0104] The technical effects of the above electronic equipment and storage medium are Figure 1 The data processing methods shown have the same technical effects and can both be used to improve computing efficiency, so they will not be described in detail here.

[0105] There are a few points to note about this disclosure:

[0106] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0107] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0108] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A data processing method, comprising: Determine whether the first operand is less than the second operand to obtain a first determination result, and set a first register based on the first determination result; Determine whether the second operand is less than or equal to the first operand to obtain a second determination result, and set a second register based on the second determination result; as well as comparing the value of the first register with the value of the second register, When the value of the first register is equal to the value of the second register, 1 is added to the value of the first register to obtain an addition result, and the addition result is used as the target value; or, when the value of the first register is not equal to the value of the second register, the value of the first register is used as the target value.

2. The data processing method according to claim 1, wherein: Setting the first register based on the first judgment result includes: In a case where the first operand is smaller than the second operand, the value of the first register is set to 1; otherwise, the value of the first register is set to 0.

3. The data processing method according to claim 1, wherein: Setting the second register based on the second judgment result includes: In a case where the second operand is less than or equal to the first operand, the value of the second register is set to 1; otherwise, the value of the second register is set to 0.

4. The data processing method according to claim 1, wherein: In the case where the value of the first register is equal to the value of the second register, the first operand or the second operand is a negation.

5. The data processing method according to claim 4, wherein: In the case that the first operand or the second operand is a non-number, the value of the first register and the value of the second register are set to 0.

6. The data processing method according to any one of claims 1 to 5, wherein: The first operand and the second operand are floating point data, The first register and the second register are floating point registers.

7. The data processing method according to claim 6, wherein: In the case where the first operand and the second operand are single-precision floating-point data, executing the flt.s instruction to determine whether the first operand is less than the second operand to obtain the first determination result, and executing the fle.s instruction to determine whether the second operand is less than or equal to the first operand to obtain the second determination result; or In the case where the first operand and the second operand are double-precision floating-point data, the flt.d instruction is executed to determine whether the first operand is less than the second operand to obtain the first judgment result, and the fle.d instruction is executed to determine whether the second operand is less than or equal to the first operand to obtain the second judgment result.

8. The data processing method according to claim 1, wherein: A Bne instruction or a Beq instruction is executed to compare the value of the first register with the value of the second register.

9. A data processing device, comprising: A first judgment unit is configured to judge whether the first operand is less than the second operand to obtain a first judgment result, and set a first register based on the first judgment result; A second judgment unit is configured to judge whether the second operand is less than or equal to the first operand to obtain a second judgment result, and set a second register based on the second judgment result; as well as a comparing unit, configured to compare a value of the first register with a value of the second register; as well as The result acquisition unit is configured to, when the value of the first register is equal to the value of the second register, add 1 to the value of the first register to obtain an addition result, and use the addition result as a target value, or, when the value of the first register is not equal to the value of the second register, use the value of the first register as the target value.

10. An electronic device comprising: processor; as well as a memory storing computer executable instructions, Wherein, when the computer executable instructions are executed by the processor, the data processing method according to any one of claims 1-8 is implemented.

11. A computer-readable storage medium for non-transitory storage of computer-executable instructions, in, When the computer executable instructions are executed by a processor, the data processing method according to any one of claims 1 to 8 is implemented.

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