Hierarchical cache non-writeback invalidating computer system and method

Abstract

A computer system and method for performing hierarchical cache write-not-allocate invalidations. In one embodiment, in response to a first instruction of an instruction set architecture that causes a write-not-allocate invalidation of a hierarchical cache based on a single specified key identification, a decoder translates at least one microinstruction. From the at least one microinstruction, a write-not-allocate invalidation request is supplied to an in-core cache via a memory order buffer, and from the in-core cache to a last level cache. In response to the write-not-allocate invalidation request, the last level cache locates all matching cache lines that match the specified key identification, and invalidates all matching cache lines found in a system memory. For a second instruction of the instruction set architecture that causes a write-not-allocate invalidation of the hierarchical cache based on multiple specified key identifications, the application implements multiple write-not-allocate invalidation requests.

Description

TECHNICAL FIELD

[0001] The present application relates to the management of hierarchical cache of a processor, and in particular to a computer system and method for invalidating a hierarchical cache based on a specified key identification code. BACKGROUND

[0002] In a computer system, there are different levels of memory. The upper level memory has higher speed, lower latency, but smaller capacity. Most computer systems have the following four levels of memory (sorted from top to bottom): registers; cache memory; system memory (main memory such as DRAM); and disk (SSD or HD).

[0003] In particular, the cache can also be designed in a hierarchical manner, arranged from fast to slow according to access, including: level 1 cache (L1), level 2 cache (L2), and level 3 cache (L3, also known as last level cache, abbreviated as LLC). The management of hierarchical cache will significantly affect system performance.

[0004] In order to achieve the protection of confidential and / or sensitive data, the prior art has appeared a transparent total memory encryption function using multiple keys to encrypt the system memory, which realizes the management of memory with key granularity; but the existing hierarchical cache lacks the corresponding management function with key granularity, resulting in that the operating system (Operating System, abbreviated as OS) cannot manage the hierarchical cache with key granularity. SUMMARY

[0005] In order to solve the above problems, the present application proposes a management technology of hierarchical cache, which can be implemented as a computer system or as a computer system operation method.

[0006] A computer system according to one embodiment of the present application includes a first core, a first processor fabricated on a first die, including a decoder, a memory order buffer, and a first in-core cache, and a first last level cache fabricated on the first processor. In response to a first instruction of an instruction set architecture that specifies no write back invalidation based on a single key identification, the decoder translates at least one microinstruction. According to the at least one microinstruction, a no write back invalidation request is supplied to the first in-core cache through the memory order buffer, and is further supplied to the first last level cache by the first in-core cache. In response to the no write back invalidation request, the first last level cache finds all matching cache lines that match the key identification, and invalidates all found matching cache lines in a system memory.

[0007] In one embodiment, the no write back invalidation request carries the key identification. The first last level cache finds all matching cache lines that match the key identification according to the key identification carried by the no write back invalidation request.

[0008] In one embodiment, the computer system of the present application further includes a first storage unit that stores the key identification parsed from the first instruction. The no write back invalidation request does not carry the key identification. The first last level cache, upon receiving the no write back invalidation request, obtains the key identification from the first storage unit, and finds all matching cache lines that match the key identification according to the obtained key identification.

[0009] One embodiment of the present application uses snoop filter technology, which is described below.

[0010] In one embodiment, the first processor further includes a first snoop filter. The first last level cache issues a snoop request corresponding to each of its matching cache lines through the first snoop filter to the first in-core cache. Each snoop request carries a tag that is common to the matching cache line in the hierarchical cache. In response to each snoop request, the first in-core cache finds a cache line that matches the tag carried by the snoop request, and invalidates the found cache line in the system memory.

[0011] In one embodiment, the first processor further includes a second core that includes a second in-core cache. Each snoop request is also delivered by the first snoop filter to the second in-core cache. In response to each snoop request, the second in-core cache finds a cache line that matches the tag carried by the snoop request, and invalidates the found cache line in the system memory.

[0012] In one embodiment, the computer system of the present application further includes a second processor fabricated on a second die. The second processor includes a third core and a second last level cache. The third core includes a third in-core cache. The first last level cache further communicates the no-write-allocate invalidate request received from the first in-core cache to the second last level cache via a channel between the first die and the second die. In response to receiving the no-write-allocate invalidate request, the second last level cache locates all matching cache lines in the second last level cache that match the specified key identifier and invalidates all located matching cache lines in the system memory.

[0013] In one embodiment, the second processor further includes a second snoop filter. The second last level cache issues a snoop request corresponding to each matching cache line in the second last level cache to the third in-core cache via the second snoop filter. Each snoop request carries a tag that is common to all cache lines in the hierarchical cache that match the corresponding matching cache line. In response to each snoop request, the third in-core cache locates all cache lines in the third in-core cache that match the tag carried by the snoop request and invalidates all located cache lines in the system memory.

[0014] In one embodiment, the computer system of the present application further includes a second processor fabricated on a second die. The second processor includes a third core and a second last level cache. The third core includes a third in-core cache. The first last level cache further communicates the no-write-allocate invalidate request received from the first in-core cache to the second last level cache via a channel between the first die and the second die. In response to receiving the no-write-allocate invalidate request, the second last level cache locates all matching cache lines in the second last level cache that match the specified key identifier and invalidates all located matching cache lines in the system memory.

[0015] In one embodiment, the first last level cache invalidates all matching cache lines in the first last level cache and returns a first notification to the first in-core cache. The first in-core cache that supplied the no-write-allocate invalidate request to the first last level cache is in a wait-for-synchronization state until the first in-core cache receives the first notification returned by the first last level cache, at which point the first in-core cache locates all matching cache lines in the first in-core cache that match the specified key identifier and invalidates all located matching cache lines in the system memory.

[0016] In one embodiment, the first processor further includes a second core that includes a second in-core cache. The no-write-allocate invalidate request is further supplied to the second core via the memory order buffer of the first core and received by the second in-core cache of the second core. The no-write-allocate invalidate request that the first last level cache responds to is the one that arrived earlier of the first core and the second core.

[0017] In one embodiment, the computer system of the present application further includes an inter-core interrupt handler that receives an interrupt request from the first core via the memory order buffer in response to the no-write-allocate invalidate request, operates a reordering buffer of the second core, and initiates an interrupt design of a microcode of the second core to cause the no-write-allocate invalidate request to be received by the second in-core cache.

[0018] In one embodiment, the first L2 cache also sends back a first notification to the second in-core cache, to initiate the second in-core cache in a state of waiting for a synchronization signal to find all matching cache lines matching the specified key identification code, and to invalidate all found matching cache lines without writing back to the system memory.

[0019] In one embodiment, the computer system of the present application further comprises a second processor fabricated on a second die. The second processor comprises a third core and a second L2 cache. The third core comprises a third in-core cache. The no-write allocate invalidate request is further supplied to the third core through the MESI buffer of the first core, through a channel between the first die and a second die, and to the second L2 cache by the third in-core cache of the third core. In response to the received no-write allocate invalidate request, the second L2 cache finds all matching cache lines matching the specified key identification code, and invalidates all found matching cache lines without writing back to the system memory. After invalidating all matching cache lines, the second L2 cache sends back a third notification to the third in-core cache, to initiate the third in-core cache in a state of waiting for a synchronization signal to find all matching cache lines matching the specified key identification code, and to invalidate all found matching cache lines without writing back to the system memory.

[0020] The first instruction of the foregoing single specified key identification code involves a single operand. The single operand indicates a register, or a system memory address, or an immediate number, to obtain the specified key identification code required by the first instruction.

[0021] The present application further has a design to respond to multiple specified key identification codes.

[0022] In one embodiment, in response to a second instruction of an instruction set architecture for no-write allocate invalidate of hierarchical caches based on multiple specified key identification codes, the decoder translates at least one microinstruction. According to the at least one microinstruction corresponding to the second instruction, the multiple specified key identification codes are stored in the storage unit of the first core, and the no-write allocate invalidate requests supplied to the first in-core cache through the MESI buffer are performed on the multiple specified key identification codes stored in the storage unit of the first core, so that the no-write allocate invalidate of the current specified key identification code is completed before the no-write allocate invalidate of the next specified key identification code is performed.

[0023] In one embodiment, the second instruction involves double operands to obtain a key identification code preliminary setting and a mask, and to form the multiple specified key identification codes required by the second instruction by performing mask processing on the key identification code preliminary setting using the mask.

[0024] In one embodiment, the second instruction involves double operands to take a system memory address indicating a start key ID in a list on the system memory, and a number of key IDs to be specified, and the specified key IDs required by the second instruction are taken from the list according to the system memory address and the number of key IDs to be specified.

[0025] According to the present application, a hierarchical cache is provided with a corresponding key-granularity management function; when transparent full memory encryption is enabled, an operating system can manage the hierarchical cache in key granularity.

[0026] The present application is described in detail below with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1A An instruction architecture for the ISA instruction WBINVD_Single_KeyID of the present application;

[0028] Figure 1B An instruction architecture for the ISA instruction WBINVD_Multiple_KeyIDs of the present application;

[0029] Figure 1C An instruction architecture for the ISA instruction INVD_Single_KeyID of the present application;

[0030] Figure 1D An instruction architecture for the ISA instruction INVD_Multiple_KeyIDs of the present application;

[0031] Figure 2A A block diagram illustrating a processor 200 and a core core_1 thereon according to one embodiment of the present application;

[0032] Figure 2B A format 250 of a cache line of a hierarchical cache according to one embodiment of the present application;

[0033] Figure 3 A computer system 300 implemented according to one embodiment of the present application is illustrated, in which a snoop filter technique is used;

[0034] Figure 4A 、 4B A computer system 400 implemented according to another embodiment of the present application is illustrated, which is related to a multi-core and multi-die design without using a snoop filter;

[0035] Figure 5Figure 2 illustrates a processor 500 implemented in accordance with another embodiment of the application, in which the in-core cache only includes a first level cache L1, and the multiple cores share a second level cache L2; and

[0036] Figure 6 Figure 3 illustrates a computer system 600 implementing a multi-core architecture in accordance with an embodiment of the application.

[0037]

Symbol Description

[0038] 102, 112, 132, 142: opcode

[0039] 104, 114, 116, 134, 144, 146: op rand

[0040] 106, 108, 110, 118, 120, 122, 136, 138, 140, 148, 150, 152: instruction architecture

[0041] 200: processor

[0042] 202: system memory

[0043] 204: instruction cache

[0044] 206: decoder

[0045] 208: instruction buffer (XIB)

[0046] 210: instruction translator (XLATE)

[0047] 212: register alias table (RAT)

[0048] 214, 218: reservation station (RS)

[0049] 216: memory order buffer (MOB)

[0050] 220: execution unit

[0051] 222: local key identification

[0052] 224: snoop filter

[0053] 226: notification delivery path

[0054] 250: cache line format

[0055] 252: valid bit

[0056] 254: key identification

[0057] 300: computer system;

[0058] 302: write back and invalidate request / no write back and invalidate request;

[0059] 304: in-core cache

[0060] 306, 310: snoop request;

[0061] 308, 408, 520: channel;

[0062] 400: computer system;

[0063] 402: in-core cache;

[0064] 500: processor;

[0065] 502, 504: second level cache;

[0066] 506: third level cache;

[0067] 508: first level cache;

[0068] 510: snoop filter;

[0069] 600: computer system;

[0070] 602: interrupt architected microcode;

[0071] 604: register allocation table (RAT);

[0072] 606: reservation station (RS);

[0073] 608: memory order buffer (MOB);

[0074] 610: interrupt request;

[0075] 612: inter-core interrupt handler;

[0076] 614: re-order buffer (ROB);

[0077] 616: interrupt architected microcode;

[0078] core_1...core_N: core;

[0079] Die_1, Die_2: die;

[0080] imm16: immediate;

[0081] INVD_Multiple_KeyIDs, INVD_Single_KeyID, WBINVD_Multiple_KeyIDs, WBINVD_Single_KeyID: instruction set architecture (ISA) instructions;

[0082] L1, L2, L3: first, second, third level cache;

[0083] LLC_1, LLC_2: last level cache;

[0084] MOB: memory order buffer (MOB);

[0085] Processor_1, Processor_2: processor;

[0086] reg: register;

[0087] Sto, Sto_Die1, Sto_Die2: storage unit;

[0088] req: write back and invalidate request / no write back and invalidate request;

[0089] r / m: register or system memory;

[0090] snoop_1, snoop_2: snoop filter;

[0091] Sys_Mem: system memory. DETAILED DESCRIPTION

[0092] The following description lists various embodiments of the present application. The following description introduces the basic concepts of the present application and is not intended to limit the scope of the present application. The actual scope of the present application should be defined according to the claims.

[0093] Nowadays, computer systems often have a transparent total memory encryption design, which uses multiple keys to encrypt the system memory to increase the security of the computer system. Each key can be represented by a key identification code (key ID). A key table can be included in the computer system to save the correspondence between the keys and the key identification codes. When performing encryption operations, the key corresponding to the key identification code can be obtained by querying the key table.

[0094] In a multi-key encryption processing of a system memory, the present application causes a computer system to list a key identification code (key ID) as one of the management parameters of a hierarchical cache (e.g., including a first-level cache L1, a second-level cache L2, and a third-level cache L3). In this way, the use of the hierarchical cache can be coordinated with the use of the transparent full-memory encryption function.

[0095] Taking a writing back and invalidation (WBINVD) or an invalidation without writing back (INVD) of the hierarchical cache as an example, the conventional technology is performed on all cache lines of the hierarchical cache. However, the present application provides a solution that can perform a writing back and invalidation (WBINVD) or an invalidation without writing back (INVD) only on cache lines matching a specified key identification code (which can specify only a single value or several values). For example, the instructions WBINVD_Single_KeyID and WBINVD_Multiple_KeyIDs to be introduced later will perform a writing back and invalidation on cache lines matching a specified key identification code; the instructions INVD_Single_KeyID and INVD_Multiple_KeyIDs to be introduced later will perform an invalidation without writing back on cache lines matching a specified key identification code. In this way, the operating system (OS) can manage the hierarchical cache in key granularity; since the cache lines to be used later can be left in the hierarchical cache, the computer system performance is significantly improved.

[0096] The present application also provides various embodiments of a computer system, including a single processor with a single core, a single processor with multiple cores, multiple processors, and the like.

[0097] The processor disclosed in the present application can provide one instruction set architecture (ISA) instruction for each of the aforementioned functions (including: write back and invalidation of a single specified key identification code; no write back and invalidation of a single specified key identification code; write back and invalidation of multiple specified key identification codes; and no write back and invalidation of multiple specified key identification codes). The instruction set architecture supported by the processor is not limited, and can be an x86 architecture, an Advanced RISC Machine (ARM) architecture, a MIPS (Microprocessor without Interlocked Pipeline Stages) instruction set architecture, a RISC-V (RISC-Five) instruction set architecture, a SPARC instruction set architecture, an IBM Power instruction set architecture, or another.

[0098] In one embodiment, the present application discloses a processor, wherein an instruction set architecture (ISA) instruction (hereinafter referred to as WBINVD_Single_KeyID) is provided to invalidate the cache lines matching a single specified key identification code (Key_ID_S) in the hierarchical cache; in particular, the cache lines with a state of M (modified, updated) in the matching cache lines are written back to the system memory first and then invalidated. This behavior is referred to as writing back and invalidation of the matching cache lines of a single specified key identification code (Key_ID_S).

[0099] Figure 1AFor an instruction architecture of the instruction WBINVD_Single_KeyID of the present application, in addition to an opcode 102 for the instruction, an operand 104 is included. The operand 104 indicates a single specified key identification (Key_ID_S). The operand 104 can have various forms. Instruction architecture 106 shows that for the corresponding instruction WBINVD_Single_KeyID, the operand 104 carries a register (reg) number to obtain the specified key identification (Key_ID_S) from a register. Instruction architecture 108 shows that for the corresponding instruction WBINVD_Single_KeyID, the operand 104 carries a register number or a system memory (r / m) address to obtain the specified key identification (Key_ID_S) from a register or a system memory (r / m). Instruction architecture 110 shows that for the corresponding instruction WBINVD_Single_KeyID, the operand 104 is an immediate number (imm 16) which is the specified key identification (Key_ID_S). In programming, other instructions can be used to fill the register / system memory / immediate number before the instruction WBINVD_Single_KeyID to prepare the specified key identification (Key_ID_S) for the instruction WBINVD_Single_KeyID to obtain from the operand 104. Before the instruction WBINVD_Single_KeyID, mode (including real mode, protected mode, 64-bit mode, etc.) setting can also be included, and the bit width of the specified key identification (Key_ID_S) indicated by the operand 104 is determined.

[0100] In one embodiment, the high bit of the physical address (PA) is the key identification (Key_ID). As shown in Figure 2B

[0101] ​In another embodiment, the present application discloses a processor, wherein an instruction set architecture (ISA) instruction (hereinafter denoted as WBINVD_Multiple_KeyIDs) is provided to invalidate cache lines in a hierarchical cache that match a plurality of specified key identification codes (Key_ID_S1...Key_ID_SN). In particular, cache lines in the matching cache lines that are in the state of modified (M) are written back to the system memory before being invalidated. This behavior is referred to as writing back and invalidation of the matching cache lines with the plurality of specified key identification codes (Key_ID_S1...Key_ID_SN).

[0102] Figure 1B For the ISA instruction WBINVD_Multiple_KeyIDs, the opcode 112 for the instruction is used to obtain values from two operands 114 and 116 to form the plurality of specified key identification codes (Key_ID_S1...Key_ID_SN). The instruction architecture 118 shows that for the instruction WBINVD_Multiple_KeyIDs, the operand 114 carries a register (reg) field and the operand 116 carries a register (reg) field or a memory (m) field to obtain values from a register (reg) and a register (reg) or a memory (m) to form the plurality of specified key identification codes (Key_ID_S1...Key_ID_SN). The instruction architecture 120 shows that for the instruction WBINVD_Multiple_KeyIDs, the operand 114 carries a register (reg) field or a memory (m) field and the operand 116 carries a register (reg) field to obtain values from a register (reg) or a memory (m) and a register (reg) to form the plurality of specified key identification codes (Key_ID_S1...Key_ID_SN). The instruction architecture 122 shows that for the instruction WBINVD_Multiple_KeyIDs, the operands 114 and 116 both carry register (reg) fields to obtain values from two registers (reg) to form the plurality of specified key identification codes (Key_ID_S1...Key_ID_SN). In programming, other instructions can be used to fill the registers / memory before the instruction WBINVD_Multiple_KeyIDs to obtain the values needed to form the plurality of specified key identification codes (Key_ID_S1...Key_ID_SN) from the operands 114 and 116.

[0103] In one embodiment, operand 114 indicates a key identification code initial setting (Key_ID_initial) and operand 116 indicates a mask. The key identification code initial setting (Key_ID_initial) is masked by the mask to derive a plurality of specified key identification codes (Key_ID_S1...Key_ID_SN).

[0104] In one embodiment, bits of the mask that are "0" allow the corresponding bits of the key identification code initial setting (Key_ID_initial) to be either "1" or "0"; bits of the mask that are "1" do not change the corresponding bits of the key identification code initial setting (Key_ID_initial). A single key identification code initial setting (Key_ID_initial) is used to derive a plurality of specified key identification codes (Key_ID_S1...Key_ID_SN). In practice, if one wants to obtain a plurality of specified key identification codes (Key_ID_S1...Key_ID_SN) in which some bits have a particular value, one can set the values of those bits in the key identification code initial setting (Key_ID_initial) to the particular value and set the values of the corresponding bits in the mask to 1 and the values of the other bits in the mask to 0. For example, if the key identification code initial setting (Key_ID_initial) is "101...010" and the mask is "111...011", the mask result is "101...010" and "101...110", representing two key identification codes. If the key identification code initial setting (Key_ID_initial) is "101...010" and the mask is "111...100", the mask result is "101...000", "101...001", "101...010", and "101...011", representing four consecutive key identification codes.

[0105] In another embodiment, the key identification code initial setting (Key_ID_initial) is XORed with a mask on a bit-by-bit basis. The bits of the result of the XOR operation that are "0" allow the corresponding bits of the key identification code initial setting (Key_ID_initial) to change from "0" to "1" or remain "0". The bits of the result of the XOR operation that are "1" do not allow the corresponding bits of the key identification code initial setting (Key_ID_initial) to change. A single key identification code initial setting (Key_ID_initial) can generate multiple specified key identification codes (Key_ID_S1...Key_ID_SN). In actual applications, if multiple specified key identification codes (Key_ID_S1...Key_ID_SN) are desired in which some bits have specific values, the values of these bits in the key identification code initial setting (Key_ID_initial) can be set to the specific values, and the values of these specific values can be inverted and used as the values of the corresponding bits in the mask. The values of the other bits in the mask can be set to the same values as the values of the corresponding bits in the key identification code initial setting (Key_ID_initial). For example, if the key identification code initial setting (Key_ID_initial) is "101...010" and the mask is "010...110", the result of the XOR operation of the key identification code initial setting (Key_ID_initial) and the mask is "111...100", so the mask result is "101...000", "101...001", "101...010", and "101...011", which represent four consecutive key identification codes.

[0106] In one embodiment, operand 114 indicates a first key identification code (Key_ID_first) and operand 116 indicates a number of key identification codes (num_of_KeyIDs). The multiple key identification codes (Key_IDs) can be listed in a list in system memory. The multiple key identification codes can be consecutive or non-consecutive. Operand 114 can be the address of the first key identification code (Key_ID_first) in system memory, which points to the location of the first key identification code (Key_ID_first) in the list. According to the number of key identification codes (num_of_KeyIDs) indicated by operand 116, multiple specified key identification codes (Key_ID_S1...Key_ID_SN) starting from the first key identification code (Key_ID_first) can be read from the list.

[0107] In one embodiment, the processor provides a special instruction WBINVD_Multiple_KeyIDs_1 for the above mask technology, which is distinguished from the instruction WBINVD_Multiple_KeyIDs_2 that takes a list of specific number of key identification codes.

[0108] In one embodiment, the present disclosure provides a processor, which provides an instruction (hereinafter denoted as INVD_Single_KeyID) of an instruction set architecture (ISA) to invalidate cache lines matching a single specified key identification code (Key_ID_S) in a hierarchical cache without writing back, without cache coherency.

[0109] Figure 1C For the ISA instruction INVD_Single_KeyID of the present disclosure, in addition to the opcode 132 for the invalidate instruction, there is a single operand 134. The operand 134 indicates the specified key identification code (Key_ID_S). The operand 134 can have various forms. For the instruction INVD_Single_KeyID, the operand 134 carries a register (reg) number to get the specified key identification code (Key_ID_S) from a register, as shown in the instruction architecture 136. For the instruction INVD_Single_KeyID, the operand 134 carries a register number or a system memory address to get the specified key identification code (Key_ID_S) from a register or a system memory (r / m), as shown in the instruction architecture 138. For the instruction INVD_Single_KeyID, the operand 134 carries an immediate number (imm16) as the specified key identification code (Key_ID_S), as shown in the instruction architecture 140. In programming, the instruction INVD_Single_KeyID can be preceded by other instructions to fill the register / memory / imm with the specified key identification code (Key_ID_S) for the instruction INVD_Single_KeyID to get the specified key identification code (Key_ID_S) from the operand 134. The instruction INVD_Single_KeyID can also be preceded by mode setting (including real mode, protected mode, 64-bit mode, etc.) and the bit width of the specified key identification code (Key_ID_S) indicated by the operand 134.

[0110] In another embodiment, the present application discloses a processor, wherein an instruction set architecture (ISA) instruction (hereinafter denoted as INVD_Multiple_KeyIDs) is provided to invalidate (without writing back) cache lines matching multiple specified key identification codes (Key_ID_S1...Key_ID_SN) in a hierarchical cache without write back and without considering cache coherency.

[0111] Figure 1D An instruction architecture for the present application ISA instruction INVD_Multiple_KeyIDs is shown in FIG. 6. In addition to the opcode 142 for the instruction, two operands 144 and 146 are used to obtain values to form the multiple specified key identification codes (Key_ID_S1...Key_ID_SN). Instruction architecture 148 shows that for the instruction INVD_Multiple_KeyIDs, operand 144 carries a register (reg) field and operand 146 carries a register (reg) field or a memory (m) field to obtain values from a register (reg) and a register (reg) or a memory (m) to form the multiple specified key identification codes (Key_ID_S1...Key_ID_SN). Instruction architecture 150 shows that for the instruction INVD_Multiple_KeyIDs, operand 144 carries a register (reg) field or a memory (m) field and operand 146 carries a register (reg) field to obtain values from a register (reg) or a memory (m) and a register (reg) to form the multiple specified key identification codes (Key_ID_S1...Key_ID_SN). Instruction architecture 152 shows that for the instruction INVD_Multiple_KeyIDs, both operand 144 and 146 carry register (reg) fields to obtain values from two registers (reg) to form the multiple specified key identification codes (Key_ID_S1...Key_ID_SN). In programming, other instructions can be used to fill registers / memory before the instruction INVD_Multiple_KeyIDs to obtain values to form the multiple specified key identification codes (Key_ID_S1...Key_ID_SN) from the operands 144 and 146.

[0112] In one embodiment, operand 144 indicates a key identification code initial setting (Key_ID_initial) and operand 146 indicates a mask; the same as the mask technique described above.

[0113] In one embodiment, operand 144 indicates a first key identification code (Key_ID_first) and operand 146 indicates a number of key identification codes (num_of_KeyIDs); similar to the above technique of taking a specific number of key identification codes from a list.

[0114] In one embodiment, regarding invalidation (no write back) of cache lines for a plurality of specified key identification codes (Key_ID_S1...Key_ID_SN), the processor is specially provided with an instruction INVD_Multiple_KeyIDs_1 for the above mask masking technique, distinguished from an instruction INVD_Multiple_KeyIDs_2 for taking a specific number of key identification codes from a list.

[0115] In one embodiment, the present application has corresponding designs in the microcode (ucode) of the processor for these instructions WBINVD_Single_KeyID, WBINVD_Multiple_KeyIDs, INVD_Single_KeyID, and INVD_Multiple_KeyIDs (i.e. each of these instructions corresponds to a set of microcode, and these microcodes are included in the ucode), and can also have corresponding modifications on the hardware of the processor.

[0116] Figure 2A As a block diagram, a processor 200 and a core core_1 thereon are illustrated according to one embodiment of the present application. The illustrated hierarchical cache includes first, second, and third level caches L1, L2, and L3. The first and second level caches L1 and L2 are in-core caches of the core core_1. The third level cache L3 is a last level cache (LLC) that can be shared by other cores. In a multi-core processor design, the in-core cache can only include the first level cache L1, and the second level cache L2 is outside the core and shared by multiple cores; relevant description examples will be given later.

[0117] After a single instruction is loaded from system memory 202 into instruction cache 204, it is decoded by a decoder 206. Decoder 206 includes an instruction buffer (XIB) 208 and an instruction translator (XLATE) 210. Instruction buffer (XIB) 208 recognizes the invalidation instructions (WBINVD_Single_KeyID, WBINVD_Multiple_KeyIDs, INVD_Single_KeyID, or INVD_Multiple_KeyIDs) presented herein, and instruction translator (XLATE) 210 translates the instruction into at least one microinstruction recognizable by the pipelined hardware to drive subsequent hardware to write back and invalidate, or invalidate without write back, the first, second, and third level caches L1, L2, and L3 based on the key identification code. The action can be for a corresponding single specified key identification code (Key_ID_S), or for a corresponding plurality of specified key identification codes (Key_ID_S1...Key_ID_SN). In one embodiment, instruction translator (XLATE) 210 translates the instruction into at least one microinstruction recognizable by the pipelined hardware based on microcode (ucode, stored in a ucode memory).

[0118] The at least one microinstruction decoded by the decoder 206 is stored in a corresponding reservation station (RS) according to a register alias table (RAT) 212, and then applied. The at least one microinstruction includes an invalidation microinstruction (a write-back and invalidation microinstruction matching a single key identification code, a write-back and invalidation microinstruction matching multiple key identification codes, a non-write-back and invalidation microinstruction matching a single key identification code, or a non-write-back and invalidation microinstruction matching multiple key identification codes), which triggers the operation of a memory order buffer (MOB) 216 via a reservation station 214, so as to invalidate the cache lines matching a single specified key identification code (Key_ID_S) or multiple specified key identification codes (Key_ID_S1…Key_ID_SN) in the first, second, and third level caches L1, L2, and L3. In some embodiments, part of the microinstructions trigger the execution unit 220 to act via a reservation station 218, so as to temporarily store the single specified key identification code (Key_ID_S) or the multiple specified key identification codes (Key_ID_S1…Key_ID_SN) in a storage unit Sto (which can be a static random access memory, a dynamic random access memory, or a register) as a local key identification code 222, and then process one by one. In an embodiment, the at least one microinstruction also includes microinstructions for functions such as exception checking (such as privilege level checking), memory address jumping (i.e., jumping to the next instruction of an invalid instruction), and the like. The storage unit Sto can be a memory of the core core_1 as shown, or can have other implementations. In a multi-core design, the local key identification code 222 can be stored in a storage unit shared by multiple cores, where the storage unit shared by multiple cores can be located in the uncore of the processor. In another embodiment, the local key identification code 222 can be stored in the storage space inside the first, second, and third level caches (L1, L2, and L3) of each core. Specifically, when the memory order buffer 216 sends an invalidation request to the first level cache L1, it carries the local key identification code 222, and the first level cache L1 saves the received local key identification code 222 in the storage space inside it; then the first level cache L1 sends an invalidation request to the second level cache L2, and carries the local key identification code 222; the second level cache L2 saves the received local key identification code 222 in the storage space inside it; then the second level cache L2 sends an invalidation request to the third level cache L3, and carries the local key identification code 222; the third level cache L3 saves the received local key identification code 222 in the storage space inside it.In one embodiment, the execution unit 220 will delete the previously saved contents in the storage unit Sto before storing the single specified key identification code (Key_ID_S) or the multiple specified key identification codes (Key_ID_S1...Key_ID_SN) in the storage unit Sto.

[0119] The following four ISA instructions WBINVD_Single_KeyID, WBINVD_Multiple_KeyIDs, INVD_Single_KeyID, and INVD_Multiple_KeyIDs of the present application are described in terms of their hardware operations. It is noted that when the four ISA instructions of the present application are used in a program code, at least one setup instruction (such as a MOV instruction) is required before the four ISA instructions of the present application to fill in the operands of the four ISA instructions of the present application in preparation for the execution of the four ISA instructions of the present application. Figure 2A

[0120] The ISA instruction WBINVD_Single_KeyID is first discussed, which is based on a single specified key identification code (Key_ID_S) for writing back and invalidation of the hierarchical cache.

[0121] Referring to the figure, the single specified key identification code (Key_ID_S) taken from a register, or the system memory 202, or interpreted from an immediate number can be loaded in a write back and invalidation request, which is sent to the first level cache LI via the communication interface implemented by the memory order buffer (MOB) 216. The write back and invalidation request loaded with the single specified key identification code (Key_ID_S) can be passed through the first level cache LI, and the second level cache L2, to the third level cache L3. Upon receiving the write back and invalidation request, the third level cache L3 finds all cache lines (possibly multiple) that match the specified key identification code (Key_ID_S) according to the specified key identification code (Key_ID_S) loaded in the write back and invalidation request, writes back to the system memory 202 the cache lines that have been modified (M state cache lines) and do not exist in the upper level caches (L2 and / or LI), and invalidates (e.g., sets a valid bit of the matching cache line to invalid) all cache lines that match the specified key identification code (Key_ID_S) regardless of whether the cache lines have been modified. The hierarchical cache (applicable to the first, second, and third level caches) how to find all cache lines that match the specified key identification code (Key_ID_S) will be described later in connection with Figure 2B

[0122] ​​The third level cache L3 further records the tag of all matching cache lines (hereinafter referred to as matching cache line tag). In a general hierarchical cache design, the use of a cache line is indicated by a tag. For example, the same tag is used for a cache line at different levels corresponding to the same physical address (PA). The same tag is also used for the cache content at different levels. Therefore, the matching cache line tag found by the third level cache L3 can be used for matching cache lines in the second level cache L2 and the first level cache Ll. The matching cache lines in the second level cache L2 and the first level cache Ll do not need to refer to the specified key identification code (Key_ID_S) but instead refer to the matching cache line tag analyzed by the third level cache L3. In one embodiment, the matching cache line tag includes a key identification code (Key_ID), a tag (TAG), an index (INDEX), and the like. In another embodiment, the matching cache line tag includes a physical address (PA).

[0123] Since there can be multiple cache lines in the third level cache L3 that match the specified key identification code (Key_ID_S), there can be multiple matching cache line tags. The third level cache L3 sends multiple snoop requests to the snoop filter 224, each snoop request having one matching cache line tag. These snoop requests are supplied by the snoop filter 224 to the second level cache L2 and then to the first level cache Ll.

[0124] In response to each snoop request from the third level cache L3, the second level cache L2 finds a cache line (if any) that also has the same matching cache line tag. If the cache line has been modified (M state) and does not exist in the upper level cache (Ll), it is written back to the system memory 202 and then invalidated (e.g., a valid bit of the cache line is set to invalid). If the cache line has not been modified (non-M state), it is directly invalidated. In response to each snoop request from the second level cache L2, the first level cache Ll finds a cache line (if any) that also has the matching cache line tag. If the cache line has been modified (M state), it is written back to the system memory 202 and then invalidated (e.g., a valid bit of the cache line is set to invalid). If the cache line has not been modified (non-M state), it is directly invalidated.

[0125] By the write back and invalidate request carrying the single specified key identification (Key_ID_S) passing through L1, L2 to L3, and the snoop request carrying the different matching cacheline flag passing back from L3 to L2, L1, the cacheline matching the specified key identification (Key_ID_S) in all hierarchical caches L1, L2, L3 is indeed written back to system memory 202 and consistently invalidated. The instruction WBINVD_Single_KeyID is completed.

[0126] In another embodiment, the memory order buffer (MOB) 216 delivers a write back and invalidate request to the hierarchical caches (including L1, L2, and L3) without the specified key identification (Key_ID_S). The microinstruction operates through the reservation station (RS) 218 execution unit 220 to store the specified key identification (Key_ID_S) in storage unit Sto as a local key identification 222. The third level cache L3 obtains the single specified key identification (Key_ID_S) from storage unit Sto after receiving the write back and invalidate request, and performs subsequent actions (write back and invalidate of matching cacheline itself, and snoop request to write back and invalidate matching cacheline of in-core caches). The instruction WBINVD_Single_KeyID is completed. In one embodiment, the third level cache L3 can obtain the local key identification from storage unit Sto by interrupt. For example, the third level cache L3 can send an interrupt signal to core core_1, and core core_1 executes an interrupt handler to write the local key identification 222 saved in storage unit Sto into a register of the third level cache L3. In another embodiment, the third level cache L3 can directly read the local key identification from storage unit Sto.

[0127] Figure 2B The format 250 of a cacheline of a hierarchical cache is illustrated according to one embodiment of the present application. Referring to the format 250 of a cacheline of a hierarchical cache, field 252 is a valid bit (VALID) with a value of 0 indicating that the cacheline is invalid, and a value of 1 indicating that the cacheline is valid. The invalid cacheline described above is a cacheline with the valid bit (VALID) set to invalid (value of 0). Field 254 records a key identification (Key_ID). When the hierarchical cache searches for a matching cacheline according to a specified key identification (Key_ID_S), if the cacheline is valid and the key identification (Key_ID) of the cacheline is identical to the specified key identification (Key_ID_S), the corresponding cacheline is a matching cacheline.

[0128] Next, we will discuss the ISA instruction WBINVD_Multiple_KeyIDs, which performs a write-back and invalidation of the hierarchical cache based on multiple specified key identification codes (Key_ID_S1…Key_ID_SN).

[0129] Please also refer to Figure 1B , 2A The values ​​indicated by the two operands 114 and 116 of the instruction WBINVD_Multiple_KeyIDs are retrieved from the register or system memory 202 and then processed by the execution unit 220 (masking or list lookup, see above for specific processing methods) to obtain multiple specified key identification codes (Key_ID_S1…Key_ID_SN), which are then stored in the storage unit Sto as local key identification codes 222. Unlike the instruction WBINVD_Single_KeyID, which resolves only a single write-back and invalidation request (corresponding to a single specified key identifier (Key_ID_S), the corresponding instruction WBINVD_Multiple_KeyIDs resolves multiple write-back and invalidation requests, corresponding to multiple specified key identifiers (Key_ID_S1…Key_ID_SN) managed by the local key identifier 222. In one implementation, the memory sequential cache (MOB) 216 transmits one write-back and invalidation request at a time, and only after the write-back and invalidation request has been processed is the next write-back and invalidation request passed to the third-level cache L3 through the first-level cache L1 and the second-level cache L2.

[0130] In one implementation, each write-back and invalidation request is formed using the local key identification code 222 of the reference storage unit Sto, carrying one of the aforementioned multiple specified key identification codes (Key_ID_S1…Key_ID_SN). Based on the single specified key identification code (Key_ID_S#) carried by each write-back and invalidation request, the third-level cache L3 performs subsequent actions (write-back and invalidation of its own matching cache line, and write-back and invalidation of matching cache lines in the kernel cache based on a snooping request; details of the specific actions are described above). After the processes triggered by multiple write-back and invalidation requests carrying the aforementioned multiple specified key identification codes (Key_ID_S1…Key_ID_SN) have been completed, in the hierarchical caches L1, L2, and L3, cache lines matching all specified key identification codes (Key_ID_S1…Key_ID_SN) are indeed written back to system memory 202 and are consistently invalidated. The instruction WBINVD_Multiple_KeyIDs is completed.

[0131] In another embodiment, a multiple write back and invalidate request to the hierarchical cache (including L1, L2 and L3) from the memory order buffer (MOB) 216 does not carry the above-mentioned multiple specified key identification codes (Key_ID_S1...Key_ID_SN). The write back and invalidate request without the specified key identification code (Key_ID_S#) is also passed from the first level cache L1, the second level cache L2 to the third level cache L3. The third level cache L3 obtains the specified key identification code (Key_ID_S#) from the local key identification code 222 of the storage unit Sto only after receiving the write back and invalidate request, and then performs the subsequent actions (write back and invalidate of the matching cache line itself, and snooping request to write back and invalidate the matching cache line of the on-chip cache, details of which are described above). By means of the multiple write back and invalidate request, the third level cache L3 repeatedly accesses the storage unit Sto to obtain the specified key identification codes (Key_ID_S1...Key_ID_SN) from the local key identification code 222 in sequence for operation. All cache lines matching the specified key identification codes (Key_ID_S1...Key_ID_SN) in the hierarchical cache L1, L2, L3 are indeed written back to the system memory 202 and invalidated consistently. The instruction WBINVD_Multiple_KeyIDs is completed.

[0132] Next, the ISA instruction INVD_Single_KeyID, which invalidates without writing back to the hierarchical cache based on a single specified key identification code (Key_ID_S), is discussed.

[0133] Please refer to Figure 1C , 2A and 2B, a single specified key identification code (Key_ID_S) taken from a register, or the system memory 202, or interpreted from an immediate number can be carried in an invalidate without write back request, which is sent to the first level cache L1 through the communication interface implemented by the memory order buffer (MOB) 216. The invalidate without write back request carrying the single specified key identification code (Key_ID_S) can be passed from the first level cache L1, and the second level cache L2 to the third level cache L3. After receiving the invalidate without write back request, the third level cache L3 finds all cache lines (possibly multiple) matching itself according to the specified key identification code (Key_ID_S) carried by the invalidate without write back request, and invalidates all cache lines matching the specified key identification code (Key_ID_S) without writing back to the system memory 202 (without considering cache coherency), for example, by setting the valid bit (VALID) 252 (as shown in Figure 2B ).

[0134] As with the previous technique, the L3 cache records the tag of all matching cache lines (matching cache line tag) for itself. All matching cache line tags found by the L3 cache are sent in a pair of snoop requests to the snoop filter 224, which supplies the matching cache line tags to the L2 cache, which supplies the matching cache line tags to the Ll cache.

[0135] In response to each snoop request from the L3 cache, the L2 cache finds a cache line (if any) for itself that also has the matching cache line tag and invalidates the cache line (without a write back to the system memory 202, without regard to cache coherency) without a write back to the system memory 202 (without regard to cache coherency). In response to each snoop request from the L2 cache, the Ll cache finds a cache line (if any) for itself that also has the matching cache line tag and invalidates the cache line (without a write back to the system memory 202, without regard to cache coherency). Figure 2B Figure 2B In response to each snoop request from the L3 cache, the L2 cache finds a cache line (if any) for itself that also has the matching cache line tag and invalidates the cache line (without a write back to the system memory 202, without regard to cache coherency) without a write back to the system memory 202 (without regard to cache coherency). In response to each snoop request from the L2 cache, the Ll cache finds a cache line (if any) for itself that also has the matching cache line tag and invalidates the cache line (without a write back to the system memory 202, without regard to cache coherency).

[0136] By the no-write-back / invalidation request with the single specified key identification (Key_ID_S) passing through the Ll, L2, and L3 caches and the string of snoop requests from the L3 cache back to the L2 and Ll caches, all cache lines in the Ll, L2, and L3 caches that match the specified key identification (Key_ID_S) are invalidated without a write back to the system memory 202. The instruction INVD_Single_KeyID is complete.

[0137] In another embodiment, the no-write-back / invalidation request to the hierarchical cache (including the Ll, L2, and L3 caches) from the memory order buffer (MOB) 216 does not include the specified key identification (Key_ID_S). The microinstruction stores the specified key identification (Key_ID_S) in the storage unit Sto through the reservation station (RS) 218 and the execution unit 220 as the local key identification 222. The L3 cache obtains the single specified key identification (Key_ID_S) from the storage unit Sto after receiving the no-write-back / invalidation request to obtain the local key identification 222 and perform the subsequent actions (self-matching cache line no-write-back / invalidation and snoop request to invalidate matching cache lines in the in-core caches, as described above). The instruction INVD_Single_KeyID is complete. ​

[0138] The ISA instruction INVD_Multiple_KeyIDs is discussed below. The instruction invalidates without writing back the hierarchical cache based on multiple specified key identification codes (Key_ID_S1...Key_ID_SN).

[0139] Please refer to Figure 1D , 2A and 2B, the multiple specified key identification codes (Key_ID_S1...Key_ID_SN) obtained by the execution unit 220 (masking, or list lookup) after the instruction INVD_Multiple_KeyIDs two-operand 144, 146 indicates the values taken from the register, or the system memory 202, are stored in the storage unit Sto as the local key identification codes 222.

[0140] In one embodiment, the memory order buffer (MOB) 216 is to pass the multiple invalidation without writing back requests through the first level cache L1, and the second level cache L2, to the third level cache L3. Each invalidation without writing back request is formed according to the local key identification codes 222 of the storage unit Sto, with one of the multiple specified key identification codes (Key_ID_S1...Key_ID_SN). According to the single specified key identification code (Key_ID_S#) carried by each invalidation without writing back request, the third level cache L3 performs the following actions (self-matching cache line invalidation without writing back, and snooping request to invalidate the matching cache line without writing back in the on-chip cache, details of the actions are described above). After all the programs triggered by the multiple invalidation without writing back requests with the multiple specified key identification codes (Key_ID_S1...Key_ID_SN) are processed, the cache lines matching all the specified key identification codes (Key_ID_S1...Key_ID_SN) in the hierarchical cache L1, L2, L3 are invalidated without writing back to the system memory 202. The instruction INVD_Multiple_KeyIDs is completed.

[0141] In another embodiment, the memory order buffer (MOB) 216 passes the multiple non-write back invalidation requests to the hierarchical cache (including L1, L2 and L3) without the multiple specified key identification codes (Key_ID_S1...Key_ID_SN). The non-write back invalidation request without the specified key identification code (Key_ID_S#) is passed from the first level cache L1, the second level cache L2 to the third level cache L3. The third level cache L3 obtains the specified key identification code (Key_ID_S#) from the local key identification code 222 of the storage unit Sto after receiving the non-write back invalidation request, and then performs the subsequent actions (self-matching cache line non-write back invalidation, and snooping request to invalidate the matching cache line non-write back in the on-chip cache, details of which are described above). By multiple non-write back invalidation requests, the third level cache L3 repeatedly accesses the storage unit Sto to obtain the specified key identification code (Key_ID_S1...Key_ID_SN) from the local key identification code 222 for operation. All cache lines matching the specified key identification code (Key_ID_S1...Key_ID_SN) in the hierarchical cache L1, L2 and L3 are directly invalidated without write back to the system memory 202. The instruction INVD_Multiple_KeyIDs is completed.

[0142] In addition to the aforementioned snoop filter 224, the present application further provides another embodiment to implement the on-chip cache (including L1, L2) to write back and invalidate (or non-write back invalidation). Please refer to Figure 2A, the implementation is that when the write-back-and-invalidate request (or no-write-back-and-invalidate request) is received, the write-back-and-invalidate request (or no-write-back-and-invalidate request) is saved into an internal register (not shown in the figure) of the in-core cache (including L1, L2) and the in-core cache (including L1, L2) enters a wait-for-sync state (no operation is performed). The write-back-and-invalidate request (or no-write-back-and-invalidate request) is transmitted to the last-level cache (L3) through the in-core cache (including L1, L2) so that the last-level cache (L3) performs write-back-and-invalidate (or no-write-back-and-invalidate) of the matching cache line and then sends a notification back to the in-core cache through the path 226. The second-level cache L2 in the wait-for-sync state does not perform any operation until the notification is received, and then performs the write-back-and-invalidate request (or no-write-back-and-invalidate request) of the matching cache line previously saved in the internal register (not shown in the figure). After the second-level cache L2 completes the write-back-and-invalidate (or no-write-back-and-invalidate) of the matching cache line, a notification is sent to the first-level cache L1 so that the first-level cache L1 in the wait-for-sync state is started to perform the write-back-and-invalidate (or no-write-back-and-invalidate) of the matching cache line previously saved in the internal register (not shown in the figure). In this implementation, the write-back-and-invalidate request (or no-write-back-and-invalidate request) transmitted in the hierarchical memory (L1 to L2 to L3) can also have the aforementioned design with / without the specified key identification code (Key_ID_S#). In an embodiment, the notification sent by the third-level cache L3 to the second-level cache L2 and by the second-level cache L2 to the first-level cache L1 is a bit value of 1. Compared with the embodiment using the snoop filter, in this embodiment, the last-level cache (L3) can directly transmit the notification to the in-core cache (including L1, L2) without the need of transmission through the snoop filter.

[0143] The present application also provides another implementation of write-back-and-invalidate (or no-write-back-and-invalidate) of the in-core cache (including L1, L2) without using the aforementioned snoop filter 224. Please refer to Figure 2AThe implementation is that when the in-core cache (including L1, L2) receives a write-back and invalidation request (or a write-back and invalidation request), it starts to perform the write-back and invalidation (or write-back and invalidation) operation of the matching cache line itself, and passes the received write-back and invalidation request (or write-back and invalidation request) to the last level cache (L3) to make the last level cache (L3) also perform the write-back and invalidation (or write-back and invalidation) operation of the matching cache line itself. In this implementation, the write-back and invalidation request (or write-back and invalidation request) passed in the hierarchical memory (L1 to L2 to L3) can also have the aforementioned design with / without a specified key identification code (Key_ID_S). In this embodiment, the in-core cache (including L1, L2) does not have to enter a waiting synchronization signal state, but performs the write-back and invalidation (or write-back and invalidation) operation of the matching cache line at the same time as the last level cache (L3), so the efficiency is higher.

[0144] A multi-core computer system is described below.

[0145] Figure 3Figure illustrates a computer system 300 implemented according to one embodiment of the present application, in which snoop filter technology is used. Each of the dies Die_1 and Die_2 includes a processor Processor_1 and a processor Processor_2. Each of the processors Processor_1 / Processor_2 includes a plurality of cores core_1-core_N. Each core includes an in-core cache (e.g., a first level, L1, and a second level, L2). The processor Processor_1 has a last level cache (e.g., a third level, L3) LLC_1 shared by the plurality of cores core_1-core_N on the processor Processor_1, and the processor Processor_1 has a snoop filter Snoop_1 associated with the last level cache LLC_1. The processor Processor_2 has a last level cache LLC_2 shared by the plurality of cores core_1-core_N on the processor Processor_2, and the processor Processor_2 has a snoop filter Snoop_2 associated with the last level cache LLC_2. Both of the processors Processor_1 and Processor_2 provided by the dies Die_1 and Die_2 are connected to a system memory Sys_Mem. The figure illustrates that a core core_i of the processor Processor_1 of the die Die_1 executes a command WBINVD_Single_KeyID, WBINVD_Multiple_KeyIDs, INVD_Single_KeyID, or INVD_Multiple_KeyIDs of the present application to perform writing back and invalidation or invalidation without writing back of a hierarchical cache based on a key identification code.

[0146] The core core_i forms a communication interface with its memory order buffer MOB to transmit the write-back-and-invalidate request (or no-write-back-and-invalidate request) 302 to the core cache 304, and then to the last level cache LLC_1. According to the received request, the last level cache LLC_1 finds the cache line matching the specified key identification Key_ID_S#. As to the write-back-and-invalidate request, the last level cache LLC_1 writes back to the system memory Sys_Mem the cache line matching the specified key identification Key_ID_S# that has been modified (the cache line in the M state) and does not exist in the upper level cache, and invalidates the matching cache line regardless of the state of the cache line. As to the no-write-back-and-invalidate request, the last level cache LLC_1 does not write back to the system memory Sys_Mem the matching cache line. The matching cache line found by the last level cache LLC_1 can have multiple flags, which are respectively loaded into multiple snoop requests 306 given to the snoop filter snoop_1, and then given by the snoop filter snoop_1 to the core caches of the cores core_1 to core_N in the processor Processor_1, so that the cache lines matching the flags of the matching cache line are written back and invalidated (or not written back and invalidated). In this way, the write-back-and-invalidate (or no-write-back-and-invalidate) of the cache lines matching the specified key identification Key_ID_S# is completed in the core caches of all the cores core_1 to core_N in the processor Processor_1, and in the last level cache LLC_1 shared by all the cores core_1 to core_N.

[0147] In particular, the last level cache LLC_1 passes the request received from the in-core cache 304 to the last level cache LLC_2 through the channel 308 between the die Die_1 and the die Die_2. According to the received request, the last level cache LLC_2 finds the cache line matching the specified key identification Key_ID_S#. For the write-back-and-invalidate request, the last level cache LLC_2 writes back to the system memory Sys_Mem the cache line matching the specified key identification Key_ID_S# that has been modified (the cache line in the M state) and does not exist in the upper level cache, and invalidates the matching cache line regardless of the state of the cache line. For the no-write-back-and-invalidate request, the last level cache LLC_2 does not write back to the system memory Sys_Mem the matching cache line. The last level cache LLC_2 also passes the matching cache line flag to the snoop filter snoop_2 in the snoop request 310. The snoop request 310 is passed by the snoop filter snoop_2 to the in-core caches of the cores core_1 to core_N in the processor Processor_2, so that the cache line matching the specified key identification Key_ID_S# is written back and invalidated (or not written back and invalidated) in the in-core caches of all the cores core_1 to core_N in the processor Processor_2 and the last level cache LLC_2 shared by all the cores core_1 to core_N. In this way, the write-back-and-invalidate (or no-write-back-and-invalidate) of the cache line matching the specified key identification Key_ID_S# is completed in the in-core caches of all the cores core_1 to core_N in the processor Processor_2 and the last level cache LLC_2 shared by all the cores core_1 to core_N.

[0148] In the present embodiment, the request 302 can have the specified key identification Key_ID_S# or not (stored in the storage unit accessible by all the hierarchical caches as a local key identification for reading by the hierarchical caches), as in the foregoing technique. When the request 302 does not have the specified key identification Key_ID_S#, the core core_i of the processor Processor_1 passes the specified key identification Key_ID_S# to the processor Processor_2 through the channel 308 between the die Die_1 and the die Die_2 and transmits the write-back-and-invalidate request (or no-write-back-and-invalidate request) 302 to the in-core cache 304. The processor Processor_2 can store the received specified key identification Key_ID_S# in the storage unit of any of the cores or in the non-core storage unit.

[0149] Figure 4A 、 4B Fig. 12 illustrates a computer system 400 according to another embodiment of the present application, which is a multi-core and multi-die design without using a snoop filter.

[0150] After the core core_i transmits the write-back and invalidation request (or invalidation without write-back) req to the in-core cache (including L1 and L2) 402 through the communication interface formed by the memory order buffer MOB, the in-core cache 402 transmits the write-back and invalidation request (or invalidation without write-back) req to the last level cache LLC_1, and then the in-core cache 402 enters the state of waiting for the synchronization signal (sync). In particular, the core core_i can transmit the same request req to other cores (other cores on the same processor Processor_1, and all cores core_1…core_N on another processor Processor_2) through the interrupt design (to be described in detail later) provided by the present application, and then the in-core cache of the other cores transmits the write-back and invalidation request (or invalidation without write-back) req to the last level cache, and then the in-core cache enters the state of waiting for the synchronization signal (sync). All in-core caches of all cores on the entire computer system 400 receive the same request req, and are all set to the state of waiting for the synchronization signal (sync). Figure 6 After the core core_i transmits the write-back and invalidation request (or invalidation without write-back) req to the in-core cache (including L1 and L2) 402 through the communication interface formed by the memory order buffer MOB, the in-core cache 402 transmits the write-back and invalidation request (or invalidation without write-back) req to the last level cache LLC_1, and then the in-core cache 402 enters the state of waiting for the synchronization signal (sync). In particular, the core core_i can transmit the same request req to other cores (other cores on the same processor Processor_1, and all cores core_1…core_N on another processor Processor_2) through the interrupt design (to be described in detail later) provided by the present application, and then the in-core cache of the other cores transmits the write-back and invalidation request (or invalidation without write-back) req to the last level cache, and then the in-core cache enters the state of waiting for the synchronization signal (sync). All in-core caches of all cores on the entire computer system 400 receive the same request req, and are all set to the state of waiting for the synchronization signal (sync).

[0151] For example, the in-core cache of each core transmits the request req received by itself to the last level cache LLC l. According to the request req received earliest, the last level cache LLC l finds the cache line matching the specified key identification Key_ID_S#. The specified key identification Key_ID_S# can be provided by the request req or by the local key identification provided by the storage unit Sto_Die l (not shown in the figure, in an embodiment, located in the non-core of the processor Processor l ) shared by the cores of the processor Processor l. In an embodiment, before transmitting the request req to the in-core cache, the core core_i resets the storage unit Sto_Die l shared by the cores and stores the local key identification therein. In another embodiment, the local key identification is provided by the cores core l …core N of the processor Processor l. The last level cache LLC l obtains the specified key identification Key_ID_S# by querying the local key identification of the core that provides the request req earliest. For the write-back and invalidate request, the last level cache LLC l writes back to the system memory Sys_Mem the cache line matching the specified key identification Key_ID_S# that has been modified (the cache line in the M state) and does not exist in the upper level cache, and invalidates the matching cache line regardless of the state of the cache line. For the no-write-back and invalidate request, the last level cache LLC l invalidates the matching cache line without writing back to the system memory Sys_Mem. After completing the request req, the last level cache LLC l sends a notification to the in-core cache of each core core l …core N of the processor Processor l. Upon receiving the notification, the second level cache L2 of the in-core cache executes the request req in the waiting state to write back and invalidate (or no-write-back and invalidate) the cache line matching the specified key identification Key_ID_S#. The specified key identification Key_ID_S# can be provided by the request req, the local key identification of the storage unit Sto_Die l, or the local key identification provided by the core itself. After completing the request req, the second level cache L2 sends a notification to the upper level cache L l. Upon receiving the notification, the first level cache L l executes the request req in the waiting state to write back and invalidate (or no-write-back and invalidate) the cache line matching the specified key identification Key_ID_S#. Similarly, the specified key identification Key_ID_S# can be provided by the request req, the local key identification of the storage unit Sto_Die l, or the local key identification provided by the core itself.

[0152] Taking Processor_2 as an example, all core caches transmit the received request (req) to the lowest-level cache LLC_2. Based on the earliest received request (req), the lowest-level cache LLC_2 finds the cache line matching the specified key identification code (Key_ID_S#) and performs an action. The specified key identification code (Key_ID_S#) can be the one transmitted by the request (req), or it can be provided by the local key identification code in the shared memory unit Sto_Die2 (not shown in the figure, located in a non-core of Processor_2 in one embodiment), or it can be obtained by querying the local key identification code of the core that first provided the request (req). In one embodiment, before core_i transmits the request (req) to the core cache, it can use the interrupt design provided in this application (which will be discussed later in conjunction with...) Figure 6 (Detailed explanation follows) The local key identification code is passed to the master core of Processor_2. The master core first resets the shared memory unit Sto_Die2 and then stores the local key identification code there. After the lowest level cache LLC_2 completes the request, it sends a notification to the core caches of all cores core_1…core_N of Processor_2. As mentioned above, the second level cache L2 of all cores core_1…core_N of Processor_2 exits the waiting state, completes the request, and sends a notification to its upper-level cache L1. After receiving the notification, the first level cache L1 also exits the waiting state and completes the request. All hierarchical caches of all cores core_1…core_N of Processor_2 have completed the request made by core_i of Processor_1.

[0153] It is worth noting that, in Figure 4A , 4BIn the illustrated embodiment, if the core_i of the computer system 400 is executing a write-back-and-invalidate request, the core_i passes the write-back-and-invalidate request to other cores (other cores on the processor Processor_1 in the die Die_1, and all cores core_1...core_N on the processor Processor_2 in the die Die_2, in an embodiment, the core_i passes the write-back-and-invalidate request to all cores core_1...core_N on the processor Processor_2 in the die Die_2 through the inter-die channel 408) before passing the write-back-and-invalidate request to the in-core cache 402, and then all cores of the computer system 400 execute the write-back-and-invalidate request synchronously. The execution of the write-back-and-invalidate request synchronously by all cores means that all cores of the computer system 400 pass the write-back-and-invalidate request to the in-core cache at the same time. In another embodiment, the execution of the write-back-and-invalidate request synchronously by all cores also means that the in-core cache of each core passes the write-back-and-invalidate request to the last level cache at the same time after receiving the write-back-and-invalidate request, and then the in-core cache of each core enters a waiting for a synchronization signal (sync) state.

[0154] In addition, in a design of implementing hierarchical cache write-back-and-invalidate without using a snoop filter, if a cacheline has been modified (the cacheline in the M state), each core needs to write back the cacheline saved in the uppermost hierarchical cache to the system memory. For example, the first level cache L1, the second level cache L2, and the third level cache L3 of the core core_i all save the modified (i.e., in the M state) cacheline cacheline1, and thus the core core_i needs to write back the cacheline cacheline1 saved in the first level cache L1 to the system memory. The second level cache L2 and the third level cache L3 of the core core_i both save the modified (i.e., in the M state) cacheline cacheline1, and the first level cache L1 does not save the cacheline cacheline1, and thus the core core_i needs to write back the cacheline cacheline1 saved in the second level cache L2 to the system memory.

[0155] In another embodiment, Figure 4A 、 4BWhen the write-back-and-invalidate (or no-write-back-and-invalidate) request is received by the in-core cache (including L1 and L2) of each core in the computer system 400, the in-core cache (including L1 and L2) starts to perform the write-back-and-invalidate (or no-write-back-and-invalidate) operation on the matching cache line, and passes the write-back-and-invalidate (or no-write-back-and-invalidate) request to the next level cache (L3) so that the next level cache (L3) also performs the write-back-and-invalidate (or no-write-back-and-invalidate) operation on the matching cache line. In this embodiment, the in-core cache (including L1 and L2) does not need to enter the waiting state for the synchronization signal, but performs the write-back-and-invalidate (or no-write-back-and-invalidate) operation on the matching cache line at the same time as the next level cache (L3), so that the efficiency is higher.

[0156] Figure 5 Fig. 5 shows a processor 500 according to another embodiment of the present application, in which the in-core cache only includes the first level cache L1, and the second level cache L2 is shared by the multiple cores.

[0157] In the processor 500, the core core_1 and the core core_2 share the second level cache 502, and the core core_3 and the core core_4 share the second level cache 504. The cores core_1 to core_4 share the third level cache 506. The core core_1 that initiates the instruction of the present application provides the request req to the first level cache 508, and the first level cache 508 passes the request req to the second level cache 502, and the second level cache 502 passes the request req to the third level cache 506.

[0158] According to the received request req, the third level cache 506 finds out the cache line matching the specified key identification (Key_ID_S#) and performs the request req action. The specified key identification (Key_ID_S#) can be transmitted by the request req, or can be a local key identification for the shared storage unit of the cores core_1…core_4 (the shared storage unit can be located in the non-core of the processor 500), or can be a local key identification for the internal storage unit of the cores core_1…core_4. After the third level cache 506 completes the request req, it sends a series of snoop requests with matching cache line flags to the snoop filter 510, to be transmitted to the second level caches 502 and 504, and further transmitted to the first level caches of the cores core_1…core_4. After the second level caches 502 and 504 receive the snoop requests, they write back and invalidate (or invalidate without writing back) the cache line matching the matching cache line flag (if any). After the first level caches of the cores core_1…core_4 receive the snoop requests, they write back and invalidate (or invalidate without writing back) the cache line matching the matching cache line flag (if any). The hierarchical cache completes the cache line management of the specified key identification.

[0159] Another embodiment does not involve the snoop filter 510. The core core_1 initiating the instruction of the present application, when providing the request req to the first level cache 508, will also transmit the same request req to the other cores core_2…core_4 through the inter-core channel 520 as shown in the figure, or the interrupt design provided by the present application (which will be described in detail below in conjunction with Figure 5 Figure 6 After the cores core_2…core_4 receive the same request req, each of them will transmit the received same request req to its own first level cache. After all the first level caches of the cores core_1…core_4 of the entire processor 500 receive the same request req, they are all set to a waiting synchronization signal (sync) state in addition to transmitting the request req to the next level cache.

[0160] ​The second level cache 502 receives the request req from the first level cache of core 1 and the first level cache of core 2. According to the request req received first, the second level cache 502 sets a wait state for a synchronization signal (sync) and forwards the request req to the third level cache 506. The second level cache 504 receives the request req from the first level cache of core 3 and the first level cache of core 4. According to the request req received first, the second level cache 504 sets a wait state for a synchronization signal (sync) and forwards the request req to the third level cache 506.

[0161] According to the request req received first, the third level cache 506 finds the cache line matching the specified key identification code (Key_ID_S#) and completes the request req, and writes back and invalidates (or invalidates without writing back) the cache line matching the specified key identification code (Key_ID_S#). The specified key identification code (Key_ID_S#) can be transmitted with the request req, can be a local key identification code for the shared storage unit of the cores core 1...core 4, or can be a local key identification code for the internal storage unit of the cores core 1...core 4. After the third level cache 506 completes the request req, a notification is sent to the second level caches 502 and 504. Upon receiving the notification, the second level caches 502 / 504 exit the wait state, execute the request req, and write back and invalidate (or invalidate without writing back) the cache line matching the specified key identification code (Key_ID_S#). Similarly, the specified key identification code (Key_ID_S#) can be transmitted with the request req, can be a local key identification code for the shared storage unit of the cores core 1...core 4, or can be a local key identification code for the internal storage unit of the cores core 1...core 4. After the second level cache 502 completes the request req, a notification is sent to the first level caches (L1) of the cores core 1 and core 2. After the second level cache 504 completes the request req, a notification is sent to the first level caches (L1) of the cores core 3 and core 4. Upon receiving the notification, the first level caches (L1) exit the wait state, execute the request req, and write back and invalidate (or invalidate without writing back) the cache line matching the specified key identification code (Key_ID_S#). The specified key identification code (Key_ID_S#) can be transmitted with the request req, can be a local key identification code for the shared storage unit of the cores core 1...core 4, or can be a local key identification code for the internal storage unit of the cores core 1...core 4.

[0162] For two processors (each like processor 500) fabricated on two dies, when any processor initiates the management of the specified key tag of the hierarchical flash memory by the instructions of the present application, all cores in the other processor will send the same request req into the first level cache (L1) through the inter-die channel. In this way, the hierarchical caches on different dies are uniformly managed.

[0163] In another embodiment not involving the snoop filter 510, Figure 5 When the in-core cache (including L1, L2) of each core in the processor 500 in theIn this embodiment, the in-core cache (including L1, L2) does not have to enter the waiting synchronization signal state, but performs the write-back and invalidation (or non-write-back and invalidation) operation of the matching cache line at the same time as the last level cache (L3), thus being more efficient.

[0164] The present application can provide an interrupt design, so that the multi-core architecture can cope with the situation where any core initiates the instructions of the present application.

[0165] Figure 6 Fig. 1 illustrates a computer system 600 implementing a multi-core architecture according to an embodiment of the present application. As shown, the relevant microcode ucode (with the Figure 6 Figure 2AThe ucode that includes the interrupt design 602 can be the same ucode as the ucode in the core core_1. The core core_1 initiates the instruction of the present application, and the at least one microinstruction that includes the interrupt design 602 is generated after the instruction is decoded by a decoder (e.g., the decoder 206). The at least one microinstruction is delivered to an execution unit (not shown in the figure) and a memory order buffer (MOB) 608 via a register allocation table (RAT) 604 and a reservation station (RS) 606. The execution unit (not shown in the figure) can send an interrupt request 610 to an inter-core interrupt handler 612 via the memory order buffer (MOB) 608 by executing the microinstruction of the interrupt design 602. The message carried by the interrupt request 610 can include a target core (e.g., the core core_2) and an interrupt reason (e.g., the write back and invalidate request / no write back and invalidate request req), which can be generated by the execution unit (e.g., an ALU, etc., not shown in the figure) by executing other microinstructions before sending the interrupt request 610. The inter-core interrupt handler 612 analyzes the interrupt request 610 and issues an interrupt to the target core core_2 with an interrupt vector number and the interrupt reason (req). When the core core_2 retires the ISA instruction that it is currently executing, the core core_2 responds to the interrupt reason (req) by executing the microinstruction of the interrupt design 616 in the ucode corresponding to the interrupt vector number via a reorder buffer (ROB) 614 of the core core_2; for example, by sending the same request req into an on-core cache of the core core_2. In a specific implementation, a reserved or undefined interrupt vector number can be selected from an interrupt vector table to be used as the interrupt vector number of the present application. One skilled in the art can write the interrupt designs 602, 616 in the ucode to meet the requirements of the present application based on the functions of the interrupt designs 602, 616 in the present application.

[0166] In another implementation, the interrupt reason (req) is carried in a storage space in the core core_2. The core core_2 can periodically check the storage space (e.g., by using a polling mechanism to check the storage space at regular intervals) to send the same request req into an on-core cache of the core core_2.

[0167] Any computer system (single-core processor, multi-core processor, or multiprocessor) that implements hierarchical cache management (write back and invalidate, or no write back and invalidate) of specified key identification codes (single specified, or multiple specified) using ISA instructions is within the scope of the present application.

[0168] According to the technology, the hierarchical cache has a corresponding key-granularity management function; when the transparent full memory encryption function is enabled, the operating system can manage the hierarchical cache in a key granularity.

[0169] Although the present application has been disclosed in its preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application is defined by the claims.

Claims

1. A computer system for performing hierarchical cache write-not-allocate invalidation based on a specified key identification code, comprising: a first core, fabricated on a first die, of a first processor, including a decoder, a memory order buffer, and a first core-internal cache; and a first last-level cache, fabricated on the first processor; wherein: in response to a first instruction of a set of instructions of an instruction set architecture for performing hierarchical cache write-not-allocate invalidation based on a single specified key identification code, the decoder translates at least one microinstruction; in accordance with the at least one microinstruction, a write-not-allocate invalidation request is supplied to the first core-internal cache via the memory order buffer, and in turn, to the first last-level cache; in response to the write-not-allocate invalidation request, the first last-level cache locates all matching cache lines matching the specified key identification code, and invalidates the located matching cache lines in the system memory.

2. The computer system for performing hierarchical cache write-not-allocate invalidation based on a specified key identification code as recited in claim 1, wherein: upon setting a valid bit of a cache line to invalid, the cache line is invalidated.

3. The computer system for performing hierarchical cache write-not-allocate invalidation based on a specified key identification code as recited in claim 1, wherein: the write-not-allocate invalidation request carries the specified key identification code; and the first last-level cache locates all matching cache lines matching the specified key identification code in accordance with the specified key identification code carried by the write-not-allocate invalidation request.

4. The computer system for performing hierarchical cache write-not-allocate invalidation based on a specified key identification code as recited in claim 1, further comprising: a first storage unit storing the specified key identification code parsed from the first instruction; wherein: the write-not-allocate invalidation request does not carry the specified key identification code; upon receiving the write-not-allocate invalidation request, the first last-level cache retrieves the specified key identification code from the first storage unit, and locates all matching cache lines matching the specified key identification code in accordance with the specified key identification code.

5. The computer system for performing hierarchical cache write-not-allocate invalidation based on a specified key identification code as recited in claim 4, wherein: the first storage unit is located in the first core and used by the first core itself, or the first storage unit is located in a non-core of the first processor and shared by a plurality of cores of the first processor.

6. The computer system for performing hierarchical cache write-not-allocate invalidation based on a specified key identification code as recited in claim 1, wherein: the first processor further includes a first snoop filter; the first last-level cache issues a snoop request corresponding to each matching cache line of the first last-level cache, and the snoop request is passed to the first core-internal cache via the first snoop filter; each snoop request carries a tag of a corresponding matching cache line in the hierarchical cache; and in response to each snoop request, the first core-internal cache locates a cache line matching the tag carried by the snoop request, and invalidates the located cache line in the system memory. ​ 7. The computer system of claim 6, wherein: the first intra-core cache comprises a first level cache and a second level cache; the first last level cache is a third level cache; the no-write-allocate requirement is passed from the first level cache to the second level cache and from the second level cache to the third level cache; each snoop request is received by the second level cache from the first snoop filter and passed from the second level cache to the first level cache; in accordance with each snoop request, the second level cache locates a cache line that it matches the tag carried by the snoop request and allocates the cache line to the system memory and invalidates the cache line; and in accordance with each snoop request, the first level cache locates a cache line that it matches the tag carried by the snoop request and allocates the cache line to the system memory and invalidates the cache line.

8. The computer system of claim 6, wherein: the first processor further comprises a second core comprising a second intra-core cache; each snoop request is also passed from the first snoop filter to the second intra-core cache; in accordance with each snoop request, the second intra-core cache locates a cache line that it matches the tag carried by the snoop request and allocates the cache line to the system memory and invalidates the cache line.

9. The computer system of claim 8, wherein: the first core and the second core each have a first level cache as the first intra-core cache and the second intra-core cache; the first processor provides a second level cache for common use by the first core and the second core; the first last level cache is a third level cache; the no-write-allocate requirement is passed from the first level cache of the first core to the second level cache for common use by the first core and the second core and from the second level cache to the third level cache; the first snoop filter gives each snoop request to the second level cache for common use by the first core and the second core and from the second level cache to the first level cache of the first core and the first level cache of the second core; in accordance with each snoop request, the second level cache locates a cache line that it matches the tag carried by the snoop request and allocates the cache line to the system memory and invalidates the cache line; in accordance with each snoop request, the first level cache of the first core locates a cache line that it matches the tag carried by the snoop request and allocates the cache line to the system memory and invalidates the cache line; and in accordance with each snoop request, the first level cache of the second core locates a cache line that it matches the tag carried by the snoop request and allocates the cache line to the system memory and invalidates the cache line.

10. The computer system of claim 1, further comprising: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a second processor fabricated on the second die, the second processor including a third core including a third in-core cache and a second last level cache; wherein: the first last level cache further passes the no-write allocate invalidate request to the second last level cache via a channel between the first die and the second die; and in response to receiving the no-write allocate invalidate request, the second last level cache locates all matching cache lines matching the specified key identifier in itself and invalidates all located matching cache lines in the system memory.

11. The computer system of claim 10, wherein: the second processor further includes a second snoop filter; the second last level cache issues a snoop request corresponding to each matching cache line in itself to the third in-core cache via the second snoop filter; each snoop request carries a tag common to the corresponding matching cache line in the hierarchical cache; and in response to each snoop request, the third in-core cache locates a cache line matching the tag carried by the snoop request in itself and invalidates the located cache line in the system memory.

12. The computer system of claim 1, wherein: after invalidating all matching cache lines in itself, the first last level cache sends a first notification back to the first in-core cache; and the first in-core cache supplying the no-write allocate invalidate request to the first last level cache is in a wait-for-synchronization signal state until receiving the first notification sent back by the first last level cache, at which point the first in-core cache locates all matching cache lines matching the specified key identifier in itself and invalidates all located matching cache lines in the system memory.

13. The computer system of claim 12, wherein: the first in-core cache includes a first level cache and a second level cache; the first last level cache is a third level cache; the no-write allocate invalidate request is passed from the first level cache to the second level cache and from the second level cache to the third level cache; the third level cache passes the first notification to the second level cache; in response to the first notification, the second level cache in the wait-for-synchronization signal state is enabled to locate all matching cache lines matching the specified key identifier in itself and invalidate all located matching cache lines in the system memory; after invalidating all matching cache lines in itself, the second level cache sends a second notification back to the third level cache; and in response to the second notification, the first level cache in the wait-for-synchronization signal state is enabled to locate all matching cache lines matching the specified key identifier in itself and invalidate all located matching cache lines in the system memory.

14. The computer system of claim 12, wherein: the first processor further comprises a second core including a second in-core cache; the no-write-allocate invalidate request is further supplied to the second core by the memory order buffer of the first core, and is delivered to the first last level cache by the second in-core cache of the second core; and the no-write-allocate invalidate request to which the first last level cache responds is the earlier of the first core and the second core.

15. The computer system of claim 14, further comprising: an inter-core interrupt handler that receives an interrupt request from the first core through the memory order buffer corresponding to the no-write-allocate invalidate request, and operates the reorder buffer of the second core to initiate an interrupt design of microcode of the second core to deliver the no-write-allocate invalidate request to the second in-core cache.

16. The computer system of claim 14, wherein: the first last level cache also returns the first notification to the second in-core cache to initiate the second in-core cache in a wait-for-synchronization signal state to snoop all matching cache lines of the second in-core cache that match the specified key identification and to invalidate all matching cache lines found in the system memory.

17. The computer system of claim 16, wherein: the first core and the second core each have a first level cache as the first in-core cache and the second in-core cache; the first processor provides a second level cache for the first core and the second core to share; the first last level cache is a third level cache; the no-write-allocate invalidate request is delivered from the first level cache of the first core to the second level cache shared by the first core and the second core, and from the second level cache to the third level cache; the third level cache delivers the first notification to the second level cache shared by the first core and the second core; in response to the first notification, the second level cache in a wait-for-synchronization signal state is initiated to snoop all matching cache lines of the second level cache that match the specified key identification and to invalidate all matching cache lines found in the system memory; the second level cache returns a second notification to the third level cache after invalidating all matching cache lines of the second level cache; in response to the second notification, the first level cache in the first core in a wait-for-synchronization signal state is initiated to snoop all matching cache lines of the first level cache that match the specified key identification and to invalidate all matching cache lines found in the system memory; and ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ According to the second notification, the first level cache in the second core in the waiting synchronization signal state initiates to find all matching cache lines matching the specified key identification code, and invalidates all matching cache lines found in the system memory without write back.

18. The computer system for performing hierarchical cache write-not-allocate or invalidate based on a specified key identification code as recited in claim 12, further comprising: a second processor fabricated on a second die, the second processor including a third core and a second last level cache, the third core including a third in-core cache; wherein: the write-not-allocate or invalidate request is further supplied to the third core through the memory order buffer of the first core, through a channel between the first and second dies, and is delivered to the second last level cache by the third in-core cache of the third core; in response to the received write-not-allocate or invalidate request, the second last level cache finds all matching cache lines matching the specified key identification code, and invalidates all matching cache lines found in the system memory without write back; and after the second last level cache invalidates all its matching cache lines, a third notification is sent back to the third in-core cache to initiate the third in-core cache in the waiting synchronization signal state to find all matching cache lines matching the specified key identification code, and invalidates all matching cache lines found in the system memory without write back.

19. The computer system for performing hierarchical cache write-not-allocate or invalidate based on a specified key identification code as recited in claim 1, wherein: the first instruction involves a single operand indicating a register, or a system memory address, or an immediate number to obtain the specified key identification code required by the first instruction.

20. A computer system for performing hierarchical cache write-not-allocate or invalidate based on a specified key identification code, comprising: a first core, a first processor fabricated on a first die, including a decoder, a memory order buffer, and a first in-core cache; and a first last level cache fabricated on the first processor; wherein: in response to a second instruction of an instruction set architecture for performing write-not-allocate or invalidate on hierarchical cache based on a plurality of specified key identification codes, the decoder translates at least one micro-instruction; and according to the at least one micro-instruction corresponding to the second instruction, the plurality of specified key identification codes are stored in a storage unit of the first core, and a plurality of write-not-allocate or invalidate requests are supplied to the first in-core cache through the memory order buffer, and the write-not-allocate or invalidate based on a current specified key identification code is completed before the write-not-allocate or invalidate based on a next specified key identification code is performed, wherein the write-not-allocate or invalidate based on a current specified key identification code includes, in response to the write-not-allocate or invalidate request, the first last level cache finding all matching cache lines matching the specified key identification code, and invalidating all matching cache lines found in the system memory without write back. ​ 21. The computer system of claim 20, wherein: the second instruction involves two operands to obtain a key identification code preliminary setting and a mask, and the mask is used to mask the key identification code preliminary setting to form the plurality of specified key identification codes required by the second instruction.

22. The computer system of claim 20, wherein: the second instruction involves two operands to obtain a system memory address indicating a start key identification code in a list on the system memory and a key identification code specified number, and the plurality of specified key identification codes required by the second instruction are obtained from the list according to the system memory address and the key identification code specified number.

23. A method of performing hierarchical cache no-write-allocate or no-allocate based on a specified key identification code, comprising: in response to a first core taking a first instruction of an instruction set architecture based on a single specified key identification code to perform no-write-allocate or no-allocate on a hierarchical cache, causing a decoder of the first core to convert the first instruction into at least one micro-instruction, wherein the first core is a first processor fabricated on a first die; in accordance with the at least one micro-instruction, supplying a no-write-allocate or no-allocate request to a first on-core cache of the first core via a memory order buffer of the first core, and further via the first on-core cache to a first last level cache, wherein the first last level cache is fabricated on the first processor and outside of the first core; and in response to the no-write-allocate or no-allocate request, operating the first last level cache to find all matching cache lines of the first last level cache matching the specified key identification code.

24. The method of claim 23, wherein: the no-write-allocate or no-allocate request carries the specified key identification code; and the first last level cache finds all matching cache lines of the first last level cache matching the specified key identification code in accordance with the specified key identification code carried by the no-write-allocate or no-allocate request.

25. The method of claim 23, further comprising: storing the specified key identification code parsed from the first instruction in a first storage unit; wherein: the no-write-allocate or no-allocate request does not carry the specified key identification code; and the first last level cache obtains the specified key identification code from the first storage unit upon receiving the no-write-allocate or no-allocate request, and uses the specified key identification code to find all matching cache lines of the first last level cache matching the specified key identification code.

26. The method of claim 23, further comprising: causing the first last level cache to issue a snoop request corresponding to each matching cache line of the first last level cache to a first snoop filter on the first processor, and further to the first on-core cache. ​ ​ wherein each snoop request carries a tag common to the corresponding matching cache line in the hierarchical cache; and In response to each snoop request, the first in-core cache locates a cache line that matches the tag carried by the snoop request and invalidates the located cache line without writing back the located cache line to the system memory.

27. The method for performing hierarchical cache write-back-ineffective based on a specified key identification code as recited in claim 26, wherein: the first processor further comprises a second core, the second core comprising a second in-core cache; each snoop request is also delivered by the first snoop filter to the second in-core cache; In response to each snoop request, the second in-core cache locates a cache line that matches the tag carried by the snoop request and invalidates the located cache line without writing back the located cache line to the system memory.

28. The method for performing hierarchical cache write-back-ineffective based on a specified key identification code as recited in claim 23, further comprising: causing the first last-level cache to further deliver the write-back-ineffective request received from the first in-core cache to a second last-level cache of a second processor on a second die via a channel between the first die and the second die, wherein the second processor further comprises a third core, and the third core comprises a third in-core cache; and in response to receiving the write-back-ineffective request, the second last-level cache locates all matching cache lines that match the specified key identification code and invalidates all the located matching cache lines without writing back the located matching cache lines to the system memory.

29. The method for performing hierarchical cache write-back-ineffective based on a specified key identification code as recited in claim 28, wherein: the second processor further comprises a second snoop filter; the second last-level cache issues snoop requests for each of its matching cache lines to the third in-core cache via the second snoop filter; wherein each snoop request carries a tag common to the corresponding matching cache line in the hierarchical cache; and In response to each snoop request, the third in-core cache locates a cache line that matches the tag carried by the snoop request and invalidates the located cache line without writing back the located cache line to the system memory.

30. The method for performing hierarchical cache write-back-ineffective based on a specified key identification code as recited in claim 23, wherein: after the first last-level cache invalidates all its matching cache lines, the first last-level cache sends back a first notification to the first in-core cache; and the first in-core cache that supplied the write-back-ineffective request to the first last-level cache is in a wait-for-synchronization signal state until receiving the first notification sent back by the first last-level cache, and then locates all matching cache lines that match the specified key identification code and invalidates all the located matching cache lines without writing back the located matching cache lines to the system memory.

31. The method for performing hierarchical cache write-back-ineffective based on a specified key identification code as recited in claim 30, wherein: the first processor further comprises a second core, the second core comprising a second in-core cache; The no-write-allocate invalidate request is supplied to the second core through the memory order buffer of the first core, and is passed to the second last level cache by the second core's second in-core cache; and The no-write-allocate invalidate request responded by the first last level cache is from the first core or the second core, whichever comes earlier.

32. The method of claim 31, wherein: The first last level cache also returns the first notification to the second in-core cache, to enable the second in-core cache in the waiting-for-synchronization signal state to find all matching cache lines matching the specified key identification code, and to invalidate all found matching cache lines in the system memory without write allocation.

33. The method of claim 30, further comprising: The no-write-allocate invalidate request is supplied to the third core of the second processor on the second die through the memory order buffer of the first core, and is passed to the third in-core cache included in the third core of the second processor on the second die through a channel between the first die and the second die, and is passed to the second last level cache on the second processor by the third in-core cache of the third core; In response to the received no-write-allocate invalidate request, the second last level cache finds all matching cache lines matching the specified key identification code, and invalidates all found matching cache lines in the system memory without write allocation; and After the second last level cache invalidates all matching cache lines, a third notification is returned to the third in-core cache, to enable the third in-core cache in the waiting-for-synchronization signal state to find all matching cache lines matching the specified key identification code, and to invalidate all found matching cache lines in the system memory without write allocation.

34. A method of performing hierarchical cache no-write-allocate invalidate based on a specified key identification code, wherein: In response to a second instruction of a set of instructions of an instruction set architecture for performing no-write-allocate invalidate of a hierarchical cache based on a plurality of specified key identification codes, a decoder of a first core converts at least one microinstruction, wherein the first core is a first processor fabricated on a first die, and the first core further includes a memory order buffer and a first in-core cache; and According to the at least one microinstruction corresponding to the second instruction, the plurality of specified key identification codes are stored in a storage unit of the first core, and a plurality of no-write-allocate invalidate requests are supplied to the first in-core cache through the memory order buffer, to perform no-write-allocate invalidate based on a current specified key identification code before performing no-write-allocate invalidate based on a next specified key identification code, wherein the no-write-allocate invalidate based on the current specified key identification code includes, in response to the no-write-allocate invalidate request, operating a first last level cache to find all matching cache lines matching the specified key identification code, and invalidating all found matching cache lines in a system memory without write allocation. ​ 35. The method for hierarchical cache write-back-less invalidation based on specified key identification codes as recited in claim 34, wherein: the second instruction involves two operands to obtain a key identification code initial setting and a mask, and the mask is used to mask the key identification code initial setting to form the specified key identification codes required by the second instruction.

36. The method for hierarchical cache write-back-less invalidation based on specified key identification codes as recited in claim 34, wherein: the second instruction involves two operands to obtain a system memory address indicating a start key identification code in a list on the system memory and a key identification code specified number, and the specified key identification codes required by the second instruction are obtained from the list according to the system memory address and the key identification code specified number.

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